# REGISTER AND COUNTER

```Registers and Counters
by
Dr. Amin Danial Asham
References
Digital Design 5th Edition, Morris
Mano
 Registers are group of FF’s.
 Each FF stores a binary bit .
 Therefore, n-bits registers has nFF’s.
 4-bits Register.
 This register has a clear
signal to reset all FF’s.
 This register is positive
edge trigger.
 Each input 𝐼𝑖 is mapped
to output 𝐴𝑖 at the clock
positive edge.
10
0
1
1
𝑰𝟎𝟎
𝑨
1
0
 𝐷𝑖 of the ith FF is:
𝐷𝑖 = 𝐿𝑜𝑎𝑑 ′ . 𝐴𝑖 +𝐿𝑜𝑎𝑑. 𝐼𝑖
 If 𝐿𝑜𝑎𝑑 = 0 , 𝐷𝑖 = 𝐴𝑖 (𝑡) ,
therefore
the
next
𝐴𝑖 𝑡 + 1 = 𝐴𝑖 (𝑡)
0
1
1
0
𝑨
𝑰𝟏𝟏
0
1
1
0
 If 𝐿𝑜𝑎𝑑 = 1 , 𝐷𝑖 = 𝐼𝑖
therefore all the FF’s are
the clock edge.
𝑨𝑰𝟐
0
1
0
1
𝑨𝑰𝟑
0
1
 Shift Register
 Data is injected serially in serial input SI into the register with each
clock pulse.
 Sine the data is shifted inside the register it comes out serially as
well from serial output SO
SI
SO
 Serial Transfer
 Data can be transferred from register A to register B serially as
shown.
 Controlling the shifted data is done by controlling the clock using
AND gate.
o Data loss in Reg. A is avoided by
circulating the information via
connecting SO to SI.
 Serial Transfer (continue)





The following table is showing that initial stored data in Reg. A
1011.
This data is transferred to Reg. B which has an initial data 0010.
This transfer is carried on at four rising edges of the four clock
pulses T1, T2, T3 , and T4.
Each rising edge shifts the data in both registers one bit.
As shown in the table, after 4 pulses both registers have the
same value.
 Two binary numbers
by bit
 A single full adder is
used.
 A D-FF is used to
store the carry out of
the current operation
to be used as carry
in for the next bit
 Universal Shift Register
 Counters
 A counter is a register that goes though a predetermined
sequence of binary states upon the applications of input
pulses.
 An n-bits binary counter has 2𝑛 states that count from 0
up to 2𝑛 − 1.
 An n bits counter has n FF’s.
 There are two categories of counters:
o Ripple Counters
o Synchronous counters
 Ripple Counters (Asynchronous)
with JK-FF’s
Two-bit asynchronous
counter
 Each FF is connected as a toggle FF
triggered by the previous FF. That is:
• Q0 is complemented each
time clock goes from 1 to 0.
• Q1 is complemented each
time Q0 goes from 1 to 0.
• That means the trigger is
propagated through the
counter as a ripple
fashion from the clock to
the most significant bit
through FF’s.
• Therefore the transition
od 𝑄1 𝑄0 from01 to 10 is
as follows:
𝟎𝟏 → 𝟎𝟎 →10
 Ripple Counters (Asynchronous)
with D-FF’s
 Ripple Counters (Asynchronous)
with T-FF’s
 2-bits Ripple countdown counter.
 2-bits ripple count down
counter which counter from
3 to 0
 All FF’s are positive edge
trigger.
 The polarity of the clock is
essential for ripple counter
counter
3
2
1
0
3
 BCD Ripple Counter (Decade Counter)
Logic
1
AND
Output
Count
FF2_J
BCD O/P= 𝑸𝟖 𝑸𝟒 𝑸𝟐 𝑸𝟏
0
1
2
3
4
5
6
7
8
9
0
 3 -BCD Ripple Counter (0-999)
 Noting that BCD counters here are triggered by the
negative edge.
 Synchronous counters
 A FF in any position is complemented if
all the lower significant bits are all 1’a.
o For example for output 𝐴3 𝐴2 𝐴1 𝐴0 =
0011 , then the next count is
𝐴3 𝐴2 𝐴1 𝐴0 = 0100.
𝐴3
is
complemented by the next count
when all the lower significant bits
𝐴1 and 𝐴0 are ones.
 When count enable is 0 all J’s and K’s
are zeros and hence the clock does
not affect the counter state.
 The polarity of the clock is not
essential for synchronous counters
 Up-Down Binary Counter
 When the Up enable signal is 1
the counter acts as count-up
counter.
o A FF in any position is
complemented if all the lower
significant bits are all 1’a.
 When the Down enable signal is
1 and UP signal is 0 the counter
acts as count-Down counter.
o A FF in any position is
complemented if all the lower
significant bits are all 0’a.
 Up-Down Binary Counter (continue)
Logic 1
Binary O/P= 𝑸𝟏 𝑸𝟎
0
1
2
3
0
3
2
1
0
 Binary Counter with Parallel Load
 The counter can be loaded with a certain value to start
counting from it.
 Then 𝐿𝑜𝑎𝑑 = 1 counting operation is disabled and the
value applied to Data_in lines is loaded into the FF’s of
the counter.
 BCD counter using Binary Parallel Loaded Counter.
 A BCD counter can be built using parallel loaded binary counter in two
ways:
o Using an and gate to activate the Load input to load zeros into the
counter if the current state is 10012(910) with the next rising edge of the
clock.
o A NAND gate can be used to reset the counter when the state 10102
(1010) immediately. This configuration is not desirable since a spike may
occur at 𝐴0 as it counts from 1010 to 1011 then immediately moves to
zero.