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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 9, SEPTEMBER 2013
An Extended-Bandwidth Three-Way
Doherty Power Amplifier
Hamed Golestaneh, Student Member, IEEE, Foad Arfaei Malekzadeh, Member, IEEE, and
Slim Boumaiza, Senior Member, IEEE
Abstract—This paper expounds a three-way Doherty power
amplifier (3W-DPA) as a solution to the need for high-efficiency
wideband power amplifiers when driven by multi-standard signals. The paper begins with a theoretical analysis of 3W-DPA
architecture from which the governing equations are derived.
This analysis enables the identification of circuit parameters for
maximizing bandwidth. A comprehensive methodology was devised to address the practical design challenges resulting from the
transistor nonidealities: nonlinear input capacitance, transistor
package, and output capacitance. Based on this methodology, a
fully analog 30-W 3W-DPA was designed and implemented using
GaN packaged transistors. The 3W-DPA prototype maintained
an average drain efficiency of 55% at an output back-off of up to
9 dB, over the frequency range of 0.73–0.98 GHz. The 3W-DPA
was successfully linearized when driven with 20-MHz four-carrier
wideband code division multiple access (WCMDA) signals. 830and 900-MHz power-added efficiencies of 47% and 53% was
achieved at 32- and 35-dBm average output power, corresponding
to a peak-to-average power ratio of 11.7 and 7.14 dB, respectively.
Index Terms—High peak-to-average power ratio (PAPR)
signals, multi-standard communications, multi-way Doherty
amplifier.
I. INTRODUCTION
M
ODERN wireless communication networks are required
to support spectrally efficient modulation schemes and
wideband signals for broadband access. In addition, these networks are expected to handle legacy communication standards.
This requires multi-standard radio systems that are capable
of operating over a broad range of carrier frequencies and of
processing various signals encoded according to dissimilar
standards. Furthermore, the signals being used and those being
introduced have high peak-to-average power ratios (PAPRs)
and wide bandwidths. These signal characteristics increase the
design complexity of the RF power amplifiers (RFPAs) to be
deployed in the modern wireless infrastructure. In fact, a single
RFPA is expected to efficiently amplify wideband and high
Manuscript received March 05, 2013; revised July 21, 2013; accepted July
23, 2013. Date of publication August 08, 2013; date of current version August
30, 2013. This work was supported by Ericsson Canada.
H. Golestaneh and S. Boumaiza are with the Emerging Radio System
Research Group (EmRG), Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada N2L 3G1 (e-mail:
hgolesta@uwaterloo.ca; sboumaiz@uwaterloo.ca).
F. A. Malekzadeh was with the Emerging Radio System Research Group
(EmRG), Department of Electrical and Computer Engineering, University of
Waterloo, Waterloo, ON, Canada N2L 3G1. He is now with the Microsemi Corporation, Ottawa, ON, Canada K2K 3H4 (e-mail: f2arfaei@uwaterloo.ca; ).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2013.2275331
PAPR signals located over a broad range of carrier frequencies.
In addition, the same RFPA must comply with the linearity
requirements imposed by wireless standards.
Among the various efficiency enhancement techniques proposed in the literature, the Doherty power amplifier (DPA) has
succeeded in improving average efficiency when applied to
amplify: 1) signals with low to moderate PAPR (up to 7 dB)
scattered over a broad range of carrier frequencies [1]–[8] and
2) single-band signals with high PAPR (up to 12 dB) [9]–[13].
The authors of [1]–[5] conducted comprehensive studies to
identify the theoretical and practical sources of bandwidth
limitations, commonly observed in different implementations
of the classical two-way Doherty power amplifier (2W-DPA).
These studies triggered attempts to devise solutions to extend
the bandwidth of 2W-DPAs. For example, the authors of [1]
and [4] transformed the quarter-wave impedance inverter
into a quasi- or complete-lumped equivalent circuit. This
allowed absorption of the two transistors’ output capacitance
and the bond-wires’ inductance and consequently alleviated
the bandwidth limitation. In spite of the excellent back-off
efficiency obtained in [1] using the 20-W DPA demonstrator
over the frequency range of 1.7–2.3 GHz, this solution required
a mixed-signal setup to ensure proper operation. In [3], the
authors suggested a novel topology that mitigated the bandwidth limitations of a classical 2W-DPA. The novel approach
required two different drain supply voltages for the main and
peaking transistors. A minimum 6-dB back-off efficiency of
52% was maintained over a fractional bandwidth of 35%.
This significant bandwidth of 2W-DPAs was achieved at the
expense of an increase in the required breakdown voltage of
the peaking transistor, and consequently, is mainly applicable
to high breakdown voltage device technologies, such as gallium–nitride (GaN).
Various approaches have also been reported to improve the
average efficiency of single-band DPAs when driven with high
PAPR signals [9]–[13]. The theory of the classical 2W-DPA
has been generalized in [9] and [10] to yield what is called
an asymmetrical 2W-DPA. This latter required larger peaking
transistors to extend the high-efficiency power range. Nevertheless, the bandwidth of the asymmetrical 2W-DPA was further
confined by the increased impedance transformation ratio of
the impedance inverter. Moreover, the noticeably increased
peaking transistor size caused further complexity and narrower
bandwidth for the input/output matching network. In addition,
the deep decrease of the efficiency between the two efficiency
peaks resulted in a considerable drop of the average efficiency
of an asymmetrical 2W-DPA for modulated signal excitation
0018-9480 © 2013 IEEE
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GOLESTANEH et al.: EXTENDED-BANDWIDTH 3W-DPA
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Fig. 1. Drain efficiency comparison of three Doherty topologies.
(see Fig. 1). Alternatively, a multi-way architecture was reported in [11] and [13] to improve the average efficiency of a
DPA under single-band and high PAPR signals. As illustrated
in Fig. 1, a three-way Doherty power amplifier (3W-DPA)
maintains a higher efficiency as compared to its two-way counterparts throughout the back-off region. However, the efficiency
improvement is only achieved under proper control of the main
transistor drain current to maintain proper load modulation in
the high-power range [11]. The additional control of the main
transistor required hinders the analog realization of this type of
3W-DPA and only a mixed-signal version has been reported
to date. To address the complexity of a classical 3W-DPA, a
novel output combining network has been proposed in [14].
A gate-adaptation technique was added to this architecture
to ensure the proper load modulation versus power [12]. An
average drain efficiency of 55% was obtained when amplifying a WiMAX signal at 2.655 GHz. Yet, the power-added
efficiency (PAE) was 10% lower due to the low gain of the PA.
Furthermore, the gate-adaptation feature imposed the addition
of two envelope tracking modules that complicated the design.
The authors of [15] and [16] recently introduced an elegant
approach to maximize the average efficiency for high PAPR signals over a broad range of frequencies by reconfiguring the drain
supply voltage of the main transistor of a 2W-DPA according
to the input signal PAPR. However, this technique is not suitable for concurrent amplification of multi-band signals. The approach also suffers from a low power utilization factor when reconfigured for high PAPR values. This paper suggests the extension of the 3W-DPA’s bandwidth to efficiently amplify signals
with high PAPR, scattered over a wide range of frequencies. It
begins with an analysis of the 3W-DPA architecture presented
in [14] to extract the governing equations in order to synthesize the output combining network parameters for a given output
power and efficiency versus power profile. The performance of
the 3W-DPA was then studied as the carrier frequency shifted to
the left or right of the design frequency, leading to the development of a design methodology, which maximizes the efficiency
over bandwidth. The theory was generalized to account for the
device nonidealities and then applied to design a 3W-DPA using
packaged GaN transistors. As a proof of the proposed theory, a
3W-DPA prototype was designed and fabricated.
Fig. 2. Simple schematic of a 3W-DPA at: (a) low-, (b) medium-, and (c) highpower region.
II. THREE-WAY DOHERTY AMPLIFIER PARAMETER SYNTHESIS
This section presents an analysis of the operation mechanism
of a 3W-DPA in different power regions. For simplicity, the
transistors are initially modeled as ideal voltage-controlled current sources. The knee voltage is supposed to be very small compared with the drain bias voltage of the device. It is also assumed
that all of the harmonics are short circuited at the current source
reference planes.
Fig. 2(c) shows a simplified schematic of a 3W-DPA, which
consists of a main and two peaking transistors, represented by
ideal current sources, ,
, and
, respectively. Our aim is
to determine the circuit design parameters for a given efficiency
profile and a given output power. In other words,
,
,
,
, and the ratio between the transistors’ peak current will be
expressed as functions of , , and
. and represent
the breakpoints at which the two efficiency peaks occur (see
Fig. 1) and
denotes the optimum load impedance of the
main transistor. The general expressions of the current profiles
are given by (1)–(3) as follows:
(1)
elsewhere.
(2)
elsewhere.
(3)
elsewhere
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 9, SEPTEMBER 2013
where
is the normalized instantaneous input voltage. Based
on these current profiles and and , the governing equations
for the impedances seen by the current sources can be derived at
three different power regions (i.e., low power, medium power,
and high power).
In the low-power region
,
, and
are equal to
0 [see Fig. 2(a)]. Hence,
(4)
and
are the magnitude of fundamental compowhere
nents of voltage and current of the main transistor, respectively.
Note that at
, the maximum efficiency should be attained, meaning that
, where
and
denote the knee voltage and the maximum voltage swing of the
main transistor, respectively. Therefore, using (4) and (1), we
obtain
On the other hand, the voltage of the first peaking transistor
can be determined using the current of the main transistor and
the
-parameters of the transmission lines [see Fig. 2(b)],
as
(11)
Note that the first peaking transistor reaches the maximum efficiency at
meaning that
. Also,
at this point, so we can conclude that
(12)
together with (12) can
Moreover, (10) evaluated at
be used to determine the ratio of the peak current of the first
peaking device to that of the main device,
, as
(13)
(5)
, where
represents the optimum
Note that
load impedance of the main transistor. Thus,
can be expressed as
(6)
In the medium-power region
, the first
peaking transistor is turned on [see Fig. 2(b)] so the impedance
of the main transistor is modulated by
, which can be calculated as
(7)
Using the
-parameters of the three
lines,
can be written as
transmission
In the high-power region, all three transistors are operating
[see Fig. 2(c)]. Note that the current of the second peaking transistor only modulates the load of the first peaking transistor, and
thus does not affect the impedance seen by the main transistor,
as long as the first peaking device does not enter into the knee
region. As a result, (10) still holds in the high-power region. In
fact, the voltage across the second peaking transistor is dictated
by the first peaking current source transformed into a voltage
source by the
impedance inverter with the characteristic
impedance of
. Thus, at the maximum input voltage,
(14)
In other words,
must be equal to the optimum load resistance of the first peaking transistor. Substituting for
using
(13), we can conclude that
(15)
(8)
Note that
can be readily determined from (12) using
and
of (15) and (6), respectively.
Additionally, (11) can be rewritten to account for the second
peaking current,
, in the high-power region. Thus,
Substituting (8) into (7) yields
(9)
which can be rearranged to give
or
(10)
As can be seen, (10) is very similar to the load modulation expression derived in [17] for the 2W-DPA. It shows that the current injected to the load by the first peaking transistor reduces
the output impedance of the main one, thereby preventing its
saturation.
(16)
Evaluating (16) at
gives
(17)
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GOLESTANEH et al.: EXTENDED-BANDWIDTH 3W-DPA
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TABLE I
3W-DPA DESIGN PARAMETERS
which can be combined with (12) and (15) to conclude
(18)
Table I summarizes the 3W-DPA synthesis equations for a
given
and . In this paper,
and
are chosen to be 1/3
and 1/2, corresponding to 9.5- and 6-dB power back-off, respectively. The fundamental current and voltage profiles are depicted in Fig. 3, using (1)–(3), (13), and (18). It is worth noting
that the voltage swing of the second peaking transistor,
, is 0
in the low-power region since it is proportional to
, which is
0 for
. Using the fundamental current and voltage profiles, one can calculate the impedance seen by each transistor in
different power regions as
(19)
(20)
indefinite
Fig. 3. Fundamental components of: (a) drain current and (b) drain voltage of
and
.
the three transistors for
(21)
The impedance profiles of the three transistors versus the normalized input voltage are plotted in Fig. 4 for the special case
of
and
. As can be seen, in this particular
case, the optimum load resistances (at peak input voltage) of all
the transistors are equal to
, which may not be the case in
general according to (19)–(21).
It can be observed from Table I that for a given output power
(or equivalently
) and efficiency profile ( and ), the
three remaining equations in the table are sufficient to fully describe the 3W-DPA’s behavior. Considering the four unknown
circuit parameters (
,
,
, and
), it can be inferred
that there is not a unique solution for this linear system of equations. Thus, we can set
as an independent parameter and calculate the other parameters based on that. This is a significant
conclusion since it implies that there are infinite possible sets
of design parameters, all yielding the exact same performance
(output power, efficiency, etc.) at the frequency of design. As
Fig. 4. Fundamental impedance profiles of the three transistors for
and
.
will be explained later, one can harness
to maximize the efficiency of the 3W-DPA over the bandwidth.
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 9, SEPTEMBER 2013
Fig. 6. Standard deviation of the main transistor impedance versus the load
values. The local optimum of 17 obtained for
resistance for different
corresponds to the maximum efficiency over the bandwidth for
the current design. The integration range was for 30% fractional bandwidth.
plicity, the ideal current sources will still be used to replace
the actual transistors. Therefore, the frequency variation will be
solely attributed to the output combining network. Later, we will
extend this analysis to include the device nonidealities.
A. Bandwidth Analysis
Fig. 5. Drain efficiency bandwidth comparison of the 3W-DPA with three different load resistances versus classical and asymmetric 2W-DPA for
at: (a) 9.5-dB IBO, (b) 6-dB IBO, and (c) 0-dB IBO (full power). Strong
gives an additional knob for bandwidth
dependence of the bandwidth on
optimization.
III. ON THE DESIGN OF THREE-WAY DOHERTY
AMPLIFIER FOR MAXIMUM BANDWIDTH
Thus far, the operation mechanism of the 3W-DPA has been
discussed at the center frequency. As the carrier frequency shifts
to the left or right of the design frequency, both the efficiency
and linearity will degrade. In this section, the frequency behavior of the 3W-DPA will be studied. For the purpose of sim-
As described in Section II, there are four circuit elements in
the 3W-DPA architecture to be determined, which include the
three inverter impedances (
through
) and the load resistance
; while the number of boundary conditions to satisfy
the governing equations is three (namely, at
).
Therefore, there will be a degree of freedom, say
, that can
be judiciously selected for optimal performance versus bandwidth. On the other hand, in the two-way topology, given the
current profiles, all the circuit parameters will be uniquely determined.
Simulations based on ideal class B and C modes of operation can provide insights about the bandwidth of the structure. For all cases, the optimum impedance
is assumed
to be 35 . Fig. 5(a)–(c) illustrates the frequency behavior of
the 3W-DPA’s drain efficiency, compared with the 2W-DPAs,
for three different
values and three different input back-off
(IBO) levels (9.5, 6, and 0 dB or full power). Note that for a fair
benchmarking, the efficiency bandwidth of 3W-DPA is compared against asymmetrical 2W-DPA at 9.5-dB IBO and classical 2W-DPA at 6-dB IBO to demonstrate the superior bandwidth of the 3W-DPA at the respective back-off levels. As illustrated in Fig. 5(a), at 9.5-dB IBO, the drain efficiency response
reaches a plateau at
equal to 17 and the efficiency drops
as we deviate from this value. The same optimum point holds
at 6-dB IBO compared to the classical 2W-DPA, as depicted in
Fig. 5(b).
Taking the 4% efficiency drop bandwidth as a reference, we
observe that the fractional bandwidth of the optimal 3W-DPA at
9.5-dB back-off is 40%, while that of the asymmetric 2W-DPA
is only 10% for the same back-off level according to Fig. 5(a).
At 6-dB IBO, the bandwidth of the 3W-DPA is 24%, compared to 17% of the 2W-DPA, as shown in Fig. 5(b). Finally,
at full output power, the fractional bandwidth of the 3W-DPA is
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GOLESTANEH et al.: EXTENDED-BANDWIDTH 3W-DPA
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Fig. 7. Schematic of the 3W-DPA with real transistors illustrating the absorption and cancellation of device output capacitances.
Fig. 8. Complete schematic of the 3W-DPA.
14%, whereas the ideal 2W-DPAs (both classical and asymmetrical configurations) are frequency independent. In real-world
modern transmitters, the PA is driven by modulated signals with
a typical PAPR of larger than 9 dB, therefore it makes sense to
select
based on the first two back-off levels, as they will
have the dominant impact on the average efficiency over the
bandwidth of operation. In Section III-B, an analytical metric
for the optimal design for bandwidth is introduced.
B. 3W-DPA Design for Maximal Bandwidth
The main reason behind the superior bandwidth of the
3W-DPA can be explained by the frequency response of the
multi-section impedance inverters. According to Fig. 2(a),
when the current sources,
and
, are turned off the
impedance seen by the main transistor,
will be a function
of frequency (i.e.,
). In the center frequency, , the
open circuit load of
will remain open at the
plane [see
Fig. 2(c)], thus, no loading effect occurs. At frequencies other
than , the impedance
will behave either inductively
or capacitively; however, the variation of
is reduced
since the variations of
and
are in opposite
directions. In other words, at frequencies above (or below) the
center frequency,
will be capacitive (or inductive),
which will partially nullify the frequency variation of the
inverter, thereby increasing the bandwidth. Consequently, the
variation rate of the inductive and capacitive parts will depend
on the chosen load resistance,
, which justifies the existence
of an optimal
to maximize the bandwidth.
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 9, SEPTEMBER 2013
Fig. 10. Measured continuous wave (CW) peak output power, the associated
gain, and drain efficiency at 6- and 9-dB back-off power versus frequency.
Fig. 9. Photograph of the fabricated broadband 3W-DPA. An external wideband three-way power splitter was used to drive the PA.
Mathematically speaking,
can be expressed as a
function of
, frequency
, and
, referred to as
. The act of providing a fixed impedance for
the main transistor at 9.5-dB back-off determines the 9.5-dB
efficiency bandwidth of the DPA. Therefore, a cost function
should be defined to maximize the efficiency bandwidth versus
. The proper cost function is the standard deviation of the
impedance of the main transistor versus frequency, defined as
(22)
There will be a global minimum for the cost function for a given
bandwidth
and
(which depends on the target output
power). Thus,
can be set to provide the maximum efficiency
over the bandwidth. Fig. 6 illustrates the standard deviation
function defined in (22), calculated over 30% fractional bandwidth versus the load resistance, for different values of
.
Similar analyses can be conducted for the output impedance
seen by each of the two peaking transistors. Nevertheless, we
realized that the standard deviation function is much more
frequency sensitive at 9.5-dB IBO. Hence, the cost function
at 9.5-dB IBO (Fig. 6) was used for the initial design of the
3W-DPA that would be later adjusted during the practical
design.
IV. PRACTICAL DESIGN AND IMPLEMENTATION
THREE-WAY DOHERTY AMPLIFIER
OF A
Based on the theoretical bandwidth analysis presented in
Section II, a 3W-DPA was designed with
and
Fig. 11. Measured CW curves for: (a) drain efficiency and (b) gain versus
output power at various frequency points.
, peak output power of 30 W, and a targeted frequency
band of 0.73–0.98 GHz. To attain this power level, a 10-W and
two 25-W GaN packaged transistors from CREE Inc. were used
for the main, peaking #1, and peaking #2 PAs, respectively.
Larger devices were exploited for the two peaking PAs due to
the larger transconductance required for class C biased transistors to insure proper load modulation. An oversized device was
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GOLESTANEH et al.: EXTENDED-BANDWIDTH 3W-DPA
Fig. 12. Normalized power spectral density (PSD) of the 3W-DPA output
without and after linearization under: (a) clipped 20-MHz WCDMA 1111 signal
at 900 MHz and (b) unclipped 20-MHz WCDMA 1111 signal at 830 MHz.
used for the first peaking PA (25 W instead of 15 W) due to the
device availability limitation. In this section, the strategies to
design each part of the circuit will be described.
A. Output Combining Network
The first step in designing the output network is to determine
the optimal load resistance
. For the 10-W main transistor
used in the current design,
is 35 . As per Fig. 6, the
optimal
for maximizing efficiency over the bandwidth was
found to be 17 . Subsequently, a
line (
in Fig. 8) is
used to match 17 to the standard 50- termination.
In order to compensate for a device’s intrinsic and parasitic
output elements, a number of solutions have been proposed in
the literature. In particular, it has been suggested that the linear
output capacitance of a GaN HEMT can be absorbed using the
-equivalent circuit of a quarter-wave line (also known as a
quasi-lumped transmission line) [1], [3]. Alternatively, an inductance may be used to simply cancel out the capacitance [4].
The latter may result in a narrower bandwidth due to the resultant high- resonance circuit. A wider bandwidth can be obtained using a negative parallel capacitance, provided it is absorbable into an equal or larger external capacitor. For this design, we have used the former (absorption method) for the
3325
Fig. 13. Measured AM/AM and AM/PM of the wideband 3W-DPA under modulated signal at: (a) 900 MHz and (b) 830 MHz.
and
transmission lines to compensate for the output capacitance of the main and the first peaking transistor, and the cancellation method was applied to the second peaking transistor
(Fig. 7). It is of note that the two peaking transistors have equal
output capacitances since they are the same size (25 W); thus,
the positive and negative capacitances will cancel each other out
(circled
and
in Fig. 8). As a result, no external inductance is required in this case.
To control the second harmonic impedance, an explicit shortcircuit
stub was employed for each device (
,
, and
). The characteristic impedance of the stubs were individually optimized to achieve high efficiency across the bandwidth.
Higher order harmonics were found to be insignificant, and thus,
were not considered in the design. It is worth mentioning that
the design did not require explicit matching network due to the
low parasitic effects of the transistor package at the targeted frequency band.
B. Input Matching Networks
We used harmonic source–pull simulation at each frequency
point within the band of interest to determine the required fundamental and second harmonic impedances for each of the transistors. The broadband input matching network (IMN) was then
realized using the simplified real frequency technique to achieve
a bandpass frequency response. The resulting L–C network was
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TABLE II
BENCHMARKS OF WIDEBAND DPAs
then optimized at different power levels to compensate for the
AM/PM response, attributed to the nonlinear input capacitance
of the devices, over the bandwidth. In particular, the main transistor’s IMN was optimized at 9.5-dB IBO, when the other transistors are off. The first peaking IMN elements as well as the
respective input delay line ( in Fig. 8) were tuned at 6-dB
IBO to align the phase responses of the main and peaking #1
paths. Subsequently, the IMN of the second peaking PA together
with the respective input delay line ( in Fig. 8) were tuned at
the peak power to adjust the phase responses of the three paths.
As previously mentioned, the peaking #1 device was oversized.
Since we used an external equi-splitting power divider, a 2-dB
broadband resistive attenuator was added to the input of the first
peaking PA to adjust the transconductance of this stage. Alternatively, one could have designed a broadband three-way divider
with the desired power division ratio to avoid the additional attenuator. Fig. 8 depicts the complete circuit schematic including
microstrip lines and discrete L–C elements.
V. MEASUREMENT RESULTS
The designed 3W-DPA was fabricated and then mounted on a
heat sink. Fig. 9 shows a photograph of the fabricated 3W-DPA.
Note that we used an external wideband power divider with even
power division at the input to obtain a fully analog single-ended
3W-DPA. As a result, no complex mixed signal was required
to drive the PA. This allowed for concurrent amplification of
multi-band multi-carrier signals. The 3W-DPA was then measured under CW and modulated stimuli. It should be noted that
the bias conditions of all the transistors were constant versus
frequency for all of the measurements.
A. CW Stimulus
The peak output power and the associated gain as well as the
drain efficiency (at 6- and 9-dB output back-off) of the 3W-DPA
versus frequency measured under CW stimulus are shown in
Fig. 10. At 9-dB output power back-off, a drain efficiency of
higher than 49% was achieved between 730–980 MHz, and
higher than 51% in the frequency range of 750–980 MHz. Also,
the peak output power varies between 42.7 dB–44.6 dBm across
the bandwidth.
Fig. 11(a) displays the measured drain efficiency as a function
of output power. One can clearly observe the efficiency plateau
in the back-off power range, which confirms proper Doherty operation over the entire frequency band. The peak drain efficiency
was degraded compared to the simulated results, attributed to
the thermal effects arising under CW stimulus. Fig. 11(b) shows
the CW gain of the amplifier at various test frequencies. A more
accurate assessment of the DPA performance was then obtained
under a modulated stimulus during which the temperature variation of the device was much more limited compared to the CW
conditions.
B. Modulated Stimulus
To evaluate the average efficiency as well as the linearizability of the wideband 3W-DPA, two test signals at different
carrier frequencies were applied to the amplifier. The carrier frequencies were selected based on actual wireless standard bands.
The PA was driven by a 20-MHz four-carrier WCDMA signal
at 900 and 830 MHz, separately. While the WCDMA signal at
900 MHz was clipped to a PAPR of 7.14 dB, we applied an unclipped signal at 830 MHz, with a PAPR of 11.7 dB. To linearize
the 3W-DPA, a digital pre-distortion (DPD) platform based on
pruned Volterra series was used [18]. The DPD engine employs
the baseband components of the input and output signals of the
DPA to construct the DPD function. For that, the baseband components of the DPA output signal are captured using a vector
signal analyzer. The input signals with and without pre-distortion are synthesized using the DPD engine, uploaded to the
vector signal generator, and then applied to the DPA.
The output spectra of the 3W-DPA driven by the clipped
20-MHz WCDMA test signal at 900 MHz is depicted in
Fig. 12(a). As can be seen, adjacent leakage power ratio
(ACLR) was improved from 34 to 51.4 dB after applying
the DPD, while an average PAE of 53% and an error vector
magnitude (EVM) of 1.2% was achieved at the average output
power of 35 dBm. Thus, the PA demonstrated excellent efficiency enhancement and linearity at 900 MHz.
Fig. 12(b) shows the output spectra under the unclipped
20-MHz WCDMA signal at 830 MHz, at an average output
power of 32 dBm. The ACLR of the linearized PA improved
to 46.5 dB. The average PAE and EVM were measured to
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GOLESTANEH et al.: EXTENDED-BANDWIDTH 3W-DPA
be 47% and 2.8%, respectively. It can be inferred that the
proposed 3W-DPA would be able to provide high efficiency,
for a wide range of PAPR values, over a broad range of carrier
frequencies.Fig. 13(a) and (b) displays the static AM/AM and
AM/PM responses of the 3W-DPA. A considerable difference
in the AM/AM profiles can be clearly observed when compared
with the CW measurements [see Fig. 11(b)]. Particularly at
high-power levels, the PA’s gain has significantly decreased due
to the thermal effects that occur during the CW measurements.
Table II compares the performance of this 3W-DPA to
state-of-the-art results from the literature. As can be seen,
this work outperforms all the other works in terms of the
9-dB back-off efficiency across the bandwidth and the average
efficiency under high-PAPR modulated signals.
VI. CONCLUSION
In this paper, the theoretical basis for a 3W-DPA architecture
was presented. Design synthesis equations for a given power
and efficiency profile were derived using the load modulation
concept. A comprehensive study of the 3W-DPA’s bandwidth
resulted in a novel design methodology to achieve optimal
efficiency over the bandwidth. Furthermore, practical design
strategies were discussed to apply the presented theory to
packaged GaN transistors. The proposed theory was validated
by designing and fabricating a fully analog 30-W 3W-DPA
demonstrator made to operate between 730–980 MHz. The
fabricated 3W-DPA provided CW drain efficiency of between
49%–64% for output back-off levels of up to 9 dB across
the frequency range. The linearizability of the 3W-DPA was
verified using digitally modulated test signals. Under a clipped
20-MHz WCDMA 1111 signal with a PAPR of 7.14 dB, an
ACLR of 51.4 dB was achieved after DPD, with an average
output power and PAE of 35 dBm and 53%, respectively. Likewise, when driven by a similar, but unclipped WCDMA signal
with 11.7-dB PAPR, the PA obtained an ACPR of 46.5 dB
after DPD, with an average output power and PAE of 32 dBm
and 47%, respectively.
ACKNOWLEDGMENT
The authors would like to thank B. Fehri, University of Waterloo, Waterloo, ON, Canada, for his help in the DPD linearization, and X. Fu, University of Waterloo, for helpful discussions
on DPA design. The authors would also like to acknowledge
the support of Cree Inc., Durham, NC, USA, for providing the
large-signal transistor models and Agilent Technology, Santa
Clara, CA, USA, for donating the Advanced Design System
(ADS) software.
REFERENCES
[1] J. Qureshi, N. Li, W. Neo, F. van Rijs, I. Blednov, and L. de
Vreede, “A wideband 20W LDMOS Doherty power amplifier,” in
IEEE MTT-S Int. Microw. Symp. Dig., Anaheim, CA, USA, May
2010, pp. 1504–1507.
[2] K. Bathich, A. Markos, and G. Boeck, “Frequency response analysis
and bandwidth extension of the Doherty amplifier,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 4, pp. 934–944, Apr. 2011.
3327
[3] D. Y.-T. Wu and S. Boumaiza, “A modified Doherty configuration for
broadband amplification using symmetrical devices,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 10, pp. 3201–3213, Oct. 2012.
[4] D. Kang, D. Kim, Y. Cho, B. Park, J. Kim, and B. Kim, “Design
of bandwidth-enhanced Doherty power amplifiers for handset applications,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 12, pp.
3474–3483, Dec. 2011.
[5] G. Sun and R. Jansen, “Broadband Doherty power amplifier via real
frequency technique,” IEEE Trans. Microw. Theory Techn., vol. 60,
no. 1, pp. 99–111, Jan. 2012.
[6] J. Rubio, J. Fang, V. Camatchia, R. Quaglia, M. Pirola, and G. Ghione,
“3–3.6-GHz wideband GaN Doherty power amplifier exploiting output
compensation stages,” IEEE Trans. Microw. Theory Techn., vol. 60, no.
8, pp. 2543–2548, Aug. 2012.
[7] K. Bathich, A. Markos, and G. Boeck, “A wideband GaN Doherty amplifier with 35% fractional bandwidth,” in Eur. Microw. Conf., Sep.
2010, pp. 1006–1009.
[8] K. Bathich and G. Boeck, “Wideband harmonically-tuned GaN Doherty power amplifier,” in IEEE MTT-S Int. Microw. Symp. Dig., Montreal, QC, Canada, Jun. 2012, pp. 1–3.
[9] M. Iwamoto, A. Williams, P.-F. Chen, A. Metzger, L. Larson, and P.
Asbeck, “An extended Doherty amplifier with high efficiency over a
wide power range,” IEEE Trans. Microw. Theory Techn., vol. 49, no.
12, pp. 2472–2479, Dec. 2001.
[10] Y. Yang, J. Cha, B. Shin, and B. Kim, “A fully matched -way Doherty amplifier with optimized linearity,” IEEE Trans. Microw. Theory
Techn., vol. 51, no. 3, pp. 986–993, Mar. 2003.
[11] W. Neo, J. Qureshi, M. Pelk, J. Gajadharsing, and L. d. Vreede, “A
mixed-signal approach towards linear and efficient N-way Doherty
amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 55, no. 5, pp.
866–879, May 2007.
[12] I. Kim, J. Moon, S. Jee, and B. Kim, “Optimized design of
a highly efficient three-stage Doherty PA using gate adaptation,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 10, pp.
2562–2574, Oct. 2010.
[13] N. Srirattana, A. Raghavan, D. Heo, P. Allen, and J. Laskar, “Analysis
and design of a high-efficiency multistage Doherty power amplifier for
wireless communications,” IEEE Trans. Microw. Theory Techn., vol.
53, no. 3, pp. 852–860, Mar. 2005.
[14] R. Gajadharsing, W. C. E. Neo, M. J. Pelk, L. C. N. d. Vreede, and J.
Zhao, “3-way Doherty amplifier with minimum output network,” U.S.
Patent 8 022 760, Jul. 2, 2009.
[15] D. Gustafsson, C. Andersson, and C. Fager, “A modified Doherty
power amplifier with extended bandwidth and reconfigurable efficiency,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 1, pp.
533–542, Jan. 2013.
[16] D. Wu and S. Boumaiza, “A mixed-technology asymmetrically biased
extended and reconfigurable Doherty amplifier with improved power
utilization factor,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 5,
pp. 1946–1956, May 2013.
[17] S. C. Cripps, Advanced Techniques in RF Power Amplifier Design.
Norwood, MA, USA: Artech House, 2002.
[18] F. Mkadem, S. Boumaiza, J. Staudinger, and J. Wood, “Systematic
pruning of Volterra series using Wiener G-functionals for power amplifier and predistorter modeling,” in Eur. Microw. Integr. Circuits Conf.,
Oct. 2011, pp. 482–485.
Hamed Golestaneh (S’10) received the B.Sc. and
M.Sc. degrees in electrical engineering from Amirkabir University of Technology, Tehran, Iran, in 2008
and 2011, respectively, and is currently working toward the Ph.D. degree at the University of Waterloo,
Waterloo, ON, Canada.
His current research interests include wideband
RF power amplifiers, efficiency-enhancement techniques for base-station applications, and nonlinear
transistor modeling. He was the recipient of the
Second Place Award of the Student Design Competition on Microwave Transistor Modeling, IEEE Microwave Theory and
Techniques Society (IEEE MTT-S) International Microwave Symposium
(IMS), 2012.
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 61, NO. 9, SEPTEMBER 2013
Foad Arfaei Malekzadeh (S’08–M’12) was born
in Tehran, Iran, in 1979. He received the M.Sc.
degree in high-frequency electronics from Tehran
Polytechnic University, Tehran, Iran, in 2003, and
the Ph.D. degree in mixed signal microelectronics
from the Eindhoven University of Technology,
Eindhoven, The Netherlands, in 2012. His thesis was
entitled “Analog Dithering Techniques for Wireless
Transmitters.”
In 2012, he joined the Emerging Radio Systems
Group, University of Waterloo, Waterloo, ON,
Canada, as a Postdoctoral Fellow, where he was involved with load modulating
PA topologies. He is currently with the Microsemi Corporation, Ottawa, ON,
Canada, as a Senior Analog Integrated Circuit Designer, where he is involved
in research on and development of fifth-generation (5G) RF transceivers. He
has been involved in several industrial projects including cellular base-station
transceiver design, RF identification (RFID) systems, and antenna design,
as a Senior RF Engineer, prior to beginning his doctoral studies. His current
research interests include switch-mode/linear PAs, waveform engineered PAs,
sigma–delta modulators, dithering techniques, linearization techniques, and
behavioral modeling of nonlinear communication systems.
Slim Boumaiza (S’00–M’04–SM’07) received
the B.Eng. degree in electrical engineering from
the École Nationale d’Ingénieurs de Tunis, Tunis,
Tunisia, in 1997, and the M.S. and Ph.D. degrees
from the École Polytechnique de Montréal, Montréal, QC, Canada, in 1999 and 2004, respectively.
He is currently an Associate Professor with
the Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON,
Canada, where he leads the Emerging Radio System
Research Group that conducts multidisciplinary
research activities in the general areas of design of RF/microwave and millimeter components and systems for wireless communications. His specific
current research interests include RF/digital signal processing (DSP) mixed
design of intelligent RF transmitters; design, characterization, modeling and
linearization of high-efficiency RF power amplifiers; and reconfigurable and
software-defined transceivers.
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