The problem to solve is this: when designing a linear amplifier for a particular OIP3, what is the
optimum output stage periphery and scaling factor to minimise the DC power consumption?
Consider an infinite cascade of amplifier stages with equal gain per stage, g. The gate width of each
transistor is scaled from the preceding stage by a uniform scaling factor, s. All stages are biased in
class A with the same drain voltage and the same current density such that the drain currents are
also scaled by s.
Let’s assume the OIP3 for each transistor is 10 dB above PCripps, where
𝑃𝐶𝑟𝑖𝑝𝑝𝑠 =
𝑜𝑖𝑝3 =
𝐼𝑑𝑞
(𝑉 − 𝑉𝑘𝑛𝑒𝑒 )
2 𝑑𝑑
10 × 𝐼𝑑𝑞
(𝑉𝑑𝑑 − 𝑉𝑘𝑛𝑒𝑒 )
2
It is usual to assume that intermodulation adds constructively in an amplifier cascade such that
1
1
1
1
=
+
+
+⋯
𝑜𝑖𝑝3𝑡𝑜𝑡𝑎𝑙 𝑜𝑖𝑝3𝑛 𝑔𝑛 × 𝑜𝑖𝑝3𝑛−1 𝑔𝑛 × 𝑔𝑛−1 × 𝑜𝑖𝑝3𝑛−2
In our amplifier cascade the individual stage intercept points are related according to the gate width
(drain current) scaling factor:
𝑜𝑖𝑝3𝑛 = 𝑠 × 𝑜𝑖𝑝3𝑛−1
And we assume that all stages, regardless of gate periphery, have the same small-signal gain:
𝑔𝑛 = 𝑔𝑛−1 = 𝑔
The cascaded oip3 can then be restated as
∞
1
1
𝑠 𝑠2
1
𝑠 𝑖
=
∑( )
(1 + + 2 + ⋯ ) =
𝑜𝑖𝑝3𝑡𝑜𝑡𝑎𝑙 𝑜𝑖𝑝3𝑛
𝑔 𝑔
𝑜𝑖𝑝3𝑛
𝑔
𝑖=0
𝑠
For an infinite cascade this is a geometric series which converges provided |𝑔| < 1 (i.e. provided the
gain per stage exceeds the scaling factor). The oip3 of the infinite cascade can therefore be
simplified to
1
1
=
𝑜𝑖𝑝3𝑡𝑜𝑡𝑎𝑙 𝑜𝑖𝑝3 (1 − 𝑠 )
𝑛
𝑔
𝑠
𝑜𝑖𝑝3𝑡𝑜𝑡𝑎𝑙 = 𝑜𝑖𝑝3𝑛 (1 − )
𝑔
The total DC power consumption is given by another series
∞
𝑃𝐷𝐶_𝑡𝑜𝑡𝑎𝑙
1 1
1 𝑖
= 𝑉𝑑𝑑 𝐼𝑑𝑞𝑛 (1 + + 2 + ⋯ ) = 𝑉𝑑𝑑 𝐼𝑑𝑞𝑛 ∑ ( )
𝑠 𝑠
𝑠
𝑖=0
For an infinite cascade the total DC power consumption is
𝑃𝑑𝑐 =
𝑉𝑑𝑑 𝐼𝑑𝑞𝑛
1
1−𝑠
We want to maximise the ratio of oip3Total to Pdc
𝑠
1
𝑜𝑖𝑝3 𝑇𝑜𝑡𝑎𝑙 𝑜𝑖𝑝3𝑛 (1 − 𝑔) (1 − 𝑠 )
=
𝑃𝑑𝑐
𝑉𝑑𝑑 𝐼𝑑𝑞𝑛
𝑜𝑖𝑝3 𝑇𝑜𝑡𝑎𝑙
𝑜𝑖𝑝3𝑛
𝑠 1 1
=
(1 − − + )
𝑃𝑑𝑐
𝑉𝑑𝑑 𝐼𝑑𝑞𝑛
𝑔 𝑠 𝑔
0.600
0.500
3dB
4dB
5dB
6dB
8dB
10dB
12dB
oip3total/PDC
0.400
0.300
0.200
0.100
0.000
1
2
3
Scaling Factor
4
Take the derivative with respect to scaling factor, s
𝑑 𝑜𝑖𝑝3 𝑇𝑜𝑡𝑎𝑙
𝑜𝑖𝑝3𝑛 1 1
(
)=
( − )
𝑑𝑠
𝑃𝑑𝑐
𝑉𝑑𝑑 𝐼𝑑𝑞𝑛 𝑠 2 𝑔
The ratio of oip3Total to Pdc is maximised when
1 1
− =0
𝑠2 𝑔
So to maximise the overall efficiency we must set
𝑠 = √𝑔
5
5
Scaling Factor
4
3
2
1
0
2
4
6
8
Gain per stage (dB)
10
12
14
and the final stage must be sized to achieve the required oip3:
𝑜𝑖𝑝3𝑛 =
𝐼𝑑𝑞𝑛 =
𝑜𝑖𝑝3𝑡𝑜𝑡𝑎𝑙
𝑜𝑖𝑝3𝑡𝑜𝑡𝑎𝑙
=
𝑠
1
(1 − 𝑔)
(1 −
)
√𝑔
2 × 𝑜𝑖𝑝3𝑡𝑜𝑡𝑎𝑙
10(𝑉𝑑𝑑 − 𝑉𝑘𝑛𝑒𝑒 ) (1 −
1
)
√𝑔
In practice, these calculations provide lower bounds on scaling factor and FET periphery. The final
stage may be optimised for linearity alone. However, the matching of preceding stages is usually
compromised to achieve gain flatness, bandwidth etc. They will therefore require additional margin.