Addressing PPA and TO Schedule Challenges with Design Compiler Graphical Thy Phan Renesas Design Vietnam August 23rd, 2017 SNUG Singapore SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 1 Agenda About Renesas & Renesas Design Vietnam (RVC) Tapeout Objectives & Our Challenges Our Targets, Problem & Focus Points Result of Our Study Summary SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 2 About Renesas & Renesas Design Vietnam (RVC) SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 3 About Renesas Global (“Renaissance Semiconductor for Advanced Solutions”) HQ operation Tokyo, Japan 23 Japan: 4 US, Europe, Asia: HC 18,884 (31 Dec 2016) (# company) OA/ICT INDUSTRIAL/HE AUTOMOTIVE Platform Value Ecosystem Software Application Ecosystem Integrated cockpit collaboration Car navigation + ADAS Industrial Ethernet Industry-standard platform Platform for network and surveillance camera Kit Value Kit device System know-how Device Value New solution for e-Mobility MCU + power device kit solution for two wheel vehicles in emerging countries Driving Steering MCU + power kit solution for motor control Kit solution for smart meter, measurement/communication Kit solution for office, communication/security Breaking Performance function Automotive General-purpose MCU Power semiconductors analog & power devices for embedded systems for industrial Network memory MCU for OA/camera (Note) HE: Home Electronics, OA: Office Automation, ICT: Information Communication Technology SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 4 About Renesas Design Vietnam (RVC) Office Ho Chi Minh City, Vietnam Started 05 Oct 2004 HC 749 (30 Apr 2017) Renesas Design Vietnam Hardware Design Software Design RTL Design Device Driver Verification Middleware Synthesis, DFT Application Software P&R, Chip Integration Dev. Tools (IDE) Hardware + Software Total Solution! Software Hardware Automotive SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. Industrial/HE OA/ICT 5 Tapeout Objectives & Our Challenges SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 6 Tapout Objectives & Our Challenges Quality (Performance, Power), Cost (Smallest Area), Delivery (Schedule) SNUG 2017 Achieve high frequency, Extreme Low Power SoC Advance timing optimization Enabling technologies & techniques Multi voltages libraries & advance power optimization Fit in smallest chip size, Max MFU ratio Advance area optimization Best modules arrangement in Design Planning Fabricate in advance technology node Shortest TAT, Meet aggressive time to market Fast feedback & optimization in Design Planning High throughput to handle large number of modes and corners, large design size Accurate modeling & signoff correlation © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 7 Our Targets, Problem and Focus Points SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 8 Targets and Problems Start Start Floorplan Floorplan DCG (*) CTS Netlist quality improvement Placement Targets of using DCG: - Maximum frequency optimization & good correlation w/ P&R tool (with floorplan and TLU+) - Maximum leakage optimization (by MCMM setting, control LowVth cell usage) - Area optimization to reduce module size - Early congestion improvement Our problems for DCG: Placement CTS Route Route End End Old flow without DCG Flow with simple DCG Gate-to-gate DCG output is not stable: good for some blocks but not good for others although same flow Can not reuse placement information from DCG: Need to run initial placement again on ICC2 Cost TAT Old DCG flow doesn’t care congestion improvement and area optimization Flow is hard to control: contain many hidden settings Motivation to work w/ Synopsys to build up better DCG flow (*) DCG: Design Compiler Graphical SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 9 Focus Points & Key of Success Focus points: Inputs Compile_ultra –spg –inc (Compile_ultra –spg –inc) Output Old DCG flow (baseline flow) SNUG 2017 Flow improvement Compile_ultra –spg Inputs Compile_ultra –spg (Zroute off) Compile_ultra –spg –inc (Zroute on) Optimize_nestlist -area Output Updated DCG flow Build up the common flow: effective for all blocks Clean up the settings: especially for hidden ones Good flow for PPA (Performance/Power/Area) & congestion optimization Key of success: Turn off congestion optimization w/ Zroute at first, focus to timing / power optimization After achieve timing/power, enable congestion optimization w/ Zroute and do incremental optimize Can repeat “compile_ultra –incr” in many loops to achieve well optimized result (in case of high PPA designs like ARM® Cortex® CPU) Run “optimize_netlist –area” at final step for area optimization w/o side effect to timing/leakage/congestion © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 10 DCG Flow Proposal: Control Settings Next settings are important to get good PPA & routing congestion result (1) Zroute, (2) group_path (user/auto), & (3) don’t_use (2) group_pathx (3) don’t_use settings (1) Zroute settings Inputs Compile_ultra –spg (Zroute off) Compile_ultra –spg –inc (Zroute on) Optimize_nestlist -area Output Zroute off: set_app_var placer_enable_enhanced_router false set_app_var placer_congestion_effort medium set_app_var spg_congestion_placement_in_incremental_compile true set placer_zrt_deterministic_mode false ;# multi-CPU enable Create USER group path create_auto_path_groups -mode mapped Compile_ultra –spg remove_auto_path_groups Control dont_use/target_library for leakage optimize Increase weight for critical timing USER group path create_auto_path_groups -mode mapped Zroute on: set_app_var placer_enable_enhanced_router true set_app_var placer_congestion_effort medium set_app_var spg_congestion_placement_in_incremental_compile true set placer_zrt_deterministic_mode false ;# multi-CPU enable Compile_ultra –spg –inc remove_auto_path_groups SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 11 Result of Our Study Spec of trial design - Blocks: ARM® Cortex®-A53 (Quad-cores) - Frequency: 1GHz & 1.4GHz - Process: 28 nm process - Compare Result just after DCG b/w old (baseline) & updated DCG flow SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 12 ARM® Cortex®-A53 CPU QoR Run1 BASELINE FLOW Run 2 – UPDATED FLOW Timing comparison Improvement 0 -0.0889 Baseline flow -0.065 Updated flow -20 WNS (ns) -0.0889 -0.065 +26.9% (better) TNS (ns) -185.009 -17.344 +90.6% (better) -60 %LVT 33.71% 31.32% +2.39% (better) -80 NVP 10925 2985 +72.67%(better) -100 -17.34 -40 -120 Congestion 0.66% 0.68% -0.02% (marginally worst) (GRC overflow) -140 -160 -180 -185.01 -200 WNS (ns) TNS (ns) Significant timing and %LVT QoR improvement Marginally area and congestion degradation that could be recovered during placement SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 13 ARM® Cortex®-A53 TOP Run1 – BASELINE FLOW QoR Run 2 – Improvement UPDATED FLOW Timing comparison 0 Baseline flow Scenario: USR WNS (ns) -0.079 -0.039 +50.6% TNS (ns) -245.16 -52.496 +78.6% Scenario: AC_SCAN WNS (ns) -0.079 -0.067 +15.2% TNS (ns) -238.76 -52.357 +78.1% %LVT 0.96% 0.48% +0.48% runtime 22.45 22.03 +1.87% Congestion (GRC overflow) 704 (0.00%) 691 (0.00%) +1.85% Updated flow -50 ACSCAN -100 USR -150 -200 -250 WNS (ns) TNS (ns) WNS (ns) TNS (ns) QoR improvement observed across the board Significant timing and %LVT QoR improvement SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 14 ARM® Cortex®-A53 TOP Initial Timing Quality @ICC2 (w/ & w/o DCG) --------------------------------------------------------------------------Original netlist Context WNS TNS NVE --------------------------------------------------------------------------Scenario1(Setup) -0.2057 -155.6834 1464 Scenario2(Setup) -0.2017 -170.0126 1490 Scenario3(Setup) -6.2325 -657.1930 3126 Scenario4(Setup) -4.6724 -626.9873 3127 Scenario5(Setup) 8.4727 0.0000 0 Scenario6(Setup) 8.4725 0.0000 0 Scenario7(Setup) -936.4851 -40135051.4866 53018 Scenario8(Setup) -975.0467 -40249773.9139 53018 Scenario9(Setup) -6.2325 -498.1713 3026 Scenario10(Setup) -4.6724 -477.4726 3027 Design (Setup) -975.0467 -40688039.6655 57637 --------------------------------------------------------------------------Applying DC-G Context WNS TNS NVE --------------------------------------------------------------------------Scenario1(Setup) 0.0640 0.0000 0 Scenario2(Setup) 0.0711 0.0000 0 Scenario3(Setup) -0.1408 -0.3998 48 Scenario4(Setup) -0.1411 -0.3093 30 Scenario5(Setup) 10.2629 0.0000 0 Scenario6(Setup) 10.2367 0.0000 0 Scenario7(Setup) 1.7176 0.0000 0 Scenario8(Setup) 1.7077 0.0000 0 Scenario9(Setup) -0.1393 -0.7546 70 Scenario10(Setup) -0.1399 -0.5766 50 Design (Setup) -0.1411 -0.7858 73 SNUG 2017 Initial timing at Placement phase is much better © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 15 Summary SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 16 Summary During the time we study DCG, we concluded below points: - DCG will give much better result about PPA of inputs Design flow is simple, no next extra setting and/or hidden setting to get good result Can apply common flow for almost blocks To have better PPA, some optimization loops may need Suggested flow can give improvement of route ability DCG should be set as default step for PnR. Should use the new technique (congestion/area optimize) for much better PPA. SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 17 Thank You SNUG 2017 © 2017 Renesas Design Vietnam Co., Ltd. All rights reserved. 18