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VHSIC: Very High Speed Integrated
Circuit
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library IEEE;
use IEEE.std_logic_1164.all;
ENTITY full_adder IS
PORT (a,b,cin: in bit;
s,cout:out bit);
END full_adder;
Architecture dataflow of full_adder is
begin
s <= a xor b xor cin;
cout <= (a and b) or (a and cin)
or (b and cin);
end dataflow;
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Behavioural : hành vi
Dataflow: dòng dữ liệu
Structural: cấu trúc
=> System or block levels
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VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS
VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS
Architecture => dataflow => Using expression operators
[
Syntax:
signal <= expression operators
Declaration:
SIGNAL name: mode type [:=initial_value]
What’s
signal
and <=?
]
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VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS
VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS
Architecture => dataflow => Using expression condition
Syntax:
Signal <= assignment 1 WHEN condition ELSE
assignment 2 WHEN condition ELSE
assignment 3 WHEN condition ELSE
…..;
EX
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VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS
Architecture => dataflow => Using expression condition
Syntax:
WITH identifier SELECT
Signal <= assignment 1 WHEN condition 1,
assignment 2 WHEN condition 2,
…..
assignment n WHEN OTHERS;
EX
VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS
Architecture => dataflow => Using expression condition
EX: WHEN / ELSE
WITH/ SELECT/ WHEN
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VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS
Architecture => dataflow => Using expression condition
VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS
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VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS
VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS
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SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Sequential statements;
SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral
ENTITY nogates IS
PORT(A, B, C: in bit;
D: buffer bit;
E: out bit);
END nogates;
ARCHITECTURE behave OF nogates IS
BEGIN
PROCESS(A, B, C)
BEGIN
D <= A or B AFTER 5 ns; -- statement 1
E <= C or D AFTER 5 ns; -- statement 2
END PROCESS;
END behave;
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SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral
SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => IF STATEMENT
The basic if statement has the form
The most general form of the if statement is
if condition then sequential statements1
if condition then sequential statements
else sequential statements2
{elsif condition then sequential statements}
end if;
-- 0 or more elsif clauses may be included
[else sequential statements]
end if;
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SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => IF STATEMENT
The basic if statement has the form
if condition then
sequential statements1
else sequential statements2
process(CLK)
begin
if CLK'event and CLK = '1' -- rising edge of CLK
then Q <= D;
end if;
end process;
end if;
SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => IF STATEMENT
The basic if statement has the form
if condition then
sequential statements1
else sequential statements2
end if;
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SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => IF and else if (ELSIF) STATEMENT
P4: Write VHDL code.
SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => IF and else if (ELSIF) STATEMENT
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SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => IF and else if (ELSIF) STATEMENT
SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => IF and else if (ELSIF) STATEMENT
Example: FIGURE 2-20: J-K Flip-Flop
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SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral =>
IF and else if (ELSIF) STATEMENT
EX: Write VHDL code for the following
Counters.
0 to 9
SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => Using Wait Statements
process
begin
sequential-statements
wait-statement
sequential-statements
wait-statement
...
end process;
Wait statements can be of three
different forms:
wait on sensitivity-list;
wait for time-expression;
wait until Boolean-expression;
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SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => Using Wait Statements
SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => Using CASE statements
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SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => Using CASE statements
SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => Using FSM (Finite State Machine)
The combinational (upper) section has
two inputs, being one pr_state
(present state) and the other the
external input proper. It has also two
outputs, nx_state (next
state) and the external output proper.
The sequential (lower) section has
three inputs (clock, reset, and
nx_state), and one output (pr_state).
Since all flip-flops are in this part of the
system, clock and reset must be
connected to it.
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SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => Using FSM (Finite State Machine)
FSM - MOORE
SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => Using FSM (Finite State Machine)
FSM - MEALY
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SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => Using FSM (Finite State Machine)
SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => Using FSM (Finite State Machine)
d
a
b
clk
rst
FSM
MOORE
x
w
clk
reset
FSM
MEALY
z
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SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => Using FSM (Finite State Machine)
Enumerated data type
TYPE name IS (data_type);
TYPE bit IS ('0', '1');
TYPE bit_vector IS ARRAY (NATURAL RANGE <>) OF BIT;
TYPE fourval IS ( ‘X’, ‘0’, ‘1’, ‘Z’ );
TYPE state IS (idle, forward, backward, stop);
TYPE color IS ( red, yellow, blue, green, orange );
SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => Using FSM (Finite State Machine)
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SEQUENTIAL STATEMENTS AND VHDL PROCESSES
Architecture => Behavioral => Using FSM (Finite State Machine)
For Moore FSM
Output <= <value>;
For Mealy FSM
For Moore FSM
Output <= <value>;
For Mealy FSM
Q&A
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