Uploaded by S M ABIR HOSSAIN

460-final-1

advertisement
10/18/21, 12:32 AM
Exam Slot (5.00PM - 7:00PM) (Summer 2021) | CSE460 Final Exam (Summer 2021) | CSE460 Courseware | buX | BRAC …
Course  CSE460 …  CSE460 …  Exam Sl…



Exam Slot (5.00PM - 7:00PM) (Summer 2021)
BRAC UNIVERSITY STUDENT HONOR CODE
On this exam, I will not cheat, use unfair means, join intentionally or unintentionally any
online or offline group in which exam answers are posted or discussed, or engage in any
behavior that would commonly be deemed to be academically unethical. I will immediately
notify the course teacher of any such activity or online or offline groups that I become
aware of. I acknowledge that I may be suspended or expelled from Brac University if I am
found to have engaged in any academically unethical behavior.
I understand that a certain percentage of students will be randomly selected for a viva after
the exam and asked about their exam answers and related information and that if called for
a viva, that I must appear for the viva within a designated time frame. I understand and
accept that the viva may be scheduled at any point in time after I submit my answers
online. I may be contacted at the email address listed below for a viva. I understand that a
failure to appear for the viva after being notified at the email address below will be
considered as evidence of cheating. An inability to explain my exam answers during the viva
may also be considered as evidence of cheating.
I consent to video/audio recording of these viva sessions. I further recognize that noncompliance with the above may lead to further disciplinary actions that I will be ready to
accept without complaint.
https://bux.bracu.ac.bd/courses/course-v1:buX+CSE460+2021_Summer/courseware/df674706283d4ae7ac1aaa45677ae657/468a7b5be3474686…
1/9
10/18/21, 12:32 AM
Exam Slot (5.00PM - 7:00PM) (Summer 2021) | CSE460 Final Exam (Summer 2021) | CSE460 Courseware | buX | BRAC …
CSE460 Final Exam Summer 2021
Full Marks: 30
Time: 1 hour 30 minutes (exam) + 15 minutes (PDF preparation & submission)
Answer any 3 from: Problems 1 - 4. Each problem is worth 10 points.
Problem 5 is for bonus credits.
Numerical answers will be graded in buX, but the complete solution to every problem (including the
numerical problems) should be provided in the PDF.
You need to fill up each boxes before you can submit your answer.
Problem 1
5.0/10.0 points (graded)
Important: Detailed written solution to all the problems should be provided in the PDF.
Problem 1. Layout of a certain CMOS gate is given below. The gate inputs are: A, B& the
output is: Y . The legend of the materials used is given in the lower right corner of the
layout.
https://bux.bracu.ac.bd/courses/course-v1:buX+CSE460+2021_Summer/courseware/df674706283d4ae7ac1aaa45677ae657/468a7b5be3474686…
2/9
10/18/21, 12:32 AM
Exam Slot (5.00PM - 7:00PM) (Summer 2021) | CSE460 Final Exam (Summer 2021) | CSE460 Courseware | buX | BRAC …
(a) Sketch the equivalent CMOS circuit of the gate layout. [2]
(b) What should be the minimum value of Distance 1in units of λ? Why? [3]
Suppose the output node Y has been connected to ground and the inputs are at
A = 0 V , B = 4.8 VThe
.
supply voltage is 4.8 V and the pMOS parameters are
2
W p = 14 λ, L p = 2 λ, μ Cox = 90 μA/V , Vtp = −0.96
. V
p
(c) Determine the current flowing through the pMOS transistor which is connected to the
input A. [2.5]
Give your answer to at least three significance digits.
0.00464
Amperes

0.00464
(d) Determine the current flowing through the pMOS transistor which is connected to the
input B. [2.5]
Give your answer to at least three significance digits.
4.800
Amperes

4.800
Submit
You have used 5 of 5 attempts
Problem 2
10.0/10.0 points (graded)
Important: Detailed written solution to all the problems should be provided in the PDF.
(a) What is a DC transfer curve? How can a DC transfer curve be used to determine the
values of VI L & VOH ? [3]
(b) In the following pass transistor network, the following nodes: A, B, C , D, E, F , Vout
are initially discharged. Assume VDD = 9 V , Gnd = 0 V , Vtn = 2.7 V , Vtp = −3.6. An
V
input Vin = 1.1 V is injected into the network.
https://bux.bracu.ac.bd/courses/course-v1:buX+CSE460+2021_Summer/courseware/df674706283d4ae7ac1aaa45677ae657/468a7b5be3474686…
3/9
10/18/21, 12:32 AM
Exam Slot (5.00PM - 7:00PM) (Summer 2021) | CSE460 Final Exam (Summer 2021) | CSE460 Courseware | buX | BRAC …
(A) What is the voltage at node A? [1]
Give your answer to at least three significance digits.
1.1
Volts

Volts

Volts

Volts

1.1
(B) What is the voltage at node B? [1]
Give your answer to at least three significance digits.
7.2
7.2
(C) What is the voltage at node C? [1]
Give your answer to at least three significance digits.
1.1
1.1
(D) What is the voltage at node D? [1]
Give your answer to at least three significance digits.
9
9
https://bux.bracu.ac.bd/courses/course-v1:buX+CSE460+2021_Summer/courseware/df674706283d4ae7ac1aaa45677ae657/468a7b5be3474686…
4/9
10/18/21, 12:32 AM
Exam Slot (5.00PM - 7:00PM) (Summer 2021) | CSE460 Final Exam (Summer 2021) | CSE460 Courseware | buX | BRAC …
(E) What is the voltage at node E? [1]
Give your answer to at least three significance digits.
0
Volts

Volts

Volts

0
(F) What is the voltage at node F ? [1]
Give your answer to at least three significance digits.
9
9
(G) What is the voltage at node Vout ? [1]
Give your answer to at least three significance digits.
6.3
6.3
Submit
You have used 1 of 5 attempts
Problem 3
0.0/10.0 points (graded)
Important: Detailed written solution to all the problems should be provided in the PDF.
Consider the following digital system where a 2-input N ORgate is driving h copies of
identical 2-input N AN Dgates.
https://bux.bracu.ac.bd/courses/course-v1:buX+CSE460+2021_Summer/courseware/df674706283d4ae7ac1aaa45677ae657/468a7b5be3474686…
5/9
10/18/21, 12:32 AM
Exam Slot (5.00PM - 7:00PM) (Summer 2021) | CSE460 Final Exam (Summer 2021) | CSE460 Courseware | buX | BRAC …
(a) Draw the equivalent RC circuit if the individual N ORand N AN Dgates have transistor
widths chosen to achieve effective rise and fall resistances equal to that of an unit inverter
(R). Assume shared diffusion nodes for series transistors. [5]
(b) Derive the analytical expression of tpdf in terms of h, R, C. What is the value of tpdf if
h = 32and a unit transistor has R = 55 kΩand C = 67 nFin a 60 nmprocess? [3]
Give your answer to at least three significant digits.
seconds
(c) Derive the analytical expression of tcdf in terms of h, R, C. What is the value of tcdf if
h = 32and a unit transistor has R = 55 kΩand C = 67 nFin a 60 nmprocess? [2]
Give your answer to at least three significant digits.
seconds
Submit
You have used 0 of 5 attempts
Problem 4
https://bux.bracu.ac.bd/courses/course-v1:buX+CSE460+2021_Summer/courseware/df674706283d4ae7ac1aaa45677ae657/468a7b5be3474686…
6/9
10/18/21, 12:32 AM
Exam Slot (5.00PM - 7:00PM) (Summer 2021) | CSE460 Final Exam (Summer 2021) | CSE460 Courseware | buX | BRAC …
0 points possible (ungraded)
Important: Detailed written solution to all the problems should be provided in the PDF.
A gate level schematic is given below:
(a) Transform the gate level schematic into a graph. Write down the nodes and cut edges
of the graph. [2]
(b) Using K ernighan − Lin
algorithm, derive the optimally partitioned graph. Assume each
edge has a unit weight. [Hint: Perform all the swaps of the algorithm, calculate the costs and
gain of each swap. Compute the maximum positive gain.] [6]
(c) What is the time complexity of the above algorithm? [2]
Submit
You have used 0 of 5 attempts
Problem 5 (Bonus)
0 points possible (ungraded)
Problem 5. For the following circuit layout assume that A = 4.91 V, B
C = 4.92 V. Threshold voltages are given as: Vtn = 0.5V, Vtp = −1V.
= 2.89 V
and
https://bux.bracu.ac.bd/courses/course-v1:buX+CSE460+2021_Summer/courseware/df674706283d4ae7ac1aaa45677ae657/468a7b5be3474686…
7/9
10/18/21, 12:32 AM
Exam Slot (5.00PM - 7:00PM) (Summer 2021) | CSE460 Final Exam (Summer 2021) | CSE460 Courseware | buX | BRAC …
(a) Draw the schematic diagram of the circuit corresponding to the layout above and
clearly mark the length and width of each of the transistors. [2]
(b) Draw the cross-section of the layout along the X − X ′line with proper labelling of the
materials. [3]
Submit
You have used 0 of 5 attempts
Submission Link
0 points possible (ungraded)
Final Exam answerscript submission link:
https://docs.google.com/forms/d/e/1FAIpQLScdbJbx6oRpooZczjOCFjUVxtYkMsU2HlSq7KH1_dffW39oA/viewform?usp=sf_link
Have you submitted the assignment PDF through google
form?
Yes
No
https://bux.bracu.ac.bd/courses/course-v1:buX+CSE460+2021_Summer/courseware/df674706283d4ae7ac1aaa45677ae657/468a7b5be3474686…
8/9
10/18/21, 12:32 AM
Exam Slot (5.00PM - 7:00PM) (Summer 2021) | CSE460 Final Exam (Summer 2021) | CSE460 Courseware | buX | BRAC …
Submit
 Previous
Next 
© All Rights Reserved
About Us
BracU Home
USIS
Course Catalog
Copyright - 2020
https://bux.bracu.ac.bd/courses/course-v1:buX+CSE460+2021_Summer/courseware/df674706283d4ae7ac1aaa45677ae657/468a7b5be3474686…
9/9
Download