Marvell. Moving Forward Faster
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11-Port GE AVB/TSN Switch with
8 integrated PHYs and 2 SERDES
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88E6390/88E6190/88E6290
Datasheet
Doc. No. MV-S110663-00, Rev. A
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
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MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
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Cover
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88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
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Document Conventions
Note: Provides related information or information of special importance.
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Technical Publication: 1.10
For more information, visit our website at: www.marvell.com
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No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose,
without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any
kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any
particular purpose.
Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document. Marvell products are not
designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use Marvell products in these
types of equipment or applications.
With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees:
1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control
Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2;
2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are
controlled for national security reasons by the EAR; and,
3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant,
not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons
by the EAR, or is subject to controls under the U.S. Munitions List ("USML").
At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any
such information.
Copyright © 1999–2018. Marvell International Ltd. All rights reserved. Alaska, ARMADA, Avanta, Avastar, CarrierSpan, FLC, HyperDuo, Kirkwood, Link Street, LinkCrypt,
Marvell logo, Marvell, Marvell EZ-Connect, Marvell Smart, Marvell VSoC, MoChi, Moving Forward Faster, PISC, Prestera, Virtual Cable Tester, The World as YOU See It,
Xelerated, and Yukon are registered trademarks of Marvell or its affiliates. ArmadaBoard, Marvell COFFEEbin, Marvell ESPRESSObin, Marvell MACCHIATObin, and
NANDEdge are trademarks of Marvell or its affiliates.
Patent(s) Pending—Products identified in this document may be covered by one or more Marvell patents and/or patent applications.
Doc. No. MV-S110663-00 Rev. A
Page 2
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Copyright © 2018 Marvell
January 23, 2018
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Document Status
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Warning: Indicates a risk of personal injury.
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MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Caution: Indicates potential damage to hardware or software, or loss of data.
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Preface
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Preface
About this Document
Link Street® 88E6390X/88E6390/88E6290/88E6190X/88E6190/88E6190R Switch
Functional Specification
Provides a functional description of the device core.

Link Street® 88E6390X/88E6390/88E6290/88E6190X/88E6190/88E6190R PHY and
SERDES Functional Specification
Provides a functional description of the PHY and SERDES.
Link Street® Integrated Micro Processor (IMP) Functional Specification
Provides a description of the Integrated Micro Processor.
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
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Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 3
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
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MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
The 88E6390/88E6190/88E6290 datasheet is part of a multi-part set that includes the following
documents:
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88E6390/88E6190/88E6290 Datasheet
The 88E6390 also includes an integrated 200MHz
microprocessor with 60Kbytes of integrated RAM. The
microprocessor’s has direct access to all switch registers
and its integrated Ethernet controller enables support for
Ethernet protocols as well as lightly managed or smart
switches.
The device’s many operating modes can be configured
using SMI (serial management interface - MDC/MDIO) or
through the Remote Management Interface. The device
also supports a standalone QoS mode or configuration
via a low cost serial EEPROM.
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The 88E6390 device includes a TCAM-based Policy
Control List (PCL) engine that supports 256 rules. The
PCL engine can inspect the first 48 bytes of a frame with
a full48 byte match. Rules can be combined to inspect
the first 96 bytes of a frame with a full 96 byte match.
Actions supported include rule based filtering, VLAN
assignment, QoS remarking, and policy based switching.The device’s RGMII (or MII/RMII) interface supports
a direct connection to Management or Router CPUs with
integrated MACs. This interface, along with BPDU han-
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 4
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The PHYs also include an integrated Advanced Virtual
Cable Tester® (VCT™) enabling fault detection and
advanced cable performance monitoring.
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The device has a high-speed, non-blocking eight traffic
class QoS switch fabric that uses the unique Marvell
Dynamic Queue Limit architecture. The QoS architecture
switches packets into one of eight traffic class queues
based upon Port, IEEE 802.1p, IPv4 Type of Service
(TOS) or Differentiated Services (Diff-Serv), IPv6 Traffic
Class, 802.1Q VLAN ID, DA MAC address or SA MAC
address. The device also contains a high-performance
address lookup engine with support for up to 16K active
nodes, and a 2 Mbit frame buffer memory.
Back-pressure and pause frame-based flow control
schemes are included to support zero packet loss under
temporary traffic congestion. The MAC units in the
devices comply fully with the applicable sections of IEEE
802.3 and support frame sizes up to 10KBytes.
The PHY units in the device support the latest 802.3az
Energy Efficient Ethernet (EEE) standard. They are
designed with Marvell® cutting-edge mixed-signal processing technology for digital implementation of adaptive
equalization and clock data recovery. The device also
integrates MDI interface termination resistors into the
PHYs. This resistor integration facilitates board layout
and reduces board cost by reducing the number of external components. Both the PHY and MAC units in the
devices comply fully with the applicable sections of IEEE
802.3, IEEE 802.3u, and IEEE 802.3x standards.
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The tenth and eleventh ports provide two Serdes
interfaces supporting 2500BASE-X (2.5Gbps)
1000BASE-X, and SGMII.
dling for IEEE 802.1D Spanning Tree Protocol, 802.1w
Rapid Spanning Tree, 802.1s Multiple VLAN Spanning
Tree, programmable per-port VLAN configurations,
802.1Q and Port States, supports fully managed
switches and truly isolated WAN vs. LAN firewall applications. The device supports 4,096 802.1Q VLAN IDs
which can be enabled on a per port basis. Three levels
of 802.1Q security is supported with error frame trapping
and logging.
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The Marvell® 88E6390/88E6190/88E6290 device is a
single-chip integration of a 11-port Ethernet switch with
eight integrated Gigabit Ethernet transceivers and two
SerDes interfaces. The device contains eight
10/100/1000 triple speed Ethernet transceivers (PHYs),
two SerDes interfaces and one digital interface that
supports a combination of RGMII, MII, and RMII
interfaces in a 144-lead QFP package.
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OVERVIEW
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11-Port GE AVB/TSN Switch with
8 integrated PHYs and 2 SERDES
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•
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•
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Applications
• Gigabit Ethernet switch with 8 1000BASE-TX LAN
ports with 2.5Gbps uplinks
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•
•
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•
•
•
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 5
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
•
frames, IPv4’s Type of Service (TOS) &
Differentiated Services (DS), IPv6’s Traffic Class
802.1Q VID, Destination MAC address, or Source
MAC address
Frame and Queue priority overrides based on DA,
SA, VID, Ethertype, BC, IP, PPPoE, ARP, or Snoop
Strict, Weighted, or mixed mode QoS selectable
per port
Programmable QoS weighting via a 128-entry table
Wake-on-LAN and Wake of Frame Event Detection
Remote Management capabilities allow device
configuration and readback via Ethernet frames
Supports 16K MAC addresses and 4K VLAN IDs
Enhanced 802.1s Per VLAN Spanning Tree
supporting up to 64 spanning tree instances
Per port, programmable MAC hardware address
learn limiting
2 integrated SerDes interfaces
- Supports 2500BASE-X, 1000BASE-X, and
SGMII
8 integrated Gigabit Ethernet PHYs fully compliant
with the applicable sections of IEEE802.3 and
IEEE802.3u
- Integrated MDI interface termination resistors
- Integrated Advanced Virtual Cable Tester®
(VCT™) cable diagnostic feature
RGMII/MII/RMII interface supporting 1.8V, 2.5V, or
3.3V I/O
Supports 2-Wire EEPROMs for configuration
- 32Kbit to 512Kbit densities supported
- Able to program attached EEPROMs to save
configurations
16 x 16mm 144-lead QFP package
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• Quality of Service support with 8 traffic classes
• QoS determined by Port, IEEE 802.1p tagged
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Management Unit
- Integrated Ethernet NIC connects directly to
switch fabric
Supports 802.1 AVB/TSN Standards
- 802.1AS - Precise Timing Protocol
- 802.1Qat - Stream Reservation Protocol
- 802.1Qav - Egress Pacing and Shaping
- 802.1Qbv - Time Aware Shaping
Supports 1588v2 over Layer 2 and Layer 4
Timing Application Interface for AVB/TSN end
nodes
Supports Synchronous Ethernet
Supports Cut-through switch fabric for low latency
applications
TCAM-based Policy Control List (PCL) Engine
- Line rate, ingress packet classification and
filtering based on packet’s first 48 or 96 bytes
- 256 rules of 48 bytes or 128 rules of 96 bytes
with independent bit-by-bit masking capability
per rule
- Allows co-existence of short (48B) and long
(96B) rules
- Flexible actions including filtering, VLAN
assignment, QoS remarking, and policy based
switching
- Rules can be assigned to any combination of
ingress or egress ports
Supports 802.3az Energy Efficient Ethernet
Wire speed performance with Maximum Frame
size up to 10K Bytes
‘Best-in-Class’ per port TCP/IP Ingress Rate
Limiting along with independent Storm Prevention
- 5 Ingress Rate Limiting buckets per port,
supporting Rate-based and Priority-based rate
limiting
- Non-Rate Limited frames based on SA or DA
Supports 802.1Qbb Priority Based Flow Control
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MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
• Integrated 200MHz Z80 compatible microprocessor
- Integrated60Kbyte zero wait state RAM
- Boots via EEPROM, SMI interface, or Remote
s
Features
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Overview
Highlighted Features
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88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
88E6290
# GE PHYs
8
8
0
# FE PHYs
0
0
8
# RGMII/MII/RMII
1
1
1
# SerDes with 1 Gbps
2
2
2
# SerDes with 2.5 Gbps
2
2
2
0
0
0
Packet Buffer Memory
XAUI/RXAUI
2 Mbit
2 Mbit
2 Mbit
Jumbo Frame Support
10K Bytes
10K Bytes
10K Bytes
16K
16K
16K
8
8
8
Yes
Yes
Yes
Programmable Weighting
Yes
Yes
Yes
Port-based VLANs
Yes
Yes
Yes
4096
4096
4096
Yes
Yes
Yes
Wake On LAN / Wake On Frame
Yes
Yes
Yes
Remote Mgmt/Ethertype DSA
Yes
Yes
Yes
Layer 2 PCLs
Yes
Yes
Yes
TCAM
Yes
No
Yes
Yes
IGMP/MLD Snooping
Yes
802.1AS / Qat / Qav / 1588
Yes
Yes
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Port Mirroring/Port Trunking
AV B
Other
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Yes
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802.1D/s/w Spanning Tree
802.1X Port & MAC Authentication
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802.1Q VLANs
Double Tagging (Q in Q)
Yes
Yes
Yes
Yes
Yes
No
Yes
802.1Qbv
Yes
No
Yes
1 Step PTP
Yes
No
Yes
Timing App I/F (TAI)
Yes
No
Yes
Integrated Micro Processor
Yes
Yes
Yes
Synchronous Ethernet
Yes
No
Yes
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802.1p, Port, TOS/DS, IPv6 TC, MAC
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Queues per Port
Cut Through Switch Fabric
Ingress Rate Limiting Resources
No
Yes
5/port
5/port
16
16
16
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GPIO Pins (shared)
Yes
5/port
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Doc. No. MV-S110663-00 Rev. A
Page 6
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
88 E6 1 90
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88E6390
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Features
88E6390/88E6190/88E6290 Device Differences
# MAC Addresses
VLAN
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Table 1:
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
s
Table 1 shows the 88E6390/88E6190/88E6290 device feature differences.
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Applications
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AVB Frame
Processing
& Limiting
Port 5's
GMAC
AVB Frame
Processing
& Limiting
Port 4's
GMAC
AVB Frame
Processing
& Limiting
Port 3's
GMAC
AVB Frame
Processing
& Limiting
10/100/1000
Copper EEE PHY
Port 2's
GMAC
AVB Frame
Processing
& Limiting
10/100/1000
Copper EEE PHY
Port 1's
GMAC
AVB Frame
Processing
& Limiting
Port 0's
GMAC
AVBFrame
Processing
& Limiting
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10/100/1000
Copper EEE PHY
10/100/1000
Copper EEE PHY
10/100/1000
Copper EEE PHY
Remote
Management Unit
60KByte
SRAM
200MHz Integrated
Management
Processor
64 Entry
802.1s per
VLAN Port
States
16,384 Entry MAC
Address Table
4,096 Entry
802.1Q
VLAN
Table
Packet Processing
Engine
256 Entry
TCAM
RESETn
XTAL_IN
XTAL_OUT
AVB Queue Controller with 8 Traffic
Classes and 802.1Qav/Qbv Shapers
ay
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P0 Interface
MAC or PHY Mode
RGMII/RMII/MII
MDC_CPU
MDIO_CPU
INTn
60 32-bit and
2 64-bit RMON
Counters per Port
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Sync-E/TAI
Interface via GPIOs
TAI &
Sync-E
I/F
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PHY Polling Unit
& Register I/F
w
2 Mbit Embedded Switch Fabric Memory
MDC & MDIO_PHY
via P0_CRS/COL
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 7
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Port 6's
GMAC
CPU/Reg
Interface
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AVB Frame
Processing
& Limiting
Switch Registers
EE_DOUT/C1_LED
EE_CLK/C0_LED
C[3:2]_LED,
R[3:0]_LED
ite
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Port 7's
GMAC
10/100/1000
Copper EEE PHY
EEPROM
I/F
& LED
Drivers
m
AVB Frame
Processing
& Limiting
Register Loader
Li
Port 8's
GMAC
10/100/1000
Copper EEE PHY
P5_MDI3
P5_MDI2
P5_MDI1
P5_MDI0
P1_MDI3
P1_MDI2
P1_MDI1
P1_MDI0
AVB Frame
Processing
& Limiting
AVB Frame
Processing
& Limiting
10/100/1000
Copper EEE PHY
P3_MDI3
P3_MDI2
P3_MDI1
P3_MDI0
P2_MDI3
P2_MDI2
P2_MDI1
P2_MDI0
Port 10's
GMAC
Port 9's
GMAC
2.5Gbps / 1Gbps
SerDes
P6_MDI3
P6_MDI2
P6_MDI1
P6_MDI0
P4_MDI3
P4_MDI2
P4_MDI1
P4_MDI0
RMU
Frame
Buffer
at
e
P8_MDI3
P8_MDI2
P8_MDI1
P8_MDI0
P7_MDI3
P7_MDI2
P7_MDI1
P7_MDI0
P0, P1,
P9, P10
Mux
Pr
iv
P9_RX/TX
2.5Gbps / 1Gbps
SerDes
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P10_RX/TX
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A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
Time Slot Port Controller & Cut Through Fabric
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
GPIOs
s
Figure 1: 88E6390 Block Diagram
d
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
Frame
Processing
& Limiting
10/100/1000
Copper EEE PHY
Port 8's
GMAC
Frame
Processing
& Limiting
10/100/1000
Copper EEE PHY
Port 7's
GMAC
Frame
Processing
& Limiting
P6_MDI3
P6_MDI2
P6_MDI1
P6_MDI0
10/100/1000
Copper EEE PHY
Port 6's
GMAC
Frame
Processing
& Limiting
P5_MDI3
P5_MDI2
P5_MDI1
P5_MDI0
10/100/1000
Copper EEE PHY
Port 5's
GMAC
Frame
Processing
& Limiting
10/100/1000
Copper EEE PHY
Port 4's
GMAC
Frame
Processing
& Limiting
10/100/1000
Copper EEE PHY
Port 3's
GMAC
Frame
Processing
& Limiting
10/100/1000
Copper EEE PHY
Port 2's
GMAC
Frame
Processing
& Limiting
10/100/1000
Copper EEE PHY
Port 1's
GMAC
Frame
Processing
& Limiting
Port 0's
GMAC
Frame
Processing
& Limiting
e0
t
qi
no
9x
1q
P4_MDI3
P4_MDI2
P4_MDI1
P4_MDI0
64
dz
P8_MDI3
P8_MDI2
P8_MDI1
P8_MDI0
P7_MDI3
P7_MDI2
P7_MDI1
P7_MDI0
P3_MDI3
P3_MDI2
P3_MDI1
P3_MDI0
P2_MDI3
P2_MDI2
P2_MDI1
P2_MDI0
P1_MDI3
P1_MDI2
P1_MDI1
P1_MDI0
Remote
Management Unit
60KByte
SRAM
200MHz Integrated
Management
Processor
64 Entry
802.1s per
VLAN Port
States
4,096 Entry
802.1Q
VLAN
Table
16,384 Entry MAC
Address Table
RESETn
XTAL_IN
XTAL_OUT
Packet Processing
Engine
Queue Controller with 8 Traffic Classes and
ay
s
P0 Interface
MAC or PHY Mode
RGMII/RMII/MII
MDC_CPU
MDIO_CPU
INTn
TAI &
Sync-E
I/F
60 32-bit and
2 64-bit RMON
Counters per Port
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
PHY Polling Unit
& Register I/F
w
2 Mbit Embedded Switch Fabric Memory
MDC & MDIO_PHY
via P0_CRS/COL
1q
no
qi
e
0t
64
dz
Sync-E/TAI
Interface via GPIOs
Doc. No. MV-S110663-00 Rev. A
Page 8
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Port 9's
GMAC
CPU/Reg
Interface
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
2.5Gbps / 1Gbps
SerDes
P9_RX/TX
Switch Registers
EE_DOUT/C1_LED
EE_CLK/C0_LED
C[3:2]_LED,
R[3:0]_LED
ite
d
Frame
Processing
& Limiting
EEPROM
I/F
& LED
Drivers
m
Port 10's
GMAC
Register Loader
Li
RMU
Frame
Buffer
at
e
P0, P1,
P9, P10
Mux
Pr
iv
2.5Gbps / 1Gbps
SerDes
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
w
ay
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
Time Slot Port Controller & Cut Through Fabric
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
GPIOs
P10_RX/TX
s
Figure 2: 88E6190 Block Diagram
d
ite
m
Overview
Pr
iv
at
e
Li
Applications
AVB Frame
Processing
& Limiting
10/100 Copper
EEE PHY
Port 8's
GMAC
AVB Frame
Processing
& Limiting
10/100 Copper
EEE PHY
Port 7's
GMAC
AVB Frame
Processing
& Limiting
P6_MDI3
P6_MDI2
P6_MDI1
P6_MDI0
10/100 Copper
EEE PHY
Port 6's
GMAC
AVB Frame
Processing
& Limiting
P5_MDI3
P5_MDI2
P5_MDI1
P5_MDI0
10/100 Copper
EEE PHY
Port 5's
GMAC
AVB Frame
Processing
& Limiting
10/100 Copper
EEE PHY
Port 4's
GMAC
AVB Frame
Processing
& Limiting
10/100 Copper
EEE PHY
Port 3's
GMAC
AVB Frame
Processing
& Limiting
10/100 Copper
EEE PHY
Port 2's
GMAC
AVB Frame
Processing
& Limiting
10/100 Copper
EEE PHY
Port 1's
GMAC
AVB Frame
Processing
& Limiting
Port 0's
GMAC
AVBFrame
Processing
& Limiting
e0
t
qi
no
9x
1q
P4_MDI3
P4_MDI2
P4_MDI1
P4_MDI0
64
dz
P8_MDI3
P8_MDI2
P8_MDI1
P8_MDI0
P7_MDI3
P7_MDI2
P7_MDI1
P7_MDI0
P3_MDI3
P3_MDI2
P3_MDI1
P3_MDI0
P2_MDI3
P2_MDI2
P2_MDI1
P2_MDI0
P1_MDI3
P1_MDI2
P1_MDI1
P1_MDI0
Remote
Management Unit
60KByte
SRAM
200MHz Integrated
Management
Processor
64 Entry
802.1s per
VLAN Port
States
16,384 Entry MAC
Address Table
4,096 Entry
802.1Q
VLAN
Table
Packet Processing
Engine
256 Entry
TCAM
RESETn
XTAL_IN
XTAL_OUT
AVB Queue Controller with 8 Traffic
Classes and 802.1Qav/Qbv Shapers
ay
s
P0 Interface
MAC or PHY Mode
RGMII/RMII/MII
MDC_CPU
MDIO_CPU
INTn
TAI &
Sync-E
I/F
60 32-bit and
2 64-bit RMON
Counters per Port
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
PHY Polling Unit
& Register I/F
w
2 Mbit Embedded Switch Fabric Memory
MDC & MDIO_PHY
via P0_CRS/COL
1q
no
qi
e
0t
64
dz
Sync-E/TAI
Interface via GPIOs
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 9
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Port 9's
GMAC
CPU/Reg
Interface
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
2.5Gbps / 1Gbps
SerDes
P9_RX/TX
Switch Registers
EE_DOUT/C1_LED
EE_CLK/C0_LED
C[3:2]_LED,
R[3:0]_LED
ite
d
AVB Frame
Processing
& Limiting
EEPROM
I/F
& LED
Drivers
m
Port 10's
GMAC
Register Loader
Li
RMU
Frame
Buffer
at
e
P0, P1,
P9, P10
Mux
Pr
iv
2.5Gbps / 1Gbps
SerDes
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
w
ay
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
Time Slot Port Controller & Cut Through Fabric
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
GPIOs
P10_RX/TX
s
Figure 3: 88E6290 Block Diagram
d
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
Pin Description ................................................................................................................................................18
1.2
Pin Assignment List.........................................................................................................................................34
2
Application Examples .................................................................................................................37
2.1
Managed switch ..............................................................................................................................................37
2.1.1
Router Gateway ................................................................................................................................39
2.2
Device Physical Interfaces ..............................................................................................................................40
2.2.1
Port 0 Configuration Options ............................................................................................................40
2.2.2
MII MAC Mode..................................................................................................................................41
2.2.3
MII PHY Mode ..................................................................................................................................42
2.2.4
MII 200 Mbps Mode ..........................................................................................................................42
2.2.5
RGMII Mode .....................................................................................................................................43
2.2.6
RMII MAC Mode ...............................................................................................................................44
2.2.7
RMII PHY Mode ................................................................................................................................45
2.2.8
1000BASE-T PHY Interface .............................................................................................................45
2.2.9
SERDES modes ...............................................................................................................................45
2.2.10 SGMII MAC or PHY Mode ................................................................................................................46
2.2.11 1000BASE-X.....................................................................................................................................46
2.2.12 Port Status Registers ........................................................................................................................46
2.2.13 PHY Polling Unit (PPU) ....................................................................................................................46
2.3
General Purpose I/O (GPIO) Configuration.....................................................................................................47
2.3.1
Configuring GPIO as a Port Enable Pin............................................................................................48
2.4
LED Interface ..................................................................................................................................................49
2.4.1
LED Options .....................................................................................................................................51
2.4.2
Special LEDs ....................................................................................................................................52
2.5
Connection of external PHYs ..........................................................................................................................53
2.5.1
Connection to 1000BASE-T PHY .....................................................................................................53
3
Electrical Specifications .............................................................................................................54
3.1
Absolute Maximum Ratings ............................................................................................................................54
3.1.1
Power Supply Sequencing................................................................................................................55
e0
t
qi
no
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
9x
1q
Recommended Operating Conditions .............................................................................................................55
3.3
Thermal Conditions .........................................................................................................................................56
3.3.1
Thermal Conditions for the 88E6390/88E6190/88E6290 device 144-pin QFP Package..................56
3.4
Current Consumption ......................................................................................................................................57
3.5
DC Electrical Characteristics...........................................................................................................................61
3.5.1
Digital Operating Conditions .............................................................................................................61
3.5.2
SGMII Interface.................................................................................................................................62
3.6
AC Electrical Specifications ............................................................................................................................67
3.6.1
Reset and Configuration Timing .......................................................................................................67
3.6.2
Clock Timing .....................................................................................................................................68
1q
no
qi
e
0t
64
dz
3.2
Doc. No. MV-S110663-00 Rev. A
Page 10
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
1.1
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Signal Description .......................................................................................................................16
64
dz
1
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table of Contents
d
Pr
iv
MII Timing .......................................................................................................................................................69
3.7.1
MII PHY Mode Receive Timing - 100 Mbps......................................................................................69
3.7.2
MII PHY Mode Transmit Timing - 100 Mbps.....................................................................................70
3.7.3
MII MAC Mode Receive Timing ........................................................................................................71
3.7.4
MII MAC Mode Transmit Timing .......................................................................................................72
3.7.5
TMII PHY Mode Receive Timing - 200 Mbps....................................................................................73
3.7.6
TMII PHY Mode Transmit Timing - 200 Mbps...................................................................................74
3.7.7
TMII MAC Mode Clock Timing - 200 Mbps .......................................................................................75
3.7.8
TMII MAC Mode Receive Timing - 200 Mbps ...................................................................................76
3.7.9
TMII MAC Mode Transmit Timing - 200 Mbps ..................................................................................77
3.8
SGMII Timing ..................................................................................................................................................78
3.8.1
SGMII Output AC Characteristics .....................................................................................................78
3.8.2
SGMII Input AC Characteristics ........................................................................................................78
3.9
RGMII Timing ..................................................................................................................................................79
3.9.1
RGMII Timing for Different RGMII Modes.........................................................................................80
3.10
RMII Timing .....................................................................................................................................................82
3.10.1 RMII Receive Timing ........................................................................................................................82
3.10.2 RMII Transmit Timing .......................................................................................................................83
3.11
Serial Management Interface (SMI) Timing.....................................................................................................84
3.11.1 SMI Clock Timing (CPU Set) ............................................................................................................84
3.11.2 SMI Data Timing (CPU Set)..............................................................................................................85
3.11.3 SMI Timing (PHY Set) ......................................................................................................................86
3.12
2500BASE-X ...................................................................................................................................................87
3.12.1 2500BASE-X Characteristics ............................................................................................................87
3.13
EEPROM Timing .............................................................................................................................................89
3.13.1 2-Wire EEPROM Timing ...................................................................................................................89
3.13.2 IEEE AC Transceiver Parameters ....................................................................................................91
4
Mechanical Drawing ....................................................................................................................92
5
Part Order Numbering/Package Marking ..................................................................................94
Package Marking ............................................................................................................................................95
5.2.1
Industrial Package Marking ..............................................................................................................95
5.2.2
Commercial Package Marking ..........................................................................................................96
A
Revision History ..........................................................................................................................97
w
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
dz
64
0t
qi
e
no
1q
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 11
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Part Order Numbering .....................................................................................................................................94
5.2
ay
s
5.1
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Pr
iv
at
e
Li
m
ite
d
9x
1q
no
qi
e0
t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
3.7
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
at
e
Li
m
ite
Table of Contents
d
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
Table 2:
Network 1G/2.5G SERDES Interface (Ports 9 to 10) .......................................................................18
Table 3:
Network 10/100/1000 PHY Interface (Ports 1 to 8) ..........................................................................19
Reference, Clock and Reset .............................................................................................................21
Table 5:
Port Status LEDs ..............................................................................................................................22
Table 6:
Port 0 xMII Receive Interface ...........................................................................................................25
Table 7:
Port 0 xMII Transmit Interface ..........................................................................................................28
Table 8:
GPIO .................................................................................................................................................30
Table 9:
System & Register Access ...............................................................................................................31
Table 10:
Power & Ground ...............................................................................................................................32
Table 11:
No Connect .......................................................................................................................................33
Table 12:
Pin List—Alphabetical by Signal Name ............................................................................................34
Table 13:
88E6390,88E6190 Interface summary .............................................................................................40
Table 14:
88E6290 Interface summary.............................................................................................................40
e0
t
qi
no
9x
1q
Table 15:
64
dz
Table 4:
Port 0 Configuration Summary .........................................................................................................40
Table 16:
Port 0 GPIO Assignments.................................................................................................................47
Table 17:
LED Mapping ....................................................................................................................................49
Port 1-8 Hardware Reset LED configuration ....................................................................................52
Table 19:
Port 9 Hardware Reset LED configuration........................................................................................52
Table 20:
Port 10 Hardware Reset LED configuration......................................................................................52
Table 21:
Absolute Maximum Ratings ..............................................................................................................54
Table 22:
Recommended Operating Conditions...............................................................................................55
Table 23:
88E6390/88E6190/88E6290 Device Current Consumption .............................................................57
ay
s
Pr
iv
at
e
Li
m
ite
d
Table 18:
Digital Operating Conditions .............................................................................................................61
Table 25:
Programming SGMII Output Amplitude ............................................................................................62
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
Table 24:
Reset and Configuration ...................................................................................................................67
Table 27:
IEEE DC Transceiver Parameters ....................................................................................................68
Table 28:
MII PHY Mode Receive Timing.........................................................................................................69
Table 29:
MII PHY Mode Transmit Timing........................................................................................................70
Table 30:
MII Receive Timing - MAC Mode ......................................................................................................71
Table 31:
MII MAC Mode Transmit Timing .......................................................................................................72
Table 32:
TMII PHY Mode Receive Timing - 200 Mbps....................................................................................73
Table 33:
TMII PHY Mode Transmit Timing - 200 Mbps...................................................................................74
Table 34:
TMII MAC Mode Clock Timing - 200 Mbps .......................................................................................75
Table 35:
TMII MAC Mode Receive Timing - 200 Mbps ...................................................................................76
Table 36:
TMII MAC Transmit Timing - 200 Mbps ............................................................................................77
Table 37:
RGMII Interface Timing.....................................................................................................................79
Table 38:
Transmit - TXC Timing when RGMII Transmit Delay Control (Offset 0x01, bit 14) = 0 ....................80
Table 39:
Transmit - TXC Timing when RGMII Transmit Delay Control (Offset 0x01, bit 14) = 1 ....................80
1q
no
qi
e
0t
64
dz
Table 26:
Doc. No. MV-S110663-00 Rev. A
Page 12
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
88E6390/88E6190/88E6290 Device Differences ...............................................................................6
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Table 1:
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
List of Tables
d
ite
Table 43:
RMII Transmit Timing using INCLK ..................................................................................................83
Table 44:
SMI Clock Timing (CPU Set) ............................................................................................................84
Table 45:
SMI Clock Timing (CPU Set) ............................................................................................................85
Table 46:
SMI Clock Timing (PHY Set) ............................................................................................................86
Table 47:
2500BASE-X Characteristics ............................................................................................................87
Table 48:
Receiver Input Parameters ...............................................................................................................88
Table 49:
2-Wire EEPROM Input Timing ..........................................................................................................89
Table 50:
2-Wire EEPROM Output Timing .......................................................................................................90
Table 51:
144-pin E-PAD TQFP (16x16 mm) Package Dimensions ................................................................93
88E6390/88E6190/88E6290 Part Order Options .............................................................................94
Table 53:
Revision History ................................................................................................................................97
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
9x
1q
no
qi
e0
t
64
dz
Table 52:
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 13
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
RMII Receive Timing using INCLK ...................................................................................................82
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Receive - INCLK (RXC) Timing when RGMII Receive Delay Control (Offset 0x01, bit 15) = 1........81
Table 42:
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
w
ay
s
Receive - INCLK (RXC) Timing when RGMII Receive Delay Control (Offset 0x01, bit 15) = 0........81
Table 41:
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 40:
Pr
iv
at
e
Li
m
List of Tables
d
88E6190 Block Diagram .....................................................................................................................8
Figure 3:
88E6290 Block Diagram .....................................................................................................................9
Figure 4:
88E6190 and 88E390 144-Pin QFP Pinout ......................................................................................16
Figure 5:
88E6290 144-Pin QFP Pinout ..........................................................................................................17
Figure 6:
Managed Switch 8GE Plus 2 SFP ports ...........................................................................................38
Figure 7:
Service or Access router...................................................................................................................39
Figure 8:
MII MAC Mode..................................................................................................................................41
Figure 9:
MII PHY Interface Pins .....................................................................................................................42
Figure 10:
RGMII Interface Pins ........................................................................................................................43
Figure 11:
RMII MAC Interface Pins ..................................................................................................................44
Figure 12:
RMII PHY Interface ..........................................................................................................................45
Figure 13:
GPIO Enable Example......................................................................................................................48
Figure 14:
LEDs plus 2 wire EEPROM ..............................................................................................................50
e0
t
qi
no
9x
1q
Figure 15:
Typical SGMII connection to external PHY connections ..................................................................53
Typical external 10G PHY connection ..............................................................................................53
Figure 17:
CML I/Os...........................................................................................................................................63
Figure 18:
AC connections (CML or LVDS receiver) or DC connection LVDS receiver ....................................64
Figure 19:
DC connection to a CML receiver .....................................................................................................65
Figure 20:
Input Differential Hysteresis ..............................................................................................................66
Figure 21:
Reset and Configuration Timing .......................................................................................................67
at
e
Li
m
ite
d
Figure 16:
Oscillator Clock Timing .....................................................................................................................68
Figure 23:
MII PHY Mode Receive Timing.........................................................................................................69
Figure 24:
MII PHY Mode Transmit Timing........................................................................................................70
Figure 25:
MII MAC Mode Receive Timing ........................................................................................................71
Figure 26:
MII MAC Mode Transmit Timing .......................................................................................................72
Figure 27:
TMII PHY Mode Receive Timing - 200 Mbps....................................................................................73
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
Figure 22:
TMII PHY Mode Transmit Timing - 200 Mbps...................................................................................74
Figure 29:
TMII MAC Clock Timing - 200 Mbps .................................................................................................75
Figure 30:
TMII MAC Mode Receive Timing - 200 Mbps ...................................................................................76
Figure 31:
TMII MAC Mode Transmit Timing - 200 Mbps ..................................................................................77
Figure 32:
Serial Interface Rise and Fall Times .................................................................................................78
Figure 33:
RGMII Multiplexing and Timing.........................................................................................................79
Figure 34:
Transmit - TXC Timing when RGMII Transmit Delay Control (bit 3) = 0...........................................80
Figure 35:
Transmit - TXC Timing when RGMII Transmit Delay Control (bit 3) = 1...........................................80
Figure 36:
Receive - INCLK (RXC) Timing when RGMII Receive Delay Control (bit 4) = 0 .............................81
Figure 37:
Receive - RXC Timing when RGMII Receive Delay Control (bit 4) = 1 ............................................81
Figure 38:
RMII Receive Timing using OUTCLK ...............................................................................................82
Figure 39:
RMII Transmit Timing using OUTCLK ..............................................................................................83
1q
no
qi
e
0t
64
dz
Figure 28:
Doc. No. MV-S110663-00 Rev. A
Page 14
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Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Figure 2:
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
88E6390 Block Diagram .....................................................................................................................7
64
dz
Figure 1:
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
List of Figures
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
d
ite
Pr
iv
SMI Clock Timing (CPU Set) ............................................................................................................84
Figure 41:
SMI Data Timing ...............................................................................................................................85
Figure 42:
SMI Timing Output (PHY Mode) .......................................................................................................86
Figure 43:
SMI Timing Input (PHY Mode) ..........................................................................................................86
Figure 44:
Driver Output Voltage Limits and Definitions ....................................................................................87
Figure 45:
High-Speed I/O AC Coupled Mode...................................................................................................88
Figure 46:
2-Wire Input Timing ..........................................................................................................................89
Figure 47:
2-Wire EEPROM Output Timing .......................................................................................................90
Figure 48:
144-pin E-PAD TQFP (16x16 mm) Mechanical Drawing..................................................................92
Figure 49:
Sample Part Number ........................................................................................................................94
88E6390 and 88E6290 Industrial Package Marking and Pin 1 Location ..........................................95
Figure 51:
Commercial Package Marking and Pin 1 Location ...........................................................................96
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
9x
1q
no
qi
e0
t
64
dz
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Figure 50:
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 15
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Figure 40:
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
at
e
Li
m
List of Figures
AVDD15
P1_MDIP[0]
P1_MDIN[0]
P1_MDIN[1]
P1_MDIP[1]
P1_AVDD33
P1_MDIP[2]
P1_MDIN[2]
P1_MDIN[3]
P1_MDIP[3]
P2_MDIP[0]
P2_MDIN[0]
P2_MDIN[1]
P2_MDIP[1]
P2_AVDD33
P2_MDIP[2]
P2_MDIN[2]
P2_MDIN[3]
P2_MDIP[3]
P3_MDIP[0]
P3_MDIN[0]
P3_MDIN[1]
P3_MDIP[1]
P3_AVDD33
P3_MDIP[2]
P3_MDIN[2]
P3_MDIN[3]
P3_MDIP[3]
P4_MDIP[0]
P4_MDIN[0]
P4_MDIN[1]
P4_MDIP[1]
P4_AVDD33
P4_MDIP[2]
P4_MDIN[2]
AVDD15
Page 16
TM
Doc. No. MV-S110663-00 Rev. A
88E6390/88E6190
Top View
Document Classification: Proprietary Information
CONFIDENTIAL
at
e
iv
Li
TM
no
ite
d
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
m
Signal Description
Figure 4: 88E6190 and 88E390 144-Pin QFP Pinout
AVDD15
P8_MDIN[2]
P8_MDIP[2]
P8_AVDD33
P8_MDIP[1]
P8_MDIN[1]
P8_MDIN[0]
P8_MDIP[0]
P7_MDIP[3]
P7_MDIN[3]
P7_MDIN[2]
P7_MDIP[2]
P7_AVDD33
P7_MDIP[1]
P7_MDIN[1]
P7_MDIN[0]
P7_MDIP[0]
P6_MDIP[3]
P6_MDIN[3]
P6_MDIN[2]
P6_MDIP[2]
P6_AVDD33
P6_MDIP[1]
P6_MDIN[1]
P6_MDIN[0]
P6_MDIP[0]
P5_MDIP[3]
P5_MDIN[3]
P5_MDIN[2]
P5_MDIP[2]
P5_AVDD33
P5_MDIP[1]
P5_MDIN[1]
P5_MDIN[0]
P5_MDIP[0]
AVDD15
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
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at
iv
VDD_CORE
108
P9_TXP[0]
107
qi 106 P9_TXN[0]
e105
P9_AVDD15
0t
104
6 P9_RXP[0]
103 4d P9_RXN[0]
102 ziTEST
jP0_CRS/MDC_PHY/GPIO[8]
t1
101
r5
100 M P0_COL/MDIO_PHY/GPIO[7]
A
99
P0_IND[3]/GPIO[6]
R 5y9
VE a
98
P0_IND[2]/GPIO[5]
97
P0_IND[1]/GPIO[4]
LL 6s8
96
P0_IND[0]/GPIO[3]
C q7
95
P0_VDDO
O 10
P0_INDV//GPIO[2]
94
N
FI y5
P0_INCLK/GPIO[1]
93
D v3
VDD_CORE
92
EN 5
P0_OUTCLK/P0_TXC/GPIO[0]
91
TI shv
P0_OUTEN/P0_VDDOS
90
A
P0_OUTD[0]/P0_MODE[0]
89
L ru
P0_OUTD[1]/P0_MODE[1] , U 8v
88
N h87
P0_VDDO
D kb
P0_OUTD[2]/P0_MODE[2]
86
ER 7
P0_OUTD[3]/NO_CPU
85
VDD_CORE
N tar9
84
D
83
SE_SCLK
A 2*
82
#
AVDD15_XTAL
5e Tru
81
XTAL_IN
bd ne
80
XTAL_OUT
79
42 xa
TST_PT
78
HSDACP
0d In
77
HSDACN
0a fo
76
w
RSET
ay
75
AVDD15
s
74
P8_MDIP[3]
Pr
73
P8_MDIN[3]
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
9x
1q
1
1
P4_MDIN[3]
no
2
P4_MDIP[3]
qi
3
P9_SMODE
e0
VDD_CORE
4
t6
5
C3_LED/EEEDis
4d C2_LED/LED_SEL
6
zi
7
EE_VDDO
jtEE_DOUT/C1_LED
8
1r
M
55
EE_CLK/C0_LED/FLOW
9
A R4_LED/ADDR[4]n
10
R y9
VE a
R3_LED/ADDR[3]n
11
6
R2_LED/ADDR[2]n
12
LL s8
R1_LED/ADDR[1]n
13
q7
CEE_VDDO
14
O
1
R0_LED/ADDR[0]n
N 0y 15
F
VDD_CORE
ID 5v 16
RESETn
E 3517
INTnN
18
s
MDIO_CPU TI 19hv
A20 ru
MDC_CPU
L,
GPIO[9]
21 U 8v
h
GPIO[10]
22 N
D -kb
GPIO[11]/SW_24Pn
23
ER 7
GPIO_VDDO
24
N tar9
GPIO[12]/GPIO_VDDOS
25
D
GPIO[13]
26
A 2*
#
GPIO[14]
27
5e Tru
GPIO[15]
28
bd ne
P10_SMODE
29
P10_RXN[0]
30
42 xa
P10_RXP[0]
31
0d In
P10_AVDD15
32
0a fo
P10_TXN[0]
w
33
ay
P10_TXP[0]
34
s
35
NC
Pr
36
VDD_CORE
1q
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
e
Li
m
d
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
January 23, 2018
Copyright © 2018 Marvell
Document Classification: Proprietary Information
CONFIDENTIAL
Li
Top View
at
e
Pr
iv
TM
TM
88E6290
AVDD15
NC
NC
P8_AVDD33
P8_MDIP[1]
P8_MDIN[1]
P8_MDIN[0]
P8_MDIP[0]
NC
NC
NC
NC
P7_AVDD33
P7_MDIP[1]
P7_MDIN[1]
P7_MDIN[0]
P7_MDIP[0]
NC
NC
NC
NC
P6_AVDD33
P6_MDIP[1]
P6_MDIN[1]
P6_MDIN[0]
P6_MDIP[0]
NC
NC
NC
NC
P5_AVDD33
P5_MDIP[1]
P5_MDIN[1]
P5_MDIN[0]
P5_MDIP[0]
AVDD15
Doc. No. MV-S110663-00 Rev. A
Page 17
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ite
d
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
m
at
Pr
iv
Figure 5: 88E6290 144-Pin QFP Pinout
VDD_CORE
108
P9_TXP[0]
107
qi
P9_TXN[0]
106
e0
P9_AVDD15
105
t6
P9_RXP[0]
104
4d
P9_RXN[0]
103
zi
102
TEST
jt1
101
P0_CRS/MDC_PHY/GPIO[8]
M r5
100
P0_COL/MDIO_PHY/GPIO[7]
A 5y
R
99
P0_IND[3]/GPIO[6]
VE 9a
P0_IND[2]/GPIO[5]
98
6
LL s8
P0_IND[1]/GPIO[4]
97
P0_IND[0]/GPIO[3]
96
C q7
95
P0_VDDO
O 10
N
94
FI y5 93 P0_INDV//GPIO[2]
D v392 P0_INCLK/GPIO[1]
VDD_CORE
EN 5
sh P0_OUTCLK/P0_TXC/GPIO[0]
TI 91
v P0_OUTEN/P0_VDDOS
A90
89
L, ruP0_OUTD[0]/P0_MODE[0]
8v
88 U P0_OUTD[1]/P0_MODE[1]
h87 N P0_VDDO
DP0_OUTD[2]/P0_MODE[2]
86
ER kb7
P0_OUTD[3]/NO_CPU
85
N tar9
VDD_CORE
84
D
83
SE_SCLK
A 2*
#
82
AVDD15_XTAL
5e Tru
81
XTAL_IN
bd ne
80
XTAL_OUT
42 xa
79
TST_PT
78
0d In
HSDACP
77
HSDACN
0a fo
w
76
RSET
ay
75
AVDD15
s
74
NC
73
NC
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
no
9x
1q
AVDD15
P1_MDIP[0]
P1_MDIN[0]
P1_MDIN[1]
P1_MDIP[1]
P1_AVDD33
NC
NC
NC
NC
P2_MDIP[0]
P2_MDIN[0]
P2_MDIN[1]
P2_MDIP[1]
P2_AVDD33
NC
NC
NC
NC
P3_MDIP[0]
P3_MDIN[0]
P3_MDIN[1]
P3_MDIP[1]
P3_AVDD33
NC
NC
NC
NC
P4_MDIP[0]
P4_MDIN[0]
P4_MDIN[1]
P4_MDIP[1]
P4_AVDD33
NC
NC
AVDD15
NC
1
NC
2
qi
3
P9_SMODE
e0
VDD_CORE
4
t6
5
C3_LED/EEEDis
4d
6
C2_LED/LED_SEL
zi
7
EE_VDDO
jt1
EE_DOUT/C1_LED
8
M r5
EE_CLK/C0_LED/FLOW
9
A 5y
R
R4_LED/ADDR[4]n
10
VE 9a
R3_LED/ADDR[3]n
11
6
LL s8
R2_LED/ADDR[2]n
12
R1_LED/ADDR[1]n
13
C q7
EE_VDDO
14
O 10
N
R0_LED/ADDR[0]n
15
FI y5
16
VDD_CORE
D v3
RESETn
17
EN 5
INTn
18
TI shv
MDIO_CPU
19
A
MDC_CPU
L, ru8
20
GPIO[9]
21
U vh
N
GPIO[10]
22
-k
DGPIO[11]/SW_24Pn
23
ER b7
GPIO_VDDO
24
ta
N
GPIO[12]/GPIO_VDDOS
25
r9
D GPIO[13]
2
26
A
*T
# GPIO[14]
5e ru 27
GPIO[15]
28
bd ne 29
P10_SMODE
x
42 a30
P10_RXN[0]
P10_RXP[0]0
31
In
P10_AVDD15 d0 32 fo
a33 w
P10_TXN[0]
ay
P10_TXP[0]
34
s
35
NC
36
VDD_CORE
no
1q
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
e
Li
m
d
ite
Signal Description
d
Table 2:
31
104
s
w
ay
Network 1G/2.5G SERDES Interface (Ports 9 to 10)
Pin Name
P10_RXP[0]
P9_RXP[0]
Ty p e
D e s c r i p t io n
Input
Receiver input – Positive. Px_RXP[0] connects directly to the fiber-optic
receiver’s positive output or to another device’s TXP (Transmitter output
– Positive) pins.
P10_RXN[0]
P9_RXN[0]
Input
Receiver input – Negative. Px_RXN[0] connects directly to the
fiber-optic receiver’s negative output or to another device’s TXN
(Transmitter output – Negative) pins.
Connections to other devices require capacitor isolation.
Output
64
dz
P10_TXP[0]
P9_TXP[0]
Transmitter output – Positive. Px_TXP[0] connects directly to the
fiber-optic transmitter’s positive input or to another device’s RXP
(Receiver input – Positive) pins.
no
qi
e0
t
34
107
9x
1q
P10_TXN[0]
P9_TXN[0]
Output
Transmitter output – Negative. Px_TXN[0] connects directly to the
fiber-optic transmitter’s negative input or to another device’s RXN
(Receiver input – Negative) pins.
Connections to other devices require capacitor isolation.
Li
m
ite
d
33
106
Connections to other devices require capacitor isolation.
Pr
iv
at
e
This device supports internal terminated media pins. They must be left floating if they
are unused.
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Note
Doc. No. MV-S110663-00 Rev. A
Page 18
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
30
103
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Connections to other devices require capacitor isolation.
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Pin #
Pin Description
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
1.1
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
d
Pin Description
Pin Name
65
56
47
38
137
128
119
110
P8_MDIP[0]
P7_MDIP[0]
P6_MDIP[0]
P5_MDIP[0]
P4_MDIP[0]
P3_MDIP[0]
P2_MDIP[0]
P1_MDIP[0]
66
57
48
39
138
129
120
111
P8_MDIN[0]
P7_MDIN[0]
P6_MDIN[0]
P5_MDIN[0]
P4_MDIN[0]
P3_MDIN[0]
P2_MDIN[0]
P1_MDIN[0]
68
59
50
41
140
131
122
113
P8_MDIP[1]
P7_MDIP[1]
P6_MDIP[1]
P5_MDIP[1]
P4_MDIP[1]
P3_MDIP[1]
P2_MDIP[1]
P1_MDIP[1]
67
58
49
40
139
130
121
112
P8_MDIN[1]
P7_MDIN[1]
P6_MDIN[1]
P5_MDIN[1]
P4_MDIN[1]
P3_MDIN[1]
P2_MDIN[1]
P1_MDIN[1]
70
61
52
43
142
133
124
115
P8_MDIP[2]
P7_MDIP[2]
P6_MDIP[2]
P5_MDIP[2]
P4_MDIP[2]
P3_MDIP[2]
P2_MDIP[2]
P1_MDIP[2]
71
62
53
44
143
134
125
116
P8_MDIN[2]
P7_MDIN[2]
P6_MDIN[2]
P5_MDIN[2]
P4_MDIN[2]
P3_MDIN[2]
P2_MDIN[2]
P1_MDIN[2]
Ty p e
s
w
ay
D e s c r i p t io n
Input/Output Media Dependent Interface [0].
In 1000BASE-T mode in MDI configuration, MDIP/N[0] corresponds to
BI_DA±. In MDIX configuration, MDIP/N[0] corresponds to BI_DB±. In
100BASE-TX and 10BASE-T mode in MDI configuration, MDIP/N[0]
are used for the transmit pair. In MDIX configuration, MDIP/N[0] are
used for the receive pair.
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
MDIP/N[1] must be left floating if not used.
Input/Output Media Dependent Interface [2].
In 1000BASE-T mode in MDI configuration, MDIP/N[2] corresponds to
BI_DC±. In MDIX configuration, MDIP/N[2] corresponds to BI_DD±. In
100BASE-TX and 10BASE-T modes, MDIP/N[2] are not used.
MDIP/N[2] must be left floating if not used.
1q
no
qi
e
0t
64
dz
88E6290 These signals are NC
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 19
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
no
9x
1q
In 1000BASE-T mode in MDI configuration, MDIP/N[1] corresponds to
BI_DB±. In MDIX configuration, MDIP/N[1] corresponds to BI_DA±. In
100BASE-TX and 10BASE-T mode in MDI configuration, MDIP/N[1]
are used for the receive pair. In MDIX configuration, MDIP/N[1] are
used for the transmit pair.
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Input/Output Media Dependent Interface [1].
qi
e0
t
64
dz
MDIP/N[0] must be left floating if not used.
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Pin #
Network 10/100/1000 PHY Interface (Ports 1 to 8)
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Table 3:
Pr
iv
at
e
Li
m
ite
Signal Description
d
s
w
ay
Pin Name
74
64
55
46
2
136
127
118
P8_MDIP[3]
P7_MDIP[3]
P6_MDIP[3]
P5_MDIP[3]
P4_MDIP[3]
P3_MDIP[3]
P2_MDIP[3]
P1_MDIP[3]
73
63
54
45
1
135
126
117
P8_MDIN[3]
P7_MDIN[3]
P6_MDIN[3]
P5_MDIN[3]
P4_MDIN[3]
P3_MDIN[3]
P2_MDIN[3]
P1_MDIN[3]
Ty p e
D e s c r i p t io n
Input/Output Media Dependent Interface [3].
In 1000BASE-T mode in MDI configuration, MDIP/N[3] corresponds to
BI_DD±. In MDIX configuration, MDIP/N[3] correspond to BI_DC±. In
100BASE-TX and 10BASE-T modes, MDIP/N[3] are not used.
MDIP/N[3] must be left floating if not used.
1q
no
qi
e
0t
64
dz
Doc. No. MV-S110663-00 Rev. A
Page 20
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
9x
1q
no
qi
e0
t
64
dz
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
88E6290 These pins are NC
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Pin #
Network 10/100/1000 PHY Interface (Ports 1 to 8) (Continued)
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Table 3:
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
d
Pin Description
81
XTAL_IN
80
XTAL_OUT
83
SE_SCLK
Analog
Resistor Current reference. A 4.99k ohm 1% resistor is placed between
the RSET and VSS. This resistor is used to set an internal bias reference
current.
Input
25 MHz system reference clock input provided from the board. The clock
source can come from an external crystal or an external oscillator. This is
the only clock required (for small package). Refer to Section
Section 3.6.2 for “Clock Timing” timing requirements.
Output
System reference clock output provided to the board. This output can
only be used to drive an external crystal. It cannot be used to drive
external logic. If an external oscillator is used this pin should be left
unconnected.
Input
Synchronous Ethernet Source Clock Conditioner. This is a 25 MHz
reference clock which can be used as a synchronous clock input from
synchronous Ethernet applications.
qi
no
9x
1q
Each PHY, via a PHY register, can select this clock input as its reference
clock input instead of using the default XTAL_IN input.
SE_CLK is internally pulled low via a resistor so the pin can be left
floating when unused.
Input
Hardware reset. Active low. The device is configured during reset. When
RESETn is low some configuration pins become inputs and the value
seen on these pins is latched on the rising edge of RESETn or sometime
after. Other configuration pins are active during RESETn low and
become inputs after RESETn rises. These pins latch their configuration
data sometime after RESETn rises and then these pins become their
defined function.
ite
d
RESETn
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
17
1q
no
qi
e
0t
64
dz
Refer to Section 3.6.1 of the AC Electrical Specifications for Reset and
Configuration Timing details.
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 21
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
RSET
D e s c r i p t io n
e0
t
76
Ty p e
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Pin Name
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Pin #
Reference, Clock and Reset
64
dz
Table 4:
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
Signal Description
d
Pin Name
R4_LED
/ADDR[4]n
11
R3_LED
/ADDR[3]n
12
R2_LED
/ADDR[2]n
13
D e s c r i p t io n
Typically
Output, PU
Parallel multiplexed LED outputs. These active low LED pins directly drive
the port’s LEDs supporting a range from 1 to 6 LEDs in a multiplexed
fashion. In this mode the cathode of each LED connects to these pins
through a series current limiting resistor. The anode of each LED
connects to one of the Cx_LED pins below Section 2.4 for LED
applications.
The LEDs can be configured to display many options (refer to
Section 2.4.1).
R1_LED
/ADDR[1]n
All LEDs are turned on whenever RESETn is low so their functionally can
be visually verified during PCB manufacturing testing.
R0_LED
/ADDR[0]n
Rx_LED are multifunction pins which are used to configure the device
after a hardware reset. After reset is asserted, the Rx_LED pins become
inputs and the configuration information below is latched 1 mSec after the
rising edge of RESETn as follows:
9x
1q
no
qi
e0
t
64
dz
15
Ty p e
Input/Output, Serial EEPROM data I/O to/from a 2-wire EEPROM device and Column 0
PU
for the LEDs. EE_DOUT is serial EEPROM data referenced to EE_CLK
used to receive and send the EEPROM address/data to/from the external
serial EEPROM (if present). 2-wire EEPROMs require that this pin is
connected to EE_VDDO through a pull-up resistor.
ay
s
Pr
iv
EE_DOUT
/C1_LED
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
8
at
e
Li
m
ite
d
ADDR[4:0]n sets the device’s SMI address. Note: The inverted values
‘seen’ on these CONFIG pins are used as the SMI address.When
ADDR[4:0]n are left floating or pulled high the device will be configured in
single chip addressing mode. In single chip addressing mode the SMI bus
can not be shared with other devices. When SMI bus is to be shared with
other devices the SMI address of this device must be a none 0 zero
value. To configure this device as SMI address 0x01 ADDR[4:0]n should
be 0x1E. To configure the device as SMI address 0x1E ADDR[4:0]n
should be 0x01.
1q
no
qi
e
0t
64
dz
EE_DOUT is internally pulled high via a resistor so the pin can be left
floating when unused.
Doc. No. MV-S110663-00 Rev. A
Page 22
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
10
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Pin #
Port Status LEDs
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Table 5:
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
d
Pin Description
Pin #
Pin Name
EE_CLK
/C0_LED
/FLOW
s
w
ay
Ty p e
D e s c r i p t io n
Typically
Output, PD
Serial EEPROM clock and column 1 for the LEDs. EE_CLK is the serial
EEPROM clock reference output by the devices. It is used to shift the
external serial EEPROM (if installed) to the next data bit so the default
values of the internal registers can be overridden.
9x
1q
no
qi
e0
t
Full-duplex flow control requires support from the end station. It is
supported on any full-duplex port that has Auto-Negotiation enabled,
advertises that it supports Pause (i.e., FLOW = 1 at reset), and sees that
the end station also supports Pause (from data returned during
Auto-Negotiation).
Half-duplex flow control is active on all half-duplex ports when enabled.
Note: The inverted values ‘seen’ on these CONFIG pins are use by
internal logic.
Typically
Output, PD
C2_LED is a multi-function pin which is used to connect to the anode of
LED column 2 for each row, if used in the multiplexed LED mode (see
R[3:0]_LED above).
It is also used to configure the device after a hardware reset. After reset is
asserted, C2_LED becomes an input and the LED_SEL configuration
information below is latched 1 mSec after the rising edge of RESETn as
follows:
0 = Link/Activity w/ Speed by 3 Color
1 = Link/Activity w/ Separate Speed LED
Pr
iv
C2_LED
/LED_SEL
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
6
at
e
Li
m
ite
d
EE_CLK is internally pulled low via a resistor so the pin can be left floating
when unused. Use a 4.7K ohm resistor to EE_VDDO for a configuration
high.
1q
no
qi
e
0t
64
dz
C2_LED is internally pulled low via a resistor so the pin can be left floating
when unused.
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 23
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
64
dz
It is also used to configure the device after a hardware reset. After reset is
asserted, EE_CLK becomes an input and the FLOW configuration
information below is latched 1 mSec after the rising edge of RESETn as
follows:
0x0 = Disable flow control on all ports
0x1 = Enable advertisement of full-duplex flow control on all PHYs and
enable “forced collision” flow control on all half duplex ports
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
EE_CLK is a multi-function pin which is also used to connect to the anode
of LED column 1 for each row, if used in the multiplexed LED mode (see
R[3:0]_LED above).
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
9
Port Status LEDs (Continued)
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Table 5:
Pr
iv
at
e
Li
m
ite
Signal Description
d
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
5
Pin Name
C3_LED
/EEEDis
s
w
ay
Ty p e
D e s c r i p t io n
Typically
Output, PD
C3_LED is a multi-function pin which is used to connect to the anode of
LED column 3 for each row, if used in the multiplexed LED mode (see
R[4:0]_LED above).
It is also used to configure the device after a hardware reset. After reset is
asserted, C3_LED becomes an input and the EEEDis configuration
information below is latched 1 mSec after the rising edge of RESETn as
follows:
0 = Advertise Energy Efficient Ethernet (EEE) in the PHYs.
1 = Do not advertise Energy Efficient Ethernet (EEE) in the PHYs.
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
9x
1q
no
qi
e0
t
64
dz
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
C3_LED is internally pulled low via a resistor so the pin can be left floating
when unused.
9x
Doc. No. MV-S110663-00 Rev. A
Page 24
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Pin #
Port Status LEDs (Continued)
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Table 5:
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
d
Pin Description
Pin #
Pin Name
Ty p e
P0_INCLK
/GPIO[1]
D e s c r i p t io n
Input/Output, Input Clock. INCLK is a reference for INDV and IND. The speed of
PU
INCLK is expected to be 125 MHz, 50 MHz, 25 MHz or 2.5 MHz
depending upon the speed of the port. In RGMII mode INCLK is used
as RXC.
INCLK is tri-stated during RESETns and it is internally pulled high so
the pin can be left floating when unused.
64
dz
P0_INDV
/GPIO[2]
Input, PD
9x
1q
no
qi
e0
t
94
Input Data Valid. Input Data Valid is used to indicate when IND[3:0] (or
IND[1:0] where appropriate) contains frame information. INDV must
be synchronous to INCLK for all modes except for RMII modes where
INDV must be synchronous to OUTCLK. In RGMII mode INDV is used
as RX_CTL.
When this port is disabled (by its P0_MODE = 0x6) this pin becomes
GPIO[2].
INDV is internally pulled low via resistor so the pin can be left floating
when unused.
P0_IND[2]
/GPIO[5]
97
P0_IND[1]
/GPIO[4]
Input Data. IND[3:0] (or IND[1:0] where appropriate) receives the data
to be sent into the switch. IND must be synchronous to INCLK for all
modes except for RMII modes. In MII, 200BASE, 100BASE and
10BASE modes IND[3:0] is used. In RMII modes only IND[1:0] are
used and they must be synchronous to OUTCLK. In RGMII mode
IND[3:0] are used as RXD[3:0].
ite
d
98
Input, PU
m
P0_IND[3]
/GPIO[6]
Pr
iv
ay
s
w
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
96
at
e
Li
99
When this port is disabled (by its P0_MODE = 0x6) these pins
becomes GPIO[6:3]. When the port is in RMII mode (by its P0_MODE
= 0x4 or 0x5) IND[3:2] become GPIO[6:5].
P0_IND[0]
/GPIO[3]
1q
no
qi
e
0t
64
dz
The IND pins are internally pulled high via resistor so the pins can be
left floating when unused.
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 25
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
INCLK is an output when the xMII is configured in a PHY mode (when
the port’s Px_MODE = 0x0, or 0x1) or when it is a GPIO pin which is
configured to be an output. When the port is in RMII mode or disabled
(by its Px_MODE = 0x4, 0x5 or 0x6) this pin becomes GPIO[1] and
becomes an input.
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
93
Port 0 xMII Receive Interface
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Table 6:
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
Signal Description
d
Ty p e
P0_CRS
/MDC_PHY
/GPIO[8]
s
w
ay
D e s c r i p t io n
Input/Output, Carrier Sense, Management Data Clock, Master, or GPIO[8].
PU
Carrier sense is used to indicate carrier has been detected on the line.
CRS is not synchronous to INCLK. CRS is used for half-duplex modes
only and is ignored when the port is in full-duplex. This pin is CRS
when the port’s Px_MODE = 0x1 or 0x2. CRS is an output for
Px_MODE = 0x1 and it’s an input for Px_MODE = 0x2.
As a Management Data Clock, in Master mode, this pin is the
reference clock output for the serial management interface (SMI) that
connects to an external SMI slave device, typically external PHYs.
This pin is MDC_PHY when the port’s Px_MODE is not 0x1 or 0x2
and the NO_CPU configuration pin was high at the rising edge of
RESETn.
no
qi
e0
t
64
dz
The Master SMI is used to access registers in any external SMI device
(like a PHY) and it is controllable via switch registers.
Alternatively, this pin becomes GPIO[8], which supports all functions
described in Section 2.3.
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
9x
1q
CRS is internally pulled high via resistor so the pin can be left floating
when unused. The function of this pin is determined by the value of
the port’s Px_MODE pins at the rising edge of RESETn (during
RESETn this pin is an input). This pin is not tri-stated by P0_
ENABLE.
9x
Doc. No. MV-S110663-00 Rev. A
Page 26
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
101
Pin Name
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Pin #
Port 0 xMII Receive Interface (Continued)
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Table 6:
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
d
Pin Description
s
w
ay
D e s c r i p t io n
e0
t
64
dz
Input/Output, Collision, or Management Data I/O, Master, or GPIO[7].
PU
Collision is used to indicate both transmit and receive are occurring at
the same time in half duplex mode. COL is not synchronous to INCLK.
COL is used for half-duplex modes only and is ignored when the port
is in full-duplex. This pin is COL when the port’s Px_MODE = 0x1 or
0x2. COL is an output for Px_MODE = 0x1 and it’s an input for
Px_MODE = 0x2.
As a Management Data I/O, in Master mode, this pin is used to
transfer management data in and out of the device synchronously to
MDC_PHY. This pin requires an external pull-up resistor in the range
of 4.7K to 10K ohm. This pin is MDIO_PHY when the port’s Px_MODE
is not 0x1 or 0x2 and the NO_CPU configuration pin was high at the
rising edge of RESETn1.
When NO_CPU is pulled low (CPU_MANAGED) mode, this pin
becomes GPIO[7].
9x
1q
no
qi
When NO_CPU is pulled high (UN-Managed mode) this pin becomes
MDC_PHY and connects to an external SMI device such as a PHY.
Refer to Section 2.5 for details.
When in CPU attached mode, this signal can be re-configured as
MDIO_PHY by clearing the NormalSmi bit in the Scratch and Misc
registers.
Pr
iv
at
e
Li
m
ite
d
COL is internally pulled high via resistor so the pin can be left floating
when unused. The function of this pin is determined by the value of
the port’s Px_MODE pins at the rising edge of RESETn (during
RESETn this pin is an input). This pin is not tri-stated by P0_
ENABLE.
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
1. The NO_CPU configuration pin is used to determine the initial function of this pin after reset. The pin’s function can
be modified by changing a register (NormalSMI bit in Scratch and Misc registers Index 0x01).
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 27
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Ty p e
P0_COL
/MDIO_PHY
/GPIO[7]
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
100
Pin Name
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Pin #
Port 0 xMII Receive Interface (Continued)
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Table 6:
Pr
iv
at
e
Li
m
ite
Signal Description
d
Table 7:
Pin #
Port 0 xMII Transmit Interface
Pin Name
P0_OUTEN
/P0_VDDOS
Ty p e
D e s c r i p t io n
Typically
Output, PD
Output Enable. Output enable is used to indicate when OUTD[3:0] or
OUTD[1:0] contains frame information. OUTEN is synchronous to
OUTCLK in all modes.
P0_OUTEN is tri-stated during RESETn or when
P0_ ENABLE is low. OUTEN is internally pulled low via resistor so the
pin can be left floating when unused. Use a 4.7K ohm resistor to
P0_VDDO for a configuration high.
Input/Output, Output Clock. OUTCLK is a clock reference for OUTEN and OUTD[3:0].
PU
The speed of OUTCLK is 125 MHz, 50 MHz, 25 MHz or 2.5 MHz
depends on the speed of the Port. The direction of OUTCLK is a function
of the port’s Px_MODE (Port offset 0x00). See the C_Mode register bits
in Port offset 0x00.
m
ite
d
In RGMII mode OUTCLK is used as TXC. In RMII mode OUTCLK is
used as REFCLK.
Pr
iv
at
e
Li
When this port is disabled (by its Px_MODE = 0x6) this pin becomes
GPIO[0].
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
OUTCLK is internally pulled high via resistor so the pin can be left
floating when unused.
Doc. No. MV-S110663-00 Rev. A
Page 28
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
P0_OUTCLK
/P0_TXC
/GPIO[0]
9x
1q
91
no
qi
e0
t
64
dz
P0_OUTEN is a multi-function pin used to configure the device during a
hardware reset. When reset is asserted, this pin become an input and
the configuration information below is latched at the rising edge of
RESETn:
P0_VDDOS
1 = The P0_VDDO pins are powered by 2.5 volts
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
In RGMII mode OUTEN is used as TX_CTL.
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
90
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
d
Pin Description
Pin Name
Ty p e
86
P0_OUTD[2]
/P0_MODE[2]
88
P0_OUTD[1]
/P0_MODE[1]
89
P0_OUTD[0]
/P0_MODE[0]
s
w
ay
Typically Output Data. OUTD[3:0] (or OUTD[1:0] where appropriate) outputs the
Output, PU data to be transmitted from the switch. OUTD is synchronous to
OUTCLK in all modes. In RGMII mode OUTD[3:0] are used as
TXD[3:0]. In RMII mode OUTD[1:0] are used and OUTD[3:2] are
tri-stated.
P0_OUTD are multi-function pins used to configure the device during a
hardware reset. When reset is asserted, these pins become inputs and
the configuration information below is latched at the rising edge of
RESETn as follows:
OUTD[3] = No CPU
OUTD[2:0] = P0_MODE[2:0]
9x
1q
no
qi
e0
t
64
dz
No CPU selects the flow control setting as follows:
0 = CPU is attached
1 = No CPU is attached
When the ‘CPU is attached’ mode is selected, all the ports will be
initialized in the Disabled Port State and the PHYs will be powered down.
This allows software time to boot and fully configure the switch before it
allows packets to flow through it. Whenever the switch is used with a
CPU, the ‘CPU is attached’ mode must be used.
w
ay
s
Pr
iv
at
e
Li
m
ite
d
P0_MODE[2:0] sets Port 0’s Mode of operation as follows:
0x0 = Full Duplex Only MII PHY Mode1
0x1 = MII PHY mode w/output MII CLKs2 at 2.5, 25 or 50 MHz3
0x2 = MII MAC mode w/input MII CLKs
0x3 = Reserved for future use
0x4 = RMII PHY mode w/output P0_OUTCLK at 50 MHz
0x5 = RMII MAC mode w/input P0_OUTCLKs at 50 MHz
0x6 = Port disabled (with its pins tri-stated)4
0x7 = RGMII mode
This mode is identical to P0_MODE 0x1 except the P0_CRS and P0_COL pins are used for other functions.
P0’s MII CLKs refer to both P0_OUTCLK and P0_INCLK.
P0_OUTCLK’s frequency is determined by the port’s ForceSpd and AltSpeed bits (Port offset 0x01).
In this mode many of P0’s pins become GPIO pins.
1q
no
qi
e
0t
64
dz
1.
2.
3.
4.
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
P0_OUTD pins are tri-stated during RESETn or when P0_ ENABLE is
low. OUTD pins are internally pulled high via resistor so the pins can be
left floating when unused. Use a 4.7K ohm resistor to VSS for a
configuration low.
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 29
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
P0_OUTD[3]
/NO_CPU
D e s c r i p t io n
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
85
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Pin #
Port 0 xMII Transmit Interface (Continued)
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Table 7:
Pr
iv
at
e
Li
m
ite
Signal Description
d
Pin Name
Ty p e
Input/Output, General Purpose I/O pins. GPIO[15:9] are general purpose input/output
PU
pins whose direction and data is controllable via switch registers
GPIO[11]
/SW_24Pn
25
GPIO[12]
/GPIO_VDDOS
26
GPIO[13]
27
GPIO[14]
28
GPIO[15]
GPIO[12:11] are the multi-function pins used to configure the device
during a hardware reset. When reset is asserted, these pins become
inputs and the configuration information below is latched at the rising
edge of RESETn:
GPIO[11] = SW_24Pn
GPIO[12] = GPIO_VDDOS
SW_24Pn
0x0 = Configures the device for cascading mode
Cross-chip SERDES on Port 9, and 10 interfaces.
Separate Port Based VLAN between Port 9 and Port 10
Enable configuration of Learn2All
Set FrameMode to DSA mode for Port 9 and Port 10
Force link up for Port 9 and Port 10
Use this mode for a 3 chip ring only.
e0
t
qi
no
9x
1q
0x1 = Normal operation
GPIO_VDDOS
1 = The GPIO_VDDO pins are powered by 2.5V
29
P10_SMODE
Px_SMODE are pins to configure the device for sets the Port’s SERDES
Mode of operation as follows
Pr
iv
Input, PU
ay
s
P9_SMODE
w
3
at
e
Li
m
ite
d
See EE_VDDO for the list of pins that are powered by this rail.
GPIO[15:9] pins are internally pulled high via resistor so the pins can be
left floating when unused. Use a 4.7K ohm resistor to VSS for a
configuration GPIO[12:11] low.
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
0x0 = 2.5 Gbps Operation
0x1 = SGMII/1000X Operation base on PHYDETECT bit in port status
register.
1q
no
qi
e
0t
64
dz
Px_SMODE pins are internally pulled high via resistor so the pins can
be left floating when unused. Use a 4.7K ohm resistor to VSS for a
configuration low.
Doc. No. MV-S110663-00 Rev. A
Page 30
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
23
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
GPIO[9]
GPIO[10]
D e s c r i p t io n
64
dz
21
22
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Pin #
GPIO
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Table 8:
w
ay
s
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
d
Pin Description
Pin #
Pin Name
MDC_CPU
Ty p e
D e s c ri p t i o n
Input
Management Data Clock, Slave. MDC_CPU is the reference clock
input for the serial management interface (SMI) that connects to an
external SMI master, typically a CPU. A continuous clock stream is not
expected. The maximum frequency supported is 20.0 MHz
MDIO_CPU
9x
1q
no
qi
e0
t
19
64
dz
NOTE: MDC_CPU is powered by the GPIO_VDDO pins.
Input/Output Management Data I/O, Slave. MDIO_CPU is used to transfer
management data in and out of the device synchronously to
MDC_CPU. This pin requires an external pull-up resistor in the range of
4.7K to 10K Ω.
The device uses one or all of the 32 possible SMI port addresses (two
modes are supported). The address(es) that are used are selectable
using the Rx_LED/ADDRn configuration pins.
m
ite
d
MDIO_CPU is internally pulled high via a resistor so it can be left
floating when unused.
Input/Open INTn is an active low, open drain pin that is asserted to indicate an
Drain Output unmasked interrupt event occurred. A single external pull-up resistor is
required somewhere on this interrupt net for it to go high when it is
inactive.
Pr
iv
INTn
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
18
at
e
Li
NOTE: MDIO_CPU is powered by the GPIO_VDDO pins.
The INTn pin will go active low which indicates the SMI interface
(MDC_CPU/MDIO_CPU pins) is available for use.
102
TEST
Input, PD
Test Input. Test is used to place the chip into its manufacturing test
modes. Do not connect this pin to anything other than VSS or improper
device operation will result.
Test should be pulled or tied low.
HSDACP
HSDACN
79
TST_PT
O
AC Test Points (Positive and Negative). The HSDACP/N outputs are
used for AC Test Points. These pins must be connected to a 50 ohm
termination resistor to VSS. These pins can be left floating if not used
for clock cascade, IEEE testing, and debug test points are not of
importance.
O
DC Test Point. The TST_PT pin should be left floating if not used.
1q
no
qi
e
0t
64
dz
78
77
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 31
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
MDC_CPU is internally pulled high via a resistor so it can be left
floating when unused.
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
The CPU’s SMI interface is used to access the device’s registers but it
cannot be used until the device’s INTn pin becomes active low
(indicating the Register Loader is done processing the EEPROM or
that no EEPROM was present).
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
20
System & Register Access
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Table 9:
w
ay
s
Pr
iv
at
e
Li
m
ite
Signal Description
d
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
Table 10: Power & Ground
Pin #
P0_VDDO
Ty p e
D e s c r i p t io n
Power
Power to Port 0’s interface. P0_VDDO must be connected to:
2.5V for 2.5V I/O or 1.8V for 1.8V I/O (and P0_VDDOS must be
configured accordingly – see P0_OUTEN).
24
GPIO_VDDO
Power
Power to LED, EEPROM interface and the RESETn pin. EE_VDDO must
be connected to 3.3V for 3.3V I/O.
Power
Power to GPIO[15:9], MDC_CPU, and MDIO_CPU interface pins.
GPIO_VDDO must be connected to: 2.5V for 2.5V I/O or 1.8V for 1.8V
I/O (and GPIO_VDDOS must be configured accordingly – see GPIO[12]).
1.8V configuration will be automatically detected by internal voltage
sensing logic.
e0
t
69
60
51
42
141
132
123
114
P[8:1]_AVDD33
37
72
75
109
144
3.3V power to analog core used to power each Gig PHY interface.
AVDD15
Power
1.5V power to analog core.
32
105
P[10:9]_AVDD15
Power
1.5V power to analog core used to power the SERDES interface.
82
AVDD15_XTAL
4
16
36
84
92
108
VDD_CORE
no
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
9x
1q
Power
1.5V power to analog core used to power on-chip XTAL.
Power
Power to digital core.
1.05 for Commercial temp operation
1.1 for Industrial temp operation.
Industrial temp operation requires industrial temperature part number. For
details, refer to Table 52, 88E6390/88E6190/88E6290 Part Order
Options, on page 94.
VSS
Ground
Ground to the device. The device is packaged in the 144 pin package
with an E-PAD (exposed die pad) on the bottom of the package. This
E-PAD must be soldered to VSS as it is the main VSS connection on the
device.
1q
no
qi
e
0t
64
dz
E-PAD
qi
Power
Doc. No. MV-S110663-00 Rev. A
Page 32
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
EE_VDDO
64
dz
7
14
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
1.8V configuration will be automatically detected by internal voltage
sensing logic.
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
87
95
Pin Name
qi
e
no
1q
9x
ay
s
w
at
e
Pr
iv
ite
d
m
Li
qi
Pin #
35
Pin Name
NC
Copyright © 2018 Marvell
January 23, 2018
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
64
dz
e0
t
Table 11: No Connect
Document Classification: Proprietary Information
CONFIDENTIAL
Ty p e
D e s c r i p t io n
-
No Connect. Do not connect this pin to anything. This pin must be left
unconnected.
Doc. No. MV-S110663-00 Rev. A
Page 33
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9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
dz
64
0t
no
9x
1q
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
s
w
ay
at
Pr
iv
e
Li
m
d
ite
Signal Description
Pin Description
d
w
ay
s
Pin Assignment List
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
1.2
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
Pin Name
37
AVDD15
93
P0_INCLK/GPIO[1]
72
AVDD15
96
P0_IND[0]/GPIO[3]
75
AVDD15
97
P0_IND[1]/GPIO[4]
109
AVDD15
98
P0_IND[2]/GPIO[5]
144
AVDD15
99
P0_IND[3]/GPIO[6]
82
AVDD15_XTAL
94
P0_INDV/GPIO[2]
6
C2_LED/LED_SEL
91
P0_OUTCLK/P0_TXC/GPIO[0]
5
C3_LED/EEEDis
89
P0_OUTD[0]/P0_MODE[0]
9
EE_CLK/C0_LED/FLOW
88
P0_OUTD[1]/P0_MODE[1]
EE_DOUT/C1_LED
86
P0_OUTD[2]/P0_MODE[2]
EE_VDDO
85
P0_OUTD[3]/NO_CPU
14
EE_VDDO
90
P0_OUTEN/P0_VDDOS
22
GPIO[10]
87
P0_VDDO
23
GPIO[11]/SW_24Pn
95
P0_VDDO
25
GPIO[12]/GPIO_VDDOS
114
P1_AVDD33
26
GPIO[13]
111
P1_MDIN[0]
27
GPIO[14]
112
P1_MDIN[1]
28
GPIO[15]
116
P1_MDIN[2]
21
GPIO[9]
117
P1_MDIN[3]
24
GPIO_VDDO
110
P1_MDIP[0]
77
HSDACN
113
P1_MDIP[1]
78
HSDACP
115
P1_MDIP[2]
18
INTn
118
P1_MDIP[3]
20
MDC_CPU
123
P2_AVDD33
19
MDIO_CPU
120
P2_MDIN[0]
35
NC
121
P2_MDIN[1]
100
P0_COL/MDIO_PHY/GPIO[7]
125
P2_MDIN[2]
101
P0_CRS/MDC_PHY/GPIO[8]
126
P2_MDIN[3]
e0
t
ite
d
m
Li
at
e
Pr
iv
ay
s
no
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
7
9x
1q
8
9x
Doc. No. MV-S110663-00 Rev. A
Page 34
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Pin
Number
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Pin Name
64
dz
Pin
Number
qi
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 12: Pin List—Alphabetical by Signal Name
d
ite
m
Li
119
P2_MDIP[0]
43
P5_MDIP[2]
122
P2_MDIP[1]
46
P5_MDIP[3]
124
P2_MDIP[2]
51
P6_AVDD33
127
P2_MDIP[3]
48
P6_MDIN[0]
132
P3_AVDD33
49
P6_MDIN[1]
129
P3_MDIN[0]
53
P6_MDIN[2]
130
P3_MDIN[1]
54
P6_MDIN[3]
134
P3_MDIN[2]
47
P6_MDIP[0]
135
P3_MDIN[3]
50
P6_MDIP[1]
128
P3_MDIP[0]
64
dz
52
P6_MDIP[2]
131
P3_MDIP[1]
qi
55
P6_MDIP[3]
P3_MDIP[2]
60
P7_AVDD33
136
P3_MDIP[3]
57
P7_MDIN[0]
141
P4_AVDD33
58
P7_MDIN[1]
138
P4_MDIN[0]
62
P7_MDIN[2]
139
P4_MDIN[1]
63
P7_MDIN[3]
143
P4_MDIN[2]
56
P7_MDIP[0]
1
P4_MDIN[3]
59
P7_MDIP[1]
137
P4_MDIP[0]
61
P7_MDIP[2]
140
P4_MDIP[1]
64
P7_MDIP[3]
142
P4_MDIP[2]
69
P8_AVDD33
2
P4_MDIP[3]
66
P8_MDIN[0]
42
P5_AVDD33
67
P8_MDIN[1]
39
P5_MDIN[0]
71
P8_MDIN[2]
40
P5_MDIN[1]
73
P8_MDIN[3]
44
P5_MDIN[2]
65
P8_MDIP[0]
45
P5_MDIN[3]
68
P8_MDIP[1]
38
P5_MDIP[0]
70
P8_MDIP[2]
41
P5_MDIP[1]
74
P8_MDIP[3]
Pin Name
1q
no
qi
e
0t
64
dz
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 35
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
e0
t
no
9x
1q
133
Pin
Number
s
P in N a m e
w
ay
Pin
Number
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Pr
iv
at
e
Pin Assignment List
d
105
P9_AVDD15
81
XTAL_IN
103
P9_RXN[0]
80
XTAL_OUT
104
P9_RXP[0]
3
P9_SMODE
106
P9_TXN[0]
107
P9_TXP[0]
32
P10_AVDD15
30
P10_RXN[0]
31
P10_RXP[0]
29
P10_SMODE
33
P10_TXN[0]
Pin Name
R0_LED/ADDR[0]n
13
R1_LED/ADDR[1]n
12
R2_LED/ADDR[2]n
11
R3_LED/ADDR[3]n
10
R4_LED/ADDR[4]n
17
RESETn
76
RSET
83
SE_SCLK
102
TEST
79
TST_PT
4
VDD_CORE
16
VDD_CORE
36
VDD_CORE
84
VDD_CORE
92
VDD_CORE
108
VDD_CORE
EPAD
VSS
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
15
ite
d
P10_TXP[0]
9x
Doc. No. MV-S110663-00 Rev. A
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Document Classification: Proprietary Information
Copyright © 2018 Marvell
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9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
64
dz
e0
t
qi
no
34
Pin
Number
s
Pin Name
w
ay
Pin
Number
9x
1q
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Pr
iv
at
e
Li
m
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
d
Managed switch
Application Examples
The 88E6390, 88E190 and the 88E6290 have 8 integrated Ethernet Phys, 2 Single lane SERDES
ports. and 1 xMII digital port. On the 88E6190 and 88E6390, the integrated PHYs are Trippe speed
1000BASE-T. The 88E6290 the integrated PHYs are Dual speed 100BASE-Tx/10BASE-T. The
integrated PHYs are the latest voltage mode PHYS with Energy Efficient Ethernet capabilities. The
SERDES ports can emulate 1000BASE-X/SGMII/2.5G modes.
Figure 6 is an example of how this device can be used in a managed switch application that
supports the following interfaces:
Up to eight PHY ports
Up to 2 SERDES ports
2 (SFP Small Form Plug) cages which can be used for optical transceivers.
xMII connection to optional management CPU to implement bridge management protocols such
as IGMP MLD 802.1X.

64
dz


1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
9x
1q
no
qi
e0
t

Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 37
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Managed switch
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
2.1
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
2
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
Application Examples
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5 xMII
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Figure 6: Managed Switch 8GE Plus 2 SFP ports
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
CPU
P9
SFP
p10
SFP
qi
no
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
9x
1q
RJ45
1q
no
qi
e
0t
64
dz
The SFP cages typically accommodate fiber modules. There is no method for the SERDES port to
auto detect the type of module inserted. When running 2.5G mode the SFP fiber modules must be
rated for the speed.
9x
Doc. No. MV-S110663-00 Rev. A
Page 38
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
P1 -P8
e0
t
64
dz
88E6390 /
88E6190 /
88E6290
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
P0
d
Managed switch
s
Router Gateway
w
ay
2.1.1
Pr
iv
at
e
Li
m
ite
Application Examples
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
In the router gateway application the ports 1-8 are used for LAN. Ports 10 is used for a WAN
connection. All LAN and wan traffic can be isolated with port based VLAN ensure that LAN to WAN
traffic is routed via the CPU attached to port 10.
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Figure 7: Service or Access router
qi
e0
t
64
dz
Port 9 (2.5G Mode)
P10 (2.5G Mode)
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
2.5G
4 Speed
PHY
ite
d
P1 -P8
m
9x
1q
no
88E6390X/
88E6190X
1q
no
qi
e
0t
64
dz
RJ45
9x
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
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CPU
s
w
ay
Device Physical Interfaces
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
2.2
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
P ort 1000BAS E-T RG M II R M II
(Tr ipl e
Sp eed)
0
x
1-8
MI I/
20 0 Mbp s
M II
x
2. 5G
S G MI I
1000 BA SE -X
x
x
x
x
9-10
100 Base TX
( Dua l sp eed)
x
64
dz
0
R GM II R M II
x
2.5G
SG M II
10 00BA S E-X
x
x
x
x
e0
t
1-8
M II/
200 Mb ps
M II
2.2.1
9x
1q
no
qi
9-10
Port 0 Configuration Options
Table 15 indicates all supported port 0 xMII modes. Some unused port 0 pins can be used as GPIO
signals.
ite
d
Table 15: Port 0 Configuration Summary
Mode
Notes
000
Full-duplex MII PHY
COL and CRS are not used
001
MII PHY
Supports connection to MAC
010
MII MAC
Supports connection to external PHY type device
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
P0_MODE[2:0]
100
101
110
OUTCLK = 50 MHZ
RMII MAC
OUTCLK is a 50 MHZ input.
Disabled
P0 is not used and pins are tri-stated until
configured for other functions via register access.
RGMII
Supports connection to external CPU and PHY
1q
no
qi
e
0t
64
dz
111
RMII PHY
Doc. No. MV-S110663-00 Rev. A
Page 40
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
P ort
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Table 14: 88E6290 Interface summary
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 13: 88E6390,88E6190 Interface summary
d
m
ite
Application Examples
s
MII MAC Mode
w
ay
2.2.2
Pr
iv
at
e
Li
Device Physical Interfaces
INCLK
IND[3:0]
INDV
CRS
COL
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
RX_CLK
RXD[3:0]
RX_DV
CRS
COL
64
dz
PHY
Device with
MII Interface
9x
1q
no
qi
e0
t
Port 0 acting
as a MAC
OUTCLK
TX_CLK
OUTD[3:0]
OUTEN
TXD[3:0]
at
e
Li
m
ite
d
TX_EN
TX_ER
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
.
If COL and CRS are not used, use a 4.7k pull-down resistor.
Note
When configured in MII MAC mode and no clock is provided, the link should be forced
down via switch port register 1.
1q
no
qi
e
0t
64
dz
Note
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 41
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ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Figure 8: MII MAC Mode
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
In MII MAC Mode, sometimes called ‘Forward MII mode, P0_INCLK and P0_OUTCLK are inputs.
The clock provided by the attached device can be from DC-50 MHz. This mode is typically used to
support connections to external PHYs. Figure 8 is an example of MII MAC mode when connected to
a device emulating a PHY.
s
MII PHY Mode
w
ay
2.2.3
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Figure 9: MII PHY Interface Pins
CPU Device
with MII MAC
9x
1q
no
qi
e0
t
64
dz
Port 0 acting
as PHY
RX_CLK
OUTCLK
OUTD[3:0]
OUTEN
RXD[3:0]
RX_DV
w
MII 200 Mbps Mode
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
2.2.4
ay
s
Pr
iv
at
e
Li
m
ite
d
CRS
COL
RX_ER
1q
no
qi
e
0t
64
dz
When port 0 is configured in MII MAC or MII PHY mode, it can configured to run at 200 Mbps mode.
This is done via register access. In 200 Mbps mode, the TX/RX clocks run at 50 MHZ.
Doc. No. MV-S110663-00 Rev. A
Page 42
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Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
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TXD[3:0]
TX_EN
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
TX_CLK
INCLK
IND[3:0]
INDV
CRS
COL
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
MII PHY Mode is sometimes called ‘Reverse MII’ mode, This mode is typically used to connect the
switch port to a CPU. In this mode, P0_INCLK and P0_OUTCLK are both outputs. Figure 9 is an
example of using port 0 MII PHY mode. INCLK and OUTCLK output frequency is 2.5 MHZ for 10
Mbps, 25 MHz for 100 Mbps and 50 MHz in 200 Mbps mode. COL and CRS are only used when
operating in half-duplex mode. RX_ER should be tied to ground because the switch does not
generate this signal.
d
m
ite
Application Examples
w
ay
s
RGMII Mode
64
dz
Figure 10: RGMII Interface Pins
9x
1q
no
qi
e0
t
Px_INCLK
Px_IND[3:0]
Px_INDV
RXC
RXD[3:0]
RX_CTL
External PHY
Pr
iv
TXD[3:0]
TX_CTL
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
Px_OUTD[3:0]
Px_OUTEN
at
e
TXC
ay
s
Px_OUTCLK
Li
m
ite
d
Port 0
Copyright © 2018 Marvell
January 23, 2018
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Document Classification: Proprietary Information
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ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
In RGMII Mode, Port 0 emulates a Reduced Gigabit Media Independent Interface (RGMII) so that it
can be directly connected to an external RGMII-based Gigabit PHY or CPU. When the RGMII mode
is selected, transmit control (P0_OUTEN) is presented on both clock edges of Px_OUTCLK.
Receive control (Px_INDV) is presented on both clock edges of Px_INCLK or Px_INCLK. A triple
speed interface is supported in RGMII mode (i.e., 10, 100 and 1000). When the PHY completes
auto-negotiation and brings the link up, the auto-negotiated speed, duplex and flow control
information must be moved from the PHY to the MAC so the MAC matches the PHY’s link state. This
is done automatically by the PPU if the port’s PHYDetect bit is set to a one (Port offset 0x00). The
default speed and duplex is 1000 Mbps/full-duplex. The speed can be changed at any time with port
register 1. RGMII supports an internal transmit and receive delay mechanism which allows for all
traces to be routed at the same length without adding additional timing skew in the board layout.
RGMII is a symmetrical interface therefore there is no need for separate MAC/PHY emulation. Refer
to Figure 10 for RGMII connections.
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2.2.5
Pr
iv
at
e
Li
Device Physical Interfaces
s
RMII MAC Mode
w
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2.2.6
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Li
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88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
RMII MAC mode supports 10 or 100 Mbps full or half-duplex. RMII mac mode is typically used to
connect an external PHY but can be used for other applications. In RMII MAC mode, REFCLK is an
input and is expected to be 50 MHz for all data rates. Refer to Figure 11 for RMII MAC connection to
an external PHY.
Px_IND[1:0]
Px_INDV
RX_ER
RMII PHY
qi
e0
t
64
dz
Port 0
9x
1q
no
Px_OUTCLK
Px_OUTD[1:0]
REFCLK
TXD[1:0]
TX_EN
1q
no
qi
e
0t
64
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ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
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Px_OUTEN
9x
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RXD[1:0]
CRS_DV
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Figure 11: RMII MAC Interface Pins
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Application Examples
s
RMII PHY Mode
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2.2.7
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Li
Device Physical Interfaces
ijt
M 1r5
A 5y
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VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
In RMII PHY mode, REFCLK (P0_OUTCLK) is an output. OUTCLK is always 50 MHZ regardless of
configured data interface speed. Figure 12 is an example of RMII PHY mode connections.
64
dz
RMII MAC
REFCLK
RXD[1:0]
CRS_DV
RX_ER
ite
d
9x
1q
no
qi
e0
t
Px_OUTCLK
Px_OUTD[1:0]
Px_OUTEN
m
If COL and CRS are not used, they should be pulled- down with a 4.7 kohm resistor.
1000BASE-T PHY Interface
ay
s
2.2.8
Pr
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Note
2.2.9
ijt
M 1r5
A 5y
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VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
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D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
On 88E6390 and 88E6190 Ports 1-8 are integrated Gigabit PHY interfaces. On the 88E6290 Ports
1-8 are 100Base TX PHYs. All integrated PHYs support IEEE 802.3az Energy Efficient Ethernet
standard. This allows the PHYs to enter a low power idle state when there is no traffic in either
direction while still maintaining the link. The MAC inside the switch works the same way regardless
of the external interface being used. Each PHY’s Link, Speed, Duplex and Flow Control information
is automatically communicated to the MAC. This information can be read on the Switch Port status
register. The PHY core registers are not directly accessible via the SMI interface. All access to PHY
registers must be performed indirectly via SMI_PHY_COMMAND and SMI_PHY_DATA registers.
Other than customer specific PHY configuration there should be no reason for a CPU to
continuously access internal PHY’s registers.
SERDES modes
1q
no
qi
e
0t
64
dz
Port 9 and 10 have 1 SERDES lane each, P9_SMODE and P10_SMODE mode selects between
1000BASE-X/SERDES and 2.5G SERDES modes. Port 9 and 10 can be configured with register
access to support other modes including SGMII MAC or PHY Modes.
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
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Port 0
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TXD[1:0]
TX_EN
Px_IND[1:0]
Px_INDV
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Figure 12: RMII PHY Interface
s
SGMII MAC or PHY Mode
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2.2.10
Pr
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m
ite
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88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
SGMII MAC mode is mode is used to connect a SERDES port to an external PHY. When the link
state on the external PHY’s media changes the new link state is communicated to switch MAC with
in-band auto negotiation to the MAC.
SGMII mode supports 10/1000/1000 Mbps full or half-duplex. It uses the same 8B/10 encoding that
1000BASE-X uses. Lower speeds are supported by repeating the same symbol 10 times for 100
Mbps and 100 times to support 10 Mbps.
1000BASE-X is typically used to connect a switch port to an SFP fiber optics module. It can also be
used to connect to another switch or CPU. 1000BASE-X supports auto negotiation bypass mode.
This means the link can be established by receiving valid symbols. If the connected device only
supports SGMII mode a link can be established by disabling auto negotiation on the connected
device.
Port Status Registers
64
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2.2.12
9x
1q
no
qi
e0
t
Each switch port has a status register that reports information about that port’s PHY, SERDES or
(x)MII interface. These registers can be used to check the current port configuration and link state.
The C_MODE bits indicate the current configuration of the port. This is especially useful for auto
media application to see which interface is currently internally connected to a given switch port. The
port status register also indicates the speed duplex and if flow control is used.
2.2.13
PHY Polling Unit (PPU)
ijt
M 1r5
A 5y
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VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
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A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
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This device has an internal PHY polling unit. Clause 22 PHYs can be connected to MDC_PHY and
MDIO_PHY pins. The PPU will automatically poll external PHYs using standard clause 22 defined
PHY registers and update speed duplex and flow control in the MAC. By default the PPU is
expecting the PHY connected to port 0 to be at external device address 0x0, Port 9 to be at external
SMI address 0x9 and port 10 to be at SMI address 0x0A. After reset the PPU will attempt to read the
registers on external PHYs. If PHY responds to SMI address 0x0 0x9 or 0xA, It will automatically set
the PHY detect bit in port register 0 of the corresponding port. The PPU will then continuously
monitor the link status of the PHY. If software does not want the PPU to perform this function it can
clear the PHY detect bit which will cause the PPU stop polling that PHY at the end of the next poling
cycle. The PPU polls PHY register 0,1,4,5,9,10 to determine the speed link duplex and flow control
state of the PHY.
The SmiSetup function in the SMI_PHY_COMMAND register can be used to change the relationship
between switch port and external PHY address. See functional spec for details.
Internal PHYs and External PHYs registers are accessed via the SMI_PHY_COMMAND register.
This part has an internal SMI bus for accessing internal PHYs and an external SMI bus for accessing
PHYs via the MDC_PHY and MDIO_PHY signals. This allows an external PHY to share the same
SMI address with an external PHY without address conflicts.
Proprietary and clause 45 managed PHYs can be connected to MDC_PHY and MDIO_PHYs
however the PPU cannot automatically manage them. In these usage cases the IMP or an external
CPU must be used to communicate the state of the external PHY to the switch port using switch port
register 1 and port register 2.
1q
no
qi
e
0t
64
dz
If NO_CPU is pulled low, the device is in CPU attached mode. The polling of external PHYs will not
work until the NormalSMI bit in the scratch and misc. registers is cleared to 0. Refer to the release
notes for the proper procedure for software to re-initialize the PPU. When the MDC_PHY and
MDIO_PHY signals are enabled after reset IMP code or CPU must manually set the PHY detect bit.
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1000BASE-X
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2.2.11
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SGMII PHY mode is typically used when the switch port is connected to a CPU or another switch.
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Application Examples
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General Purpose I/O (GPIO) Configuration
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M 1r5
A 5y
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EN 5
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2.3
Pr
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General Purpose I/O (GPIO) Configuration
This device has 16 GPIO signals. GPIO[15:9] are dedicated GPIOs. GPIO[8:0] are available on Port
0 interface signals. Table indicates GPIO availability in all supported xMII modes.
000
Full-duplex MII
PHY
G P I O Av a il a b l e o n P o r t 0
GPIO [8:7]
When NO_CPU signal is pulled low at reset,
These signals are defined as GPIO[8:7]
By clearing the NormalSMI bit (Global 2
Register 0x1A Index 0x2) the affect of the
NO_CPU signal is inverted.
MII PHY
010
MII MAC
None Available
100
RMII PHY
GPIO [8:7], GPIO [6:5], GPIO [1]
101
RMII MAC
GPIO [8:7], GPIO [6:5], GPIO [1]
110
Disabled
GPIO[8:0]
111
RGMII
GPIO [8;7]
None Available
ite
d
When NO_CPU signal is pulled low at reset,
These signals are defined as GPIO[8:7]
Li
m
no
qi
e0
t
001
9x
1q
64
dz
When NO_CPU signal is pulled high at reset
these signals are defied as
MDC_PHY,MDIO_PHY.
w
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s
Pr
iv
at
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When NO_CPU signal is pulled high at reset
these signals are defied as
MDC_PHY,MDIO_PHY.
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
By clearing the NormalSMI bit (Global 2
Register 0x1A Index 0x2) the affect of the
NO_CPU signal is inverted.
Once configured as a GPIO, the pin can be programmed to the following functions:
P0_ENABLE
General Purpose Input
General Purpose Output
Timing Application Interface (TAI)




• PTP Trigger Output (PTP_TRIG)
• PTP Event Request Input (PTP_EVREQ)
• PTP External Clock Input (PTP_EXTCLK)
Synchronous Ethernet Recovered Clock 0 Output (SE_RCLK0)
Synchronous Ethernet Recovered Clock 1 Output (SE_RCLK1)
125 MHz Clock output
Port Stall – can be used to stall the transmission of a specific port (or ports) as needed


64
dz

1q
no
qi
e
0t

Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
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x M I I S e t ti n g
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P5_MODE
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Table 16: Port 0 GPIO Assignments
Pr
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88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
2.3.1
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
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L, ru8
U vh
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D -kb
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0d In
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These functions can be programmed through the Scratch and Misc Register at Switch Global 2,
Offset 0x1A (see Functional Specification).
Configuring GPIO as a Port Enable Pin
To use a GPIO as a Port Enable pin, the GPIO must first be configured as an input.
9x
1q
no
qi
e0
t
Figure 13: GPIO Enable Example
GPIO[0]
0x0
0x1
Li
0xE
0xF
at
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“1"
Pr
iv
GPIO[14]
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P0_ENABLE
1q
no
qi
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0t
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ijt
M 1r5
A 5y
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VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
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D -kb
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5e Tru
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42 xa
0d In
0a fo
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Port’s
Enable Select
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64
dz
For example, setting the Enable Select to 0x0 selects GPIO 0, 0x1 selects GPIO 1, etc. Setting the
bits to 0xF connects the enable function to a logic high, enabling the interface. Refer to Figure 13 for
a configuration diagram. When the port does not have any GPIO selected the input state to
Px_Enable is 1 so the link will be up if the PHY Detect bit in port register 0=0. When the PHY detect
bit is 1 the link state will be driven by the PPU results.
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
To select the specific GPIO to be used as an enable pin, program the xMII port’s Enable Select
register (Port Offset 0x1F, bits 15:12) to the number of the GPIO pin that will be used as the enable
pin.
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Each of the GPIO pins has the capability to be used as the P0_Enable pin for the xMII interfaces
(Port 0) which can drive the link state of the port. When GPIO is used as P0_Enable the xMII output
is tristated.
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Application Examples
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LED Interface
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M 1r5
A 5y
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VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
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A 2*
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5e Tru
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42 xa
0d In
0a fo
2.4
Pr
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LED Interface
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The device uses a matrix LED interface allowing each PHY port to have up to two LEDs. The
cathode of each LED is connected to a single row signal (Rx_LED). The anode of each LED is
connected to a single column signal (Cx_LED). The physical LEDs on the device pins are organized
as 5 rows with 4 columns. Table 17 shows the port to physical mapping.
C2_LED
C 3_ L E D
R0_LED
Port 1, LED 0
Port 1, LED 1
Port 2, LED 0
Port 2, LED 1
R1_LED
Port 3, LED 0
Port 3, LED 1
Port 4, LED 0
Port 4, LED 1
R2_LED
Port 5, LED 0
Port 5, LED 1
Port 6, LED 0
Port 6, LED 1
R3_LED
Port 7, LED 0
Port 7, LED 1
Port 8, LED 0
Port 8, LED 1
R4_LED
Port 9, LED 0
Port 9, LED 1
Port 10, LED 0
Port 10, LED 1
9x
1q
no
qi
e0
t
The column signals (Cx_LED) are also shared with the EEPROM interface, and the architecture
allows for the LEDs and EEPROM to operate at the same by time multiplexing the bus into 6 time
cycles (C0_LED, C1_LED, C2_LED, C3_LED, and EEPROM). This prevents EEPROM access from
interfering with LED operation and vice versa.
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
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Refer to Figure 14 for EEPROM LED design.
9x
Copyright © 2018 Marvell
January 23, 2018
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Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
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C1_LED
64
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C0_LED
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Table 17: LED Mapping
Pr
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88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
LED Sink
10ma Pad
R2_LED Pin
LED Sink
10ma Pad
R1_LED Pin
LED Sink
10ma Pad
R0_LED Pin
w
ay
9x
1q
LED Source
50ma Pad
no
qi
e0
t
64
dz
Possible 2 color LED
location per port – must be
3-wire common cathode
EE_CLK/C0_LED Pin
A0
VCC
A1
MODE/WCn
A2
SCL
I/O Pad
50ma Source
EE_DOUT/C1_LED Pin
LED Source
50ma Pad
C2_LED Pin
ite
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LED Source
50ma Pad
Li
SDA
24Cxxx
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
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Pr
iv
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VSS
m
C3_LED Pin
1q
no
qi
e
0t
64
dz
The EEPROM type can be 24C32-24C512
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Copyright © 2018 Marvell
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R3_LED Pin
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LED Sink
10ma Pad
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
R4_LED Pin
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
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A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
LED Sink
10ma Pad
s
Figure 14: LEDs plus 2 wire EEPROM
d
LED Interface
s
LED Options
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2.4.1
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Application Examples
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Each port supports up to two LEDs that can be configured individually to support many different
options. Please note some functions are not supported on all LEDs.
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









64
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
e0
t

9x
1q
no
qi


Link/Act/Speed by Blink Rate3 (off = no link, on = link, blink = activity,
blink speed = link speed4)
100/Gb Link/Act (off = no link, on = 100 or Gb link, blink = activity)
Gb Link/Act (off = no link, on = Gb link, blink = activity)
Link/Act (off = no link, on = link, blink = activity)
Duplex/Collision (off = half-duplex, on = full-duplex, blink = col)
10/Gb Link/Act (off = no link, on = 10 or Gb link, blink = activity)
Link (off = no link, on = link)
10 Link (off = no link, on = 10 link)
10 Link/Act (off = no link, on = 10 link, blink = activity)
100/Gb Link (off = no link, on = 100 or Gb link)
PTP Act (blink on = PTP activity) - not valid on 88E6190 & 6190X
Force Blink
Force Off
Force On
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92




Pr
iv
at
e

m

Li
10/100 Link/Act (off = no link, on = 10 or 100 link, blink = activity)
10/100 Link/Act (off = no link, on = 10 or 100 link, blink = activity)
Gb Link (off = no link, on = Gb link)
Link/Act (off = no link, on = link, blink = activity)
10/Gb Link/Act (off = no link, on = 10 or Gb link, blink = activity)
10/Gb Link (off = no link, on = 10 or Gb link)
Gb Link/100 Blink (off = no link or 10 Link, blink = 100 Link, on = Gb
Link)
100 Link (off = no link, on = 100 link)
100 Link/Act (off = no link, on = 100 link, blink = activity)
10/100 Link (off = no link, on = 10 or 100 link)
PTP Act (blink on = PTP activity) - not valid on 88E6190 & 6190X
Force Blink
Force Off
Force On

ite
d
Port 1-8 LED1 can be configured in one of the following modes:

ay
s

ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w







1q
no
qi
e
0t
64
dz
The LED select configuration signal determines the value of port register 0x16 Index 0x0
Table 18,Table 19 and Table 20 indicates the default behavior of the LEDs for each supported
hardware configuration. The LED configuration can be changed at any time with register access.
9x
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 51
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Port 1-8 LED0 can be configured in one of the following modes:
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
LED 0
LED 1
1
0x2
Gb Link/Act:
off = No link
on = Gb link
blink = Activity
10/100 Link/Act
off = No link
on = 10/100 link, blink = Activity)
0
0x3
Link/Act:
off = No link
on = Link
blink = Activity
0x3 = Gb Link (off = no link, on = Gb
link)
64
dz
Table 19: Port 9 Hardware Reset LED configuration
LED Mode
(Port 9 Register 0x16 Index
0x0)
LED 0
LED 1
0x2
Port 0 Link/Activity
Port 10 Link Activity
0x3
Port 9 Link/Activity
Combined Link/Activity for ports
1-8
0
ite
d
Table 20: Port 10 Hardware Reset LED configuration
m
1
9x
1q
no
qi
e0
t
LED_SEL
LED Mode
(Port register 0x16)
LED 0
LED 1
1
0x2
PTP Activity
Port 9 Link/Activity
0
0x3
Port 10 Link Activity
at
e
Pr
iv
ay
s
w
Port Link/Activity
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
2.4.2
Li
LED_SEL
Special LEDs
1q
no
qi
e
0t
64
dz
Special LEDs are used to display the Link/Activity status on a group of ports.This device supports 4
Special LED groups. A special LED group can be assigned to LED 0 or LED 1 on any port. A typical
applicator where Special LEDs are used is all the LAN ports are combined into a single LED. A
special LED group can be assigned to more than one LED. See LED control registers in the
Functional specification.
Doc. No. MV-S110663-00 Rev. A
Page 52
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Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
LED Mode
(Port 1-8 register 0x16
Index 0x0)
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
LED_SEL
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 18: Port 1-8 Hardware Reset LED configuration
d
m
ite
Application Examples
w
ay
s
Connection of external PHYs
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
2.5
Pr
iv
at
e
Li
Connection of external PHYs
2.5.1
Connection to 1000BASE-T PHY
SGMII
PHY
9x
1q
no
qi
e0
t
64
dz
Port 9
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Figure 15: Typical SGMII connection to external PHY connections
Port 0x10
SGMII
PHY
MDC_PHY
ay
s
Pr
iv
at
e
Li
m
ite
d
MDIO_PHY
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
Figure 16: Typical external 10G PHY connection
RXAUI
Port 9
PHY
RXAUI
Port 0x10
PHY
MDC_PHY
dz
MDIO_PHY
1q
no
qi
e
0t
64
.
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 53
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Figure 15 represents a typical connection to an external 1000BASE- T PHY using SGMII on ports 9
and 10. Unused SERES lanes can be used in auto media detect mode with ports 2-7. Depending on
trace length, if multiple PHYs are connected, a buffer on MDC_PHY is advisable.
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Port 0, Port 9 and Port 10 can be connected to external PHYs. The PHY polling unit can be used to
poll any standard 802.3 Clause 22 compliant PHY. The PHY polling unit communicates the link,
speed, duplex, and flow control state of the PHY. After reset the PPU will poll SMI address 0x00 for
port 0, 0x09 for port 9 and 0x0A for port 10. With register access, the association between external
SMI address and switch port can be changed by using the SmiSetup operation in Global 2. An
external PHY’s SMI addresses can be any PHY address between 0 and 0x1F.
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
3
Electrical Specifications
3.1
Absolute Maximum Ratings
Parameter
Min
Ty p
Max
U n i ts
VDD(3.3)
Power Supply Voltage on any 3.3V signal with
respect to VSS
-0.5
3.3
+3.6
V
VDD(2.5)
Power Supply Voltage on any 2.5V signal with
respect to VSS
-0.5
2.5
+3.6 or VDD(3.3)
+0.51
whichever is less
V
VDD(1.8)
Power Supply Voltage on any 1.8V supply with
respect to VSS
-0.5
1.8
+3.6 or
VDD(2.5)
+0.52
whichever is less
V
VDD(1.5)
Power Supply Voltage on any 1.5V supply with
respect to VSS
-0.5
1.5
+3.6 or
VDD(1.8)
+0.53
whichever is less
V
VDD(1.1)
Power Supply Voltage on any 1.05V supply
with respect to VSS
-0.5
1.1
1.1(I-grade)
VPIN
Voltage applied to any input pin with respect to
VSS
TSTORAGE
Storage temperature
Pr
iv
at
e
Li
m
ite
d
9x
1q
no
qi
e0
t
64
dz
Symbol
V
-0.5
+3.6 or
VDDO_PIN5
+0.56
whichever is less
V
-55
+1257
°C
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
+3.6 or
VDD(1.5)
+0.54
whichever is less
1q
no
qi
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0t
64
dz
1. VDD(2.5) must never be more than 0.5V greater than VDD(3.3) or damage will result. Power must be applied to VDD(3.3) before or at the
same time as VDD(2.5).
2. VDD(1.8) must never be more than 0.5V greater than VDD(2.5) or damage will result. Power must be applied to VDD(2.5) before or at the
same time as VDD(1.8).
3. VDD(1.5) must never be more than 0.5V greater than VDD(1.8) or damage will result. Power must be applied to VDD(1.8) before or at the
same time as VDD(1.5).
4. VDD(1.1) must never be more than 0.5V greater than VDD(1.5) or damage will result. Power must be applied to VDD(1.5) before or at the
same time as VDD(1.05).
5. The VDDO pad ring has separate I/O power supply options. Therefore, the voltage applied to a group of I/O pins must follow what is
defined in Section 1.
6. VPIN must never be more than 0.5V greater than VDDO or damage will result.
7. 125°C is the re-bake temperature. For extended storage time greater than 24 hours, +85°C should be the maximum.
Doc. No. MV-S110663-00 Rev. A
Page 54
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Table 21: Absolute Maximum Ratings
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated under Recommended Operating Conditions is not implied.
Exposure to absolute maximum ratings for extended periods may affect device reliability.
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
w
ay
s
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
d
m
ite
Electrical Specifications
s
Power Supply Sequencing
w
ay
3.1.1
Pr
iv
at
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Li
Recommended Operating Conditions
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
3.2
Recommended Operating Conditions
Min
Ty p
Max
U n i ts
VDD(3.3)
3.3V power supply
For any 3.3V supply pin1
3.135
3.3
3.465
V
VDD(2.5)
2.5V power supply
For any 2.5V supply pin2
2.375
2.5
2.625
V
VDD(1.8)
1.8V power supply
For any 1.8V supply pin
1.710
1.8
1.890
V
VDD(1.5)
1.5V power supply
For any 1.5V supply pin
1.425
1.5
1.575
V
VDD(1.05)Commercial
1.05V power supply
For any 1.05V supply pin
0.998
1.05
1.155
V
1.1
1.155
V
qi
no
9x
1q
1.10V Power supply
For any 1.10V supply
1.045
TA
Ambient operating
temperature3
Commercial parts
0
70
°C
Industrial parts4
-40
85
°C
1252
°C
5050
Ω
m
Li
at
e
External resistor value
required to be placed
between RSET and VSS
pins
Pr
iv
Internal bias
reference
4950
5000
ay
s
RSET
w
Maximum junction
temperature
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
TJ
ite
d
VDD(1.10)Industrial
1q
no
qi
e
0t
64
dz
1. Some VDDO pins can be set to either 1.8V or 2.5V or 3.3V. To guarantee proper operation they must be set within the appropriate ranges
in this table. VDDO voltages between 1.890V and 2.375V, and between 2.625V and 3.135V are not supported.
2. Some VDDO pins can be set to either 1.8V or 2.5V or 3.3V. To guarantee proper operation they must be set within the appropriate ranges
in this table. VDDO voltages between 1.890V and 2.375V, and between 2.625V and 3.135V are not supported.
3. The important parameter is maximum junction temperature. As long as the maximum junction temperature is not exceeded, the device can
be operated at any ambient temperature. Refer to White Paper on "TJ Thermal Calculations" for more information.
4. Industrial part numbers have an "I" following the commercial part numbers. For details see Section 5, Part Order Numbering/Package
Marking, on page 94.
Copyright © 2018 Marvell
January 23, 2018
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C o n d it i o n
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
P a r a m e te r
e0
t
Symbol
64
dz
Table 22: Recommended Operating Conditions
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Power supply voltage on any pin must never be more than 0.5V greater than the next highest
voltage pin, or damage will result. Power must be applied to the higher voltage pin before or at the
same time as power is applied to the pins with the next lower voltage.
Pr
iv
Thermal Conditions
3.3.1
Thermal Conditions for the 88E6390/88E6190/88E6290
device 144-pin QFP Package
w
ay
C o n d i ti o n
θJA
Thermal resistance1 junction to ambient of the
144-Pin QFP package
64
dz
θJA = (TJ - TA)/ P
P = Total Power
Dissipation
Ty p
Max
23.6
°C/W
JEDEC 3 in. x 4.5 in.
4-layer PCB with 1 meter/sec air flow
21.2
°C/W
JEDEC 3 in. x 4.5 in.
4-layer PCB with 2 meter/sec air flow
20.1
°C/W
JEDEC 3 in. x 4.5 in.
4-layer PCB with 3 meter/sec air flow
19.3
°C/W
JEDEC 3 in. x 4.5 in. 4-layer PCB
with no air flow
0.24
°C/W
JEDEC 3 in. x 4.5 in.
4-layer PCB with 1 meter/sec air flow
0.35
°C/W
JEDEC 3 in. x 4.5 in.
4-layer PCB with 2 meter/sec air flow
0.47
°C/W
JEDEC 3 in. x 4.5 in.
4-layer PCB with 3 meter/sec air flow
0.53
°C/W
JEDEC with no air flow
8.5
Thermal resistance1 junction to board of the
144-Pin QFP package
ite
d
m
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
θJC = (TJ - TC)/ PTop
PTop = Power
Dissipation from the top
of the package
θJB
°C/W
Li
Thermal resistance1 junction to case of the
144-Pin QFP package
at
e
θJC
Pr
iv
no
9x
1q
ψJT = (TJ - TTOP)/P.
TTOP = Temperature on
the top center of the
package
Units
JEDEC 3 in. x 4.5 in.
4-layer PCB with no air flow
qi
e0
t
Thermal characteristic
parameter1 - junction to
top center of the 144-Pin
QFP package
Min
JEDEC with no air flow
14.6
°C/W
θJB = (TJ - TB)/ Pbottom
Pbottom = power
dissipation from the
bottom of the package to
the PCB surface.
1q
no
qi
e
0t
64
dz
1. Refer to white paper on TJ Thermal Calculations for more information.
Doc. No. MV-S110663-00 Rev. A
Page 56
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
P a r a m e te r
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Symbol
ψJT
s
3.3
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
d
Current Consumption
s
Current Consumption
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
3.4
Pr
iv
at
e
Li
m
ite
Electrical Specifications
Table 23: 88E6390/88E6190/88E6290 Device Current Consumption
Units
All ports active
(Port 1 - Port 8 at 1000 Mbps)
Not applicable to 88E6290
418
mA
All ports active
(Port 1 - Port 8 at 100 Mbps)
114
mA
All ports active
(Port 1 - Port 8 at 10 Mbps)
213
mA
EEE disabled, all ports idle (Port 1
- Port 8 linked at 1000 Mbps but
idle)
418
mA
EEE disabled, all ports idle (Port 1
- Port 8 linked at 100 Mbps but
idle)
113
mA
EEE disabled, all ports idle (Port 1
- Port 8 linked at 10 Mbps but idle)
117
mA
EEE enabled, all ports idle (linked
at 1000 Mbps)
12
mA
EEE enabled, all ports idle (linked
at 100 Mbps)
12
mA
65
mA
26
mA
1 port linked at 10 Mbps
full traffic, all other GPHY’s
powered down
38
mA
1 port linked at 1000 Mbps, idle
65
mA
1 port linked at 100 Mbps, idle
26
mA
1 port linked at 10 Mbps, idle
26
mA
1 port Gig EEE, all other GPHY’s
powered down
18
mA
1 port 100 EEE, all other GPHY’s
powered down
13
mA
No link on any port
12
mA
Reset
12
mA
at
e
Pr
iv
ay
s
w
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
1 port linked at 100 Mbps
full traffic, all other GPHY’s
powered down
Li
EEE disabled 1 port linked at 1000
Mbps full traffic, all other GPHY’s
powered down
1q
no
qi
e
0t
64
dz
Max
9x
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 57
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
e0
t
qi
no
9x
1q
Ty p
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
3.3V power to analog
core for Gig PHY
interfaces
Min
ite
d
Px_AVDD33
64
dz
C o n d it i o n
m
P a r a m e te r
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Pins
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
Px_AVDD15
1.5V power to analog
core for Gig PHY
interfaces
Min
Ty p
Max
Units
All ports active
(Port 1 - Port 8 at 1000 Mbps)
273
mA
All ports active
(Port 1 - Port 8 at 100 Mbps)
141
mA
All ports active
(Port 1 - Port 8 at 10 Mbps)
110
mA
EEE disabled, all ports idle (Port 1
- Port 8 linked at 1000 Mbps but
idle)
270
mA
EEE disabled, all ports idle (Port 1
- Port 8 linked at 100 Mbps but
idle)
138
mA
EEE disabled, all ports idle (Port 1
- Port 8 linked at 10 Mbps but idle)
107
mA
EEE enabled, all ports idle (linked
at 1000 Mbps)
135
mA
EEE enabled, all ports idle (linked
at 100 Mbps)
105
mA
1 port linked at 1000 Mbps, full
traffic
40
mA
1 port linked at 100 Mbps,
full traffic
23
ite
d
m
Li
at
e
mA
40
mA
1 port linked at 100 Mbps, idle
23
mA
1 port linked at 10Mbps, idle
19
mA
1 port 1000 Mbps EEE idle
25
mA
1 port 100 Mbps EEE idle
18
mA
No link on any port
88
mA
Reset
27
mA
--
6
mA
Pr
iv
19
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
1 port linked at 1000 Mbps, idle
1.5V power to power the
on-chip XTAL.
1q
no
qi
e
0t
64
dz
AVDD15_
XTAL
mA
ay
s
1 port linked at 10 Mbps,
full Traffic
w
9x
1q
no
qi
e0
t
64
dz
C o n d it i o n
9x
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P a r a m e te r
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Pins
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Table 23: 88E6390/88E6190/88E6290 Device Current Consumption (Continued)
d
Current Consumption
Pr
iv
at
e
Li
m
ite
Electrical Specifications
9x
1q
no
qi
e0
t
64
dz
2.5V for Port 0’s
RGMII/MII/RMII I/O pins.
1.8V for Port 0’s
RGMII/MII/RMII I/O pins.
Ty p
Max
Units
All ports active at max speed
34
mA
All ports active at 100 Mbps
19
mA
All ports active at 10 Mbps
19
mA
Reset
39
mA
No link on any port
4
mA
Port active at 1000 Mbps
33
mA
Port active at 100 Mbps
9
mA
Port active at 10 Mbps
5
mA
Reset
3
mA
Link down
5
mA
Interface disabled
(P0_MODE = 0x6)
4
mA
Port active at 1000 Mbps
23
mA
Port active at 100 Mbps
6
mA
Port active at 10 Mbps
6
mA
Reset
2
mA
3
mA
3
mA
2
mA
1
mA
ay
s
Reset
1.8V for GPIO pins.
See GPIO_VDDO pin
definition in Table 8 for
details as to which pins
are powered by
GPIO_VDDO.
Reset
1.5V power to SERDES
Port 9 and Port 10 2500BASE-X
140
mA
Port 9 and Port 10 1000BASE-X
80
mA
All Lanes powered down
7
mA
Reset
7
mA
1q
no
qi
e
0t
64
dz
P9_AVDD15
P10_AVDD15
2.5V for GPIO pins.
See GPIO_VDDO pin
definition in Table 8 for
details as to which pins
are powered by
GPIO_VDDO.
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
GPIO_VDDO
w
Interface disabled
(P0_MODE = 0x6)
Pr
iv
at
e
Li
Link Down
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January 23, 2018
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3.3V to EEPROM and
LED pins.
Min
ite
d
EE_VDDO
P0_VDDO
C o n d it i o n
m
P a r a m e te r
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Pins
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
w
ay
s
Table 23: 88E6390/88E6190/88E6290 Device Current Consumption (Continued)
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
Max
Units
All ports active at max speed, P9
and P10 2500BASE-X
1065
mA
All ports active at 100 Mbps
P9 and P10 2500BASE-X
552
mA
All ports active at 10 Mbps, P9 and
P10 2500BASE-X
524
mA
EEE disabled, all ports idle and
linked at 1000 Mbps, P9 and P10
1000BASE-X
181
mA
EEE disabled, all ports idle and
linked at 100 Mbps, P9 and P10
1000BASE-X
135
mA
EEE disabled, all ports idle and
linked at 10 Mbps, P9 and P10
1000BASE-X
129
mA
No link on any port
145
mA
EEE enabled
(All ports idle @ 1G, P9 and P10
1000BASE-X)
175
mA
Link on one port 1000 Mbps
(RGMII disabled, P2-8 Powered
down, P9, P10 EEE disabled, All
SERDES Powered down)
138
mA
at
e
Pr
iv
mA
Link on one port 10 Mbps
(RGMII disabled, P2-8 Powered
down, P9, P10 EEE disabled, All
SERDES Powered down)
86
mA
One port linked 1000Mbps EEE
(RGMII disabled, P2-8 Powered
down, P9, P10 EEE disabled, All
SERDES Powered down)
90
mA
All ports powered down
(RGMII disabled, P1-8 Powered
down, P9, P10 EEE disabled, All
SERDES Powered down)
82
mA
Reset
41
mA
w
ay
s
90
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Link on one port 100 Mbps
(RGMII disabled, P2-8 Powered
down, P9, P10 EEE disabled, All
SERDES Powered down)
9x
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e0
t
qi
no
9x
1q
Ty p
ite
d
1.1V power to digital
core
Min
m
VDD_
CORE
64
dz
C o n d it i o n
Li
P a r a m e te r
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Pins
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Table 23: 88E6390/88E6190/88E6290 Device Current Consumption (Continued)
d
m
ite
Electrical Specifications
Digital Operating Conditions
s
3.5.1
w
ay
DC Electrical Characteristics
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
3.5
Pr
iv
at
e
Li
DC Electrical Characteristics
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
VDDO
3.3V
power.
2.5V/1.8V
power.
Ty p
Max
U n it s
See EE_VDDO pin
definition in Table 10
for details.
3.135
3.3
3.465
V
See P0_VDDO and
GPIO_VDDO pin
definitions in Table 10
for details.
2.375
2.5
2.625
V
1.71
1.8
1.89
V
XTAL_IN, SE_SCLK
AVDD15
1.4
1.99
V
EE_VDDO
VDDO = 3.135V
VDDO*70%
VDDO+0.4
V
P0_VDDO
GPIO_VDDO
VDDO = 2.375V
V
VDDO = 1.710V
V
qi
no
9x
1q
Low level
input voltage
VIL
XTAL_IN, SE_SCLK
AVDD15
-0.3
0.54
V
EE_VDDO
VDDO = 3.135V
-0.4
VDDO*30%
V
P0_VDDO
GPIO_VDDO
VDDO = 2.375V
V
ite
d
High level
input voltage
M in
e0
t
VIH
C o n d it i o n
V
Li
m
VDDO = 1.710V
IILK
CIN
All others (except
INTn 1)
IOH = -4 mA
VDDO - 0.4
Low level
output
voltage
Input leakage
current
Input
capacitance
V
at
e
VDDO - 0.4
Pr
iv
IOH = -7 mA
V
w
ay
s
LED pins
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
VOL
High level
output
voltage
Others @ 1.8V
IOH = -2 mA
INTn and LED pins
IOL= 7 mA
0.4
V
All others
IOL= 4 mA
0.4
V
Others 1.8V
IOL= 2 mA
0.2
V
With pull-up
resistor
0<VIN<VDDO
+ 10
- 60
μA
With pull-down
resistor
0<VIN<VDDO
+ 60
- 10
μA
Others
0<VIN<VDDO
+ 10
- 10
μA
VDDO - 0.2
XTAL_IN, SE_SCLK
dz
VOH
5
pF
5
pF
0t
64
All others
V
1q
no
qi
e
1. The INTn is an active low, open drain pin. See INTn description in the Signal Description.
Copyright © 2018 Marvell
January 23, 2018
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Pins
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Parameter
64
dz
Symbol
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 24: Digital Operating Conditions
s
SGMII Interface
w
ay
3.5.2
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Transmitter DC Characteristics
P a ra m e t e r 1
VOH
Output Voltage High
VOL
Output Voltage Low
VRING
|VOD|
2
Min
Ty p
Max
Units
1400
mV
700
mV
Output Ringing
10
%
Programmable - see Table 25.
mV
peak
VOS
Output Offset Voltage (also called
Common mode voltage)
Variable - see 3.5.2.2 for details.
mV
RO
Output Impedance (single-ended)
(50 ohm termination)
40
60
Ωs
Mismatch in a pair
10
%
Delta VOD
Change in VOD between 0 and 1
25
mV
Delta VOS
Change in VOS between 0 and 1
25
mV
IS+, IS-
Output current on short to VSS
40
mA
IS+-
Output current when S_OUT+ and
S_OUT- are shorted
12
mA
IX+, IX-
Power off leakage current
10
ite
d
mA
at
e
Li
m
Delta RO
9x
1q
no
qi
e0
t
64
dz
Output Voltage Swing (differential,
peak)
R e g i s te r 2 6 _ 1 B it s F i e l d
2:0
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Table 25: Programming SGMII Output Amplitude
w
ay
s
Pr
iv
1. Parameters are measured with outputs AC connected with 100 ohm differential load.
2. Output amplitude is programmable by writing to Register 26_1.2:0.
D e s c r ip t io n
SGMII/Fiber Output Differential voltage peak measured.
Amplitude1
Note that internal bias minus the differential peak voltage must be greater
than 700 mV.
000 = 14 mV
001 = 112 mV
010 = 210 mV
011 = 308 mV
100 = 406 mV
101 = 504 mV
110 = 602 mV
111 = 700 mV
1q
no
qi
e
0t
64
dz
1. Cisco SGMII specification limits are |VOD| = 150 mV - 400 mV peak differential.
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Symbol
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3.5.2.1
9x
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SGMII specification is a de-facto standard proposed by Cisco. It is available at the Cisco website
ftp://ftp-eng.cisco/smii/sgmii.pdf. It uses a modified LVDS specification based on the IEEE standard
1596.3. Refer to that standard for the exact definition of the terminology used in the following table.
The device adds flexibility by allowing programmable output voltage swing and supply voltage
option.
d
m
ite
Electrical Specifications
Pr
iv
at
e
Li
DC Electrical Characteristics
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Figure 17: CML I/Os
CML Outputs
CML Inputs
Internal bias1
50 ohm
50 ohm
S_OUT+
S_OUT-
S_IN+
Internal bias
Isink
64
dz
e0
t
qi
Common Mode Voltage (Voffset) Calculations
no
3.5.2.2
9x
1q
There are four different main configurations for the SGMII/Fiber interface connections. These are:
DC connection to an LVDS receiver
AC connection to an LVDS receiver
DC connection to an CML receiver
AC connection to an CML receiver
ite
d
•
•
•
•
at
e
Li
m
If AC coupling or DC coupling to an LVDS receiver is used, the DC output levels are determined by
the following:
•
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
Internal bias. See Figure 17 for details. (If AVDD18 is used to generate the internal bias, the
internal bias value will typically be 1.05V.)
• The output voltage swing is programmed by Register 26_1.2:0 (see Table 25).
• Voffset (i.e., common mode voltage) = internal bias - single-ended peak-peak voltage swing.
See Figure 18 for details.
If DC coupling is used with a CML receiver, then the DC levels will be determined by a combination
of the MACs output structure and the input structure shown in the CML Inputs diagram in Figure 19.
Assuming the same MAC CML voltage levels and structure, the common mode output levels will be
determined by:
•
Voffset (i.e., common mode voltage) = internal bias - (single-ended peak-peak voltage swing/2).
See Figure 19 for details.
If DC coupling is used, the output voltage DC levels are determined by the AC coupling considerations above, plus the I/O buffer structure of the MAC.
1q
no
qi
e
0t
64
dz
•
Copyright © 2018 Marvell
January 23, 2018
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Doc. No. MV-S110663-00 Rev. A
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S_IN-
1. Internal bias is generated from the
AVDDH supply and is typically 1.05V.
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
50 ohm
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
50 ohm
Internal bias1
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
CML Outputs
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Figure 18: AC connections (CML or LVDS receiver) or DC connection LVDS receiver
Internal bias1
V = Internal bias - Vpeak
AC coupling Cap.
50 ohm
S_OUT+
V = Voffset
9x
1q
no
qi
e0
t
1. Internal bias is generated from the
AVDDH supply and is typically 1.05V.
Single-ended Voltage details
Internal bias - Vpeak
Vpeak
V = Voffset (i.e., common mode voltage) = Internal bias - Vpeak-peak
Pr
iv
at
e
Li
m
ite
d
S_OUTP
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Vmin = Internal bias - 3 * Vpeak
Vmin must be greater than 700 mV
1q
no
qi
e
0t
64
dz
S_OUTN
Doc. No. MV-S110663-00 Rev. A
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64
dz
Isink
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
S_OUT(opposite of
S_OUT+)
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
50 ohm
d
m
ite
Electrical Specifications
Pr
iv
at
e
Li
DC Electrical Characteristics
w
ay
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
CML Outputs
s
Figure 19: DC connection to a CML receiver
CML Inputs
Internal bias1
Internal bias1
V = Internal bias
50 ohm
50 ohm
S_IN+
V = Internal bias Vpeak-peak
Internal bias
50 ohm
S_IN-
no
qi
e0
t
64
dz
1. Internal bias is generated from the
AVDDH supply and is typically 1.05V.
9x
1q
Single-ended Voltage details
Internal bias
Vpeak
V = Voffset (i.e., common mode voltage) = Internal bias - Vpeak
Li
m
ite
d
S_OUTP
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Internal bias
Pr
iv
at
e
Vmin = Internal bias - Vpeak-peak (single ended)
(V min must be greater than 700 mV)
1q
no
qi
e
0t
64
dz
S_OUTN
Copyright © 2018 Marvell
January 23, 2018
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Isink
V = Voffset
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
S_OUT+
S_OUT(opposite of
S_OUT+)
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
50 ohm
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Receiver DC Characteristics
Symbol
P a ra m e t e r
Min
VI
Input Voltage range a or b
VIDTH
Input Differential Threshold
VHYST
Input Differential Hysteresis
25
RIN
Receiver 100 Ω Differential Input
Impedance
80
Ty p
Max
U n i ts
675
1725
mV
-50
+50
mV
mV
Ω
120
Receiver High
+50 mV
-VIDTH
VIDTH
VS_IN+ - VS_IN-
e0
t
64
dz
-50 mV
no
qi
Receiver Low
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
9x
1q
VHYST
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Figure 20: Input Differential Hysteresis
9x
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3.5.2.3
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
d
m
ite
Electrical Specifications
Reset and Configuration Timing
s
3.6.1
w
ay
AC Electrical Specifications
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
3.6
Pr
iv
at
e
Li
AC Electrical Specifications
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
Min
TPU_RESET
Valid power to RESETn
de-asserted or RESETn
assertion time
TSU_CLK
Ty p
Max
Units
At power up or subsequent resets after
power up
10
ms
Number of valid
REFCLK cycles prior to
RESETn
de-asserted
10
Clks
TSU
Configuration data valid
prior to RESETn
de-asserted1
200
ns
THD
Config data valid after
RESETn de-asserted
0
ns
e0
t
qi
no
9x
1q
1. When RESETn is low all configuration pins become inputs, and the value seen on these pins is latched on the rising edge of
RESETn. All configuration pins that become outputs during normal operation will remain tri-stated for 40 ns after the rising
edge of RESETn.
ite
d
Figure 21: Reset and Configuration Timing
Li
m
TPU_RESET
TSU_CLK
ay
s
Pr
iv
at
e
Power
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
CLK
RESETn
Config Data
TH
1q
no
qi
e
0t
64
dz
TSU
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C o n d i ti o n
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P a ra m e t e r
64
dz
Symbol
9x
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Table 26: Reset and Configuration
s
Clock Timing
w
ay
3.6.2
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
Min
Ty p
Max
Units
XTAL_IN period
40
-50
ppm
40
40
+50
ppm
ns
TH
XTAL_IN high time
13
20
27
ns
TL
XTAL_IN low time
13
20
27
ns
TR
XTAL_IN rise
3
ns
TF
XTAL_IN fall
3
ns
TJ_XTAL_IN
XTAL_IN total jitter2
200
ps3
9x
1q
no
qi
e0
t
1. If the crystal option is used, ensure that the frequency is 25.000 MHz ± 50 ppm.
2. PLL generated clocks are not recommended as input to XTAL_IN since they can have excessive jitter. Zero delay buffers are
also not recommended for the same reason.
3. Broadband peak-peak = 200 ps, Broadband rms = 3 ps, 12 kHz to 20 MHz rms = 1 ps.
Figure 22: Oscillator Clock Timing
TP
TH
TL
ite
d
1.4V
Li
m
XTAL_IN
TR
at
e
0.54V
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
TF
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TP1
C o n d i ti o n
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
P a ra m e t e r
64
dz
Symbol
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 27: IEEE DC Transceiver Parameters
d
m
ite
Electrical Specifications
Pr
iv
at
e
Li
MII Timing
MII Timing
3.7.1
MII PHY Mode Receive Timing - 100 Mbps
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
3.7
In PHY mode, the P[x]_INCLK pins are outputs.
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
MII PHY Mode Receive Timing
TH_TX_CLK
P ar amete r
C ondi tio n
P[x]_INCLK period
10BASE mode
400
ns
100BASE mode
40
ns
P[x]_INCLK high
P[x]_INCLK low
TL_TX_CLK
Min
Max
U nit s
10BASE mode
160
200
240
ns
100BASE mode
16
20
24
ns
10BASE mode
160
200
240
ns
100BASE mode
16
20
24
ns
MII inputs (P[x]_IND[3:0],
P[x]_INDV) valid prior to
P[x]_INCLK going high.
15
ns
0
ns
qi
e0
t
64
dz
TSU_TX
Typ
MII inputs (P[x]_IND[3:0],
P[x]_INDV) valid after
P[x]_INCLK going high.
9x
1q
no
THD_TX
1. 2.5 MHz for 10 Mbps or 25 MHz for 100 Mbps.
Figure 23: MII PHY Mode Receive Timing
m
Li
TL_TX_CLK
Pr
iv
at
e
INCLK
ite
d
TH_TX_CLK
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
TP_TX_CLK
INPUTS
THD_TX
TSU_TX
1q
no
qi
e
0t
64
dz
NOTE: INCLK is the clock used to clock the input data.
It is an output in this mode.
Copyright © 2018 Marvell
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TP_TX_CLK
1
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S ymbo l
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Table 28:
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
MII PHY Mode Transmit Timing - 100 Mbps
w
ay
s
3.7.2
MII PHY Mode Transmit Timing
TP_RX_CLK
C ondi tio n
P[x]_OUTCLK period
P[x]_OUTCLK high
TH_RX_CLK
TL_RX_CLK
P[x]_OUTCLK low
P[x]_OUTCLK to outputs
(P[x]_OUTD[3:0],
P[x]_OUTEN) valid
TCQ_MIN
P[x]_OUTCLK to outputs
P[x]_OUTD[3:0],
P[x]_OUTEN) invalid
Typ
Max
U nit s
10BASE mode
400
ns
100BASE mode
40
ns
10BASE mode
160
200
240
ns
100BASE mode
16
20
24
ns
10BASE mode
160
200
240
ns
100BASE mode
16
20
24
ns
25
ns
64
dz
TCQ_MAX
Min
ns
no
qi
e0
t
10
9x
1q
1. 2.5 MHz for 10 Mbps or 25 MHz for 100 Mbps.
Figure 24: MII PHY Mode Transmit Timing
Li
TL_RX_CLK
Pr
iv
at
e
OUTCLK
m
ite
d
TH_RX_CLK
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
TP_RX_CLK
OUTPUTS
TCQ_MAX
OUTCLK is the clock used to clock the output data.
It is an output in this mode.
1q
no
qi
e
0t
64
dz
NOTE:
TCQ_MIN
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P ar amete r
1
9x
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S ymbo l
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Table 29:
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
In PHY mode, the P[x]_OUTCLK pins are outputs.
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
d
m
ite
Electrical Specifications
s
MII MAC Mode Receive Timing
w
ay
3.7.3
Pr
iv
at
e
Li
MII Timing
MII Receive Timing - MAC Mode
C ondi tio n
Min
Typ
Max
U nit s
TSU_RX
MII inputs (P[x]_IND[3:0],
P[x]_INDV) valid prior to
P[x]_INCLK going high
With 10 pF load
10
ns
THD_RX
MII inputs (P[x]_IND[3:0],
P[x]_INDV) valid after
P[x]_INCLK going high
With 10 pF load
10
ns
64
dz
Figure 25: MII MAC Mode Receive Timing
9x
1q
no
qi
e0
t
INCLK
THD_RX
INPUTS
TSU_RX
1q
ite
d
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
NOTE:
INCLK is the clock used to clock the input data.
It is an input in this mode.
Copyright © 2018 Marvell
January 23, 2018
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S ymbo l
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MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 30:
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
In MAC mode, the P[x]_INCLK pins are inputs.
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
s
MII MAC Mode Transmit Timing
w
ay
3.7.4
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
MII MAC Mode Transmit Timing
C ondi tio n
TCQ_MAX
P[x]_OUTCLK to outputs
(P[x]_OUTD[3:0],
P[x]_OUTEN) valid
With 10 pF load
TCQ_MIN
P[x]_OUTCLK to outputs
(P[x]_OUTD[3:0],
P[x]_OUTEN) invalid
With 10 pF load
Min
Typ
Max
25
0
U nit s
ns
ns
64
dz
Figure 26: MII MAC Mode Transmit Timing
9x
1q
no
qi
e0
t
OUTCLK
OUTPUTS
TCQ_MAX
ite
d
OUTCLK is the clock used to clock the output data.
It is an input in this mode.
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
NOTE:
TCQ_MIN
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P ar amete r
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S ymbo l
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MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 31:
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
In MAC mode, the P[x]_OUTCLK pins are inputs.
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
d
m
ite
Electrical Specifications
s
TMII PHY Mode Receive Timing - 200 Mbps
w
ay
3.7.5
Pr
iv
at
e
Li
MII Timing
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
In PHY mode, the P[x]_INCLK pins are outputs.
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
Symb ol
Pa rame ter
Con dit ion
TP_TX_CLK
P[x]_INCLK period
200BASE mode
TH_TX_CLK
P[x]_INCLK high
200BASE mode
8
10
12
ns
TL_TX_CLK
P[x]_INCLK low
200BASE mode
8
10
12
ns
TSU_TX
MII inputs (P[x]_IND[3:0],
P[x]_INDV) valid prior to
P[x]_INCLK going high.
5
ns
THD_TX
MII inputs (P[x]_IND[3:0],
P[x]_INDV) valid after
P[x]_INCLK going high.
3
ns
Typ
Max
e0
t
qi
no
9x
1q
TH_TX_CLK
TL_TX_CLK
INCLK
Li
m
ite
d
TP_ TX_CLK
ay
s
INCLK is the clock used to clock the input data.
It is an output in this mode.
1q
no
qi
e
0t
64
dz
NOTE:
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
TSU_TX
w
THD_TX
Pr
iv
at
e
INPUTS
Copyright © 2018 Marvell
January 23, 2018
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Document Classification: Proprietary Information
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ns
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
20
U nit s
64
dz
M in
Figure 27: TMII PHY Mode Receive Timing - 200 Mbps
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 32: TMII PHY Mode Receive Timing - 200 Mbps
s
TMII PHY Mode Transmit Timing - 200 Mbps
w
ay
3.7.6
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
In PHY mode, the P[x]_OUTCLK pins are outputs.
(Over full range of values listed in the Recommended Operating Conditions unless otherwise
specified).
S ymbo l
Par amet er
Co ndit ion
TP_RX_CLK1
P[x]_OUTCLK period
200BASE mode
TH_RX_CLK
P[x]_OUTCLK high
200BASE mode
8
10
12
ns
TL_RX_CLK
P[x]_OUTCLK low
200BASE mode
8
10
12
ns
TCQ_MAX
P[x]_OUTCLK to outputs
(P[x]_OUTD[3:0],
P[x]_OUTEN) valid
15
ns
TCQ_MIN
P[x]_OUTCLK to outputs
P[x]_OUTD[3:0],
P[x]_OUTEN) invalid
Typ
Max
ns
ns
no
qi
e0
t
64
dz
2
9x
1q
Figure 28: TMII PHY Mode Transmit Timing - 200 Mbps
TH_RX_CLK
TL_RX_CLK
m
ite
d
OUTCLK
Pr
iv
at
e
Li
T P_RX_CLK
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
OUTPUTS
TCQ_MAX
OUTCLK is the clock used to clock the output data.
It is an output in this mode.
1q
no
qi
e
0t
64
dz
NOTE:
TCQ_MIN
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Document Classification: Proprietary Information
Copyright © 2018 Marvell
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20
U ni ts
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
M in
1. 2.5 MHz for 10 Mbps or 25 MHz for 100 Mbps.
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 33: TMII PHY Mode Transmit Timing - 200 Mbps
d
m
ite
Electrical Specifications
Pr
iv
at
e
Li
MII Timing
TMII MAC Mode Clock Timing - 200 Mbps
w
ay
s
3.7.7
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
In MAC mode, INCLK and OUTCLK are inputs.
(Over full range of values listed in the Recommended Operating Conditions unless otherwise
specified).
Symbo l
P ara meter
TP1
MACCLK_IN period
0
TH
MACCLK_IN high time
8
ns
TL
MACCLK_IN low time
8
ns
TR
MACCLK_IN rise
3
ns
MACCLK_IN fall
3
ns
Typ
Max
20
20
+50 ppm
Uni ts
ns
e0
t
9x
1q
no
qi
Figure 29: TMII MAC Clock Timing - 200 Mbps
TP
TH
TL
2.0 V
ite
d
MACCLK
TR
Li
m
0.8V
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
TF
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M in
64
dz
1. DC to 25 MHz
C ondi tio n
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
TF
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 34: TMII MAC Mode Clock Timing - 200 Mbps
s
TMII MAC Mode Receive Timing - 200 Mbps
w
ay
3.7.8
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
In MAC mode, the P[x]_INCLK pins are inputs.
(Over full range of values listed in the Recommended Operating Conditions unless otherwise
specified).
C ond iti on
M in
Typ
Max
U nit s
TSU_RX
MII inputs (P[x]_IND[3:0],
P[x]_INDV) valid prior to
P[x]_INCLK going high
With 10 pF load
5
ns
THD_RX
MII inputs (P[x]_IND[3:0],
P[x]_INDV) valid after
P[x]_INCLK going high
With 10 pF load
2
ns
e0
t
64
dz
Figure 30: TMII MAC Mode Receive Timing - 200 Mbps
9x
1q
no
qi
INCLK
THD_RX
INPUTS
TSU_RX
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
INCLK is the clock used to clock the input data.
It is an input in this mode.
NOTE:
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Table 35: TMII MAC Mode Receive Timing - 200 Mbps
d
m
ite
Electrical Specifications
s
TMII MAC Mode Transmit Timing - 200 Mbps
w
ay
3.7.9
Pr
iv
at
e
Li
MII Timing
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
In MAC mode, the P[x]_OUTCLK pins are inputs.
Table 36: TMII MAC Transmit Timing - 200 Mbps
C ond iti on
TCQ_MAX
P[x]_OUTCLK to outputs
(P[x]_OUTD[3:0],
P[x]_OUTDV valid
With 10 pF load
TCQ_MIN
P[x]_OUTCLK to outputs
(P[x]_OUTD[3:0],
P[x]_OUTDV invalid
With 10pF load
M in
Typ
Max
15
0
U nit s
ns
ns
e0
t
64
dz
Figure 31: TMII MAC Mode Transmit Timing - 200 Mbps
9x
1q
no
qi
OUTCLK
m
Li
TCQ_MAX
TCQ_MIN
OUTCLK is the clock used to clock the output data.
It is an input in this mode.
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
NOTE:
ite
d
OUTPUTS
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(Over full range of values listed in the Recommended Operating Conditions unless otherwise
specified).
Pr
iv
SGMII Timing
3.8.1
SGMII Output AC Characteristics
P a r a m e te r
Min
TFALL
VOD Fall time (20% - 80%)
TRISE
Max
U n it s
100
200
ps
VOD Rise time (20% - 80%)
100
200
ps
CLOCK
Clock signal duty cycle @ 625 MHz
48
52
%
TSKEW11
Skew between two members of a
differential pair
20
ps
TSOUTPUT2
SERDES output to RxClk_P/N
440
ps
TOutputJitter
Total Output Jitter Tolerance
(Deterministic + 14*rms Random)
360
Ty p
400
127
ps
64
dz
1. Skew measured at 50% of the transition.
2. Measured at 50% of the transition.
9x
1q
no
qi
e0
t
Figure 32: Serial Interface Rise and Fall Times
S_OUTP/N
TRISE
TFALL
Li
m
ite
d
TSOUTPUT
TRISE
at
e
S_CLKP/N
3.8.2
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
TFALL
SGMII Input AC Characteristics
P a ra m e t e r
Min
TInputJitter
Total Input Jitter Tolerance (Deterministic
+ 14*rms Random)
Ty p
Max
Units
599
ps
1q
no
qi
e
0t
64
dz
Symbol
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Symbol
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
3.8
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
d
RGMII Timing
w
ay
s
RGMII Timing
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
3.9
Pr
iv
at
e
Li
m
ite
Electrical Specifications
Table 37: RGMII Interface Timing
Min
Ty p
Max
Units
TskewT
Data to Clock output Skew (at transmitter)
-500
0
500
ps
TskewR
Data to Clock input Skew (at receiver)
1.0
-
2.6
ns
TCYCLE
Clock Cycle Duration
7.2
8.0
8.8
ns
TCYCLE_
High Time for 1000BASE-T 1
3.6
4.0
4.4
ns
0.75
ns
HIGH1000
TRISE/TFALL
Rise/Fall Time (20-80%)
e0
t
64
dz
1. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet’s clock
domain as long as minimum duty cycle is not violated and stretching occurs for no more than three TCYCLE of the
lowest speed transitioned between.
9x
1q
no
qi
Figure 33: RGMII Multiplexing and Timing
GTX_CLK (TXC)
at transmitter
TSKEWT
OUTD[7:4][3:0]
OUTD[3:0]
OUTD[7:4]
TSKEWR
ite
d
OUTEN
Li
m
OUTEN (TX_CTL)
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
GTX_CLK (TXC)
at receiver
RX_CLK (RXC)
at transmitter
TSKEWT
IND[7:4][3:0]
INDV (RX_CTL)
IND[3:0]
IND[7:4]
TSKEWR
INDV
1q
no
qi
e
0t
64
dz
INCLK (RXC)
at receiver
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Symbol
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For other timing modes see Section 3.9.1, RGMII Timing for Different RGMII Modes, on page 80.
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
RGMII Timing for Different RGMII Modes
3.9.1.1
RGMII Transmit Timing
w
ay
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Table 38:
s
3.9.1
Transmit - TXC Timing when RGMII Transmit Delay Control (Offset 0x01, bit 14) = 0
Symbol
P a ra m e t e r
tsskew
RGMII Transmit Delay Control (bit 3) = 0
Min
Ty p
-0.5
Max
Units
0.5
ns
OUTD[3:0] (TXD[3:0]),
OUTEN (TX_CTL)
e0
t
64
dz
TXC
no
qi
tskew
tskew
9x
1q
tskew
Transmit - TXC Timing when RGMII Transmit Delay Control (Offset 0x01, bit 14) = 1
ite
d
Table 39:
tskew
tsetup
RGMII Transmit Delay Control (bit 3) = 1
1.2
Ty p
1.2
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
thold
Max
Pr
iv
Min
ay
s
P a ra m e t e r
w
Symbol
at
e
Li
m
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
Units
ns
ns
Figure 35: Transmit - TXC Timing when RGMII Transmit Delay Control (bit 3) = 1
TXC
OUTD[3:0] (TXD[3:0]),
OUTEN (TX_CTL)
thold
thold
tsetup
1q
no
qi
e
0t
64
dz
tsetup
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Figure 34: Transmit - TXC Timing when RGMII Transmit Delay Control (bit 3) = 0
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(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
d
RGMII Timing
s
RGMII Receive Timing
Table 40:
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
3.9.1.2
Pr
iv
at
e
Li
m
ite
Electrical Specifications
Receive - INCLK (RXC) Timing when RGMII Receive Delay Control (Offset 0x01, bit 15) = 0
Symbol
P a ra m e t e r
tsetup
RGMII Receive Delay Control (bit 4) = 0
thold
Min
Ty p
Max
Units
1.0
ns
0.8
ns
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
INCLK (RXC)
64
dz
IND[3:0] (RXD[3:0]),
INDV (RX_CTL)
qi
e0
t
thold
tsetup
9x
1q
no
tsetup
thold
Table 41:
Receive - INCLK (RXC) Timing when RGMII Receive Delay Control (Offset 0x01, bit 15) = 1
RGMII Receive Delay Control (bit 4) = 1
-0.9
2.7
Units
ns
ns
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
thold
Max
Li
tsetup
Ty p
at
e
Min
Pr
iv
P a ra m e t e r
ay
s
Symbol
m
ite
d
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
Figure 37: Receive - RXC Timing when RGMII Receive Delay Control (bit 4) = 1
INCLK (RXC)
IND[3:0] (RXD[3:0]),
INDV (RX_CTL)
tsetup
tsetup
thold
1q
no
qi
e
0t
64
dz
thold
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Figure 36: Receive - INCLK (RXC) Timing when RGMII Receive Delay Control (bit 4) = 0
9x
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(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
RMII Timing
3.10.1
RMII Receive Timing
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
3.10
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
RMII Receive Timing using INCLK
C ondi ti on
1
Min
Typ
20
U nit s
TP_TX_CLK
P[x]_OUTCLK period
ns
TH_TX_CLK
P[x]_OUTCLK high
100BASE mode
8
10
12
ns
TL_TX_CLK
P[x]_OUTCLK low
100BASE mode
8
10
12
ns
TSU_TX
RMII inputs
(P[x]_IND[1:0],
P[x]_INDV) valid prior to
P[x]_OUTCLK going
high.
4
ns
THD_TX
RMII inputs
(P[x]_IND[1:0],
P[x]_INDV) valid after
P[x]_OUTCLK going
high.
2
ns
9x
1q
no
qi
e0
t
64
dz
100BASE mode
Max
1. 50 MHz for 100 Mbps.
Figure 38: RMII Receive Timing using OUTCLK
m
Li
T L_TX_CLK
Pr
iv
at
e
OUTCLK
ite
d
TH_TX_CLK
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
TP_ TX_CLK
INPUTS
T HD_TX
T SU_TX
1q
no
qi
e
0t
64
dz
NOTE: OUTCLK is the clock used to clock the input data.
It is an output in this mode.
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Table 42:
d
m
ite
Electrical Specifications
s
RMII Transmit Timing
w
ay
3.10.2
Pr
iv
at
e
Li
RMII Timing
RMII Transmit Timing using INCLK
P ar amete r
C ondi tio n
P[x]_OUTCLK period
100BASE mode
TH_RX_CLK
P[x]_OUTCLK high
100BASE mode
8
10
12
ns
TL_RX_CLK
P[x]_OUTCLK low
100BASE mode
8
10
12
ns
TCQ_MAX
P[x]_OUTCLK to outputs
(P[x]_OUTD[1:0],
P[x]_OUTEN) valid
16
ns
TCQ_MIN
P[x]_OUTCLK to outputs
P[x]_OUTD[1:0],
P[x]_OUTEN) invalid
Min
Typ
Max
20
U nit s
ns
2
ns
64
dz
1. 50 MHz for 100 Mbps.
qi
e0
t
Figure 39: RMII Transmit Timing using OUTCLK
9x
1q
no
TH_RX_CLK
OUTCLK
T L_RX_CLK
ite
d
T P_RX_CLK
Pr
iv
T CQ_MIN
ay
s
T CQ_MAX
at
e
Li
m
OUTPUTS
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
NOTE: OUTCLK is the clock used to clock the output data.
It is an output in this mode.
Copyright © 2018 Marvell
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TP_RX_CLK
1
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Table 43:
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
Serial Management Interface (SMI) Timing
3.11.1
SMI Clock Timing (CPU Set)
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
3.11
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
MDC period
TH
Min
Ty p
Max
U n it s
Notes
50
ns
20
MHz
MDC high time
25
ns
TL
MDC low time
25
ns
TR
MDC rise
TF
MDC fall
3
ns
3
ns
9x
1q
no
qi
e0
t
Figure 40: SMI Clock Timing (CPU Set)
TP
TH
TL
2.0 V
MDC
0.8V
TR
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
TF
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TP
C o n d it i o n
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
P a ra m e t e r
64
dz
Symbol
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 44: SMI Clock Timing (CPU Set)
d
m
ite
Electrical Specifications
s
SMI Data Timing (CPU Set)
w
ay
3.11.2
Pr
iv
at
e
Li
Serial Management Interface (SMI) Timing
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
C o n d it i o n
Min
Ty p
Max
U n it s
TDLY_MDIO
MDC to MDIO (Output)
delay time
0
30
ns
TSU
MDIO (Input) to MDC setup
time
10
ns
THD
MDIO (Input) to MDC hold
time
10
ns
Notes
64
dz
Figure 41: SMI Data Timing
9x
1q
no
qi
e0
t
MDC
MDIO (Output)
Li
m
ite
d
TDLY_MDIO
ay
s
Pr
iv
at
e
MDC
THD
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
TSU
1q
no
qi
e
0t
64
dz
MDIO (Input)
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P a ra m e t e r
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Symbol
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 45: SMI Clock Timing (CPU Set)
s
SMI Timing (PHY Set)
w
ay
3.11.3
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
TP
MDC period
TH
C o n d it i o n
Ty p
Max
Units
N o te s
10
ns
9.09
MHz
MDC high time
48
ns
TL
MDC low time
48
ns
TR
MDC rise
TF
MDC fall
TTX_SU
MDIO output setup time
10
ns
1
TTX_HD
MDIO output hold time
10
ns
2
TRX_SU
MDIO input setup time
TRX_HD
MDIO input hold time
ns
2
6
ns
6
ns
9x
1q
TDLY_MDIO
no
qi
e0
t
M in
MDC to MDIO (Output)
delay time
0
5
1. MDIO input setup and hold time is intentionally sampled with respect to the MDC falling edge.
2. MDIO data is intentionally clocked out on the falling edge of MDC.
m
ite
d
Figure 42: SMI Timing Output (PHY Mode)
Li
TP
at
e
TL
Pr
iv
TH
ay
s
2.0V
w
MDC
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
0.8V
TR
TF
TTX_HD
TTX_SU
MDIO (Output)
Figure 43: SMI Timing Input (PHY Mode)
MDC
TRX_HD
64
dz
TRX_SU
1q
no
qi
e
0t
MDIO (Input)
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P a ra m e t e r
64
dz
Symbol
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
SMI Clock Timing (PHY Set)
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 46:
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
d
m
ite
Electrical Specifications
Pr
iv
at
e
Li
2500BASE-X
2500BASE-X
3.12.1
2500BASE-X Characteristics
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
3.12
Symbol
P a ra m e t e r
M in
Ty p
Max
U n i ts
Baud rate
3.125
Gbd
Unit interval
320
ps
Differential amplitude
800
1600
mVp-p
0.17
uI
0.35
uI
Deterministic Jitter
0.37
uI
Total Jitter
0.55
uI
Total Jitter
0.2
no
qi
e0
t
64
dz
Far-end Output Jitter
9x
1q
Figure 44: Driver Output Voltage Limits and Definitions
2.3V
Maximum absolute output
S_OUT+
m
ite
d
S_OUT-
Minimum absolute output
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
Ground
-0.4
(S_OUT+) - (S_OUT-)
Differential
peak amplitude
1q
no
qi
e
0t
64
dz
S_OUT+ and S_OUT- are the Positive and Negative Sides of the Differential Signal Pair for Lane i (i
= 0, 1, 2, 3)
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Deterministic Jitter
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Near-end Output Jitter
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 47: 2500BASE-X Characteristics
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
Table 48: Receiver Input Parameters
Baud rate
Condition
Min
Ty p
Max
3.125
Gbd
±100
320
Return loss2
Jitter amplitude tolerance3
ppm
ps
200
1600
mVp-p
Differential
10
dB
Common mode
6
dB
Peak-Peak total jitter
0.65
UIp-p
Peak-Peak
deterministic jitter
0.47
UIp-p
Differential input
amplitude1
qi
e0
t
64
dz
1. See 47.3.4.3 for detailed receive signal parameters in IEEE 802.3ae.
2. Measured from 100 MHz to 2.5 GHz. See clause 47.3.43 in IEEE 802.3ae for details.
3. See 47.3.4.6 for jitter tolerance details. The maximum random jitter is equal to the maximum total jitter minus the actual
deterministic jitter.
9x
1q
no
Figure 45: High-Speed I/O AC Coupled Mode
S_OUT+
S_IN+
50 ohm
50 ohm
Li
at
e
Receiver
w
Media
ay
s
S_IN-
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
Transmitter
Pr
iv
50 ohm
S_OUT-
m
-
50 ohm
ite
d
+
1q
no
qi
e
0t
64
dz
The interface shall be AC coupled to allow for maximum inter-operability.
Doc. No. MV-S110663-00 Rev. A
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MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Baud rate tolerance
Unit interval (UI)
U n it s
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P a ra m e t e r
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Symbol
d
EEPROM Timing
Pr
iv
at
e
Li
m
ite
Electrical Specifications
EEPROM Timing
3.13.1
2-Wire EEPROM Timing
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
3.13
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
C o n d it i o n
Min
Ty p
Max
U n it s
Freq
EE_CLK frequency
3.3V
1
Mhz
TH
EE_CLK high time
3.3V
500
ns
TL
EE_CLK low time
3.3V
500
ns
TIN
Data input time
3.3V
50
ns
THIGH
TLOW
no
qi
e0
t
64
dz
Figure 46: 2-Wire Input Timing
9x
1q
EE_CLK
EE_DOUT
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
TIN
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P a ra m e t e r
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Symbol
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 49: 2-Wire EEPROM Input Timing
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
Freq
EE_CLK frequency
3.3V
TH
EE_CLK high time
3.3V
500
ns
TL
EE_CLK low time
3.3V
500
ns
THD:STA
Start condition hold time
3.3V
250
ns
TSU:STA
Start condition setup time
3.3V
250
ns
THD:DAT
EE_DOUT data output hold
time
3.3V
250
ns
TSU:DAT
EE_DOUT data output
setup time
3.3V
250
ns
TSU:STO
Start condition setup time
3.3V
250
ns
e0
t
Ty p
Max
U n it s
1000
kHz
no
qi
Min
9x
1q
Figure 47: 2-Wire EEPROM Output Timing
THIGH
TLOW
EE_CLK
TSU:STA
TSU:STO
ite
d
TSU:DAT
Li
m
EE_DOUT
at
e
THD:DAT
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
THD:STA
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C o n d it i o n
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
P a ra m e t e r
64
dz
Symbol
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Table 50: 2-Wire EEPROM Output Timing
d
EEPROM Timing
s
w
ay
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
IEEE AC Transceiver Parameters
IEEE tests are typically based on templates and cannot simply be specified by number. For an exact description of the
templates and the test conditions, refer to the IEEE specifications:
-10BASE-T IEEE 802.3 Clause 14-2000
-100BASE-TX ANSI X3.263-1995
-1000BASE-T IEEE 802.3ab Clause 40 Section 40.6.1.2 Figure 40-26 shows the template waveforms for transmitter
electrical specifications.
Parameter
Pins
C o n d i t io n
Min
Ty p
Max
Units
TRISE
Rise time
MDIP/N[1:0]
100BASE-TX
3.0
4.0
5.0
ns
TFALL
Fall Time
MDIP/N[1:0]
100BASE-TX
3.0
4.0
5.0
ns
MDIP/N[1:0]
100BASE-TX
0
0.5
ns
MDIP/N[1:0]
100BASE-TX
0
0.51
ns,
peakpeak
MDIP/N[1:0]
100BASE-TX
0
1.4
ns,
peakpeak
TRISE/
TFALL
e0
t
Duty Cycle
Distortion
Transmit
Jitter
9x
1q
no
qi
DCD
64
dz
Symmetry
1q
no
qi
e
0t
64
dz
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
d
1. ANSI X3.263-1995 Figure 9-3
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Symbol
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
3.13.2
Pr
iv
at
e
Li
m
ite
Electrical Specifications
qi
e
no
1q
9x
ay
s
w
at
e
Pr
iv
ite
d
m
Li
qi
Figure 48: 144-pin E-PAD TQFP (16x16 mm) Mechanical Drawing
Page 92
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
64
dz
e0
t
Doc. No. MV-S110663-00 Rev. A
Document Classification: Proprietary Information
CONFIDENTIAL
Copyright © 2018 Marvell
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s
w
ay
4
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
dz
64
0t
no
9x
1q
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
at
Pr
iv
e
Li
m
d
ite
88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
Mechanical Drawing
d
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
w
ay
s
Pr
iv
at
e
Li
m
ite
Mechanical Drawing
Table 51: 144-pin E-PAD TQFP (16x16 mm) Package Dimensions
Nom
Max
A
1.00
1.10
1.20
A1
0.05
--
0.127
A2
0.95
1.00
1.05
b
0.13
0.18
0.23
b1
0.13
0.16
0.19
c
0.09
--
0.20
c1
0.09
--
0.16
D
18.00 BSC
D1
16.00 BSC
6.00 BSC
6.20 BSC
6.40 BSC
E
18.00 BSC
E1
16.00 BSC
5.30 BSC
5.70 BSC
0.40 BSC
Li
e
5.50 BSC
ite
d
E2
m
qi
no
9x
1q
D2
1.00 REF
L1
0.08
--
R2
0.08
--
0.20
S
0.20
--
--
θ
0°
3.5°
7°
θ1
0°
--
--
θ2
11°
12°
13°
θ3
11°
12°
13°
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
R1
aaa
0.20
bbb
0.20
ccc
0.08
ddd
0.07
--
1q
no
qi
e
0t
64
dz
0.75
Pr
iv
at
e
0.60
ay
s
0.45
w
L
9x
Copyright © 2018 Marvell
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Min
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Dimension in mm
e0
t
64
dz
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Symbol
d
ijt
M 1r5
A 5y
R
VE 9a
LL 6s8
C q7
O 10
N
FI y5
D v3
EN 5
TI shv
A
L, ru8
U vh
N
D -kb
ER 7
N tar9
D
A 2*
#
5e Tru
bd ne
42 xa
0d In
0a fo
5
Part Order Numbering/Package Marking
5.1
Part Order Numbering
qi
no
Custom code (optional)
9x
1q
Part number
88E6390
88E6190
88E6290
e0
t
64
dz
88E6x90 –xx–xxx–x000–xxxx
Custom code
Temperature code
C = Commercial
I = Industrial
Custom code
Custom code
ite
d
Environmental code
2 = Green
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Package code
TLA = 144-Pin E-PAD
Table 52: 88E6390/88E6190/88E6290 Part Order Options
P a c k a g e Ty p e
P a rt O r d e r N u m b e r
144-pin E-PAD TQFP (16x16 mm)
88E6390-xx-TLA2I000 (Industrial Green compliant package)
88E6290-xx-TLA2I000 (Industrial Green compliant package)
88E6390-xx-TLA2C000 (Commercial Green compliant package)
88E6190-xx-TLA2C000 (Commercial Green compliant package)
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88E6290-xx-TLA2C000 (Commercial Green compliant package)
Doc. No. MV-S110663-00 Rev. A
Page 94
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Figure 49: Sample Part Number
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Figure 49 shows the part order numbering scheme for the 88E6390/88E6190/88E6290. Refer to
Marvell Field Application Engineers (FAEs) or representatives for further information when ordering
parts.
9x
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88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
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Package Marking
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Part Order Numbering/Package Marking
Package Marking
5.2.1
Industrial Package Marking
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Country of origin
qi
the package.)
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(Contained in the mold ID or
marked as the last line on
88E6x90-TLAe
Lot Number
YYWW xx@
Country of Origin
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Part number, package code, environmental code
88E6390 or 88E6290 = Part number
TLA = Package code
e = Environmental code
(2 = Green)
Date code, custom code, assembly plant
code
YYWW = Date code (YY = year, WW = Work
Week)
xx = Custom code
@ = Assembly plant code
I = Industrial Grade
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Pin 1 location
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Note: The above drawing is not drawn to scale. Location of markings is approximate.
Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 95
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
Marvell logo
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Figure 50: 88E6390 and 88E6290 Industrial Package Marking and Pin 1 Location
9x
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Figure 50 shows a sample Industrial package marking and pin 1 location for the 88E6390 and
88E6290 devices.
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Commercial Package Marking
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5.2.2
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88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
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Figure 51 shows a sample Commercial package marking and pin 1 location for the
88E6390/88E6190/88E6290 devices.
Country of origin
(Contained in the mold ID or
e0
t
64
dz
marked as the last line on
the package.)
Part number, package code, environmental code
88E6390, 88E6190, or 88E6290 = Part number
TLA = Package code
e = Environmental code
(2 = Green)
no
qi
Date code, custom code, assembly plant
code
YYWW = Date code (YY = year, WW = Work
Week)
xx = Custom code
@ = Assembly plant code
9x
1q
Pin 1 location
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Note: The above drawing is not drawn to scale. Location of markings is approximate.
Doc. No. MV-S110663-00 Rev. A
Page 96
CONFIDENTIAL
Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
88E6x90-TLA2
Lot Number
YYWW xx@
Country of Origin
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Marvell logo
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MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Figure 51: Commercial Package Marking and Pin 1 Location
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Revision History
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A
Rev. A
v1.10
Rev. A
v1.01
D e s c ri p t i o n
January 23, 2018
Rev. A release.
November 28, 2017
Section 3, Electrical Specifications
• Table 24, Digital Operating Conditions updated VDDO
Parameter and Pins to separate EE_VDDO (3.3V) and P0_
VDDO/GPIO_VDDO (2.5V/1.8V). Corrected VIL All VDDO to
EE_VDDO.
September 7, 2017
Initial release.
August 17, 2017
Section 1, Signal Description
• Table 9, System & Register Access, on page 31 MDC_CPU
and MDIO_CPU pins - removed GPIO 3.3V tolerance in
NOTE.
• Table 10, Power & Ground, on page 32 P0_VDDO pin removed “and the CPU interface” and GPIO 3.3V tolerance.
• Table 10, Power & Ground, on page 32 GPIO_VDDO
removed GPIO 3.3V tolerance.
• Table 10, Power & Ground, on page 32 VDD_CORE
updated definition to include I-temp
Section 3, Electrical Specifications
• Table 23, 88E6390/88E6190/88E6290 Device Current
Consumption VDD_CORE to 1.1V
• Table 24, Digital Operating Conditions VIH All VDDO to EE_
VDDO
August 15, 2017
Added Revision History
Section 1, Signal Description
• Table 6, Port 0 xMII Receive Interface, on page 25 updated
Pin# 101, P0_CRS definition and updated table footnotes
• Table 7, Port 0 xMII Transmit Interface, on page 28 updated
table footnotes.
• Table 9, System & Register Access, on page 31 Pin# 20 and
19, MDC_CPU and MDIO_CPU definitions - P0_VDDO to
GPIO_VDDO
• Table 10, Power & Ground, on page 32, Pin# 24, GPIO_
VDDO added MDC_CPU and MDIO_CPU to definition.
Section 2, Application Examples
• Section 2.2.9, SERDES modes updated
• Section 2.4, LED Interface updated
• Figure 15, Typical SGMII connection to external PHY
connections title updated
Section 3, Electrical Specifications
• Added Section 3.1.1, Power Supply Sequencing
• Table 22, Recommended Operating Conditions updated
• Table 23, 88E6390/88E6190/88E6290 Device Current
Consumption added AVDD15_XTAL
• Section 3.5.2, RESET, removed
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M 1r5
A 5y
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Rev. -v1.00
D a te
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Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 97
Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
Revision
9x1qnoqie0t64dzijt1r55y9a6s8q710y5v35shvru8vh-kb7tar92
Table 53: Revision History (Sheet 1 of 3)
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88E6390/88E6190/88E6290 Datasheet
11-Port GE AVB/TSN Switch with 8 integrated PHYs and 2 SERDES
August 11, 2017
Section 1, Signal Description
• Table 6, Port 0 xMII Receive Interface, on page 25 updated
Pin# 101, P0_CRS definition and updated table footnotes
• Figure 8 through Figure 12 added resistors to figures
December 15, 2016
Section 1, Signal Description
• Figure 4 and Figure 5 updated pin names to remove Px_
LEDx names from pins 5, 6, 9, 10, 11, 12, 13 and 15
• Table 5, Port Status LEDs, on page 22 updated pin names
to remove Px_LEDx names
• Table 12, Pin List—Alphabetical by Signal Name, on
page 34 updated pin names to remove Px_LEDx names
from pins 5, 6, 9, 10, 11, 12, 13 and 15
Section 4, Mechanical Drawing
• Table 51, 144-pin E-PAD TQFP (16x16 mm) Package
Dimensions, on page 93 updated D2 and E2 dimensions
December 14, 2016
Section 2, Application Examples
• Table 17, LED Mapping, on page 49 updated table column
headings
Rev. -v0.11
December 9, 2016
Section 1, Signal Description
• Table 10, Power & Ground, on page 32 VDD_CORE from
1.05V to 1.1V
Rev -v0.10
November 9, 2016
Removed all edit marks.
Rev. -v0.09
October 27, 2016
Section 5, Part Order Numbering/Package Marking
• Table 52, 88E6390/88E6190/88E6290 Part Order Options,
on page 94 added 88E6290 I-Grade
Rev. -v0.08
October 28, 2016
Section , Overview
• Table 1, 88E6390/88E6190/88E6290 Device Differences
updated table
• Figure 2, 88E6190 Block Diagram and Figure 3, 88E6290
Block Diagram, updated figures
Section 1, Signal Description
• Table 2, Network 1G/2.5G SERDES Interface (Ports 9 to 10)
updated pin definitions
• Table 4, Reference, Clock and Reset updated XTAL_IN,
SE_SCLK and RESETn pin definitions
• Table 5, Port Status LEDs updated Px_LED, EE_DOUT and
C3_LED pin definitions
• Table 6, Port 0 xMII Receive Interface updated P0_INCLK,
P0_INDV, P0_CRS and P0_COL definitions
• Table 7, Port 0 xMII Transmit Interface updated P0_OUTEN
definition
• Table 8, GPIO updated GPIO[x] and Px_SMODE definitions
• Table 9, System & Register Access updated TEST definition
• Table 10, Power & Ground updated P0_VDDO and GPIO_
VDDO definitions
Section 3, Electrical Specifications
• Section Table 22:, Recommended Operating Conditions
added I-grade details
64
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Rev. -v0.13
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Doc. No. MV-S110663-00 Rev. A
Page 98
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Document Classification: Proprietary Information
Copyright © 2018 Marvell
January 23, 2018
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Description
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Rev. -v0.14
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
D a te
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Revision
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Table 53: Revision History (Sheet 2 of 3)
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•
Table 23, 88E6390/88E6190/88E6290 Device Current
Consumption added Typ values
• Table 46, SMI Clock Timing (PHY Set) updated MDC period
values, removed footnote 1
• Table 49, 2-Wire EEPROM Input Timing updated Freq and
TIN values
Section 5, Part Order Numbering/Package Marking
• Added I-grade details
October 26, 2016
Section , Overview
• Table 1, 88E6390/88E6190/88E6290 Device Differences
updated table
September 09, 2016
Section , Overview
• Started adding 88E6190 and 88E6290 device details
throughout
• Table 1, 88E6390/88E6190/88E6290 Device Differences
added table
• Figure 2, 88E6190 Block Diagram and Figure 3, 88E6290
Block Diagram, added figures
Section 2, Application Examples added section
Section 5, Part Order Numbering/Package Marking
• Added 88E6190 and 88E6290 details
Rev. -v0.05
September 29, 2015
Section 1, Signal Description
• Table 5, Port Status LEDs added PD resistors to EE_CLK,
C2_LED and C3_LED Type
• Table 6, Port 0 xMII Receive Interface Pin 100 renamed
from P5_COL to P0_COL
Rev. -v0.04
September 24, 2015
Section 3, Electrical Specifications
• Table 3.3.1, Thermal Conditions for the
88E6390/88E6190/88E6290 device 144-pin QFP Package
added Typ values
Rev. -v0.07
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Rev. -v0.06
August 4, 2015 September 21, 2015
Created datasheet.
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Rev.-v0.03 v0.01
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Copyright © 2018 Marvell
January 23, 2018
CONFIDENTIAL
Document Classification: Proprietary Information
Doc. No. MV-S110663-00 Rev. A
Page 99
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October 28, 2016
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Description
Rev. -v0.08
(cont.)
MARVELL CONFIDENTIAL - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
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Revision
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Table 53: Revision History (Sheet 3 of 3)
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Marvell Technology Group
http://www.marvell.com
Marvell. Moving Forward Faster
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Trunexa Infoways Private Limited * UNDER NDA# 5ebd420d0a
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