Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOSTM transistor
GENERAL DESCRIPTION
N-channel enhancement mode
standard level field-effect power
transistor in a plastic envelope using
’trench’ technology. The device
features very low on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended for use in switched mode
power supplies and general purpose
switching applications.
PINNING - TO220AB
PIN
IRFZ24N
QUICK REFERENCE DATA
SYMBOL
PARAMETER
VDS
ID
Ptot
Tj
RDS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 10 V
PIN CONFIGURATION
MAX.
UNIT
55
17
45
175
70
V
A
W
˚C
mΩ
SYMBOL
DESCRIPTION
d
tab
1
gate
2
drain
3
source
tab
g
drain
s
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDS
VDGR
±VGS
ID
ID
IDM
Ptot
Tstg, Tj
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
RGS = 20 kΩ
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
-
- 55
55
55
20
17
12
68
45
175
V
V
V
A
A
A
W
˚C
MIN.
MAX.
UNIT
-
2
kV
TYP.
MAX.
UNIT
-
3.3
K/W
60
-
K/W
ESD LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
VC
Electrostatic discharge capacitor
voltage, all pins
Human body model
(100 pF, 1.5 kΩ)
THERMAL RESISTANCES
SYMBOL
PARAMETER
CONDITIONS
Rth j-mb
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
-
Rth j-a
February 1999
in free air
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOSTM transistor
IRFZ24N
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
V(BR)DSS
Drain-source breakdown
voltage
Gate threshold voltage
VGS = 0 V; ID = 0.25 mA;
VGS(TO)
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
IDSS
Zero gate voltage drain current
VDS = 55 V; VGS = 0 V;
VGS = ±10 V; VDS = 0 V
IGSS
Gate source leakage current
±V(BR)GSS
RDS(ON)
Gate source breakdown voltage IG = ±1 mA;
Drain-source on-state
VGS = 10 V; ID = 10 A
resistance
Tj = 175˚C
Tj = 175˚C
Tj = 175˚C
MIN.
TYP.
MAX.
UNIT
55
50
2.0
1.0
16
-
3.0
0.05
0.04
60
-
4.0
4.4
10
500
1
20
70
157
V
V
V
V
µA
µA
µA
µA
V
mΩ
mΩ
MIN.
TYP.
MAX.
UNIT
DYNAMIC CHARACTERISTICS
Tmb = 25˚C unless otherwise specified
SYMBOL
PARAMETER
CONDITIONS
gfs
Forward transconductance
VDS = 25 V; ID = 10 A
1
-
-
S
Ciss
Coss
Crss
Input capacitance
Output capacitance
Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
-
365
110
60
500
135
85
pF
pF
pF
Qg
Qgs
Qgd
Total gate charge
Gate-cource charge
Gate-drain (miller) charge
VDD = 44 V; ID = 20 A; VGS = 10 V
-
-
19
5.2
7.2
nC
nC
nC
td on
tr
td off
tf
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 30 V; ID = 10 A;
VGS = 10 V; RG = 10 Ω
Resistive load
-
9
16
14
13
14
21
25
20
ns
ns
ns
ns
Ld
Internal drain inductance
-
3.5
-
nH
Ld
Internal drain inductance
-
4.5
-
nH
Ls
Internal source inductance
Measured from contact screw on
tab to centre of die
Measured from drain lead 6 mm
from package to centre of die
Measured from source lead 6 mm
from package to source bond pad
-
7.5
-
nH
MIN.
TYP.
MAX.
UNIT
-
-
17
A
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL
PARAMETER
IDR
IDRM
VSD
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
IF = 19.7 A; VGS = 0 V
-
0.95
68
1.2
A
V
trr
Qrr
Reverse recovery time
Reverse recovery charge
IF = 19.7 A; -dIF/dt = 100 A/µs;
VGS = -10 V; VR = 30 V
-
32
0.12
-
ns
µC
February 1999
CONDITIONS
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOSTM transistor
IRFZ24N
AVALANCHE LIMITING VALUE
SYMBOL
PARAMETER
CONDITIONS
WDSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
ID = 10 A; VDD ≤ 25 V;
VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
120
Normalised Power Derating
PD%
MIN.
TYP.
MAX.
UNIT
-
-
30
mJ
100
tp =
110
ID/A
100
1 us
RDS(ON) = VDS/ID
90
80
10us
70
60
10
50
100 us
40
30
DC
1 ms
20
10
10ms
100ms
0
0
20
40
60
80 100
Tmb / C
120
140
160
180
1
Fig.1. Normalised power dissipation.
PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
120
10
100
VDS/V
Fig.3. Safe operating area. Tmb = 25 ˚C
ID & IDM = f(VDS); IDM single pulse; parameter tp
Normalised Current Derating
ID%
1
10
Zth/ (K/W)
110
100
90
80
1
70
0.5
0.2
60
0.1
50
PD
0.05
40
0.1
30
tp
D=
0.02
tp
T
t
T
0
20
10
0
0
20
40
60
80 100
Tmb / C
120
140
160
0.01
180
Fig.2. Normalised continuous drain current.
ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V
February 1999
1.0E-06
0.0001
t/s
0.01
1
100
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOSTM transistor
IRFZ24N
9
50
16
14
VGS/V =
12
gfs/S
8
ID/A
10.0
9.5
9.0
8.5
40
7
8.0
30
6
7.5
7.0
20
5
6.5
4
6.0
10
5.5
0
5.0
4.5
4.0
0
2
4
VDS/V 6
8
10
3
2
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
120
0
5
10
ID/A
15
20
25
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
RDS(ON)/mOhm
2.5
VGS/V =
BUK959-60
a
Rds(on) normlised to 25degC
110
6
2
100
6.5
7
90
8
80
1.5
9 10
1
70
60
50
0
5
10 ID/A 15
20
25
0.5
-100
30
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
-50
0
50
Tmb / degC
100
150
200
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 10 A; VGS = 10 V
25
5
VGS(TO) / V
ID/A
BUK759-60
max.
20
4
typ.
15
3
10
2
min.
1
5
Tj/C =
0
0
1
2
175
3
25
4
5
VGS/V
6
7
8
0
-100
9
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
February 1999
-50
0
50
Tj / C
100
150
200
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOSTM transistor
IRFZ24N
100
Sub-Threshold Conduction
1E-01
IF/A
80
1E-02
2%
1E-03
typ
60
98%
Tj/C =
20
1E-05
0
0
1
2
3
4
5
Fig.11. Sub-threshold drain current.
ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
0
0.5
1
VSDS/V
1.5
Fig.14. Typical reverse diode current.
IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
1
Thousands pF
25
40
1E-04
1E-06
175
120
.9
110
.8
100
WDSS%
90
.7
80
.6
70
.5
60
50
.4
40
Ciss
.3
30
.2
20
.1
0
0.01
0.1
1
10
VDS/V
10
Coss
Crss
100
0
20
Fig.12. Typical capacitances, Ciss, Coss, Crss.
C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
40
60
80
100
120
Tmb / C
140
160
180
Fig.15. Normalised avalanche energy rating.
WDSS% = f(Tmb); conditions: ID = 17 A
12
VGS/V
L
VDS = 14V
8
VDS
VDS = 44V
-
VGS
6
-ID/100
T.U.T.
0
4
RGS
2
0
VDD
+
10
0
5
QG/nC
10
15
Fig.16. Avalanche energy test circuit.
WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD )
Fig.13. Typical turn-on gate-charge characteristics.
VGS = f(QG); conditions: ID = 20 A; parameter VDS
February 1999
R 01
shunt
5
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOSTM transistor
+
IRFZ24N
VDD
RD
VDS
-
VGS
RG
0
T.U.T.
Fig.17. Switching test circuit.
February 1999
6
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOSTM transistor
IRFZ24N
MECHANICAL DATA
Dimensions in mm
4,5
max
Net Mass: 2 g
10,3
max
1,3
3,7
2,8
5,9
min
15,8
max
3,0 max
not tinned
3,0
13,5
min
1,3
max 1 2 3
(2x)
0,9 max (3x)
2,54 2,54
0,6
2,4
Fig.18. SOT78 (TO220AB); pin 2 connected to mounting base.
Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to mounting instructions for SOT78 (TO220) envelopes.
3. Epoxy meets UL94 V0 at 1/8".
February 1999
7
Rev 1.000
Philips Semiconductors
Product specification
N-channel enhancement mode
TrenchMOSTM transistor
IRFZ24N
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
 Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
February 1999
8
Rev 1.000