Transmit
Buffer
Data Bus
Buffer
WR
RD
RESET
CLK
CID
TXD
I
Read/Write
Control
Logic
N
T
E
R
N
A
L
TXRDY
Transmit
Control
TXEMPTY
Receiver
Buffer
RXD
TXC
cs
B
u
s
DSR
DTR
CTS
RTS
Modem
Control
RXRDY
Receive
Control
Fig.
825 IA Internal Architecture
RXC
SYNDET/BRKDET
01
2
28
27
3
26
Vee
4
25
RXC
04
5
24
DTR
Ds
Ds
D7
6
23
7
22
21
RTS
DSR
RESET
TXC
-g
20
CLK
D2
1
D3
RXD
GND
8
8251A
Do
WR
10
19
TXD
cs
11
18
TXEMP~
CID
-
12
17
CTS
RD
13
16
RXRDY
14
15
SYNDET/8D
TXRDY
Fig.
825 I A Pin Configuration
'
Stopbit
Selection
Invalid
1 bit
1 bit
2 bits
D7
D5
D5
PEN
D4
L2
D3
L1
D
B2
D
B1
D
I
Baud Rate Select
0
1
0
7 Bits
6 Bits
5 Bits
1
1
0
0
1
0
1
0
64 XAsynch
16 XAsynch
1 XAsynch
Synch. Mode
Character Length
Selection
0
0
8 Bits
'
1
1
'
1
l
EP
t
1-Parity
enable
0 -Disable
'
S1
,,
parity
0-0dd
1-Even
parity
, I;
S2
'
0
1
0
0
0
1
1
1
N .B.-Stop bit selection as above is only for transmitter. Receiver never requires
'
Mode Instruction Format Asynchronous Mode
more than one stop bit
fif
Generated by 8251
D0-D1
Transmitter Output
Dx
~---'/- - - - -. - - r - - 1 - - ~ ~
)
TXD Marking
Start
Bit
Parity
Bit
l
Stop
Bit
l..- X Programmed-\
I by character length
Does not appear
on data bus
Dx
Receiver Input
RXD
Parity
Bit
Start
Bit
____
Transmission Format
Stop
Bit
\ CPU Byte (5-8 bits/char.)
__,
Assembled Data_ 0/P TXD
-4
Start
Bit
Receive Format
Data Character
Parity
Bit
Stoo
- Bit
~l:-Serial Data Input
Start
Bit
Data Character
Parity
Bit
Stop
Bit
CPU Byte (5-8 bits)
Fig.
Asynchronous Mode Transmit and Receive Formats
Do
02
SCS
ESD
EP
PEN
0
L2
0
Character Length*
0
0
5 Bits
0
1
6 Bits
Single Char. Sync
1
0
7 Bits
1-Single SYNC Char.
0-Double SYNC Char.
1
1
8 Bits
1-Parity enable
0-Disable
1-Even parity generate and che
0-Odd parity
External Sync. Detect
1-SYNDET is Input
....-------0-SYNDET is Output
* If the character size less than 8-bits, the remaining bits are set to 'O' .
Fig. 6.30
Synchronous Mode Instruction Format
Automatically inserted by 8251A
DATA
DATA
SYNC1
SYNC2
DATA
l-- -----------
'
TXEMPTY _
____,/
Fig.
Falls after CPU write
DATA to 8251
TXEMPTY Signal and SYNC Characters
* N .B . -If the character size is less than 8-bits, the remaining bits are set to 'O' .
DATA CHARACTERS (5-8 BITS )
ASSEMBLED SERIAL DATA OUPUT (TXD )
SYNC
CHAR 1
DATA CHARACTERS (5-8 BITS )
SYNC
CHAR 2
RECEIVE FORMAT
SERIAL DATA INPUT (RXD)
SYNC
CHAR 1
DATA CHARACTERS (5-8 BITS )
SYNC
CHAR 2
RECEIVED BYTE
l
DATA CHARACTERS (5-8 BITS )
Fig. 6.32
Data Formats
of Synchronous Mode
Do
EN
IR
RTS
ER
SBRK
RXE
DTR
TXEN
1- Transmit Enable
0- Disable
i-'It= 1, HUNT
For SYNC Character
Internal Reset "High"
Forces
8251A to mode Inst.
Format
Request to Send
If= 1
Forces RTS o
=
Reset Error Flags
PE, OE, FE if ER = 1
Data Terminal Ready
If= 1, DTR 0
=
..'
Receive Enable
1- Enable
0- Disable
-
-
,
Fi&
Command Instruction Format
Send Brake Character
1- TXD forced •o '
0- Normal Operation
D7
D5
FE*
D5
OE*
D4
PE*
D3
t
D2
,-
01
Do
TXRDY
w
This bit indicates, USART
is ready to accept a data
character or command.
This has a different meaning than TXRDY pin .
Same
functions
as pins
t
TXEMPTY I RXRDY
.,.
Status Read Instruction Format
* Any of the Flag setting does not inhibit the 8251A operation
Parity Error
Flag is set
if error detected.
Reset by ER bit
of command
instruction
""'
SYNDET
...
DSR
This bit
indicates
that DSR
is at zero
level.
Framing error flag
is set when a valid
stop bit is not detected
at the end of every
character and reset by
ER bit of command
instruction.
This flag is set when
the CPU does not read
a character before the
next one becomes
available and is reset by
command instruction.
The overrun character
is lost.
-
Fii