Lecture 10 FlipFlops/Latches
• Sequential switching network
– Output depends on present input
and past sequence of inputs.
– Need to remember past history.
– Flip-flop (latch) is a memory that
has a pair of complementary
outputs.
Chap 11
CH1
Gate Delay
• Propagation delay
• Timing diagram
Chap 11
CH2
Network with Feedback
• Inverter with feedback.
– Propagation delay (d = ½ period of CK)
– Oscillate between 1 and 0.
• Stable state
Chap 11
CH3
S-R Latch
• Set-reset latch
– Use NOR gate to construct a stable
state network
Chap 11
CH4
S-R Latch (cont.)
• When S=R=1, the S-R latch will not
operate properly. (Is it a stable state,
if S=R=1?)
– Q an P are not complementary.
– If S=R=1 changed to S=R=0, then the
network will oscillate assuming both
gates have the same delay. (Critical race
occurs)
Chap 11
CH5
S-R Latch Timing and
State
• S duration > delay time
• S-R latch behavior
– Present state
• The state of Q output at the time the input
signals are applied.
– Next state
• The state of Q output after the latch has reacted
to the input signals.
Chap 11
CH6
S R latch Analysis
• Total state table
• If next state = present state, stable
0
y0(t)
0
y1(t)
1
1
0
1
Chap 11
y1(t)
y0(t)
CH7
K-map for Q(t+)
• Q+ = S + R’Q
(SR=0)
– S and R can not be 1 at the same time.
– Q: present state
– Q+: next state
– Next state equation or characteristic
equation.
Chap 11
CH8
Debouncing Circuit
• Use S-R latch for debouncing.
• Pull-down resistors
• a switch to b.
S= 1 set Q
S = 0, (R=0)
Q remained
R = 1 set Q = 0
Chap 11
CH9
S-R Latch using NAND
gates
• S#-R# Latch, when S#= 0 sets Q = 1
and R#=0 resets Q = 0
S#
1
1
1
1
0
0
0
0
Chap 11
R#
1
1
0
0
1
1
0
0
Q
0
1
0
1
0
1
0
1
Q+
0
1
0
0
1
1
-
C H 10
Gated D Latch
• Gate input G
– Transparent latch (when G= 1, Q = D)
Chap 11
G
0
0
0
0
1
1
1
1
D
0
0
1
1
0
0
1
1
Q
0
1
0
1
0
1
0
1
Q+
0
1
0
1
0
0
1
1 C H 11
Edge-Triggered D FlipFlop
• Output changes in response to clock
edge
Chap 11
C H 12
D Flip-Flop
• Using two gated D latches
• Output changes occur at the rising
edge
– CK = H, output follows input.
– CK = L, output remains
P follows
D
Q follows
P follows
PChap 11
D
Q follows
PC H 13
D Flip-Flop
• Output changes occur at the rising
edge
Move towards rising edge of G2
∆t = D1 latch’s propagation delay
This is the setup time for this FF.
Chap 11
C H 14
Setup and Hold Time
• Edge-Triggered D FF
– Propagation delay of a FF is the time
btw the active edge of the clock and
resulting change in the output
Chap 11
C H 15
Minimum Clock Period
• tp
– inverter = 2 ns,
– FF = 5ns
• Setup time 3 ns
Chap 11
C H 16
Master-Slave S-R Flip-Flop
•
•
•
FF has a clock input.
Change state after rising edge
This figure shows a case that (S, R) are
changed at CLK = H (A,B), then at
CLK=L for C.
– What if (S,R) becomes (1,0) nears t5? (OK)
•
Asserted Input (S-R) has effect on output
Q only at the time of Master on.
CLK’
P
H
A
H
B
Q
C
(1,0)
M on
S on
Chap 11
M on S on
M on
H
Input
changed
at CLK
low to
(0,0) has
no effect
to P due to
S-R latch
feature.
S on C H 17
Explaining at CLK =
H clock is correct.
Toggle FF
• T flip-flop
– Single input
– When T = 1, at clock edge, T FF
changes state. If T = 0, no state changes.
T
0
0
1
1
Q
0
1
0
1
Q+
0 Q+ = T’Q + TQ’ = T xor Q
1
1
0
Chap 11
C H 18
T FF
• T flip-flop
– Converted from D to T
– Q+ = D = Q xor T= TQ’ + T’Q
T
0
0
1
1
Q
0
1
0
1
Q+
0 Q+ = T’Q + TQ’ = T xor Q
1
1
0
Chap 11
C H 19
J-K Flip Flop
• J-K FF = S-R FF + T FF.
– Allow J = K = 1. This case works like a
T FF.
J K Q Q + = JQ’ + K’Q
– Split T to J and K 0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Chap 11
C H 20
J-K Flip Flop
• J-K FF rising
edge trigger
J
0
0
0
0
1
1
1
1
K Q Q + = JQ’ + K’Q
0 0 0
0 1 1
1 0 0
1 1 0
0 0 1
0 1 1
1 0 1
1 1 0
Chap 11
C H 21
Master-Slave J-K FlipFlop
• Clocked J-K FF (falling edge)
– Realization using two S-R latches
– Note where J and K change.
Chap 11
C H 22
T Flip-Flop
Implementation
• Conversion
– Using a J-K FF
– Using a D FF
Chap 11
C H 23
D FF Register
• Register = many clocked D FFs
• Q+ = D
Chap 11
C H 24
Clear and Presets
• Active low inputs
• Asynchronous clear and preset
Chap 11
preset
C H 25
Clock Enable
•
•
•
•
D-CE flip-flop
Hold existing data even input changes.
Q+ = Q.CE’ + D.CE
In Fig. c, Q+ = D = Q.CE’ + Din.CE
– No gating in clock line, no synchronization
problem.
CLK
Move effective falling edge ahead
(falling edge time is changed)
En
Risk of loss
of synchronization
Chap 11
C H 26
Clocked Latches
Clocked latch:
The state changed whenever the
inputs change and the clock is
asserted.
A D latch with NOR gates and
clock (level trigger)
Chap 11
C H 27
Unclocked Latch
• SR latch
– State may change if input changes.
Chap 11
C H 28
S R latch Analysis
• Total state table
• Next internal state
y1(t)
y0(t)
y1(t)
y0(t)
Chap 11
C H 29
D Flip Flop
• Master latch with a slave latch
– State changes only at clock edge.
– Falling edge.
Chap 11
C H 30
Timing Requirement
• Falling edge trigger
– Set up time
– Hold time
• Hold time requirement is either 0
or very small.
Chap 11
C H 31
Clock Period Requirement
• Clock period requirement
– t_propagation + t_combinational
+ t_setup + t_skew
– t_propagation is the time for FF
inputs to FF outputs.
– t_skew is the time difference
when two state elements see a
clock edge.
Chap 11
C H 32
Asynchronous inputs
• Why makes it a synchronous
input?
– Used to change state of a system
– If not synchronized, the signals
may violate the setup time or hold
time of a receiving device.
• Metastable behavior
– State in the middle of 1 and 0.
Chap 11
C H 33
A Gated D Latch
Whenever D or Clk changes, Q changes
.
Clk
Not a real register!!
A Verilog register
needed because of
assignment in
always block
Clk
module D_latch (D, Clk, Q);
input D, Clk;
output reg Q;
always @(D, Clk)
if (Clk)
Q = D;
endmodule
Q = D if Clk = 1. The Verilog compiler assumes that
the value of Q caused by the if must be
maintained when Clk is not equal to 1.
This implies that a memory, a latch is instantiated.
34
A D Flip-Flop
module flipflop (D, Clk, Q);
input D, Clk;
output reg Q;
always @(posedge Clk)
Q = D;
endmodule
posedge
negedge
35
Blocking assignment: evaluation and
assignment are immediate
Blocking assignment:
always @ (a or b or c)
begin
x = a | b;
1. evaluate a | b, and assign result to x
y = a ^ b ^ c;
2. evaluate a ^ b^c, and assign result to y
end
36
Non-Blocking assignment
Nonblocking assignment: all assignments deferred until all righthand sides have been evaluated (end of simulation timestep)
always @ (a or b or c)
begin
x <= a | b;
1. evaluate a | b, but defer assignment of x
y <= a ^ b ^ c;
2. evaluate a ^ b^c, but defer assignment of y
end
3. assign x, y with their new values
• Non-blocking assignment is 2-step processes:
• Step 1: Evaluate the RHS
• Step 2: Update the LHS
• Sometimes, as above, blocking and non-blocking produce the same
result.
• Sometimes, not!
37
Why two ways of assigning values?
38
Verilog Simulation Behavior
• Always blocks and “assign” statements execute in parallel
• Signals in the sensitivity list (@(..)) trigger the always blocks.
• “assign” triggered when RHS signal changes.
• All non-blocking assignment statements in an always block are
evaluated using the values that the variables have when the always
block is entered.
• That is, a given variable has the same value for all statements in the block.
• The result of each non-blocking assignment is not seen until the end of the
always block.
39
Blocking Assignment
module two-FFs (D, Clock, Q1, Q2);
input D, Clock;
output reg Q1, Q2;
always @(posedge Clock)
begin
Q1 = D;
Q2 = Q1;
end
// blocking assignment here, so at rising clock
edge,
Q1=D, after that, Q2 = Q1, so Q2=Q1=D
This implies a circuit below:
D
D
Clock
Q
Q1
Q
endmodule
在+ edge 時
Q1及 Q2
都變成D
D
Q
Q2
Q
40
Non-Blocking Assignment
// at the rising clock edge,
Q1 and Q2 simultaneously receive the old values of D, and Q1.
module two-FFs (D, Clock, Q1, Q2);
input D, Clock;
output reg Q1, Q2;
D
always @(posedge Clock)
begin
Clock
Q1 <= D;
Q2 <= Q1;
end
// at the end of always block, Q1 and Q2
change to a new value concurrently.
endmodule
D
Q
Q
Q1
D
Q
Q2
Q
41
D-FF with Asynchronous Reset (Clear)
module flipflop (D, Clock, ClrN, Q);
input D, Clock, ClrN;
output reg Q;
always @(negedge ClrN, posedge Clock)
if (!ClrN) // if clear, then,
Q <= 0;
else
// normal update
Q <= D;
endmodule
What about both? PreN and ClrN
42
D-FF with Synchronous Reset
module flipflop (D, Clock, ClrN, Q);
input D, Clock, ClrN;
output reg Q;
always @(posedge Clock)
if (!ClrN) // if clear, then,
Q <= 0;
else
// normal update
Q <= D;
endmodule
43