Renewable and Sustainable Energy Reviews 89 (2018) 194–203
Contents lists available at ScienceDirect
Renewable and Sustainable Energy Reviews
journal homepage: www.elsevier.com/locate/rser
A review on carbon nanotube field effect transistors (CNTFETs) for ultra-low
power applications
T
⁎
P. Prakasha, , K. Mohana Sundarama, M. Anto Bennetb
a
b
Department of Electrical and Electronics Engineering, Vel Tech Multitech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai 600062, India
Department of Electronics and Communication Engineering, Vel Tech, Chennai 600062, India
A R T I C LE I N FO
A B S T R A C T
Keywords:
MOSFET scaling
CNTFET
Device modeling
Simulation
Device fabrication
Presently, the battery life and high spectral efficiency are found to be a perennial problem in smartphones. With
the advancement in the technologies towards 5 G, it has become mandatory to meet these challenges before
problems are aggravated. Besides, CNTFET technology is found to be a promising field of research that is recommended in this review to solve these problems. The intention of this study is to provide an overview of most
recent research on the state-of-the-art of CNTFETs. Several papers were reviewed that include the device
modeling, simulation, device fabrication and its applications. However, the majority of these papers were observed to deal with digital applications, while the papers related to analog applications were limited. Moreover,
this review provides the information regarding the results obtained from the device circuit performance and the
scope for future prospects.
1. Introduction
Recent studies indicate that the supply of affordable and sustainable
energy is required to maintain and improve the quality of life. Also, the
sustainable energy influences technologies involving solar energy, hydroelectricity, wave power, wind energy, bioenergy, geothermal energy, and tidal power. Amongst these, the sun is a natural source of
power and is expected to provide radiation for about 4 billion years.
Thus, solar power (photovoltaic) systems are considered as a sustainable method to convert the energy from the sun into electricity [1]. The
existing solar technology was found to limit efficiency and is acknowledged as a significant obstacle in implementing the large-scale
generation of solar powered energy. Presently, photovoltaic (PV) panels
were observed to convert only 16% of the sunlight that penetrates
through them. Researchers at the Energy Department's National Renewable Energy Laboratory (NREL) have found out that Single-Walled
Carbon Nano Tube (SWCNT) semiconductors could be favorable for
photovoltaic systems because it can efficiently convert sunlight into
electricity without losing much energy. Besides, the films made of
SWCNTs were observed to have a large effective area conferring them
high optical absorption and were found to contribute towards the energy harvesting utilizing Si. In this research, it was observed that up to
12% photo conversion efficiency was reported on employing photovoltaic devices and 100% of internal quantum efficiency (IQE) was
reported [2].
⁎
In this review, it is noticed that majority of the PV devices need the
electrons and holes present in the interface to be separated as soon as
the absorption of the photons is processed and in return produces the
electric current. During this process, the molecules involved will undergo a structural reorganization of the bonds resulting in energy loss
and is referred to as reorganization of energy. Most recently, the NREL
researchers have found that only little amount of energy is lost when
the Single-Walled Carbon Nano Tube (SWCNT) semiconductors are
combined with the fullerene molecules [3]. Therefore, this has opened
new avenues in the research of Carbon Nanotube-based semiconductor
device technology. A semiconductor is a significant part of the electronics industry, and entirely the computerized systems depend on
them, including solar cells. A carbon nanotube field-effect transistor
(CNTFET) corresponds to a FET that uses single or multiple carbon
nanotubes as the channel instead of using bulk silicon as in the traditional MOSFET structure.
1.1. Scaling of MOSFET
In 1965, Dr Gordon E. Moore predicted an increase in the number of
transistors integrated on an IC and suggested that it would be doubled
every year [4]. This was presented as an observation in the initial
phase. However, it became the base for the current semiconductor
technology and paved a glorious path for more than 50 years of miniaturization and continues till date. Tragically, the recent prediction of
Corresponding author.
E-mail address: mp.prakash09@gmail.com (P. Prakash).
https://doi.org/10.1016/j.rser.2018.03.021
Received 30 August 2016; Received in revised form 10 March 2018; Accepted 14 March 2018
1364-0321/ © 2018 Elsevier Ltd. All rights reserved.
Renewable and Sustainable Energy Reviews 89 (2018) 194–203
P. Prakash et al.
be prepared in a selected material [13].
Lorraine Rispal et al. [14] have reported on the fabrication of
CNTFETs by using CVD (Chemical Vapour Deposition) Method. The
work is summarized as below.
the 2015 International Technology Roadmap for Semiconductors [5]
states that the transistor could stop shrinking in another five years. This
has been interpreted as death knell regarding Moore's Law. This is because the industry is not able to sustain the scaling of CMOS. The SiMOSFET scaling has already moved towards its limiting value for several reasons including very high leakage currents, high power density,
large parametric variations and decreased gate control which makes it
less suitable for the near future ultra-low-power and ultra-high-speed
applications. These drawbacks of the current technology lead to the
investigations of various alternatives to keep the Moore's Law “get
going”. Furthermore, compared to conventional silicon MOSFETs,
Carbon nanotube MOSFETs were found to provide better scalability and
performance with suppressed short-channel effects and higher carrier
mobility. This indicates future scope in the use of carbon as a promising
candidate to replace silicon as the fundamental building material of
integrated circuits in the future [6].
(1) In the first step, highly doped p-type silicon wafers were used to
serve as back-gate.
(2) Oxidation was performed. Nickel (1 nm) on Aluminum (10 nm) was
chosen to be the catalyst layer and was evaporated to facilitate
SWNT growth.
(3) The next step involved annealing in inert ambient followed by CVD.
Nitrogen followed by methane was supplied, and the CNT growth
takes place for 10 mins.
(4) Finally, using lift-off method palladium source and drain electrodes
were structured.
2.2. Improved CCVD method
1.2. Investigation of various alternatives
The expansion of CCVD is Catalyst Chemical Vapour Deposition.
This method is the enhanced method of CVD growth. In this method,
metal catalysts are used for depositing materials on thermally sensitive
substrates at low temperature. Therefore, the researchers suggest that
the growth window of ACCVD will provide the platform to improve the
robustness of ACCVD and the controllability over the product, thereby
providing a better understanding of the growth mechanisms involved in
Carbon Nano Tubes [15]. Martin Keyn and UdoSchwalke [16] conducted the experimental investigation of CCVD (Catalytic Chemical
Vapour Deposition) grown CNTs. The highlights of the fabrication
methodology are presented as follows.
Recent study, suggests the beginning of a new era with the advancement of technology beyond CMOS [7]. Many alternatives for
MOSFET such as FinFET [10], TFET [11] and JLITFET [12] were proposed. However, those alternatives were not able to compete with
CNTFET for numerous remarkable reasons. For many researchers, the
quest for an ideal semiconductor to be used in FETs was quenched when
Carbon Nanotubes (CNTs) were first shown to yield promising properties of these devices [7]. Its natural ultrathin body, efficient electron
and hole transport properties and reasonable energy gap offer best solutions when compared to other semiconductors that are scaled to the
sub-10 nm regime.
Therefore, it has been suggested and accepted by practically all the
researchers and industry experts that CNTFET would be the device of
choice for next generation VLSI chips with its high performance and
smaller dimensions. This has also been emphasized by M. Schröter et al.
[8] in the review article. Owing to the similarity between CNTFET and
CMOS in case of operation principle and the device structure, the established CMOS design infrastructure can be performed in the CNTFET
technology at ease. Also, the CNTFET based circuits are expected to be
3× faster than silicon transistors, while consuming the same power.
Besides, Marani et al. stated that future scope of CNTFET will involve
the investigation of the circuit model and its characteristics that could
be used to provide the required power and could be tested on real-time
devices [9].
The present review gives a rapid overview of important literature
presented on carbon nanotube FETs for ultra-low power applications.
Firstly, it reviews the technology involved in the fabrication of
CNTFETs. Secondly, the reports on the Device Modeling of CNTFETs are
compiled. Thirdly, the different design approaches and the simulated
characteristics of CNTFETs are discussed. Finally, the possible applications of CNTFETs presented in the literature are compiled.
(1) One-sided polished and p-doped silicon wafers were taken as substrates.
(2) Oxidation was carried out at 1000 oC in a dry oxygen atmosphere
and the resulting oxide served as a gate oxide.
(3) The catalytic double layer is composed of a 5 nm aluminum layer
and the 0.9 nm nickel layer. Annealing and CCVD were carried out
successfully for 5 min
(4) Lift-off lithography was performed to realize the electrical contacts
which are connected by the beforehand grown CNTs. The adhesion
of the contacts was improved by annealing at 400 oC in forming the
gas. Finally, undiluted HCl was used to remove the backside oxide.
Above approaches were able to supersede the previous processes by
focusing on three parameters that made the difference which are (1)
Oxygen plasma treatment (2) CCVD processing time and (3)
Composition of the catalytic double layer. Such process of fabrication
technique had big advantages when compared to other existing technologies. As a result of growing CNTs in-situ, all the undesirable effects
of misplacement and possible damages were avoided. In this manner,
CNTFET of excellent quality were produced.
2. Process technology
2.3. Dielectrophoresis (DEP)
The Process Technology refers to the overall integration process
including lithography, doping, etching, deposition, testing methodology and the equipment used for testing etc. The front-runners in the
process technology of CNTFETs are illustrated in this section.
Dielectrophoresis is defined as the phenomenon in which a force is
exerted onto a dielectric material when it is under the influence of a
non-uniform electric field. The application of DEP-assisted integration
approach was investigated on the sensor resistance distribution which
has the ability to control the property of sensor distribution [17].
Furthermore, Zhigang Xiao et al. [18] have fabricated the CNTFET with
dielectrophoresis method. The designed CNTFET has 3 µm as channel
length and 10 µm as width. The step by step procedure is presented
here.
2.1. CVD growth
CVD stands for Chemical Vapour Deposition. This process refers to
the deposition of a material from a gas onto a substrate that involves
chemical reactions. Chemical Vapour Deposition was utilized to determine the characterization of the films that will affect the morphology
and crystallinity of the films. This study used appropriate deposition
conditions to allow the coatings with superior photocatalytic activity to
(1) The silicon wafer of 350 µm thickness was taken as the substrate
and it was oxidized for 20 mins at 1100o C temperature in the
presence of moisture.
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P. Prakash et al.
circuit indicates that these would enhance the efficiency of spin injection in CNT and would be useful for spintronics applications. Thus,
further research is required to add more functionality in the future CNTbased logic devices and circuits [22]
(2) Ultra-Violet lithography and lift-off process did the patterning
process.
(3) Two electrodes such as Chromium (Cr with 5-nm thickness) and
gold (Au with 50-nm thickness) were used for deposition and
alignment of SWCNTs. Application of Dielectrophoresis process was
responsible for aligning and depositing the CNTs across the electrodes.
(4) Through electron-beam evaporation Hafnium dioxide (HfO2) of
20 nm thickness was deposited for gate oxide. Finally, an aluminum
thin film of 500 nm thickness was deposited and etched forming the
metallization step and annealed the wafer for 20 mins at 350 °C in
the vacuum of 5 × 10–5 Torr. The above method produced
SWCNTs with the higher level of purity.
3.1.2. Quasi-ballistic
Quasi-Ballistic conduction refers to the transportation in which the
electrons face only a small amount of scattering in its path from the
source to drain. This conduction is explored in developing the Quasi
Ballistic CNTFET. Chi-Shuen Lee et al. [23] have reported a compact
virtual-source model of CNTFETs. In this model, the carrier transport
was assumed to be quasi-ballistic. The drain current was defined as the
product of the mobile charge density and carrier velocity where the
carrier velocity was a crucial factor in determining the drive current
and the delay of any device. Here the carrier velocity was directly extracted from the measured data of the model. The experimental results
revealed that the VS-model could achieve a carrier velocity of
3.8 × 107 cm/s with 15-nm gate length. Moreover, several experiments
were conducted to gain insight towards the underlying mechanism of
the observed experimental results; the study was conducted to provide a
principle indication on the interaction of interhalogens with metallic
and semi conductive CNTs [24]. It is observed that CNTFETs possess the
higher potential for the future semiconductor technology.
2.4. Photo stepper-based process
A photo stepper is an equipment used in the IC manufacturing. The
circuit pattern modulated with EM radiation is exposed over a layer of
resist on the semiconductor wafer by this equipment. M. Schroter et al.
[19] have fabricated Depletion-mode CNTFETs on 4′’ Wafer with photo
stepper process. The process used a stepper with i-line lithography, and
the carbon nanotubes were grown from a catalyst. This enabled the
placement of CNTFETs having different sizes anywhere on the chip.
After the catalyst got deposited which was referred to as mask1 the
CNTs were grown in a CVD furnace. A mask2 was used to place the
source and drain electrodes. Mask3 was used for the gate terminal. A
mask4 was used for the inter-dielectric isolation layer. Finally, a fifth
mask defined the contacts and pads which are then tested by fabricating
RF-amplifier and have concluded that the test chip contained devices
over 200 different structures and sizes per die on a 4′’ wafer and attributed the success to the massively parallel nature of the channel. The
presently used CNTFETs were limited in output power and the fabrication process by employing photo stepper will drive the available
capabilities comprising of a large density of residual metallic tubes,
power consumption and phase noise will be reduced with established
and mature technologies [20].
3.1.3. Non- ballastic model
In contrast, the non-ballistic conduction of electrons corresponds to
the electron flow that is limited by scattering due to the resistivity in
the path. The non-ballistic model utilizes this phenomenon in modeling
the CNTFET.
Igor Bejenari and Martin Claus [25] have developed a novel nonballistic model where the ohmic contacts and the electron-photon
scattering methodology were incorporated to determine the accumulation of electrons at the bottom of the conduction sub band. Thus, it
justifies the use of the Boltzmann transport equation solver.
The findings are summarized as follows:
1. The injection of drain electrons into the channel was affected by
back-scattered source electrons that accumulated at the bottom of
the conduction sub band.
2. While modeling, both the forward and backward electron scattering
by optical phonons should be considered.
3. Device modeling
A device model is an equivalent circuit comprising of components
that will assist in the prediction, analyzing the device behavior and
circuit performance. Besides, efforts regularly made to accurately
model the CNTFETs are still in progress.
These studies provide an overview about CNTFETs with n-type
ohmic contacts and considered electron scattering by both acoustic and
optical phonons. The channel length was set to 100 nm in order to make
it compatible with high-frequency analog applications. The schematic
band diagram of the CNTFET, considering the electron backscattering
by optical phonons has been illustrated for three different gate bias
conditions.
3.1. Transport models
A Transport Model aids in understanding the steady-state electron
transport inside the transistor. It also explains the process involved in
the electron drifts and its limitations. Specific transport models available in the literature are compiled and presented below.
3.1.4. Tunneling-based
Tunneling is a phenomenon in which the electrons tunnel through a
barrier because it couldn’t jump over it. This effect is the major cause of
the leakage of current and also causes heat dissipation. BTBT (Band-toBand Tunneling) refers to the ability of electrons to tunnel from the
valence band to conduction band or vice-versa. Merging of SWCNTs
and BTBT has been the hot subject of the recent years. It has been taken
into account while modeling the Tunneling-based CNTFETs. Azzedin D
Es- Sakhi and Masud H Chowdhury [26] have constructed and demonstrated the concept and operation of Multichannel Tunneling
Carbon Nanotube Field Effect Transistor. Three SWCNTs were placed as
the channel that formed the tunneling path. The gate surrounded the
SWCNTs. The arrangement supports a high ION and provided three
identical and parallel current paths increasing the overall tunneling
current density. The outcome proves that a careful placement of the
SWCNTs between the source and drain would increase the probability
3.1.1. Ballistic
Ballistic conduction means that the electron conductivity takes
place in a medium without any resistance. It also means that there is no
unnecessary scattering of electrons due to the presence of impurities.
This is considered in modeling ballistic CNTFET. Mostafa Fedway et al.
[21] have successfully studied the I-V characteristics model for the
ballistic CNTFET. Major objectives were to calculate the sub band
minima, the number of effective subbands and the output drain current
of CNTFET which was eventually succeeded For this purpose, a
MOSFET like CNTFET numerical model was developed based on zone
folding method. The I-V characteristics of the ballistic CNTFET were
dependent on the number of contributed sub bands. The results show
the model reduced 23% of the running time and also achieved a root
mean square error of 0.9%.
Furthermore, recent study on a more sophisticated CMOS logic
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of tunneling current leading to higher ION. Further, studies were conducted to provide insights into the efficiency of introduced nanoparticles. In addition, examining the particles in the fraction that will be
utilized for the participation in conduction and the arrangement of
geometrical parameters and fraction of nanoparticles in the compound
were also carried out. This research was utilized to optimize the doping
strategy. However, more conductive materials need to be designed
using fewer nanoparticles in order to reduce the production cost and the
environmental footprint [27].
6. The steps 2–5 were repeated for all the conditions of Vd and Vg.
7. Finally, using EF, αg, αd and β the transfer and output characteristics were optimized.
3.3. FEM model
This model subdivides a larger problem into smaller sub problems
called Finite Elements. The equations that model these elements are
assembled to obtain the system of equations that model the entire
problem. The finite element models were developed to control the
fracture in fabrics in addition to delamination progression and fabric
fracture that were identified by utilizing the observations obtained from
the microscope. Thus, experiments in accordance with the numerical
data are conducted to assess the effectiveness of the implemented
methodology [32]. Md. Rakibul Karim Akanda and Quazi D. M. Khosru
[33] have developed an accurate 3D-model of the CNTFET for evaluating the circuit performance in terms of ON-current, speed and power.
Here multiple cylindrical conducting channels with wrap-around gate
structure were considered. The device was constructed with k1 as a
dielectric constant for gate oxide and k2 as a dielectric constant for the
substrate. Firstly, when modeling of Gate-to-channel capacitance the
shape of gate dielectric around the CNT channel was considered to be
rectangular. The objects at the end of the array will have capacitance as
Cgc,e as the screening objects are only at one side. Cgc,m and Cgc,e are
the unit capacitance of the gate to the middle cylinders and unit capacitance of the gate to the end cylinders.
The Table 1 presents the list of drain currents as illustrated by different models presented in this review.
3.1.5. Thermionic
Thermionic emission refers to the emission of electrons from a heated source. Where the thermionic model assumes that the electric field
heats the electrons released form the thermionic emission of hot electrons. Montassar Najari et al. [28] have modeled the compact model for
Schottky Barrier (SB) Carbon nanotube field effect transistor. The SBCNTFET were operated by varying the source and drain transparence.
In the modeling approach, the carriers at the metal and CNT interface
encountered different barrier heights. Here the carriers possessing energy above the SB height reached the channel by thermionic emission.
The remaining carriers with energy less than the SB height reached the
channel by tunneling emission and the transparency of the SB at the
source/drain interface with Wentzel-Kramers-Brillouin (WKB) approximation. Finally, verification of the model was performed against Monte
Carlo simulations and also proved it suitable for circuit simulations.
In addition, the heat trap effect was employed for an efficient localized heating of carbon nanotube arrays using light. This research led
to the generation of electron emission through the thermionic mechanism. However, this process was found to use an excessive amount
of optical power that was available from sources such as handheld lasers. Thus, additional research including thermionic and thermoelectric
conversion for solar-energy harvesting and simple electron beam systems need to be conducted for potential applications [29].
4. Device simulation and characterization
Numerous simulators are available for simulating the CNTFETs and
analyzing the characteristics while SPICE platform is chosen to be the
best choice. The Stanford University CNFET Model is the mostly used
SPICE-compatible compact model. It uses single-walled CNTs as channels. Recently, a VS-CNFET model was developed that was found to be
suitable for studying the characteristics of the ultra-scaled CNFETs. This
model can be instantiated directly in SPICE netlists to explore the impacts of CNFETs on the circuit performance. [34]
3.1.6. NEGF-based
NEGF stands for Non-Equilibrium Green's Function. It is used for
calculating the charge and current densities in biased semiconductors
or conductors. SoheliFarhana et al. [30] have illustrated the NEGFbased transport phenomena of the CNTFETs. For this purpose, the chiral
vector of the CNT was chosen to be (25, 0) with 14 nm of channel
length and 1.95 nm of diameter mounted on the FET. It emphasizes on
the need to include the quantum tunneling around CNTs. By using
NEGF accurate modeling of the quantum simulations are performed.
The total charge in the calculation meant both the electron and hole
concentrations. The model achieved a drain current of 69 µA until the
drain voltage reached 0.2 V. Also, the transconductance was found to be
1.8 mS at both the Vgs and Vds being 0.4 V.
4.1. Current-voltage transfer characteristics
The CV- Characteristics is defined as the relationship between the
current flowing through the CNTFET and the applied voltage.The device behavior in a circuit is modeled mathematically by using these
findings.
4.1.1. Effect of gate – oxide thickness
Nirjhor Tahmidur Rouf et al. [35] have considered a (13,0) nonballistic zig-zag CNT with a diameter of 1.0184 nm for studying the
Current-Voltage Characteristics of the CNTFET. A 3D-view of the effect
of the change in gate oxide thickness on the CV-Characteristics was
presented and demonstrated that the drain current decreases as the gate
oxide thickness increases. The study further shows that the change rate
decreases as the gate becomes thicker. It was inferred that as the gate
oxide thickness increases, the rate of decline of drain current starts to
stabilize.
This study was used to investigate the CV relationship due to the
variation of gate oxide thickness considering both the non-ballistic as
well as the ballistic effects. When non-ballistic effects were considered,
the deduction was that the output current grew smaller as the gate
became thicker. When ballistic effects were considered, the output also
declined with the increase of gate oxide thickness. Finally, from these
studies, it can be concluded that the reduction in gate oxide thickness
would increase the on-state current which in turn will improve the
performance of the transistor.
3.2. Charge model
The charge model considers the capacitance between different elements of the transistor as the components of the model. It also takes
into account the parasitic capacitances modeled as constant capacitors.
VisheshDokania et al. [31] have accurately modeled the CNTFET with
parasitic capacitances and Density of States. Potential and carrier
densities were obtained by solving the Poisson-Schrodinger equations.
Analytical expressions for the CNTFET density of states and the drain
current were derived. The model was a SPICE-compatible model.
The algorithm steps of the proposed model were:
1. Firstly, Effective gate capacitance (Cg) was calculated.
2. Bias-induced mobile charge (ΔN) was calculated.
3. Self-consistent potential (USCF) was calculated by adding the
Laplace potential (UL) and potential due to mobile charge (Up).
4. ηF1 and ηF2 were calculated for the calculated USCF.
5. ID was computed for ηF1 and ηF2.
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Table 1
List of drain currents.
S.no
Model
Equation of drain current
1
Ballistic Model [19]
ID =
2
4
5
∫0∞ [
Quasi-Ballistic Model [21]
I=
3
2qKB T
h
Non-Ballistic Model [23]
4q
K T
h B
ID =
Tunneling Model [25]
4qkB T
h
I=
4q
h
I=
4ekB T
h
I=
4e
h
1 + exp(
ln [
1 + exp(
NEGF-based Model [28]
7
Charge Model [30]
8
FEM Model [31]
1
y + Δf 2
+
]
KB T
Ψs − Eg / 2q
1 + exp[
∫ exp(
4 2m* Eg3/2
3qℏξ
KB T
] dy
]
)
KB T / q
]
Ψs − Eg / 2q − Vds
)
KB T / q
× ∑m ⎧Thigh ln ⎡1 + exp
⎨
⎣
⎩
Thermionic Model [26]
6
1
y + Δf 1
1 + exp[
(
q (ψcc − VDS − Δ) − Em (0)
kB T
) ⎤⎦ ⎫⎬⎭
)[fs (E ) − fD (E )] dE
eff
I1(2) =
+∞
∑p = 1
eVs + ΦSB S − sbbd [p]
⎡
⎤
) ⎥
⎢ ln(1 + exp
kB T
⎢
⎥
eff
⎢
eVD + ΦSB D − sbbd [p] ⎥
)⎥
⎢− ln(1 + exp
k
T
B
⎣
⎦
∫ T (E )[fs (E ) − fD (E )] dE
Nc
q
2
2kT
f (ηF1(2) )
πm* 1/2
–
chirality. This shows smaller the chirality or diameter; lesser is the
energy dissipated from the CNTFETs.
4.1.2. Effect of dielectric constant
Nirjhor Tahmidur Rouf et al. [36] postulated the effect of Dielectric
Constant on the current-voltage characteristics of CNTFET. The performance of the CNTFET was evaluated considering distinct dielectric
materials such as Silicon Dioxide, Aluminum Oxide, Hafnium Silicate,
Hafnium Oxide, Zirconium Oxide, and Lanthanum Oxide. Through
these experiments, it was observed that the increase in the dielectric
value of the gate materials would not inevitably improve the performance. The positive effect of gate dielectric reduced with the value
going higher and the comparison between the ballistic and non-ballistic
conduction of the CNTFET was also presented. From this study it can be
concluded that the value of dielectric constant of the gate material
greatly improved the output current of the CNTFET in the non-ballistic
regime.
In a recent study, it was noticed that HSPICE is used for the simulation of the proposed CNTFET. In addition, the parameters involving
digital and analog variables such as current ratio, subthreshold swing
(SS), transconductance, and intrinsic gain were studied. Besides, in this
study, it was observed that the proposed CNTFET outperforms the existing conventional CNTFETs in terms of current ratio, transconductance, and intrinsic gain. Moreover, the limitations observed in this
study could be overcome by utilizing alternative materials and technologies [37].
4.3. On and off current ratio characteristics
Another significant parameter of the CNTFET is the ON/OFF current
ratio. It is defined as the ratio of the currents in the ON- and OFF- state.
It is desirable to maximize the ON-state current and minimize the OFFstate current. Safayat-Al-Imam at al. [39] has investigated the temperature effect on the ION/IOFF current ratio with different oxide
thickness and higher k values and revealed that the current ratio decreases with the increase of the oxide thickness. The investigation
showed that by increasing the temperature above 500 K, the current
ratio diminished linearly for all range of k values. As a result, for high k
values the current ratio decreased with an increase in temperature. This
was due to the thermionic emission leakage on the top of the potential
barrier which resulted in high leakage current.
4.4. PDP analysis
Power Delay Product is the measure of the average energy consumed/dissipated per switching operation. It is also an important figure
of merit for determining the quality of the CNTFET.
Recently, CNFET-based TCAM cell was designed, and the influence
of this proposed model based on performance parameters such as delay,
PDP, and SNM was studied. From this study it was observed that a
significant improvement in PDP was noted during the write operation
by 38% and 98% was observed during search operation suggesting an
improved performance. Habib Muhammad Nazir Ahmad et al. [40]
performed an experimental investigation of the figure of merit PDP
(Power Delay Product) by using GDI CNTFET based Full-adder. These
were compared with 12-CNTFET Full-adder and proved the superior
performance of GDI CNTFET.
Some benefits of CNTFETs are summarized as follows:
4.2. Voltage transfer characteristics
The voltage Transfer Characteristics is referred to as the response of
the CNTFET circuit concerning the specified input voltages. This could
be used as a figure of merit for determining the static behavior of any
circuit. Sonal Shreya and Rajeevan Chandel [38] presented an article
with Voltage Transfer Characteristics for different chirality values of
CNTFET inverter.
The following notations were extracted:
1. CNTFETs have been found to have steeper VTC curve with decreasing diameter.
2. Both SWCNTs and MWCNTs have demonstrated the same VTC for a
given chirality.
3. It has been shown that the power consumption reduced with the
reduction in chirality while the delay increased.
4. Besides, the drain current was found to be reduced with the reduction in chirality which in turn reduced the speed.
5. Finally, PDP (Power-Delay-Product) decreases with reduced
1. The PDP remained almost constant throughout different temperatures indicating high stability at high temperatures.
2. CNTFET based circuits were observed to demonstrate its tolerance
towards the PVT (Process, Voltage, and Temperature) variations
significantly better than CMOS circuits.
Finally, this study suggests a method for increasing the number of
CNTs per device to enhance the speed of the circuit.
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developing any electronic digital system. Rajendra Prasad Somineni
et al. [45] enhanced the performance of the traditional full-adder circuit by incorporating the CNTFET with stacked single transistor leakage
feedback technique. The stacking was applied for the p-type transistor
with chirality which is responsible for retaining of the data during the
standby mode. It is observed that the design reduced 65.83% of the
leakage power with 0.9 V supply.
Two interesting behaviours of the CNTFETs are (1) CNTFETs can act
as both metal and a semiconductor depending on the chirality. (2)
CNTFETs can be realized with different threshold voltages by changing
the diameter. B. Srinivasu et al. [46] have made use of these advantages
to carry out the experiments. Here, CNTFET- based ternary multiplexer
and a multi-trit multiplier was proposed. The operating voltage used for
this study was 0.9 V and the channel length was 32 nm. It is observed
that the ternary multiplexer needed only 15 CNTFETs and a single-trit
multiplier needed 26 CNTFETs. Thereby the design needed 67% less
number of CNTFETs when compared to other recent designs. Therefore,
this study claimed that the developed configuration revealed an excellent performance with respect to power, delay as well as noise
margin. José G. Delgado-Frias et al. [47] have reported a study of
power reduction of an 8-T SRAM cell. The two techniques such as gated
power supply technique and word-line boosting technique were successfully applied. These techniques have enhanced the performance and
yield of 8-T SRAM cells. The concluding remarks are summarized as
follows: (1) The best Energy Delay Product was obtained at
Vdd = 0.5 v. (2) The gated power supply technique eliminated all the
write failures at Vdd of 0.5 v. (3) The boosting technique remarkably
reduced the read as well as write delays. (4) The gated power supply
method also decreased the leakage power by 6.8× at Vdd = 0.5 v.
4.5. Frequency analysis
The frequency response of the CNTFET circuit is used to determine
the process involved in the output gain and the phase changes at a
particular frequency or over a range of frequencies. SoheliFarhana et al.
[41] developed a SPICE model of CNTFET. This model focused on the
determination of the high-frequency performance of the devices such as
cut-off frequency. The parameters selected to simulate the small-signal
model of CNTFET were Vth = 0.2 v, Cgs = 14 aF and gm = 1.8 mA/V.
This led them to achieve a frequency of 6.7 THz. The experimental result shows the cut-off frequency ranged from 1 Hz to 100 THz. Finally,
this model was compared with the existing model, and it was proved
that the model outperformed.
4.6. Radiation effect analysis
Exposure of the CNTFET to the ionizing radiation will cause serious
damage or malfunctioning of the device. Besides, circuits operating in
the space and near the nuclear reactors were prone to this type of damage. Therefore, it is necessary to develop radiation-resistant circuits.
An interesting report on Radiation Effects in CNTFETs was proposed by
Cory D. Cress et al. [42]. Also, it was observed that cumulative radiation exposure causes two effects. These were recognized as ionizing
energy absorption (TID-Total Ionizing Dose) and Crystalline damage
(DDD-Displacement Damage Dose). These two effects eventually lead to
changes in the overall device behavior. For analyzing these effects, an
SWCNT-TFT (Single-Walled Carbon Nanotube Thin Film Field Effect
Transistor) on SiO2-Si substrates from 98% pure semiconducting
SWCNTs was fabricated. After fabricating the device, it was irradiated
with 2000 krad (Si) at a dose rate of 0.240 krad (Si). Irradiating the
device was done in two environments, one in vacuum and another in
the air. During this experiment, it was found that the device characteristics remained unchanged for 10 min in the static vacuum. When
irradiated under vacuum, a gradual shift of the transfer characteristics
to the negative gate bias was observed in the device characteristics with
incremental TID. Later, additional dosage was given to the device in the
air and the response. Finally, the comparisons between the threshold
voltage VT and mobility with TID exposure in the vacuum and air were
presented.
5.2. HealthCare
Today, VLSI is widely implemented in many of the Biomedical applications to improve healthcare diagnosis, monitoring and cure.
Therefore, present-day applications such as Pacemaker, Hearing aids
etc. need to be power efficient as it will be a life risky process. B.N.
Shobha et al. [48] have developed an ultrasensitive and selective biological sensor for PSA (Prostate Specific Antigen) detection. For this
purpose, a CNTFET inverter with improved characteristics was designed. Also the signal conditioning unit was realized using CNTFET.
The output signal of the developed biosensor could detect PSA concentration in the range from 5 to 5000 pg/mL. RostyslavSklyar [49]
reviewed on the CNTFET based Nanowired Induction Two-way Transducers. He has focused on the application of CNTFETs for the design of
the superconducting transducers. He has suggested the following recommendations. (1) The serial connection of the external PCs allowed
them to gain integrated, accurate sensing signal. (2) The proposed BioNano-sensors were passive and did not affect the functions of the organs.
In recent years, the development of carbon nanomaterials has led to
a widespread interest in using carbon nanotubes (CNTs) and graphene
in development of novel biosensors. This study suggests employing of
CNTs and graphene as their properties would make the sensors more
reliable, accurate, and fast. Besides, different strategies could be applied
based on the types of target molecular to design sensor device
[50]. AbhishekPuri et al. [51] have presented a low power CNTFET
based two-stage Operational Amplifier for Biomedical A/D converters. A Sample and Hold circuit using CNTFET based Op-Amp was
implemented. The input frequency 40 kHz was sampled at 400 kHz.
Finally, a comparative analysis of the traditional MOSFET based OpAmp and the proposed circuit were performed and concluded that the
power consumption was improved up to 80%.
5. Applications of CNTFETs
CNTFETs can be used as a promising candidate in a wide range of
applications in almost all the fields where MOSFETs are currently being
used and further considered as a replacement for silicon transistors.
CNTFETs were found to have efficient electrical properties, such as
quasi-ballistic carrier mobility in the diffusive regime. Presently,
CNTFET devices were found to exhibit characteristics similar to Sibased MOSFETs [43]. Furthermore, Carbon nanotubes (CNTs) are currently considered as promising building blocks of a future nanoelectronics technology. A summary of possible applications in the key areas
is presented below.
5.1. Logic and storage devices
The digital logic circuits play a significant role in the semiconductor
device production. The memory products represent the next major role.
The main parameters that are to be considered while designing these
circuits are high speed, less area, low power consumption and lower
cost. SoheliFarhana et al. [44] have elucidated the High-Frequency
CNTFET based different logic gates such as inverter, NOR gate and
NAND gate in the work. 500 mV was observed to be the Q point voltage
concerning the output voltage. Here high-frequency response was obtained and also by analyzing the voltage transfer characteristics it was
concluded that CNTFETs are the apt candidates that can be employed to
design the logic gates, which are the fundamental components in
5.3. RF applications
Radio Frequency Technology is described as the base for the
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deficiencies of these components. CNTFET and graphene FET (GFET) is
employed for the development of these biosensors that can be integrated on-chip, and have longevity, high sensitivity and also speed
detection [59].
Wireless Communication Sector, which is growing rapidly. This technology depends on the system that is constructed with FETs. The requirements for such systems are in terms of power consumption, cost,
frequency band and size of the unit. A. Taghavi et al. [52] have successfully designed a CNTFET amplifier that could be used as an active
element for RF circuits which was implemented on the FR-4 substrate
with Surface Mount Device (SMD) components. A common-source stage
with negative feedback was incorporated with the amplifier. By using
these configurations, the amplifier could operate at 538 MHz of frequency with 5.6 dB of gain and an excellent matching of −21 dB.
5.5. Electrical applications
CNTFETs possess superior electrical properties such as higher carrier velocity and mobility that can be explored for several electrical
applications. The other demands of electrical instruments are high gain,
better precision with no error and less noise. Wang Qian et al. [60] have
presented an explicit-pulse Generator using CNTFET. The output was
controlled by using delayed clock signal. Also, for reducing the power
consumption, pseudo PMOS was discarded. For the simulation purpose,
the parameters chosen were a supply voltage of 0.9 v and clock frequency of 125 MHz. The chirality vector chosen was (19,0). Comparative analysis showed that the design saved 83.21% of power consumption when compared to the existing design along with higher
speed and short pulse delay.
Jean- Marie Retrouvey et al. [61] have extensively studied the
Optically Gated Carbon Nanotube Field Effect Transistor (OG-CNTFET).
A neural crossbar using Verilog A compact model was designed. Here
the Delta Rule was integrated for the purpose of weight calculations and
learning incoming data. Electrical pulses were used by them for programming the neural network. Finally,OG-CNTFET demonstrated better
efficiency in learning linearly separable Boolean Functions.
VinithZachariaJoshy et al. [62] have performed the experimental
investigation on a 5–2 compressor and a 5–3 compressor with FullAdder cell as the basic building block. The parameters like chiral vector,
diameter of the tube, channel length, oxide thickness and dielectric
constant were taken as (17, 0), 1.33 nm, 10 nm, 2 nm and 15 respectively. The circuit was operated at 0.9 v. The findings were that (1) The
CNTFET model based Full-Adder consumed 88.85% less power than the
MOSFET model. (2) The 5–3 compressors were 43.8% more efficient
than the MOSFET model.
Presently, the increase in the use of mobile electronic devices and
media processors have led to the need for developing CNTFET circuits
design with low power consumption. Besides, the use of CMOS technology was found to have limitations such as short channel effect, high
leakage power, degraded gate control, parametric variations, and
higher power density [63]. Also, the development of a higher power
density increases the chip temperature and leads to performance degradation. Thus, it is necessary to utilize the inherent properties of the
carbon nanotube field effect transistor (CNTFET) in these applications.
5.4. Bio-sensing
Electronic detection of biomolecules plays a vital role in
Biotechnology, Clinical Diagnosis and Pharmacy. Sensitiveness, costeffectiveness and disposable properties are demanded from the
Biosensors. Raquel A. Villamizar et al. [53] have accomplished a very
interesting work on the rapid detection of Aspergillus flavours in rice
using CNTFETs. The CNTFET that was protected with 1.5% Tween and
2% gelatine was exposed to 103-fold diluted rice samples with high
concentration 100 ng/mL. The CNTFETs were immersed for 30 min at
37 oC and were thoroughly rinsed and dried with nitrogen. Then when
it was viewed using a microscope the presence of the molds was confirmed. Finally, CNTFET was able to detect the mycotoxigenic molds at
low concentrations in a short time.
Mohammad Abdul Barik et al. [54] have fabricated a compact ntype CNTFET for acetylcholine detection by integrating chitosan/nickel
oxide as sensing membrane. The device was inserted in a glass pot
containing 20 mL Phosphate Buffer Saline (PBS) of 50 mM with pH as 7.
A constant voltage of 0.6 v was applied to the reference electrode and
the gate terminal. The drain currents against each acetylcholine concentration were monitored by a digital multimeter. The Limit of Detection was calculated and found to be 0.37 µM.Here CNTFET improved
sensitivity of 1.25 V/decade. Jung-Tang Huang et al. [55] have studied
the performance of CNTFET as Biosensor in detecting Influenza or
H1N1 virus in the droplet. The sample with H1N1 virus model to be
detected is diluted with PBS solution. The vds and vgs were supplied
with 2 v respectively. The key point used in distinguishing the difference of H1N1 concentration is by utilizing the current variation and
slope.
Habib Muhammad Nazir Ahmad et al. [56] have conducted an experimental analysis of a CNTFET based Potentiostat and have implemented it by using fully differential architecture. Furthermore, this
study was able to suppress all of the common mode interference. The
proposed Potentiostat demonstrated PVT variation tolerance remarkably better than MOSFET. The simulation analysis has shown 40%
improvement in performance regarding power, speed and stability.
Jeseung Oh et al. [57] have developed a CNTFET based biosensor for
amyloid-beta detection in human serum and also developed a CNT filmbased biosensor with a MESFET (Metal Semiconductor Field Effect
Transistor) which exhibited higher sensitivity than CNTFET based
biosensor. Using the CNT-MESFET biosensor, amyloid-β (Aβ) was detected in human serum for the early diagnosis of Alzheimer's disease.
This could measure human serum Aβ at the level of 1 pg/mL.
Kagan Kerman et al. [58] have reported the development of a Nano
sensor array based on CNTFETs for DNA hybridization detection. When
the DNA samples were introduced via a PDMS-based microflow chip,
there was a conductance change observed. The results indicated a Limit
of Detection of 6.8 FM WT DNA. Based on the above process, it was
concluded that CNTFET-based biochip was a promising candidate for
nucleic-acid based diagnostics. Moreover, acetylcholine behaves as a
carrier and is found to be significant for neurotransmission and decrease in these component leads to numerous nervous disorders such as
Alzheimer's disease, Huntington disease, Parkinson's disease, and multiple sclerosis. Therefore, development of a low-cost, integrated, disposable, and reliable biosensors is required for early detection of
5.6. Communication engineering
CNTFETs exhibit a linear relationship between the drain current and
the input voltage. This linearity property can be explored in the Mobile
Communication Systems that incorporate complex modulation
schemes. The other demands from the communication industry are high
data rate, high pulse amplitude and low power loss. FahimRahman
et al. [64] have evaluated the performance of a 10 GHz 32 nm-CNTFET
based Ultra-Wideband transmitter for wireless communication. The
clock was generated from a voltage-controlled oscillator, and the pulsegenerator was an edge-triggered circuit. The results reported by them
for optimal 10 GHz data rate with 650mv pulse amplitude was only
1.069 MW of power consumption and the output as −32.27 dB. It was
reported that the transmitter had operated satisfactorily up to 15 GHz.
The Table 2 presents the summary of all the applications of
CNTFETs presented in this review.
6. Challenges and scope for future studies
Extensive research works have been conducted based on the modeling and applications of the CNTFETs. Moreover, from the survey, it is
evident that CNTFET technology has a bright future in the area of
200
Soheli Farhana et al. [44]
Rajendra Prasad Somineni et al. [45]
José G. Delgado-Frias et al. [47]
Abhishek Puri et al. [51]
A. Taghavi et al. [52]
Wang Qian et al. [60]
B. Srinivasu et al. [46]
Mohammad Abdul Barik et al. [54]
Simulation
Simulation
Simulation and Implementation
Simulation
Simulation
Simulation and Implementation
VinithZachariaJoshy et al. [62]
FahimRahman et al. [64]
Simulation
Simulation
Numerical and Simulation
Simulation
RostyslavSklyar [49]
Theoretical (Review)
Habib Muhammad Nazir Ahmad et al. [56]
B.N. Shobha et al. [48]
Jung-Tang Huang et al. [55]
Simulation and Implementation
Simulation
Simulation
Jean - Marie Retrouvey et al. [61]
Raquel A. Villamizar et al. [53]
Simulation
Simulation and Implementation
Jeseung Oh et al. [57]
Kagan Kerman et al. [58]
Fabrication and Implementation
Fabrication and Implementation
Reference
Method
Table 2
Summary of applications.
201
2016
2016
2015
2015
2015
2015
2015
2015
2014
2014
2013
2012
2013
2012
2011
2010
2011
2005
Year
Acetylcholine Detection
Ternary Multiplexer and Trit Multiplier
Low Power Operational Amplifier
RF Amplifier
Explicit-pulseGenerator
SRAM Cell
HF Logic Gates
Low-Leakage Full Adders
Amy-Loid Beta Detection in Human
Serum
Potentiostat
Prostate Cancer Detection
Compressor
IR-Ultra Wideband Transmitter
Two-Way Transducers
H1N1 Virus Detection
Neural Crossbar
AspergillusFlavus Detection in Rice
Detection of DNA Hybridization
Application
The CNTFET based circuits possess high immunity to Process, Voltage and Temperature (PVT) variations.
The current handling capability of CNTFET has been demonstrated and found advantageous to be used in
low power devices and portable applications.
The CNTFETs have the potential to operate in the higher GHz range.
The CNTFETs when implemented by the stacked single transistor leakage feedback technique reduced more
leakage power.
The CNTFET based SRAM cell consumed very less power when gated power supply and word-line boosting
techniques were applied.
The Op-Amps when designed using CNTFETs have better performance and consume low power.
The CNTFETs provide competitive performance when employed in active RF circuits.
The CNTFETs have lower latency and when pulse generators are designed by using CNTFETs they consume
very less power.
The CNTFET based circuits when implemented using multi ternary configuration will require only a small
number of CNTFETs.
The CNTFET based biosensors could be easily fabricated and also required only a less instrumentation.
CNTFET based bio-chips could be exploited in developing portable devices that are integrated and highly
throughput producing.
The OG-CNTFET based circuits possess higher learning efficiency when implemented in Neural Networks.
The CNTFET's antibodies recognition ability and also the transduction capability reduce the need for
additional reagent for labelling process and thereby the cost is reduced.
The CNTFET when used as a biosensor has the capability of sensing even dried specimens easily and
accurately.
The CNTFETs can be used in transducers that can be transduced into density of chemical and biomolecules
and electric voltage.
CNTFET based circuits showed a significant decrease in delay showing better performance.
The CNTFET based RF transmitter provides the advantages of very low dynamic power consumption and also
negligible static current.
The CNT-MESFET based biosensors had exhibited a higher level of sensitivity.
Results and remarks
P. Prakash et al.
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Renewable and Sustainable Energy Reviews 89 (2018) 194–203
P. Prakash et al.
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1. New materials for synthesis and integration of CNTFETs ought to be
found out.
2. The scalability of CNTFETs should be investigated in detail
3. The problems related to the positioning of tubes during the fabrication process need to be resolved.
4. In the modeling of CNTFETs, a consistent model suitable for both
analog and digital applications with the capability of manufacturing
in a large-scale must be developed.
5. The basic research indicates that the existing CAD tools are appropriate for simulating the CNTFET devices while few additions and
changes are required.
6. Fault-tolerance of the CNTFET circuits needs to be explored.
Besides, very few research works is conducted in the architectural
level design of the CNTFET circuits.
7. Novel design methodologies are required to optimize the speed,
power consumption, delay, and the area of the CNTFET circuits.
From an extensive research review, it is found that the physical and
chemical properties of CNTFETs are often used in immune sensing
applications due to the high surface-to-volume ratio, high electrical
conductivity, and rapid electrode kinetics abilities [65].Also, the
property of massive loading capacity in CNTFETs facilitates the conjugation of biomolecules and incorporation of nanoparticles that improve the sensitivity and amplification of the electrical or optical signals [66]. The electron transfer was mediated by the high conductivity
of CNTFETs that further enhances the measured current. Furthermore,
the enhancement in the solubility and biocompatibility is performed by
the chemical functionalization of CNTs [67].Thus, this review paper
focuses on the research areas that are available for further research on
the CNTFETs. Hence, supplementary research is required to make utilize CNTFETs efficiently and effectively for various real-time applications.
7. Conclusion
The technological advancements have led to numerous scientific
research with vast possibility, and from these papers, it can be found
that CNTFETs could be a better alternative compared to the conventional CMOS with regards to its high performance and smaller dimensions. However, several factors have been listed in the literature which
affects the characteristics of CNTFETs such as reliability and greater
manufacturing cost. Also, the properties such as excellent carrier mobility, high dielectric property, ballistic conduction, channel length,
transconductance, heat dissipation and threshold voltage play a vital
role.
It is also evident that the power dissipation in CNTFETs is remarkably less when compared to the conventional CMOS. Both numerical and experimental studies prove the above fact and thereby
CNTFET is identified as novel FET to reduce the power consumption.
Furthermore, modeling the CNTFETs with optimal parameters have
been succeeded by researchers for yielding better results.
Despite much recent advancement, exploration of effects such as
self-heating, hysteresis, low-cost and mass fabrication, high-density
integration problems and the development of a unique model with
small-signal behavior is still unsolved. Therefore, it is essential to
conduct huge theoretical and experimental studies to explore the feasibilities of CNTFETs for different applications and a benchmark standard is required for these devices.
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