module ALU (
input [15:0]
input [15:0]
input [2:0]
output [15:0]
ALU_OUT,
output
);
/********************************
Write your own code here.
*********************************/
reg
CarryOut;
reg [15:0]
reg [15:0]
assign Cout
CarryOut;
assign ALU_OUT
Output;
B;
always @* begin
// Add
if (SEL == 3'b000) begin
temp
Output
temp[15:0];
+ 1);
temp;
// Both numbers are negative
if((A[15] == 1) && (B[15] == 1) && (temp[15] == 0)) begin
CarryOut
end
// Both numbers are positive
else if((A[15] == 0) && (B[15] == 0) && (temp[15] == 1)) begin
CarryOut
end
else begin
CarryOut
end
end
// Sub
else if (SEL == 3'b001) begin
temp
Output
// Both numbers are negative
if ((A[15] == 1) && (temp[15] == 1) && (Output[15] == 0))begin
A,
B,
SEL,
Cout
Output;
temp;
=
=
=A+
=
= 1'b1;
= 1'b1;
= 1'b0;
= (~B
=A+
CarryOut
end
// Both numbers are positive
else if ((A[15] == 0) && (temp[15] == 0) && (Output[15] == 1)) begin
CarryOut
end
else begin
CarryOut
end
~(A&B);
~(A|B);
A>>1;
end
= 1'b1;
= 1'b1;
= 1'b0;
end
// Nand
else if (SEL == 3'b010) begin
Output
=
end
// Nor
else if (SEL == 3'b011) begin
Output
=
end
// Not
else if (SEL == 3'b100) begin
Output
end
// Shift
else if (SEL == 3'b101) begin
Output
end
endmodule
= ~A;
=