250
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 5, NO. 3, SEPTEMBER 1997
S. 250 - 257
Fully Coupled Dynamic Electro-Thermal Simulation
Georg Digele, Steffi Lindenkreuz, and Erich Kasper
Abstruct- Fully coupled dynamic electro-thermal simulation
on chip and circuit level is presented. Temperature dependent
thermal conductivity of silicon is taken into account, thus solving
the nonlinear heat diffusion equation. The numerical solution is
carried out by using the industry-standard simulator SABER,
therefore for electro-thermmal simulations we are able to use the
common electrical compact models by adding a heatsource and
thermal pins to them. The application of this technique and need
for electro-thermmalsimulation is illustrated with the simulation
of a current control circuit built into a multiwatt package.
I. INTRODUCTION
B
Y the ever-increasing integration density on chip level,
there is need to consider and take into account selfheating of power generating elements as well as lateral heat
propagation on chip level resulting in thermal coupling and
thereby electro-thermal interaction between components. Selfheating affects device behavior, crucial for SOI-technologies
[l] as well as for power devices in bulk technologies [2].
Especially in power electronic mixed devices where power
components like VDMOS transistors are integrated besides
analog control circuitry, there is need to know the isolines
of temperature at a critical timestep during the simulation or
under steady state condition. This critical timestep could be the
moment when transient pulses reach their maximum or power
shut off circuits begin to work or simply the steady state.
The thermal isolines are necessary for the layout engineer
to place symmetrical components like current mirrors onto
an isoline in order to make them work under the same
thermal influence. Thermal isolines are also needed to reach
an optimum placement of heat sources.
Electro-thermmal interaction between components has to be
considered because it can affect the performance, even the
functionality of the whole integrated circuit. Important for circuit design engineers is the absolute temperature of the single
component, but essentially the temperature gradient existing
between symmetrical components to be able to decide whether
the specification is fulfilled concerning lateral heat expansion,
that means thermal interaction between components.
The common way in circuit simulation up to date is to
introduce either a globally constant temperature or locally constant temperature as parameter into the circuit simulator. The
Manuscript received May 15, 1997. This paper was presented at the 2nd
THERMINIC Workshop, Budapest, Hungary, Sept. 25-27, 1996, pp. 73-77.
G. Digele is with the Robert Bosch GmbH, KXDIC, Reutlingen D-72703
Germany. He is also with the Institute for Semiconductor Engineering,
University of Stuttgart, Stuttgart D-70174 Germany.
S. Lindenkreuz is with the Robert Bosch GmbH, KXDIC, Reutlingen D72703 Germany.
E. Kasper is with the Institute for Semiconductor Engineering, University
of Stuttgart, Stuttgart D-70174 Germany.
Publisher Item Identifier S 1063-8210(97)06354-3.
globally constant temperature could be either the “worst case
ambient temperature” or the maximum “junction temperature”
which can be determined by the use of “Rth-tables” delivered
by packaging companies [3]. Locally constant temperatures
can be obtained by thermal simulation of major heat sources on
chip level, then to introduce the temperatures at the location of
temperature dependent elements as parameters into the circuit
simulator. Here, for the thermal simulations ANSYS as an
FEM-simulator plays an important role.
Last, but not least, it is important for the packaging engineer
to know the maximum temperature (hot spot) in order to
choose a suitable package as an optimum between sufficient
heat conduction and an acceptable price.
11. PREVIOUSWORK
Right now for thermal and electro-thermal modeling there
are several approaches to consider. All of the approaches have
in common that they solve the thermal diffusion equation,
either in a coupled or a relaxation way. We want to start with
the analytical solutions of the thermal diffusion equation.
One of these is the method of images [4] which uses a
“green function” which is the temperature distribution resulting from a point heat source. Then the principle of superposition is applied to adjust the correct boundary conditions [5],
[6]. However, most of the analytical solutions are based on
Fourier expansions of rectangular chip, solder/adhesive and
leadframe materials [71-[ 101. Transient behavior is modeled
by the use of Laplace transforms [5] or numerical approaches
[ I l l , [12]. Besides the fact that these Fourier solutions are
limited by the number of layers, all analytical solutions are
forced to assume a constant heat conductivity, that means they
solve the linear transient heat flow equation V72T(z,y,z,t)
-
( l / D ) ( a T / d t )with D = X/c, being the diffusion constant,
X the “constant” thermal conductivity and c, the product
of heat capacity c and density p. However, Selberherr [13]
described an exponential behavior for the thermal conductivity
X = 1.5486(W/K~m)(T/300K)-~/~.
Supposing a rise of
temperature of 100 K the error of solutions of the linear heat
diffusion equation is in the order of 32%.
A promising way out of the restriction to the linear differential equation seems to be the application of the Kirchhofftransformation to transform the nonlinear behavior into a
linear one by the use of an “apparent temperature” [14].
Unfortunately the Kirchhoff-transformation is useless for multilayer structures due to problems concerning the continuity of
temperature at adjacent boundaries.
Concerning electro-thermal simulation there are two different methods to itemize. The first one is the “relaxation
method” which stands for two separate simulations, an elec-
1063-X210/97$10.00 0 1997 IEEE
25 1
DIGELE et al.: FULLY COUPLED DYNAMIC ELECTRO-THERMAL SIMULATION
temperaturedependent
trical and a thermal one [15]. The thermal simulation can
elements
be either one of the analytical solutions mentioned above
or a numerical discretization algorithm [16]. Starting with
the electrical simulation the power dissipation is calculated
and forwarded into a thermal simulator which calculates the
heat source
temperature distribution at the respective timestep and give
back the temperature to the electrical simulator a.s.0. This
silicon die
as 3D discretized
procedure is repeated iteratively until thermal and electrical
differentialequations
convergence is reached. However, strongly coupled thermal
problems may cause a lot of iterations, even ending with
adhesive layer
divergence. Furthermore, most relaxation approaches deal only
with electrical or thermal derivatives concerning the Jacobian.
Thermal equations derived with respect to electrical variables
and vice versa are not realized by this approach.
The second numerical approach is a direct- or fully coupled
solution. Here only one matrice exists, containing electrical and thermal components, handling electrical states and
signals simultaneous with thermal ones. Concerning selfheating of components there are a lot of papers dealing with
electro-thermal models by introducing thermal RC-networks
to calculate the temperature at every timestep for one single Fig. 1. Electro-thermal model: chip and adhesive mounted on an ideal
component [17]-[19]. In [20], [21] self-heating under the heatsink as approximation of a power package with small thermal resistance.
influence of packaging is accounted for by discretizing the
silicon chip in one dimension, while taking the temperature behavioral model into the circuit simulator SABER [28] thus
taking care of the nonconstant heat conductivity of silicon
dependence of the thermal conductivity into account.
For lateral thermal interaction, an FDM-method (finite dif- (Fig. 1).
To derive the discretization algorithm and to estimate the
ference method) was used to model chip and header by a netlist
consisting of thermal capacitances and resistances [22], [23]. truncation error we demonstrate one-dimensional (1-D) heat
These resistances were constant, and thus only the linear heat conduction and assume three nodes T,-1,T, and T,+1 with
flow equation was modeled. SzCkely et al. [24] and Sabry distances between T,-1 and T, named h- and between T, and
et al. [25] model electro-thermmal interaction by the use of T,+l named h+. By calculating the temperature of T,+l by
automatically generated thermal lumped element networks. developing 7'(z) into a Taylor series around the center of h+,
we obtain
While these approaches are computationally very efficient they defined here as x = i
are forced to assume a constant thermal conductivity.
Ti+l = Ti+(l/Z)+ - Right now there is no satisfying solution for electro-thermal
2 ax i + ( 1 / 2 )
simulation on chip (isolines of temperature necessary for
layout) and circuit level (electro-thermal interaction concerning circuit design) which is able to cope with the nonlinear
heatflow equation. The industrial requirements of such a
simulator are the following.
It should be specifically oriented to IC-problems, i.e.,
easy integration into the already existing designflow of
After calculation of Ti using the same Taylor series around
industry.
x
= i
f we obtain
The thermal model or netlist should be generated automatically with minimum inputs of the user, for example
only adhesive material information and geometries of the
die are required.
Ti+l - Ti
The temperature sensitivity of components must be modO(h$).
(3)
h+
eled accurately.
The same procedure used to calculate dT/dxli-(l/z) results
Isolines shall be created as guideline for the layout for an
in the 1-D Laplace-operator
optimum placement of components
Electro-thermal interaction is to be taken into account,
dT I
that means fully coupled transient as well as ac analysis.
$44
4
+
h+
+
+
111. METHOD
Our approach is to use FDM-methods [26], [27] to discretize
the chip in three dimensions and build these equations like a
2
IEEE TRANSACTIONS ON VERY L ARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 5 , NO. 3, SEPTEMBER 1997
252
2
1
1
(4)
+
for h = (h+ h-)/2. As a result, we obtain a truncation error
with linear relation to the mesh density. Same for the threedimensional (3-D) Laplace-operator. Supposing the thermal
conductivity to be constant, we can state the thermal heat flow
equation to be [291
p , is the density of dissipated power. For nonconstant thermal
conductivity and therefore the nonlinear heatdiffusion equation
we can use either the exponential model of Selberherr [13]
(Section 11) or a formula suggested by Glasbrenner and Slack
[301, [311
I
’(T)
=
a
+ bT + cT2
with a = 0.03 K cm/W, b = 1.56 lop3 cm/W, c = 1.65
lop6 c d ( W K) in silicon. The thermal heat flow equation in
1-D form, using the model of Selberherr, was given in [21]. In
three dimensions, simulating the thermal conductivity by either
the model of Glasbrenner and Slack or the one of Selberherr,
we can state the heat diffusion equation for a node inside the
silicon chip (not on a surface or interface) to be
gridding, for an example, refer to Fig. 9). By this way, the size
of the grid will be determined by the temperature gradient,
ideally the mesh density is proportional to the temperature
gradient. That means, besides the heat sources there will be a
fine grid, while area with little change in temperature will be
discretized with a coarse grid.
The adhesive layer is modeled by a thermal resistance layer
conducting the heat one-dimensionally from the silicon to
the heatsink. As the common thickness of adhesive layers
is in the order of 10 to 50pm, thermal capacitance of the
adhesive is negligiable compared to silicon thicknesses of
several hundred pm (typical values are 300 to 400pm) and
leadframe thicknesses up to the order of millimeters. The same
argument is valid for lateral heat transport in the adhesive
layer. For this reason, the adhesive is modeled by the use of
a thermal resistance layer standing for 1-D heat-flow through
the adhesive.
In automotive applications, where big power dissipating
components are integrated, there is need to use power packages
like PowerSO, Multiwatt or even TO packages to conduct
the generated heat efficiently to the heatsinks. The thermal
resisance of those power packages is in the order of some
WW, TO packages offer even resistances smaller than 1 K/W.
For this reason we model this kind of packages as if the silicon
die is connected via adhesive to an ideal heatsink (Fig. 1).
CONDITIONS
IV. BOUNDARY
Coming now to the boundary conditions, we assume all
outer surfaces to be adiabatic (VT = 0). Only power packages are considered where heat conduction is dominant, like
PowerS020, Multiwatt or TO families. Therefore we can
neglect the influence of convection and radiation. Nevertheless
we have implemented the mechanism of an :adiabatic heat
transfer coefficient” h at the outer surface of the silicon chip.
This is to model approximately convective losses of heat to
the environment.
w, is the convective heat flux to the ambient. By this way
we neglect the influence of heat conduction through the mold
compound. Knowing well that the convective heat transfer
depends on air velocity, mounted position of the IC or PCB
(vertically or horizontally) and system environment, we regard
h as parameter to fit the thermal resistance of a package to
(7) an application specific system environment. As we mentioned
already it is not intended to physically model adiabatic heat
The discretized thermal equations are built into the circuit transfer or radiation.
Heat sources (Neumann boundary condition) containing
simulator SABER as supplementary equations replacing the
already existing “electrical” Jacobian by an “electro-thermal” more than one node are realized by returning the average
Jacobian with electrical equations derived with respect to temperature of the involved nodes to the circuit simulator.
thermal variables and vice versa. As a matter of fact, SABER Concerning large area elements like the VDMOS-transistor
solves thermal differential equations and electrical equations there is an error rising from the reduction of threedimensional
geometries to only one single point of the component represimultaneously (“direct solution method”).
The discretization of the heat diffusion equation (7) is senting the thermal node of the circuit simulator’s compact
executed by involving a former thermal solution (adaptive model. This error can be overcome by partitioning large heat
DIGELE ef al.: FULLY COUPLED DYNAMIC ELECTRO-THERMAL SIMULATION
253
Chip-therm.sin
””’
_L
Adhesive
THGNL)
Fig. 2. Thermal model of six temperature dependent elements. Three of them generate power; conceming the other three, power dissipation can be neglected
compared to the elements on the left side. The electrical circuit is to be connected to the electrical pins of the respective element. Depending on which port
the electro-thermmal component is connected (“active” or “passive” contact), it acts either as heat generating element which needs imperatively one mesh
node at least, or as only temperature dependent element without forwarding generated power to the mesh.
generating elements and using an array of elements, connected
electrically in parallel, with one thermal node respectively.
Heat sinks (Diriclet boundary condition) furnish the sum of
the heatfluxes of the connected nodes.
As simulation speed depends heavily on the number of
nodes, we offer two kinds of thermal contacts to the user,
refer to Fig. 2. The first one is the general contact where heat
generating elements have to be connected. This contact, we
call it an active contact, contains imperatively one mesh point
at least, to put the power, dissipated by the connected element,
into the thermal model.
The average temperature of the involved nodes is calculated during the simulation and fed back as signal to the
element. However, for temperature dependent elements where
dissipated power can be neglected concerning heating of the
chip, this element can be connected to the second kind of
contact, we call it a passive contuct. The power dissipated
by the element is not forwarded to the thermal model. The
temperature of the contact nodes is a result of the dissipated
power of the power dissipating components connected to the
active contacts. It is calculated by linear interpolation of the
temperature of the eight surrounding mesh nodes. To be sure,
that the dissipated power of the connected elements does not
influence the adiabatic behavior of such a passive contact, the
contact is implemented as an ideal temperature source (analog
to the electrical voltage source), where heatflow depends
on either the calculated dissipated power of an electrical
component or the thermal resistance of the connected element.
Any way, heatflow to or from passive contacts is not taken
into account when calculating the temperature distribution of
the chip. By this way, for thermally passive elements only
one thermal equation is needed to be solved, this is the
-
Schematic
C
Electro-thermal
Layout
Thermal
A
Simulation
\
1
Isolines of temperature
Fig. 3. Design flow for an efficient fully coupled electro-thermal simulation.
interpolation equation. This results in a considerable reduction
of mesh density, and thus, a gain in simulation speed.
V. DESIGN-FLOW
In Fig. 3, we see the design flow which is needed for
an efficient fully coupled electro-thermal simulation. Starting
with the schematics, the circuit designer should simulate the
critical power dissipation of only the main heat sources. As an
alternative way, the critical power dissipation of these sources
can be estimated by rules of thumb. The information about
the type of the heatsource and the critical (mostly steady
state) power dissipation should be given to the layout in
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 5, NO. 3, SEPTEMBER 1997
254
os
W/L=k
D
4b
-
D
VDRAIN
PWL
A
4)
TO=O
vo=o
T1=1OMV1=10
T4
+
R=42M
Fig 4 Part of a final stage as an application example Current stabilizer VDMOS TE1 stands symbolically for parallel operation of VDMOS TEl to TE4
ISDC approximates the operation point of the current mrror translstors T2 and T3 Voo = 10 V
order to place these heatsources onto the chip to be able to
calculate heat propagation, depending on the position of the
heat generating elements.
Taking into account the placement of the heatsources on the
chip, a thermal model is automatically generated with pins to
heatsources and thermal ground. This thermal model contains
the discretized nonlinear heat flow differential equation and
the “adhesive” thermal resistance layer, boundary and contact
conditions. The thermal equations are built into the circuit
simulator SABER as supplementary equations, resulting in a
“general” Jacobian, containing electro-thermmal and thermoelectrical derivatives.
This is done by generating MAST-code [32], which is
read into SABER like some kind of “behavior model.” As a
matter of fact SABER solves thermal differential equations and
electrical equations simultaneously (“direct solution method”).
The results of this first simulation (self-heating of the heat
generating elements) are criterions for an eventual redesign.
At the same time the isolines of temperature or a contour
plot will be created as guideline for the layout engineer for
further placement of temperature dependent circuitry (for an
example, refer to Fig. 9).
The circuit designer continues the design, by bringing the
whole circuit or circuit blocks by a pure electrical simulation
into spec. Here only electrical simulation is used in order to
obtain high simulation speed. The layout is designed by using
the “temperature layer” for placing “symmetrical components”
onto the isolines of temperature. The thermal netlist is generated, followed by the new generation of a thermal model,
having as many pins as heatsources plus components which
should be electro-thermally simulated (Fig. 2).
This thermal model will be coupled with the electrical netlist
and results in an electro-thermal netlist, then a fully coupled
electro-thermal simulation will be executed until electrical and
thermal characteristics are in spec.
VI. APPLICATION
EXAMPLE
In Fig. 4, we see an application in the field of power
electronics. Four vertical DMOS transistors TE1 to TE4,
which are connected in parallel and presented by TE1 in the
schematic, shall control the output current through RL. This
current IEL shall be exactly 1 A, which is realized by a shunt
resistor of RSH = 42mR and the multi-emitter transistor T4
by the relation ( k T / q )In 5 M RSH. I E L .
Two bipolar transistors T4 and T5 control the gate voltage of
TE1 to TE4 in a manner, that voltage fluctuations of the drain
voltage caused by VD are neutralized and by switching on VD
from 0 to 10 V, JRL shall be stable within 5 ms. The BPT’s
work in a current mirror, consisting of T2 and T3, which are
controlled by a circuitry whose functionality is presented by a
constant current source ISDC in this schematic.
As one can see, T4 and T5 as strongly temperature dependent elements shall be placed on an isoline of temperature. In
this application example we will simulate the electro-thermmal
response, when the voltage of VD is raised linearly from 0 to
10 V within 10 ms.
We have four major heat generating elements, the VDMOS
transistors TE1 to TE4, with different sizes, as schematically
DIGELE et al.: FULLY COUPLED DYNAMIC ELECTRO-THERMAL SIMULATION
255
.................................................................
P(TE2)
Siliron chip
4
Adhesive layer
THGND
Fig. 5. Thermal model of layout, chip and adhesive. Sidewalls and top
surface are adiabatic. T4 and T5 are placed on locations, where a thermal
isoline is to he expected. VDMOS transistors TE1 to TE4 arc different in the
number of cells and therefore in size.
shown in Fig. 5. For IRL = 1 A we can easily calculate the
power dissipation of the transistors in steady state. There is
a voltage drop of V,,, = 0.042 V across the shunt resistor
and a voltage drop of VRL= 1 V across the load, that means
we have a steady state power consumption of P, = 8.958
W. We assume a chip size of 9 mm2, an adhesive thickness of
50 pm, the position and size of the transistors as schematically
shown in Fig. 5 and as package a multiwatt package which is
approximated by an ideal heatsink beneath the adhesive layer.
We extract a thermal model with seven pins (four pins are
the heatsources, that means the VDMOS transistors, two pins
correspond to the thermally passive BPT T4 and T5 and one
pin corresponds to the bottom of the IC, which is considered
to be thermal ground (THGND).
We want to simulate electro-thermmal interaction between
the heat generating VDMOS transistors which are electrically
dependent on the control circuitry especially on the strongly
temperature dependent BPT’s T4 and T5. For this reason we
use electro-thermmal compact models, which are based on
the electrical compact models extended by two thermal nodes.
One of them is connected to thermal ground, the other to the
automatically generated thermal model of chip and adhesive.
In the electro-thermmal VDMOS compact model, the power
consumption is calculated and forwarded as a “SABERthrough” variable into the generated thermal model. In this
respect we consider only Joule heating, consisting of the
“in-phase’’ product of internal voltages and currents.
In common circuit simulators the variable “temperature”
is a parameter which has to be transformed into the signal
“temperature” as a SABER “across-variable” analog to the
electrical potential.
The heat generation of the BPT’s is neglected in this respect,
though we use heat generating electro-thermal compact models. Remember, that the calculated dissipated power does not
influence the behavior of the chip, “passive contacts” where
the BPT’s are connected to, are considered to be adiabatic
(Section IV).
In Fig. 6, we see the dissipated power of TE1 to TE4. The
nearly constant slope up to t = 10 ms is due to the linear
rise of VD from 0 to 10 V. From that moment on, we would
expect a constant dissipated power, which is not the case. We
0.0
0.01
0.02
0.04
0.03
t(s)
Fig. 6. Dissipated power of VDMOS TE1 to TW, calculated by an
electro-thermmal simulation with thermal interaction between VDMOS and
BPT’s. The voltage VD is ramped from 0 to 10 V within 10 ms.
50.01
TE2
TE3
......
40.0
-0
TE4
T4
30.0
T5
-
20.0
10.0
0.0
0.0
0.01
0.02
0.03
0.04
0.05
0.06
W
Fig. 7. Transient temperature response of VDMOS TEl to TE4 and the two
BPT T4 and T5 which are placed on an isoline.
observe a rise of the dissipated power due to electro-thermmal
coupling between the VDMOS and the BPT’s.
In Fig. 7, we see the transient temperature which is observed
at the VDMOS transistors and the two BPT’s. We can state the
thermal delay to be approximately 1 to 2 ms, caused by the
distance d = 325pm between the heat-generating VDMOS
and the BPT’s.
The time which is needed to reach thermal and electrical
steady state is in the order of about 50 ms which is due to the
ideal heat sink to which the chip is fixed by the adhesive.
We expect from Fig. 7 that the steady state temperatures
of the bipolar transistors will be approximately 20 K higher
than the ambient temperature. This results in a slight increase
of the collector voltage of T5, which equals the gate voltage
of the VDMOS transistors. This effect is quite surprising,
one would expect the contrary, as the collector current of
bipolartransistors has a positive temperature coefficient (as
well as the built-in base-emitter voltage VBEhas a negative
one).
As we can see in Fig. 4, we have used for T4 a multiemitter
transistor with five emitters, while T5 has only one. This means
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 5, NO. 3, SEPTEMBER 1997
256
The best possible solution would be to place T4 and T5
on an isoline far away from the heat generating area. For an
efficient placement consider Fig. 9, which corresponds to the
steady state at the end of a transient fully coupled electrothermal simulation.
VII. CONCLUSIONS
0.0
0.01
0.02
0.03
w
0.04
0.06
0.05
Fig. 8. Drain current through the load resistance RL as result of the fully
coupled electro-thermmal simulation. The increase in output current is due
to thermal interaction between the heat generating VDMOS-transistors and
the BPT’s.
I
0
I
Fig. 9. Electro-thermal simulation with SABER. The isolines correspond
to 10, 20, 30, 40, 50, and 60 K difference to the ambient temperature
respectively. 11 . 1 2 . 6 = 792 nodes standing for a fast thermal model.
T4 dominates the base potential which decreases more with
rising temperature than the base potential of T5 would do,
without being electrically connected. As they are connected,
this decrease in base voltage results in a slight increase of
collector voltage of T5.
If we look at the drain current in Fig. 8, we observe a peak
at t = 1.75 ms which is due to the decreasing gate voltage
of the VDMOS transistors, when the desired operating point
is reached. After this peak, based on electrical behavior, we
observe an increase in output current which is due to electrothermmal interaction. The thermal time constant needed to
reach thermal steady state is approximately t = 50 ms and thus
dominates the electrical time constant. An interesting point is,
that even if BPT T4 and T5 work under same temperature
conditions, they are sensible to the absolute temperature. The
situation would become worse, if there were a temperature
gradient between them.
We developed a 3-D thermal model generator making
possible the simulation of electro-thermmal interaction with
one single circuit simulator. Also, we can use this circuit
simulator for purely thermal simulations of temperature distributions and transient behavior on chip level. The isolines
of temperature at every timestep of the simulation can be
drawn, which is an important guideline for the layout to place
temperature dependent components. The requirement for the
application of this thermal model generator is the mounting
of the chip into power packages, where heat conduction is
essential and the silicon die is connected via an adhesive
layer to the heatsink. The discretization algorithm is based
on the nonlinear heat flow differential equation in silicon ( 5 ) ,
making possible the simulation of power circuits, where big
temperature gradients occur. For reduction of mesh density, we
use adaptive gridding and offer the possibility to use “passive
contacts” for components where only temperature dependence
is essential and the dissipated power can be neglected in
respect to chip heating, compared to major power dissipating
components connected to “active contacts.”
Summing up, this is the first reported solution for fully
coupled dynamic electro-thermal simulation on chip (isolines
of temperature) and circuit level (electro-thermmal interaction
concerning circuit design) which is able to cope with the
nonlinear heat diffusion equation.
REFERENCES
[1] V. Dudek, W. Appel, L. Beer, G. Digele, and B. Hofflinger,
“Lithography-independent nanometer silicon MOSFET’s on insulator,”
IEEE Trans. Electron Devices, vol. 43, pp. 1626-1632, Oct. 1996.
[2] A. R. Hefner, Jr., “A dynamic electro-thermal model for the IGBT,”
IEEE Trans. Ind. Applicat., vol. 30, pp. 394405, Mar. 1994.
[3] SGS-Thomson, “Thermal management in surface mount technology,”
SGS-Thomson, Munich, Germany, Tech. Rep., July 1988.
[4] C. C. Lee and A. L. Palisoc, “Real-time thermal design of integrated
circuit devices,” IEEE Trans. Comp., Hybrids, Manufact. Technol., vol.
11, pp. 485492, Dec. 1988.
[SI Y. J. Min, A. L. Palisoc, and C. C. Lee, “Transient thermal study
of semiconductor devices,” IEEE Trans. Comp., Hybrids, Manufact.
Technol., vol. 13, pp. 980-988, Dec. 1990.
[6] P. Leturcq, J.-M. Dorkel, A. Napieralski, and E. Lachiver, “A new
approach to thermal analysis of power devices,” IEEE Trans. Electron
Devices, vol. ED-34, pp. 1147-1156, May 1987.
171 P. Antognetti, G. R. Bisio, F. Curatelli, and S. Palara, “Threedimensional transient thermal simulation: Application to delayed short
circuit protection in power IC’s,” ZEEE J. Solid-state Circuits, vol.
SC-15, pp. 277-281, June 1980.
[8] F. Curatelli and G. M. Bisio, “Characterization of the thermal behavior
in IC’s,” Solid-State Electron., vol. 34, no. 7, pp. 751-760, July 1991.
[9] P. R. Gray, D. J. Hamilton, and J. D. Lieux, “Analysis and design of
temperature stabilized substrate integrated circuits,” ZEEE J. Solid-state
Circuits, vol. SC-9, pp. 61-69, Apr. 1974.
[ 101 R. Castello and P. Antognetti, “Integrated-circuit modeling,” IEEE J.
Solid-Srate Circuits, vol. SC-13, pp. 363-366, 1978.
[ l l ] V. A. Koval, A. I. Ostapchuk, I. V. Farmaga, and D. V. Fedasyuk,
“Cad: The numerical and analytical methods combined analysis of IC’s
thermal fields,” in Proc. EURO-DAC ’93, European Design Automation
Con$ Euro-VHDL ‘93, 1993.
DIGELE et al.: FULLY COUPLED DYNAMIC ELECTRO-THERMAL SIMULATION
V. Koval and I. W. Farmaga, “MONSTR: A complete thermal simulator
of electronic systems,” in Proc. 31st Design Automation Cor$, 1994,
pp. 570-575.
S. Selberherr, Analysis and Simulation of Semiconductor Devices. New
York: Springer-Verlag, 1984.
F. Bonani and G. Ghione, “On the application of the kirchhoff transformation to the steady-state thermal analysis of semiconductor devices
with temperature-dependent and piecewise inhomogeneous thermal conductivity,” Solid-State Electron., vol. 38, no. 7, pp. 1409-1412, July
1995.
W. van Petegem, B. Geeraerts, W. Sansen, and B. Graindourse, “Electrothermal simulation and design of integrated circuits,” IEEE J. Solid
State Circuits, vol. 29, pp. 143-146, Feb. 1994.
S . 4 . Lee and D. J. Allstot, “Electrothermal simulation of integrated
circuits,” IEEE J. Solid-State Circuits, vol. 28, pp. 1283-1293, Dec.
1993.
P. C. Munro and F.-Q. Ye, “Simulating the current mirror with a
self-heating BJT model,” IEEE J, Solid-State Circuits, vol. 26, pp.
1321-1324, Sept. 1991.
J. Bielefeld, G. Pelz, H. B. Abel, and G. Zimmer, “Dynamic SPICEsimulation of the electrothermal behavior of SO1 MOSFET’s,” IEEE
Trans. Electron Devices, vol. 42, pp. 1968-1974, Nov. 1995.
K. E. Mortenson, “Transistor junction temperature as a function of time,”
Proc. IRE, Apr. 1957.
A. R. Hefner and D. L. Blackbum, “Simulating the dynamic electrothermal behavior of power electronic circuits and systems,” IEEE Trans.
Power Electron., vol. 8, pp. 376-385, Oct. 1993.
-,
“Thermal component models for electrothermal network simulation,” IEEE Trans. Comp., Packag. Manufact. Tecknol., vol. 17, pp.
413-424, Sept. 1994.
K. Fukahori and P. R. Gray, “Computer simulation of integrated circuits
In the presence of electrothermal interacction,” IEEE J. Solid Stute
Circuits, vol. SC-I 1, pp. 834-846, Dec. 1976.
M. Latif and P. R. Bryant, “Network analysis approach to multidimensional modeling of transistors including thermal effects,” IEEE Trans.
Conzputer-Aided Design, vol. CAD-I, pp. 94-101, Apr. 1982.
V. Szekely. A. Poppe, A. Pihi, A. Csendes, G. Hajas, and M. Rencz,
“Electro-thermal and logi-thermal simulation of vlsi designs,” in Proc.
IEEE Yherminic-lnt. Workshop Thermal Investigations of IC’s and
Microstructures, Budapest, Hungary, Sept. 1996, pp. 79-88.
M.-N. Sabry, A. Bontemps, V. Aubert, and R. Vahrmann, “Realistic
and efficient simulation of electro-thermal effects in vlsi circuits,” in
Proc. IEEE Therminic-lnt. Workshop Thermal Investigations of IC’s
and Microstructures, Budapest, Hungary, Sept. 1996, pp. 95-103.
S. Muller, K. Kells, and W. Fichtner, “Automatic rectangle-based adaptive mesh generation without obtuse angles,” IEEE Trans. ComputerAided Design, vol. 11, pp. 855-863, July 1992.
M. S. Adler, “A method for achieving and choosing variable density
grids in finite difference formualtions and the importance of degeneracy
and band gap narrowing in device modeling,” in Proc. NASECODE I
Con$, 1979, pp. 3-30.
Analogy, Inc., SABER Manual, 9205 S. W. Gemini Drive, Beaverton,
OR 97008, Oct. 1990.
G. Digclc, S. Lindcnkrcuz, and E. Kaspcr, “Fully-couplcd dynamic
electro-thermal simulation,” in Proc. IEEE Therminic-int. Workshop
Thermal Investigations of IC’s and Microstructures, Budapest, Hungary,
Sept. 1996, pp. 73-77.
G. A. Slack and C. J. Glasbrenner, “Thermal conductivity of silicon and
germanium from 3 I< and the melting point,” Phys. Rev. , vol. 134, no.
4 A, pp. 1058-1069, 1964.
251
[3 I] ISE Integrated Systems Engineering AG, ETH-Zentrum, ETZ, Gloriastr.
35, CH-8092 Zurich, Switzerland, DESSIS-ISE Reference Manual, 1994.
[32] Analogy, Inc., MAST Reference Manual, 9205 S.W. Gemini Drive,
Beaverton, OR 97008, Oct. 1990.
Georg Digele received the Dip1.-Ing. degree in
electrical engineering from the University of
Stuttgart, Germany, in 1995.
From 1994 to 1995, he worked on the process
development and fabrication of lithographyindependent nanometer silicon MOSFET’s on
insulator at the Institute of Microelectronics,
Stuttgart, Germany. He then joined Robert Bosch
GmbH, Reutlingen, Germany, where he is currently
working toward the Ph.D. degree in electrical
engineering in cooperation with the University
of Stuttgart. His research interests include the simulation and modeling of
electro-thermal interaction on circuit, chip, and device level by taking into
account the influence of packaging in a transient way.
Steffi Lindenkreuz received the diploma degree in
physics from the Technical University of Dresden,
Germany, in 1978.
From 1978 to 1989, she worked in a circuit development group at Zentrum Mikroelektronik Dresden,
Germany, and was responsible for the test structure
methodology and process characterization. In 1989.
she moved to a development group for Automotive
Equipment at the Robert Bosch GmbH, Reutlingen,
Germany. Her main fields were process simulation, device characterization, and measurement techniques. In recent years, she has established a group for process characterization
and device modeling at Robert Bosch.
Erich Kasper studied experimental physics at the University of tiraz, Austria,
where he received the Ph.D. degree in physics in 1971 with a dissertation on
electrical properties of dislocations in silicon.
He was active as a Scientist in the research laboratories of Telefunken,
AEG, and Daimler Benz, Genriany. His main research topics were solid-state
analysis by X-ray topography and electron microscopy, material synthesis
by molecular beam epitaxy and semiconductor device preparation for microwave applications. Since 1987, he was responsible for “novel silicon
devices and technology” within Daimler BenL Research, Ulm, Germany,
with main emphasis on SiGe/Si-based heterostmctures for fast transistors
(HBT, MODFET) and optoelectronic transceivers (ultrathin superlattices).
Since 1993, he has been working at the University of Stuttgart, Germany,
as Profcssor of Electrotcchnics and Head of the Institute of Semiconductor
Engineering. His main interest is directed to silicon-based nano-electronics,
integration of millimeter-wave circuits, and SiGelSi-quantum-well devices.