PCS-902
Line Distance Relay
Instruction Manual
NR Electric Co., Ltd.
Preface
Preface
Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.
Documentation for equipment ordered from NR is dispatched separately from manufactured goods
and may not be received at the same time. Therefore, this guide is provided to ensure that printed
information normally present on equipment is fully understood by the recipient.
Before carrying out any work on the equipment, the user should be familiar with the contents of
this manual, and read relevant chapter carefully.
This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.
Health and Safety
The information in this chapter of the equipment documentation is intended to ensure that
equipment is properly installed and handled in order to maintain it in a safe condition.
When electrical equipment is in operation, dangerous voltages will be present in certain parts of
the equipment. Failure to observe warning notices, incorrect use, or improper use may endanger
personnel and equipment and cause personal injury or physical damage.
Before working in the terminal strip area, the equipment must be isolated.
Proper and safe operation of the equipment depends on appropriate shipping and handling,
proper storage, installation and commissioning, and on careful operation, maintenance and
servicing. For this reason, only qualified personnel may work on or operate the equipment.
Qualified personnel are individuals who:

Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;

Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;

Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;

Are trained in emergency procedures (first aid).
Instructions and Warnings
The following indicators and standard definitions are used:
PCS-902 Line Distance Relay
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Preface
DANGER! means that death, severe personal injury and considerable equipment damage
will occur if safety precautions are disregarded.
WARNING! means that death, severe personal and considerable equipment damage
could occur if safety precautions are disregarded.
CAUTION! means that light personal injury or equipment damage may occur if safety
precautions are disregarded.
NOTICE! is particularly applies to damage to device and to resulting damage of the protected
equipment.
DANGER!
NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously high
voltage that cause death.
WARNING!
ONLY qualified personnel should work on or in the vicinity of this device. This personnel
MUST be familiar with all safety regulations and service procedures described in this
manual. During operating of electrical device, certain part of the device is under high
voltage. Severe personal injury and significant device damage could result from
improper behavior.
WARNING!
Do NOT touch the exposed terminals of this device while the power supply is on. The
generated high voltage causes death, injury, and device damage.
WARNING!
Thirty seconds is NECESSARY for discharging the voltage. Hazardous voltage can be
present in the DC circuit just after switching off the DC power supply.
CAUTION!
 Earthing
Securely earthed the earthing terminal of the device.
 Operating environment
ONLY use the device within the range of ambient environment and in an
ii
PCS-902 Line Distance Relay
Date: 2019-03-01
Preface
environment free of abnormal vibration.
 Ratings
Check the input ratings BEFORE applying AC voltage/current and power supply to
the device.
 Printed circuit board
Do NOT attach or remove printed circuit board if the device is powered on.
 External circuit
Check the supply voltage used when connecting the device output contacts to
external circuits, in order to prevent overheating.
 Connection cable
Carefully handle connection cables without applying excessive force.
NOTICE!
The firmware may be upgraded to add new features or enhance/modify existing
features, please MAKE SURE that the version of this manual is compatible with the
product in your hand.
Copyright © 2019 NR. All rights reserved.
We reserve all rights to this document and to the information contained herein. Improper use in particular reproduction and dissemination
to third parties is strictly forbidden except where expressly authorized.
The information in this manual is carefully checked periodically, and necessary corrections will be included in future editions. If
nevertheless any errors are detected, suggestions for correction or improvement are greatly appreciated.
We reserve the rights to make technical improvements without notice.
NR ELECTRIC CO., LTD.
Tel: +86-25-87178888
Headquarters: 69, Suyuan Avenue, Jiangning, Nanjing 211102, China
Manufactory: 18, Xinfeng Road, Jiangning, Nanjing 211111, China
P/N: ZL_PCS-902_X_Instruction Manual_EN_Overseas General_X
PCS-902 Line Distance Relay
Fax: +86-25-87178999
Website: www.nrec.com/en
Version: R3.10
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Date: 2019-03-01
Preface
Documentation Structure
The manual provides a functional and technical description of this relay and a comprehensive set
of instructions for the relay’s use and application.
All contents provided by this manual are summarized as below:
1 Introduction
Briefly introduce the application, functions and features about this device.
2 Technical Data
Introduce the technical data about this device, such as electrical specifications, mechanical
specifications, ambient temperature and humidity range, communication port parameters, type
tests, setting ranges and accuracy limits and the certifications that our products have passed.
3 Operation Theory
Introduce a comprehensive and detailed functional description of all protective elements.
4 Supervision
Introduce the automatic self-supervision function of this device.
5 Management
Introduce the management function (measurement and recording) of this device.
6 Hardware
Introduce the main function carried out by each plug-in module of this device and providing the
definition of pins of each plug-in module.
7 Settings
List settings including system settings, communication settings, label settings, logic links and etc.,
and some notes about the setting application.
8 Human Machine Interface
Introduce the hardware of the human machine interface (HMI) module and a detailed guide for the
user how to use this device through HMI. It also lists all the information which can be view through
HMI, such as settings, measurements, all kinds of reports etc.
9 Configurable Function
Introduce configurable function of the device and all configurable signals are listed.
10 Communication
Introduce the communication port and protocol which this device can support, IEC60970-5-103,
IEC61850 and DNP3.0 protocols are introduced in details.
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PCS-902 Line Distance Relay
Date: 2019-03-01
Preface
11 Installation
Introduce the recommendations on unpacking, handling, inspection and storage of this device. A
guide to the mechanical and electrical installation of this device is also provided, incorporating
earthing recommendations. A typical wiring connection to this device is indicated.
12 Commissioning
Introduce how to commission this device, comprising checks on the calibration and functionality of
this device.
13 Maintenance
A general maintenance policy for this device is outlined.
14 Decommissioning and Disposal
A general decommissioning and disposal policy for this device is outlined.
15 Manual Version History
List the instruction manual version and the modification history records.
Typographic and Graphical Conventions
Deviations may be permitted in drawings and tables when the type of designator can be obviously
derived from the illustration.
The following symbols are used in drawings:
&
AND gate
≥1
OR gate
Comparator
BI
SET
EN
Binary signal via opto-coupler
I>
Input signal from comparator with setting
Input signal of logic setting for function enabling
PCS-902 Line Distance Relay
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Preface
SIG
Input of binary signal except those signals via opto-coupler
XXX
Output signal
Timer
t
t
Timer (optional definite-time or inverse-time characteristic)
10ms
0ms
Timer [delay pickup (10ms), delay dropoff (0ms), non-settable]
[XXX]
0ms
Timer (delay pickup, settable)
0ms
[XXX]
Timer (delay dropoff, settable)
[XXX]
[XXX]
Timer (delay pickup, delay dropoff, settable)
IDMT
Timer (inverse-time characteristic)
---xxx is the symbol
Symbol Corresponding Relationship
Basic
A, B, C
L1, L2, L3
R, Y, B
AN, BN, CN
L1N, L2N, L3N
RN,YN, BN
ABC
L123
RYB
U (voltage)
V
U
Example
Ia, Ib, Ic, I0
IL1, IL2, IL3, IN
IR, IY, IB, IN
Ua, Ub, Uc
VL1, VL2, VL3
UR, UY, UB
Uab, Ubc, Uca
VL12, VL23, VL31
URY, UYB, UBR
U0, U1, U2
VN, V1, V2
UN, U1, U2
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PCS-902 Line Distance Relay
Date: 2019-03-01
1 Introduction
1 Introduction
Table of Contents
1 Introduction ....................................................................................... 1-a
1.1 Application....................................................................................................... 1-1
1.2 Function ........................................................................................................... 1-4
1.3 Features ........................................................................................................... 1-7
List of Figures
Figure 1.1-1 Typical application of PCS-902 for single circuit breaker ................................. 1-1
Figure 1.1-2 Typical application of PCS-902 for double circuit breakers .............................. 1-2
Figure 1.1-3 Functional diagram of PCS-902............................................................................ 1-3
PCS-902 Line Distance Relay
1-a
Date: 2018-02-12
1 Introduction
PCS-902 Line Distance Relay
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Date: 2018-02-12
-02-27
1 Introduction
1.1 Application
PCS-902 is a digital line distance protection with the main and back-up protection functions, which
is designed for overhead line or cables and hybrid transmission lines of various voltage levels.
52
52
PCS-902
Optical fibre channel or PLC channel
PCS-902
Communication channel via direct dedicated fibre, MUX or PLC
Figure 1.1-1 Typical application of PCS-902 for single circuit breaker
In the case of main protection, PCS-902 provides dual-channels pilot distance protection (PUTT,
POTT, blocking and unblocking) and pilot directional earth-fault protection (selectable for
independent communication channel or sharing channel with POTT), which can clear any internal
fault instantaneously for the whole line with the aid of protection signal. Deviation of power
frequency component (DPFC) distance protection with fixed forward direction can perform
extremely high speed operation for close-up faults. There is direct transfer trip (DTT) feature
incorporated in the device.
PCS-902 also includes distance protection (1 forward zones and 4 settable forward or reverse
zone distance protection with selectable mho or quadrilateral characteristic, dedicated pilot
distance zone for pilot distance protection), out-of-step protection, 4 stages directional earth fault
protection, 4 stages directional phase overcurrent protection, 4 stages directional
negative-sequence overcurrent protection, 3 stages voltage protection (under/over voltage
protection), 3 stages residual overvoltage protection, 1 stage negative-sequence overvoltage
protection, 4 stages frequency protection (under/over frequency protection), broken conductor
protection, reverse power protection, pole discrepancy protection, breaker failure protection,
thermal overload protection, and dead zone protection etc. Moreover, a backup overcurrent and
earth fault protection will be automatically enabled when VT circuit fails.
In addition, stub differential protection is provided for one and a half breakers arrangement when
transmission line is put into maintenance.
PCS-902 can be configured to support single circuit breaker application or double circuit breakers
application by PCS-Explorer. If the device is applied to double circuit breakers mode, all protection
functions related to the number of circuit breaker will be affected, including circuit breaker position
supervision, breaker failure protection, dead zone protection, pole discrepancy protection,
synchrocheck, automatic reclosure, trip logic, CT circuit supervision, control and synchrocheck for
manual closing.
PCS-902 Line Distance Relay
1-1
Date: 2018-02-12
1 Introduction
Bus1
Single-phase
voltage
52
PCS-902
Line 1
Three-phase
voltage
52
Line 2
Single-phase
voltage
52
Bus2
Figure 1.1-2 Typical application of PCS-902 for double circuit breakers
PCS-902 has selectable mode of single-phase tripping or three-phase tripping and configurable
auto-reclosing mode for 1-pole, 3-poles and 1/3-pole operation.
PCS-902 with appropriate selection of integrated protection functions can be applied for various
voltage levels and primary equipment such as cables, overhead lines, interconnectors and
transformer feeder, etc. It also supports configurable binary inputs, binary outputs, LEDs and IEC
61850 protocol.
PCS-902 Line Distance Relay
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Date: 2018-02-12
-02-27
1 Introduction
BUS
52
81
85
21
50/51P
50/51G
50/51Q
50GVT
50PVT
50BF
49
46BC
32R
62PD
FR
59Q
21D
59G
78
59P
FL
Data Transmit/Receive
27P
50DZ
87STB (Only for one and a half breakers arrangement)
SOTF
25
79
LINE
Figure 1.1-3 Functional diagram of PCS-902
No.
Function
ANSI
1
Pilot protection
85
2
DPFC distance protection
21D
3
Distance protection
21
4
Out-of-step protection
78
5
Phase overcurrent protection
50/51P
6
Earth fault protection
50/51G
7
Negative-sequence overcurrent protection
50/51Q
8
Overvoltage protection
59P
9
Negative-sequence overvoltage protection
59Q
10
Residual overvoltage protection
59G
11
Undervoltage protection
27P
12
Frequency protection
81
13
Broken conductor protection
46BC
14
Reverse power protection
32R
15
Breaker failure protection
50BF
16
Thermal overload protection
49
17
Stub differential protection
87STB
18
Dead zone protection
50DZ
19
Pole discrepancy protection
62PD
20
Switch onto fault
SOTF
21
Phase overcurrent protection when VT circuit failure
50PVT
22
Earth fault protection when VT circuit failure
50GVT
23
Synchronism check
25
24
Automatic reclosure
79
25
Fault recorder
FR
PCS-902 Line Distance Relay
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Date: 2018-02-12
1 Introduction
26
Fault location
FL
1.2 Function
1.
Protection Function

Distance protection (including eight zones)

One zone DPFC distance protection with fixed forward direction

One zone distance protection with fixed forward direction (including phase-to-ground and
phase-to-phase, mho or quadrilateral characteristic)

One zone pilot distance protection with fixed forward direction (including phase-to-ground
and phase-to-phase, mho or quadrilateral characteristic)

One zone pilot distance protection with fixed reverse direction (including phase-to-ground
and phase-to-phase, mho or quadrilateral characteristic)

Four zones distance protection with settable forward or reverse direction (including
phase-to-ground and phase-to-phase, mho or quadrilateral characteristic)

Load encroachment for mho and quadrilateral characteristic distance element

Power swing blocking releasing, selectable for each of above mentioned zones

Out-of-step protection

Overcurrent protection


Four stages phase overcurrent protection, selectable time characteristic (definite-time or
inverse-time) and directionality (forward direction, reverse direction or non-directional)

Four stages directional earth fault protection, selectable time characteristic (definite-time
or inverse-time) and directionality (forward direction, reverse direction or non-directional)

Four stages negative-sequence overcurrent protection, selectable time characteristic
(definite-time or inverse-time) and directionality (forward direction, reverse direction or
non-directional)
Breaker failure protection

Optional instantaneously re-tripping

One stage with two delay timers

Thermal overload protection

Stub differential protection

Dead zone protection

Pole discrepancy protection

Broken conductor protection
PCS-902 Line Distance Relay
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Date: 2018-02-12
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1 Introduction

Reverse power protection

Switch onto fault (SOTF)







Via distance measurement elements

Via dedicated earth fault element

Via phase overcurrent element
Backup protection when VT circuit failure

Phase overcurrent protection when VT circuit failure

Ground overcurrent protection when VT circuit failure
Voltage protection

Three stages overvoltage protection

Three stages undervoltage protection

Three stages residual overvoltage protection

One stage negative-sequence overvoltage protection
Frequency protection

Four stages overfrequency protection

Four stages underfrequency protection

df/dt block criterion for underfrequency protection
Control function

Synchro-checking

Automatic reclosure (single shot or multi-shot (max. 4) for 1-pole AR and 3-pole AR)
Pilot scheme logic

Phase-segregated communication logic of distance protection

Weak infeed logic of pilot distance protection

Weak infeed logic of pilot directional earth fault protection
Communication scheme of optical pilot channel (Optional)

Direct optical link

Connection to a communication network, support G.703 and C37.94 protocol

Dual-channels redundancy
2.
Measurement and control function

Remote control (open and closing)
PCS-902 Line Distance Relay
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Date: 2018-02-12
1 Introduction


Synchronism check for remote and manual closing
Energy metering (active and reactive energy are calculated in import respectively export
direction)
3.
Logic

User programmable logic
4.
Additional function

Fault location

Fault phase selection

Parallel line compensation for fault location

VT circuit supervision

CT circuit supervision

Self diagnostic

DC power supply supervision



Event Recorder including 1024 disturbance records, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs.
Disturbance recorder including 32 disturbance records with waveforms (The file format of
disturbance recorder is compatible with international COMTRADE file.)
Four kinds of clock synchronization methods



Conventional

PPS (RS-485): Pulse per second (PPS) via RS-485 differential level

IRIG-B (RS-485): IRIG-B via RS-485 differential level

PPM (DIN): Pulse per minute (PPM) via the optical coupler

PPS (DIN): Pulse per second (PPS) via the optical coupler
SAS

SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network

SNTP (BC): Broadcast SNTP mode via Ethernet network

Message (IEC103): Clock messages through IEC103 protocol
Advanced

IEEE1588: Clock message via IEEE1588

IRIG-B (Fiber): IRIG-B via optical-fibre interface

PPS (Fiber): Pulse per second (PPS) via optical-fibre interface
PCS-902 Line Distance Relay
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Date: 2018-02-12
-02-27
1 Introduction

5.

NoTimeSync
Monitoring
Number of circuit breaker operation (single-phase tripping, three-phase tripping and
reclosing)

Channel status

Frequency
6.
Communication

Optional 2 RS-485 communication rear ports conform to IEC 60870-5-103 protocol

1 RS-485 communication rear ports for clock synchronization


Optional 2 or 4 Ethernet ports (depend on the chosen type of MON plug-in module) conform
to IEC 61850 protocol, DNP3.0 protocol or IEC 60870-5-103 protocol over TCP/IP
Optional 2 Ethernet ports via optic fiber (ST interface) conform to IEC 61850 protocol, DNP3.0
protocol or IEC 60870-5-103 protocol over TCP/IP

GOOSE and SV communication function (optional NET-DSP plug-in module)
7.
User Interface

Friendly HMI interface with LCD and 9-button keypad on the front panel.

1 front multiplex RJ45 port for testing and setting

1 RS-232 or RS-485 rear ports for printer

Language switchover—English+ selected language

Auxiliary software—PCS-Explorer
1.3 Features



The intelligent device integrated with protection, control and monitor provides powerful
protection function, flexible protection configuration, user programmable logic and
configurable binary input and binary output, which can meet with various application
requirements.
High-performance hardware platform and modularized design, fault detector DSP＋protection
DSP. Fault detector DSP manages fault detector and protection DSP manages protection
calculation. Their data acquisition system is completely independent in electronic circuit. DC
power supply of output relay is controlled by the operation of fault detector element, which
prevents maloperation due to error from ADC or damage of any apparatus.
Fast fault clearance for faults within the protected line, the operating time is less than 10 ms
for close-up faults, less than 15ms for faults in the middle of protected line and less than 25ms
for remote end faults.
PCS-902 Line Distance Relay
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Date: 2018-02-12
1 Introduction






The unique DPFC distance element integrated in the protective device provides extremely
high speed operation and insensitive to power swing.
Self-adaptive floating threshold which only reflects deviation of power frequency component
improves the protection sensitivity and stability under the condition of load fluctuation and
system disturbance.
Advanced and reliable power swing blocking releasing feature which ensure distance
protection operate correctly for internal fault during power swing and prevent distance
protection from maloperation during power swing
Flexible automatic reclosure supports various initiation modes and check modes
Multiple setting groups with password protection and setting value saved permanently before
modification
Powerful PC tool software can fulfill protection function configuration, modify setting and
waveform analysis.
PCS-902 Line Distance Relay
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Date: 2018-02-12
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2 Technical Data
2 Technical Data
Table of Contents
2 Technical Data ................................................................................... 2-a
2.1 Electrical Specifications ................................................................................. 2-1
2.1.1 AC Current Input .................................................................................................................. 2-1
2.1.2 AC Voltage Input .................................................................................................................. 2-1
2.1.3 Power Supply ....................................................................................................................... 2-1
2.1.4 Binary Input .......................................................................................................................... 2-2
2.1.5 Binary Output ....................................................................................................................... 2-2
2.2 Mechanical Specifications.............................................................................. 2-3
2.3 Ambient Temperature and Humidity Range .................................................. 2-4
2.4 Communication Port ....................................................................................... 2-4
2.4.1 EIA-485 Port ........................................................................................................................ 2-4
2.4.2 Ethernet Port ........................................................................................................................ 2-4
2.4.3 Optical Fibre Port ................................................................................................................. 2-4
2.4.4 Print Port .............................................................................................................................. 2-5
2.4.5 Clock Synchronization Port ................................................................................................. 2-5
2.5 Type Tests ........................................................................................................ 2-5
2.5.1 Environmental Tests............................................................................................................. 2-5
2.5.2 Mechanical Tests ................................................................................................................. 2-6
2.5.3 Electrical Tests ..................................................................................................................... 2-6
2.5.4 Electromagnetic Compatibility ............................................................................................. 2-6
2.6 Certifications ................................................................................................... 2-7
2.7 Terminals ......................................................................................................... 2-7
2.8 Measurement Scope and Accuracy ............................................................... 2-7
2.9 Management Function .................................................................................... 2-8
2.9.1 Control Performance............................................................................................................ 2-8
PCS-902 Line Distance Relay
2-a
Date: 2019-03-01
2 Technical Data
2.9.2 Clock Performance .............................................................................................................. 2-8
2.9.3 Fault and Disturbance Recording ........................................................................................ 2-8
2.9.4 Binary Input Signal............................................................................................................... 2-8
2.10 Protective Functions..................................................................................... 2-8
2.10.1 Fault Detector .................................................................................................................... 2-8
2.10.2 Distance Protection ............................................................................................................ 2-8
2.10.3 Phase Overcurrent Protection ........................................................................................... 2-9
2.10.4 Earth Fault Protection ........................................................................................................ 2-9
2.10.5 Negative-sequence Overcurrent Protection ...................................................................... 2-9
2.10.6 Overvoltage Protection ...................................................................................................... 2-9
2.10.7 Negative-sequence Overvoltage Protection ...................................................................... 2-9
2.10.8 Residual Overvoltage Protection ..................................................................................... 2-10
2.10.9 Undervoltage Protection .................................................................................................. 2-10
2.10.10 Overfrequency Protection .............................................................................................. 2-10
2.10.11 Underfrequency Protection ............................................................................................ 2-10
2.10.12 Breaker Failure Protection ............................................................................................. 2-10
2.10.13 Thermal Overload Protection ..........................................................................................2-11
2.10.14 Stub Differential Protection .............................................................................................2-11
2.10.15 Dead Zone Protection .....................................................................................................2-11
2.10.16 Pole Discrepancy Protection ..........................................................................................2-11
2.10.17 Broken Conductor Protection .........................................................................................2-11
2.10.18 Reverse Power Protection ............................................................................................. 2-12
2.10.19 Auto-reclosing ................................................................................................................ 2-12
2.10.20 Transient Overreach ...................................................................................................... 2-12
2.10.21 Fault Locator .................................................................................................................. 2-12
PCS-902 Line Distance Relay
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Date: 2019-03-01
2 Technical Data
2.1 Electrical Specifications
NOTICE!
“System phase sequence”, which can be set by PCS-Explorer, this setting informs the
device of the actual system phase sequence, either ABC or ACB. CT and VT inputs on
the device, labeled as A, B and C, must be connected to system phase A, B and C for
correct operation.
2.1.1 AC Current Input
Phase rotation
ABC or ACB
Nominal frequency (fn)
50Hz, 60Hz
Rated current (In)
1A
Linear to
5A
0.05In~40In (It should measure current without beyond full scale against
20 times of related current and value of DC offset by 100%.)
Thermal withstand
-continuously
4In
-for 10s
30In
-for 1s
100In
-for half a cycle
250In
Burden
< 0.15VA/phase @In
Number
Up to 7 current input according to various applications
< 0.25VA/phase @In
2.1.2 AC Voltage Input
Phase rotation
ABC or ACB
Nominal frequency (fn)
50Hz, 60Hz
Rated voltage (Un)
100V~130V
Linear to
1V~170V
Thermal withstand
Phase-to-ground
Phase-to-phase
-continuously
200V
346V
-10s
260V
450V
-1s
300V
519V
Burden at rated
< 0.20VA/phase @Un
Number
Up to 6 voltage input according to various applications
2.1.3 Power Supply
Standard
IEC 60255-11:2008
Rated voltage
110Vdc/125Vdc/220Vdc/250Vdc
110Vac/220Vac
Permissible voltage range
88~300Vdc
88~264Vac
Permissible AC ripple voltage
≤15% of the nominal auxiliary voltage
Burden
Quiescent condition
<30W
Operating condition
<35W
PCS-902 Line Distance Relay
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Date: 2019-03-01
2 Technical Data
2.1.4 Binary Input
1.
Settable pickup voltage and dropoff voltage
Rated voltage
110Vdc
220Vdc
Rated current drain
1.1mA
2.2mA
On value
85-132Vdc (default set)
170-264Vdc (default set)
Off value
<66Vdc
<132Vdc
Maximum permissible voltage
300Vdc
Withstand voltage
2000Vac, 2800Vdc (continuously)
Response time for logic input
≤1ms
Number
Up to 54 binary input according to various hardware configurations
2.
Fixed pickup voltage and dropoff voltage
Rated voltage
110Vdc
125Vdc
220Vdc
220Vdc
Rated current drain
1.1mA
1.25mA
2.2mA
2.85mA
On value
77-132Vdc
87.5-150Vdc
154-264Vdc
176-264Vdc
Off value
<55Vdc
<62.5Vdc
<110Vdc
<140Vdc
Maximum permissible voltage
300Vdc
Withstand voltage
2000Vac, 2800Vdc (continuously)
Response time for logic input
≤1ms
Number
Up to 54 binary input according to various hardware configurations
2.1.5 Binary Output
1.
Tripping/signaling contact
Output mode
Potential free contact
Maximal system voltage
380Vac, 250Vdc
Continuous carry
8A
Pickup time (Typical Value)
<5ms
Dropoff time
<5ms
0.65A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=40ms)
0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
12A@3s
Short duration current
18A@1s
24A@0.5s
40A@0.2s
Durability (Loaded contact)
10000 operations
Number
Up to 55 binary output according to various hardware configurations
2.
Heavy-capacity tripping contact
Output mode
Potential free contact
PCS-902 Line Distance Relay
2-2
Date: 2019-03-01
2 Technical Data
Maximal system voltage
250Vdc
Continuous carry
10A
Pickup time
<1ms
Dropoff time
<10ms
Breaking capacity (L/R=40ms)
10A
Short duration current
15A@3s
30A@1s
Durability (Loaded contact)
10000 operations
Number
Up to 30 binary output according to various hardware configurations
3.
Fast signaling contact
Output mode
Potential free contact
Maximal system voltage
380Vac, 250Vdc
Continuous carry
5A
Pickup time
<1ms
Dropoff time
<5ms
0.65A@48Vdc
0.35A@110Vdc
Breaking capacity (L/R=0ms)
0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
8A@3s
Short duration current
12A@1s
16A@0.5s
30A@0.2s
Durability (Loaded contact)
10000 operations
Number
Up to 20 binary output according to various hardware configurations
2.2 Mechanical Specifications
Mounting Way
Flush mounted
Chassis color
Silver grey
Weight per device
Approx. 15kg
Chassis material
Aluminum alloy
Location of terminal
Rear panel of the device
Device structure
Plug-in modular type @ rear side, integrated frontplate
Protection class
Standard
IEC 60255-1:2009
Front side
IP51
Other sides
IP30
Rear side, connection terminals
IP20
PCS-902 Line Distance Relay
2-3
Date: 2019-03-01
2 Technical Data
2.3 Ambient Temperature and Humidity Range
Standard
IEC 60255-1:2009
Operating temperature
-40°C to +70°C (Readability of display may be impaired below -20°C)
Transport and storage temperature
range
-40°C to +70°C
Permissible humidity
5%-95%, without condensation
Pollution degree
Ⅱ
Altitude
<3000m
2.4 Communication Port
2.4.1 EIA-485 Port
Baud rate
4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Protocol
IEC 60870-5-103:1997
Maximal capacity
32
Max. transmission distance
500m
Safety level
Isolation to ELV level
Twisted pair
Screened twisted pair cable
2.4.2 Ethernet Port
Connector type
RJ-45
ST (Multi mode)
Transmission rate
100Mbits/s
Transmission standard
100Base-TX
100Base-FX
Max. transmission distance
100m
2km (1310nm)
Protocol
IEC 60870-5-103:1997, DNP 3.0 or IEC 61850
Safety level
Isolation to ELV level
2.4.3 Optical Fibre Port
2.4.3.1 For Station Level
Characteristic
Glass optical fiber
Connector type
ST
Fibre type
Multi mode
Max. transmission distance
2km
Wave length
1310nm
Transmission power
Min. -20.0dBm
Minimum receiving power
Min. -30.0dBm
Margin
Min +3.0dB
2.4.3.2 For Process Level
Characteristic
Glass optical fiber
Connector type
LC
Fibre type
Multi mode
PCS-902 Line Distance Relay
2-4
Date: 2019-03-01
2 Technical Data
Max. transmission distance
2km
Wave length
1310nm
Transmission power
Min. -20.0dBm
Minimum receiving power
Min. -30.0dBm
Margin
Min +3.0dB
2.4.3.3 For Pilot Channel (only for Dedicated Optical Channel)
Characteristic
Glass optical fiber
Connector type
FC
ST
Fibre type
Single mode
Multi mode
Wave length
1310nm
1550nm
850nm
Max. transmission distance
60km
110km
2km
Transmission power
-11.0dBm ~ -7.0dBm
-5.0dBm ~ 0dBm
-20dBm ~ -12dBm
Minimum receiving power
Min. -36dBm
Min. -36dBm
Min. -30dBm
2.4.3.4 For Synchronization Port
Characteristic
Glass optical fiber
Connector type
ST
Fibre type
Multi mode
Wave length
850nm
Minimum receiving power
Min. -25.0dBm
Margin
Min +3.0dB
2.4.4 Print Port
Type
RS-232
Baud Rate
4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Printer type
EPSON® 300K printer
Safety level
Isolation to ELV level
2.4.5 Clock Synchronization Port
Type
RS-485
Max. transmission distance
500m
Maximal capacity
32
Timing standard
PPS, IRIG-B
Safety level
Isolation to ELV level
2.5 Type Tests
2.5.1 Environmental Tests
Dry cold test
IEC60068-2-1:2007
Dry heat test
IEC60068-2-2:2007
Damp heat test, cyclic
IEC60068-2-30:2005
PCS-902 Line Distance Relay
2-5
Date: 2019-03-01
2 Technical Data
2.5.2 Mechanical Tests
Vibration
IEC 60255-21-1:1988 Class Ⅰ
Shock and bump
IEC 60255-21-2:1988 Class Ⅰ
2.5.3 Electrical Tests
Standard
IEC 60255-27:2013
Dielectric tests
Test voltage 2kV, 50Hz, 1min
Impulse voltage tests
Test voltage 5kV
Overvoltage category
Ⅲ
Insulation
resistance
measurements
Isolation resistance >100MΩ@500VDC
2.5.4 Electromagnetic Compatibility
IEC 60255-26:2013
1MHz burst disturbance test
Common mode: class Ⅲ 2.5kV
Differential mode: class Ⅲ 1.0kV
IEC 60255-26:2013 class Ⅳ
Electrostatic discharge test
For contact discharge: 8kV
For air discharge: 15kV
IEC 60255-26:2013 class Ⅲ
Frequency sweep
Radiated amplitude-modulated
10V/m (rms), f=80~1000MHz
Radio frequency interference tests
Spot frequency
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
Radiated pulse-modulated
10V/m (rms), f=900MHz
IEC 60255-26:2013
Fast transient disturbance tests
Power supply, I/O, Earth: class Ⅳ, 4kV, 2.5kHz, 5/50ns
Communication terminals: class Ⅳ, 2kV, 5kHz, 5/50ns
IEC 60255-26:2013
Surge immunity test
Power supply, AC input, I/O port: class Ⅳ, 1.2/50us
Common mode: 4kV
Differential mode: 2kV
Conducted
RF
Electromagnetic
Disturbance
IEC 60255-26:2013
Power supply, AC, I/O, Comm. Terminal: Class Ⅲ , 10Vrms, 150
kHz~80MHz
Power Frequency Magnetic Field
IEC 61000-4-8:2001
Immunity
class Ⅴ, 100A/m for 1min, 1000A/m for 3s
Pulse Magnetic Field Immunity
Damped oscillatory magnetic field
IEC 61000-4-9:2001
class Ⅴ, 6.4/16μs, 1000A/m for 3s
IEC 61000-4-10:2001
PCS-902 Line Distance Relay
2-6
Date: 2019-03-01
2 Technical Data
immunity
class Ⅴ, 100kHz & 1MHz–100A/m
Auxiliary power supply performance
IEC 60255-26:2013
- Voltage dips
Up to 200ms for dips to 40% of rated voltage without reset
-Voltage short interruptions
100ms for interruption without rebooting
2.6 Certifications

ISO9001:2008

ISO14001:2004

OHSAS18001:2007

ISO10012:2003

CMMI L5

EMC: 2014/30/EU, EN60255-26:2013

Products safety (LVD): 2014/35/EU, EN60255-27:2014
2.7 Terminals
Connection Type
Wire Size
Screw Type
2
AC current
Screw terminals, 2.5mm lead
2
AC voltage
Screw terminals, 1.5mm lead
Power supply
0.6~1.3N·m
M3
0.6~1.3N·m
2
M2.5
0.3~0.6N·m
2
2
M2.5
0.3~0.6N·m
M4
1.6~1.8N·m
Screw terminals, 1.0mm ~2.5mm lead
Grounding (Earthing) Connection
M3
2
Screw terminals, 1.0mm ~2.5mm lead
Contact I/O
Torque
2
BVR type, 2.5mm²~6.0mm lead
2.8 Measurement Scope and Accuracy
Item
Range
Accuracy
Phase range
0°~ 360°
≤±3°
Frequency
fn±3 Hz
≤ 0.02Hz
Currents from protection measurement current transformers
Current
0.05~5.00In
Voltage
0.05~1.50Un
Active power (W)
Reactive power (VAr)
Apparent power (VA)
Energy (Wh)
≤ 2.0% of rating (0.05~1.00In)
≤ 2.0% of applied quantities (1.00~5.00In)
≤ 1.0% of rating (0.05~1.00Un)
≤ 1.0% of applied quantities (1.00~1.50Un)
0.05~1.50Un
≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
0.05~5.00In
≤ 3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)
0.05~1.50Un
≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
0.05~5.00In
≤ 3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)
0.05~1.50Un
≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
0.05~5.00In
≤ 3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)
0.05~1.50Un
≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
0.05~5.00In
≤ 3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)
PCS-902 Line Distance Relay
2-7
Date: 2019-03-01
2 Technical Data
Energy (VAh)
0.05~1.50Un
≤ 3.0% of rating (0.05~1.00In, 0.05~1.00Un)
0.05~5.00In
≤ 3.0% of applied quantities (1.00~5.00In, 1.00~1.50Un)
2.9 Management Function
2.9.1 Control Performance
Control mode
Local or remote
Accuracy of local control
≤ 1s
Accuracy of remote control
≤ 3s
2.9.2 Clock Performance
Real time clock accuracy
≤ 3s/day
Accuracy of GPS synchronization
≤ 1ms
External time synchronization
IRIG-B (200-98), PPS, IEEE1588 or SNTP protocol
2.9.3 Fault and Disturbance Recording
Maximum duration
10000 sampled points (24 sampled points per cycle)
Recording position
10 cycles before pickup of trigger element
2.9.4 Binary Input Signal
Resolution of binary input signal
≤1ms
Binary input mode
Potential-free contact
2.10 Protective Functions
2.10.1 Fault Detector
2.10.1.1 DPFC Current Element
Setting range
0.050In~30.000In (A)
Accuracy
≤2.5% of setting or 0.02In, whichever is greater
2.10.1.2 Residual Current Element
Setting range
0.050In~30.000In (A)
Accuracy
≤2.5% of setting or 0.02In, whichever is greater
2.10.1.3 Overvoltage Element
Setting range
Un~2Unn (V)
Accuracy
≤2.5% of setting or 0.01Un, whichever is greater
2.10.2 Distance Protection
Setting range
(0.000~4Unn)/In (ohm)
Accuracy
≤2.5% of setting or 0.1Ω/In, whichever is greater
Resetting ratio
105%
PCS-902 Line Distance Relay
2-8
Date: 2019-03-01
2 Technical Data
Time delay
0.000~10.000 (s)
Accuracy
≤1%×Setting+30ms
2.10.3 Phase Overcurrent Protection
Setting range
0.050In~30.000In (A)
Accuracy
≤2.5% of setting or 0.02In, whichever is greater
Resetting ratio
97%
Time delay
0.000~20.000 (s)
Accuracy (definite-time characteristic)
≤1%×Setting+30ms (at 2 times current setting)
Accuracy (inverse-time characteristic)
≤5% of operating time or 30ms, whichever is greater
(for current between 1.2 and 20 multiples of pickup)
2.10.4 Earth Fault Protection
Setting range
0.050In~30.000In (A)
Accuracy
≤2.5% of setting or 0.02In, whichever is greater
Resetting ratio
97%
Time delay
0.000~20.000 (s)
Accuracy (definite-time characteristic)
≤1%×Setting+30ms (at 2 times current setting)
Accuracy (inverse-time characteristic)
≤5% of operating time or 30ms, whichever is greater
(for current between 1.2 and 20 multiples of pickup)
2.10.5 Negative-sequence Overcurrent Protection
Setting range
0.050In~30.000In (A)
Accuracy
≤2.5% of setting or 0.02In, whichever is greater
Resetting ratio
97%
Time delay
0.000~20.000 (s)
Accuracy (definite-time characteristic)
≤1%×Setting+30ms (at 2 times current setting)
Accuracy (inverse-time characteristic)
≤2.5% of operating time or 30ms, whichever is greater
(for current between 1.2 and 20 multiples of pickup)
2.10.6 Overvoltage Protection
Setting range
Un~2Unn (V)
Accuracy
≤2.5% of setting or 0.01Un, whichever is greater
Resetting ratio
98%
Time delay
0.000~30.000 (s)
Accuracy (definite-time characteristic)
≤1%×Setting+30ms (at 1.2 times voltage setting)
Accuracy (inverse-time characteristic)
≤2.5% of operating time or 30ms, whichever is greater
(for voltage between 1.2 and 2 multiples of pickup)
2.10.7 Negative-sequence Overvoltage Protection
Setting range
0~Un (V)
Accuracy
≤2.5% of setting or 0.01Un, whichever is greater
Resetting ratio
95%
PCS-902 Line Distance Relay
2-9
Date: 2019-03-01
2 Technical Data
Time delay
0.000~30.000 (s)
Accuracy (definite-time characteristic)
≤1%×Setting+30ms (at 1.2 times voltage setting)
2.10.8 Residual Overvoltage Protection
Setting range
0~2Unn (V)
Accuracy
≤2.5% of setting or 0.1V, whichever is greater
Resetting ratio
95%
Time delay
0.000~3600.000 (s)
Accuracy (definite-time characteristic)
≤1%×Setting+30ms (at 1.2 times voltage setting)
≤2.5% of operating time or 30ms, whichever is greater
Accuracy (inverse-time characteristic)
(for residual voltage between 1.2 and 2 multiples of
pickup)
2.10.9 Undervoltage Protection
Setting range
0~Unn (V)
Accuracy
≤2.5% of setting or 0.01Un, whichever is greater
Resetting ratio
102%
Time delay
0.000~30.000 (s)
Accuracy (definite-time characteristic)
≤1%×Setting+30ms (at 0.8 times voltage setting)
Accuracy (inverse-time characteristic)
≤2.5% of operating time or 30ms, whichever is greater
(for voltage between 0.5 and 0.8 multiples of pickup)
2.10.10 Overfrequency Protection
Setting range
50.00~65.00 (Hz)
Accuracy
≤ 0.02Hz
Resetting value
Setting-0.05Hz
Time delay
0.000~100.000 (s)
Accuracy
≤1%×Setting+30ms (at 1.2 times frequency setting)
2.10.11 Underfrequency Protection
Setting range
45.00~60.00 (Hz)
Accuracy
≤ 0.02Hz
Resetting value
Setting+0.05Hz
Time delay
0.000~100.000 (s)
Accuracy
≤1%×Setting+30ms (at 0.8 times frequency setting)
df/dt blocking setting range
0.200~20.000 (Hz/s)
Accuracy
≤ 0.02Hz/s
2.10.12 Breaker Failure Protection
Pick-up time
<25ms
Drop-off time
<20ms
Setting range of phase current
0.050In~30.000In (A)
Setting range of zero-sequence current
0.050In~30.000In (A)
PCS-902 Line Distance Relay
2-10
Date: 2019-03-01
2 Technical Data
Setting range of negative-sequence current
0.050In~30.000In (A)
Accuracy
≤2.5% of setting or 0.02In, whichever is greater
Time delay (first)
0.000~10.000 (s)
Time delay (second)
0.000~10.000 (s)
2.10.13 Thermal Overload Protection
Base current setting range
0.050In~30.000In (A)
Accuracy
≤2.5% of setting or 0.02In, whichever is greater
Line thermal time constant
0.100~100.000 (min)
Thermal overload coefficient for trip
1.000~3.000
Thermal overload coefficient for alarm
1.000~3.000
Resetting ratio
95%
Drop-off time
<30ms
≤2.5% of operating time or 30ms, whichever is greater
Time accuracy
(for current between 1.2 and 20 multiples of pickup)
2.10.14 Stub Differential Protection
Setting range
0.050In~30.000In (A)
Accuracy
≤2.5% of setting or 0.02In, whichever is greater
Resetting ratio
95%
Time delay
0.000~10.000 (s)
Accuracy
≤1%×Setting+30ms (at 2 times current setting)
2.10.15 Dead Zone Protection
Setting range
0.050In~30.000In
Accuracy
≤2.5% of setting or 0.02In, whichever is greater
Resetting ratio
95%
Time delay
0.000~10.000s
Accuracy
≤1%×Setting+30ms
2.10.16 Pole Discrepancy Protection
Setting range (zero-sequence current)
0.050In~30.000In (A)
Setting range (negative-sequence current)
0.050In~30.000In (A)
Accuracy
≤2.5% of setting or 0.02In, whichever is greater
Resetting ratio
95%
Time delay
0.000~600.000 (s)
Accuracy
≤1%×Setting+30ms (at 2 times current setting)
2.10.17 Broken Conductor Protection
Setting range (I2/I1)
0.20~1.00
Accuracy
≤2.5% of setting
Resetting ratio
95%
Time delay
0.000~600.000 (s)
PCS-902 Line Distance Relay
2-11
Date: 2019-03-01
2 Technical Data
Accuracy
≤1%×Setting+30ms
2.10.18 Reverse Power Protection
Setting range
0.100In~50.000In
Accuracy
≤2% of setting or 0.5W, whichever is greater
Resetting ratio
95%
Time delay
0.010~300.000 (s)
Accuracy
≤1%×Setting+30ms
2.10.19 Auto-reclosing
Phase difference setting range
0~89 (Deg)
Accuracy
2.0Deg
Voltage difference setting range
0.02Un~0.8Un (V)
Accuracy
Max(0.01Un, 2.5%)
Frequency difference setting range
0.02~1 (Hz)
Accuracy
0.01Hz
Operating time of synchronism check
≤1%×Setting+20ms
Operating time of energizing check
≤1%×Setting+20ms
Operating time of auto-reclosing
≤1%×Setting+20ms
2.10.20 Transient Overreach
Tolerance for all high-speed protection
≤2%
2.10.21 Fault Locator
Accuracy for multi-phase faults with single end feed
< ±2.5%
Tolerance will be higher in case of single-phase fault with high ground resistance.
PCS-902 Line Distance Relay
2-12
Date: 2019-03-01
3 Operation Theory
3 Operation Theory
Table of Contents
3 Operation Theory .............................................................................. 3-a
3.1 System Parameters ......................................................................................... 3-1
3.1.1 General Application.............................................................................................................. 3-1
3.1.2 Function Description ............................................................................................................ 3-1
3.1.3 Settings ................................................................................................................................ 3-1
3.2 Line Parameters .............................................................................................. 3-2
3.2.1 General Application.............................................................................................................. 3-2
3.2.2 Function Description ............................................................................................................ 3-2
3.2.3 Settings ................................................................................................................................ 3-2
3.3 Frequency Calculation.................................................................................... 3-2
3.3.1 General Application.............................................................................................................. 3-2
3.3.2 Function Description ............................................................................................................ 3-3
3.3.3 Function Block Diagram ...................................................................................................... 3-3
3.3.4 I/O Signal ............................................................................................................................. 3-3
3.3.5 Logic .................................................................................................................................... 3-4
3.4 Circuit Breaker Position Supervision ............................................................ 3-4
3.4.1 General Application.............................................................................................................. 3-4
3.4.2 Function Description ............................................................................................................ 3-4
3.4.3 Function Block Diagram ...................................................................................................... 3-4
3.4.4 I/O Signals ........................................................................................................................... 3-5
3.4.5 Logic .................................................................................................................................... 3-6
3.4.6 Settings ................................................................................................................................ 3-8
3.5 Fault Detector (FD) .......................................................................................... 3-8
3.5.1 Application............................................................................................................................ 3-8
3.5.2 Fault Detector in Fault Detector DSP .................................................................................. 3-9
3-a
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
3.5.3 Protection Fault Detector in Protection Calculation DSP .................................................. 3-12
3.5.4 Function Block Diagram .................................................................................................... 3-13
3.5.5 I/O Signals ......................................................................................................................... 3-13
3.5.6 Logic .................................................................................................................................. 3-13
3.5.7 Settings .............................................................................................................................. 3-13
3.6 Auxiliary Element .......................................................................................... 3-14
3.6.1 General Application............................................................................................................ 3-14
3.6.2 Function Description .......................................................................................................... 3-14
3.6.3 Function Block Diagram .................................................................................................... 3-16
3.6.4 I/O Signals ......................................................................................................................... 3-17
3.6.5 Logic .................................................................................................................................. 3-18
3.6.6 Settings .............................................................................................................................. 3-21
3.7 Distance Protection....................................................................................... 3-22
3.7.1 General Application............................................................................................................ 3-22
3.7.2 Function Description .......................................................................................................... 3-22
3.7.3 DPFC Distance Protection ................................................................................................. 3-30
3.7.4 Load Encroachment........................................................................................................... 3-34
3.7.5 Mho Distance Protection.................................................................................................... 3-36
3.7.6 Quadrilateral Distance Protection ...................................................................................... 3-48
3.7.7 Pilot Distance Zone ............................................................................................................ 3-55
3.7.8 Out-of-step Protection........................................................................................................ 3-58
3.7.9 Power Swing Blocking Releasing ...................................................................................... 3-65
3.7.10 Distance SOTF Protection ............................................................................................... 3-72
3.8 Optical Pilot Channel (Option) ..................................................................... 3-80
3.8.1 General Application............................................................................................................ 3-80
3.8.2 Function Description .......................................................................................................... 3-80
3.8.3 Function Block Diagram .................................................................................................... 3-86
3.8.4 I/O Signals ......................................................................................................................... 3-86
3.8.5 Logic .................................................................................................................................. 3-87
3.8.6 Settings .............................................................................................................................. 3-87
3-b
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
3.9 Pilot Distance Protection .............................................................................. 3-88
3.9.1 General Application............................................................................................................ 3-88
3.9.2 Function Description .......................................................................................................... 3-88
3.9.3 Function Block Diagram .................................................................................................. 3-104
3.9.4 I/O Signals ....................................................................................................................... 3-104
3.9.5 Settings ............................................................................................................................ 3-106
3.10 Pilot Directional Earth-fault Protection ................................................... 3-107
3.10.1 General Application........................................................................................................ 3-107
3.10.2 Function Description ...................................................................................................... 3-107
3.10.3 Function Block Diagram .................................................................................................3-116
3.10.4 I/O Signals ......................................................................................................................3-116
3.10.5 Settings ...........................................................................................................................3-117
3.11 Current Direction ........................................................................................ 3-118
3.11.1 General Application .........................................................................................................3-118
3.11.2 Function Description .......................................................................................................3-119
3.11.3 Function Block Diagram ................................................................................................. 3-124
3.11.4 I/O Signals ...................................................................................................................... 3-124
3.11.5 Settings .......................................................................................................................... 3-125
3.12 Phase Overcurrent Protection ................................................................. 3-125
3.12.1 General Application........................................................................................................ 3-125
3.12.2 Function Description ...................................................................................................... 3-125
3.12.3 Function Block Diagram ................................................................................................ 3-128
3.12.4 I/O Signals ..................................................................................................................... 3-128
3.12.5 Logic .............................................................................................................................. 3-129
3.12.6 Settings .......................................................................................................................... 3-130
3.13 Earth Fault Protection............................................................................... 3-131
3.13.1 General Application........................................................................................................ 3-131
3.13.2 Function Description ...................................................................................................... 3-131
3.13.3 Function Block Diagram ................................................................................................ 3-134
3.13.4 I/O Signals ..................................................................................................................... 3-134
3-c
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
3.13.5 Logic .............................................................................................................................. 3-135
3.13.6 Settings .......................................................................................................................... 3-137
3.14 Negative-sequence Overcurrent Protection ........................................... 3-139
3.14.1 General Application........................................................................................................ 3-139
3.14.2 Function Description ...................................................................................................... 3-139
3.14.3 Function Block Diagram ................................................................................................ 3-142
3.14.4 I/O Signals ..................................................................................................................... 3-142
3.14.5 Logic .............................................................................................................................. 3-143
3.14.6 Settings .......................................................................................................................... 3-144
3.15 Overcurrent Protection for VT Circuit Failure......................................... 3-146
3.15.1 General Application........................................................................................................ 3-146
3.15.2 Function Description ...................................................................................................... 3-146
3.15.3 Function Block Diagram ................................................................................................ 3-148
3.15.4 I/O Signals ..................................................................................................................... 3-148
3.15.5 Logic .............................................................................................................................. 3-149
3.15.6 Settings .......................................................................................................................... 3-150
3.16 Phase Current SOTF Protection .............................................................. 3-152
3.16.1 General Application........................................................................................................ 3-152
3.16.2 Function Description ...................................................................................................... 3-152
3.16.3 Function Block Diagram ................................................................................................ 3-153
3.16.4 I/O Signals ..................................................................................................................... 3-153
3.16.5 Logic .............................................................................................................................. 3-154
3.16.6 Settings .......................................................................................................................... 3-155
3.17 Residual Current SOTF Protection .......................................................... 3-156
3.17.1 General Application........................................................................................................ 3-156
3.17.2 Function Description ...................................................................................................... 3-156
3.17.3 Function Block Diagram ................................................................................................ 3-157
3.17.4 I/O Signals ..................................................................................................................... 3-157
3.17.5 Logic .............................................................................................................................. 3-158
3.17.6 Settings .......................................................................................................................... 3-158
3-d
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
3.18 Voltage Protection ..................................................................................... 3-158
3.18.1 Overvoltage Protection .................................................................................................. 3-159
3.18.2 Negative-sequence Overvoltage Protection .................................................................. 3-165
3.18.3 Residual Overvoltage Protection ................................................................................... 3-166
3.18.4 Undervoltage Protection ................................................................................................ 3-171
3.19 Frequency Protection ............................................................................... 3-178
3.19.1 Overfrequency Protection .............................................................................................. 3-178
3.19.2 Underfrequency Protection ............................................................................................ 3-180
3.20 Breaker Failure Protection ....................................................................... 3-183
3.20.1 General Application........................................................................................................ 3-183
3.20.2 Function Description ...................................................................................................... 3-183
3.20.3 Function Block Diagram ................................................................................................ 3-184
3.20.4 I/O Signals ..................................................................................................................... 3-185
3.20.5 Logic .............................................................................................................................. 3-186
3.20.6 Settings .......................................................................................................................... 3-187
3.21 Thermal Overload Protection ................................................................... 3-188
3.21.1 General Application........................................................................................................ 3-188
3.21.2 Function Description ...................................................................................................... 3-188
3.21.3 Function Block Diagram ................................................................................................ 3-189
3.21.4 I/O Signals ..................................................................................................................... 3-189
3.21.5 Logic .............................................................................................................................. 3-190
3.21.6 Settings .......................................................................................................................... 3-190
3.22 Stub Differential Protection ...................................................................... 3-191
3.22.1 General Application........................................................................................................ 3-191
3.22.2 Function Description ...................................................................................................... 3-191
3.22.3 Function Block Diagram ................................................................................................ 3-192
3.22.4 I/O Signals ..................................................................................................................... 3-193
3.22.5 Logic .............................................................................................................................. 3-193
3.22.6 Settings .......................................................................................................................... 3-194
3.23 Dead Zone Protection ............................................................................... 3-195
3-e
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
3.23.1 General Application........................................................................................................ 3-195
3.23.2 Function Description ...................................................................................................... 3-195
3.23.3 Function Block Diagram ................................................................................................ 3-196
3.23.4 I/O Signal ....................................................................................................................... 3-196
3.23.5 Logic .............................................................................................................................. 3-197
3.23.6 Settings .......................................................................................................................... 3-197
3.24 Pole Discrepancy Protection .................................................................... 3-197
3.24.1 General Application........................................................................................................ 3-197
3.24.2 Function Description ...................................................................................................... 3-198
3.24.3 Function Block Diagram ................................................................................................ 3-198
3.24.4 I/O Signals ..................................................................................................................... 3-198
3.24.5 Logic .............................................................................................................................. 3-198
3.24.6 Settings .......................................................................................................................... 3-199
3.25 Broken Conductor Protection .................................................................. 3-200
3.25.1 General Application........................................................................................................ 3-200
3.25.2 Function Description ...................................................................................................... 3-200
3.25.3 Function Block Diagram ................................................................................................ 3-201
3.25.4 I/O Signals ..................................................................................................................... 3-201
3.25.5 Logic .............................................................................................................................. 3-201
3.25.6 Settings .......................................................................................................................... 3-202
3.26 Reverse Power Protection ........................................................................ 3-202
3.26.1 General Application........................................................................................................ 3-202
3.26.2 Function Description ...................................................................................................... 3-202
3.26.3 Function Block Diagram ................................................................................................ 3-203
3.26.4 I/O Signals ..................................................................................................................... 3-203
3.26.5 Logic .............................................................................................................................. 3-204
3.26.6 Settings .......................................................................................................................... 3-205
3.27 Synchrocheck............................................................................................ 3-205
3.27.1 General Application........................................................................................................ 3-205
3.27.2 Function Description ...................................................................................................... 3-205
3-f
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
3.27.3 Function Block Diagram ................................................................................................ 3-214
3.27.4 I/O Signals ..................................................................................................................... 3-215
3.27.5 Logic .............................................................................................................................. 3-216
3.27.6 Settings .......................................................................................................................... 3-219
3.28 Automatic Reclosure ................................................................................ 3-221
3.28.1 General Application........................................................................................................ 3-221
3.28.2 Function Description ...................................................................................................... 3-221
3.28.3 Function Block Diagram ................................................................................................ 3-223
3.28.4 I/O Signals ..................................................................................................................... 3-223
3.28.5 Logic .............................................................................................................................. 3-225
3.28.6 Settings .......................................................................................................................... 3-237
3.29 Transfer Trip .............................................................................................. 3-239
3.29.1 General Application........................................................................................................ 3-239
3.29.2 Function Description ...................................................................................................... 3-239
3.29.3 Function Block Diagram ................................................................................................ 3-239
3.29.4 I/O Signals ..................................................................................................................... 3-240
3.29.5 Logic .............................................................................................................................. 3-240
3.29.6 Settings .......................................................................................................................... 3-240
3.30 Trip Logic ................................................................................................... 3-241
3.30.1 General Application........................................................................................................ 3-241
3.30.2 Function Description ...................................................................................................... 3-241
3.30.3 Function Block Diagram ................................................................................................ 3-241
3.30.4 I/O Signals ..................................................................................................................... 3-242
3.30.5 Logic .............................................................................................................................. 3-242
3.30.6 Settings .......................................................................................................................... 3-248
3.31 VT Circuit Supervision .............................................................................. 3-248
3.31.1 General Application........................................................................................................ 3-248
3.31.2 Function Description ...................................................................................................... 3-249
3.31.3 Function Block Diagram ................................................................................................ 3-249
3.31.4 I/O Signals ..................................................................................................................... 3-249
3-g
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
3.31.5 Logic .............................................................................................................................. 3-250
3.31.6 Settings .......................................................................................................................... 3-251
3.32 CT Circuit Supervision ............................................................................. 3-251
3.32.1 General Application........................................................................................................ 3-251
3.32.2 Function Description ...................................................................................................... 3-252
3.32.3 Function Block Diagram ................................................................................................ 3-252
3.32.4 I/O Signals ..................................................................................................................... 3-252
3.32.5 Logic .............................................................................................................................. 3-252
3.33 Control and Synchrocheck for Manual Closing ..................................... 3-252
3.33.1 General Application........................................................................................................ 3-252
3.33.2 Function Description ...................................................................................................... 3-253
3.33.3 Function Block Diagram ................................................................................................ 3-264
3.33.4 I/O Signals ..................................................................................................................... 3-265
3.33.5 Settings .......................................................................................................................... 3-266
3.34 Faulty Phase Selection ............................................................................. 3-270
3.34.1 General Application........................................................................................................ 3-270
3.34.2 Function Description ...................................................................................................... 3-270
3.34.3 Function Block Diagram ................................................................................................ 3-273
3.34.4 I/O Signals ..................................................................................................................... 3-273
3.35 Fault Location............................................................................................ 3-274
3.35.1 Application...................................................................................................................... 3-274
3.35.2 Function Description ...................................................................................................... 3-274
3.35.3 Function Block Diagram ................................................................................................ 3-277
3.35.4 I/O Signals ..................................................................................................................... 3-278
List of Figures
Figure 3.3-1 Logic diagram of frequency calculation.............................................................. 3-4
Figure 3.4-1 Logic diagram of CB position supervision ......................................................... 3-6
Figure 3.4-2 Logic diagram of trip&closing circuit supervision ............................................ 3-7
Figure 3.4-3 Logic diagram of circuit breaker position ........................................................... 3-7
3-h
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
Figure 3.4-4 Logic diagram of pole open states ...................................................................... 3-8
Figure 3.5-1 Flow chart of protection program ...................................................................... 3-12
Figure 3.5-2 Logic diagram of fault detector .......................................................................... 3-13
Figure 3.6-1 Logic diagram of auxiliary element (ROC) ........................................................ 3-18
Figure 3.6-2 Logic diagram of auxiliary element (ROV) ........................................................ 3-18
Figure 3.6-3 Logic diagram of auxiliary element (OC)........................................................... 3-19
Figure 3.6-4 Logic diagram of auxiliary element (UVG) ........................................................ 3-19
Figure 3.6-5 Logic diagram of auxiliary element (UVS)......................................................... 3-20
Figure 3.6-6 Logic diagram of auxiliary element (UVD) ........................................................ 3-20
Figure 3.6-7 Logic diagram of auxiliary element (OCD) ........................................................ 3-20
Figure 3.6-8 Logic diagram of auxiliary element (Startup) ................................................... 3-21
Figure 3.7-1 Operating time of single-phase fault (50Hz, SIR=1) ......................................... 3-25
Figure 3.7-2 Operating time of single-phase fault (60Hz, SIR=1) ......................................... 3-25
Figure 3.7-3 Operating time of two-phase fault (50Hz, SIR=1) ............................................. 3-26
Figure 3.7-4 Operating time of two-phase fault (60Hz, SIR=1) ............................................. 3-26
Figure 3.7-5 Operating time of three-phase fault (50Hz, SIR=1) ........................................... 3-27
Figure 3.7-6 Operating time of three-phase fault (60Hz, SIR=1) ........................................... 3-27
Figure 3.7-7 Operating time of single-phase fault (50Hz, SIR=30) ....................................... 3-28
Figure 3.7-8 Operating time of single-phase fault (60Hz, SIR=30) ....................................... 3-28
Figure 3.7-9 Operating time of two-phase fault (50Hz, SIR=30) ........................................... 3-29
Figure 3.7-10 Operating time of two-phase fault (60Hz, SIR=30) ......................................... 3-29
Figure 3.7-11 Operating time of three-phase fault (50Hz, SIR=30) ....................................... 3-30
Figure 3.7-12 Operating time of three-phase fault (60Hz, SIR=30) ....................................... 3-30
Figure 3.7-13 Operation characteristic for forward fault....................................................... 3-31
Figure 3.7-14 Operation characteristic for reverse fault ....................................................... 3-32
Figure 3.7-15 Logic diagram of DPFC distance protection................................................... 3-33
Figure 3.7-16 Distance element with load trapezoid.............................................................. 3-34
Figure 3.7-17 Phase-to-ground operation characteristic for forward fault ......................... 3-36
Figure 3.7-18 Operation Characteristic of quadrilateral distance element ......................... 3-38
Figure 3.7-19 Phase-to-phase operation characteristic for forward fault ........................... 3-38
3-i
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
Figure 3.7-20 Operation characteristic for reverse fault ....................................................... 3-39
Figure 3.7-21 Steady-state characteristic of three-phase short-circuit fault ...................... 3-40
Figure 3.7-22 Operation characteristic of three-phase close up short-circuit fault........... 3-40
Figure 3.7-23 Shift impedance characteristic of zone 1 and zone 2 .................................... 3-41
Figure 3.7-24 Logic diagram of enabling distance protection (Mho)................................... 3-43
Figure 3.7-25 Logic diagram of distance protection (Mho zone 1) ...................................... 3-44
Figure 3.7-26 Logic diagram of distance protection (Mho zone i) ....................................... 3-45
Figure 3.7-27 Quadrilateral forward distance element characteristics ............................... 3-48
Figure 3.7-28 Quadrilateral reverse distance element characteristic .................................. 3-49
Figure 3.7-29 Logic diagram of enabling distance protection (Quad) ................................. 3-51
Figure 3.7-30 Logic diagram of distance protection (Quad zone 1) .................................... 3-51
Figure 3.7-31 Logic diagram of distance protection (Quad zone i) ..................................... 3-53
Figure 3.7-32 Protected zone of pilot distance protection.................................................... 3-55
Figure 3.7-33 Pilot reverse weak infeed element ................................................................... 3-56
Figure 3.7-34 Logic diagram of pilot distance zone (Mho characteristic) ........................... 3-56
Figure 3.7-35 Logic diagram of pilot distance zone (Quad characteristic) ......................... 3-57
Figure 3.7-36 Dual-machine equivalent system ..................................................................... 3-59
Figure 3.7-37 Dual-machine equivalent system ..................................................................... 3-59
Figure 3.7-38 Variation curve of oscillation center voltage .................................................. 3-61
Figure 3.7-39 The variation rule of oscillation center voltage .............................................. 3-61
Figure 3.7-40 Vector diagram of the oscillation center voltage ........................................... 3-62
Figure 3.7-41 Operation characteristic of zone detector element........................................ 3-63
Figure 3.7-42 Logic diagram of out-of-step protection ......................................................... 3-64
Figure 3.7-43 Logic diagram of PSBR ..................................................................................... 3-71
Figure 3.7-44 Logic diagram of enabling distance SOTF protection ................................... 3-73
Figure 3.7-45 Logic diagram of manual closing signal ......................................................... 3-74
Figure 3.7-46 Logic diagram of manual closing signal ......................................................... 3-75
Figure 3.7-47 Logic diagram of distance SOTF protection by manual closing signal ...... 3-76
Figure 3.7-48 Logic diagram of distance SOTF protection by 1-pole or 3-pole AR ........... 3-77
Figure 3.7-49 Logic diagram of distance SOTF protection by PD condition ...................... 3-78
3-j
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
Figure 3.7-50 Logic diagram of distance SOTF protection ................................................... 3-78
Figure 3.8-1 Direct optical link up to 2km with 850nm .......................................................... 3-81
Figure 3.8-2 Direct optical link up to 60km with1310nm or 110km with 1550nm ............... 3-81
Figure 3.8-3 Connect to a communication network via communication convertor........... 3-82
Figure 3.8-4 Connect to a communication network via MUX-64 .......................................... 3-82
Figure 3.8-5 Connect to a communication network via MUX-2M ......................................... 3-83
Figure 3.8-6 Schematic diagram of communication channel time ...................................... 3-85
Figure 3.8-7 Logic diagram of receiving signal i.................................................................... 3-87
Figure 3.9-1 Enabling/disabling logic of pilot distance protection ...................................... 3-89
Figure 3.9-2 Logic diagram of receiving signal...................................................................... 3-90
Figure 3.9-3 Zone extension ..................................................................................................... 3-91
Figure 3.9-4 Simple schematic of PUTT .................................................................................. 3-92
Figure 3.9-5 Logic diagram of pilot distance protection (PUTT) .......................................... 3-93
Figure 3.9-6 Simple schematic of POTT.................................................................................. 3-94
Figure 3.9-7 Logic diagram of pilot distance protection (POTT) .......................................... 3-96
Figure 3.9-8 Simple schematic of system fault ...................................................................... 3-97
Figure 3.9-9 Simple schematic of blocking ............................................................................ 3-97
Figure 3.9-10 Logic diagram of pilot distance protection (Blocking) .................................. 3-98
Figure 3.9-11 Logic diagram of pilot distance protection (Unblocking) .............................. 3-99
Figure 3.9-12 Current reversal ................................................................................................. 3-99
Figure 3.9-13 Logic diagram of current reversal blocking.................................................. 3-100
Figure 3.9-14 Line fault description ....................................................................................... 3-101
Figure 3.9-15 Weak infeed logic during pickup .................................................................... 3-102
Figure 3.9-16 Weak infeed echo logic without pickup ........................................................ 3-102
Figure 3.9-17 Weak infeed trip logic without pickup ........................................................... 3-103
Figure 3.9-18 Simplified CB echo logic for POTT ................................................................ 3-103
Figure 3.10-1 Enabling/disabling logic of pilot directional earth-fault protection ........... 3-108
Figure 3.10-2 Logic diagram of receiving signal.................................................................. 3-108
Figure 3.10-3 Forward/reverse direction of zero-sequence power .................................... 3-108
Figure 3.10-4 Simple schematic of DEF (permissive scheme) ........................................... 3-109
3-k
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
Figure 3.10-5 Logic diagram of DEF (permissive scheme) ................................................. 3-110
Figure 3.10-6 Simple schematic of blocking .........................................................................3-111
Figure 3.10-7 Logic diagram of DEF (Blocking scheme) .................................................... 3-112
Figure 3.10-8 Logic diagram for unblocking ........................................................................ 3-113
Figure 3.10-9 Current reversal ............................................................................................... 3-114
Figure 3.10-10 Logic diagram of current reversal blocking ............................................... 3-114
Figure 3.10-11 Simplified CB Echo logic for POTT .............................................................. 3-115
Figure 3.11-1 Line fault description ....................................................................................... 3-118
Figure 3.11-2 Vector diagram of current and voltage .......................................................... 3-119
Figure 3.11-3 Vector diagram of zero-sequence power....................................................... 3-121
Figure 3.12-1 Logic diagram of phase overcurrent protection .......................................... 3-129
Figure 3.13-1 Logic diagram of stage 1 of earth fault protection ....................................... 3-135
Figure 3.13-2 Logic diagram of stage i of earth fault protection ........................................ 3-136
Figure 3.14-1 Logic diagram of stage i of negative-sequence overcurrent protection ... 3-143
Figure 3.14-2 Logic diagram of stage 4 of negative-sequence overcurrent protection .. 3-144
Figure 3.15-1 Logic diagram of overcurrent protection for VT circuit failure................... 3-150
Figure 3.16-1 Logic diagram of phase current SOTF protection ....................................... 3-154
Figure 3.17-1 Logic diagram of residual current SOTF protection .................................... 3-158
Figure 3.18-1 Logic diagram of stage i of overvoltage protection ..................................... 3-163
Figure 3.18-2 Logic diagram of negative-sequence overvoltage protection .................... 3-166
Figure 3.18-3 Logic diagram of stage 1 of residual overvoltage protection ..................... 3-169
Figure 3.18-4 Logic diagram of stage 2 of residual overvoltage protection ..................... 3-169
Figure 3.18-5 Logic diagram of stage 3 of residual overvoltage protection ..................... 3-169
Figure 3.18-6 Blocking logic of undervoltage protection ................................................... 3-175
Figure 3.18-7 Enabling logic of undervoltage protection ................................................... 3-175
Figure 3.18-8 Current releasing logic of undervoltage protection ..................................... 3-175
Figure 3.18-9 Logic diagram of stage i of undervoltage protection................................... 3-176
Figure 3.19-1 Logic diagram of overfrequency protection (start) ...................................... 3-179
Figure 3.19-2 Logic diagram of stage i of overfrequency protection ................................ 3-179
Figure 3.19-3 Logic diagram of underfrequency protection (start) ................................... 3-182
3-l
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
Figure 3.19-4 Logic diagram of stage i of underfrequency protection .............................. 3-182
Figure 3.20-1 Logic diagram of breaker failure protection ................................................. 3-186
Figure 3.21-1 Characteristic curve of thermal overload model .......................................... 3-189
Figure 3.21-2 Logic diagram of stage i of thermal overload protection ............................ 3-190
Figure 3.22-1 3/2 breakers arrangement ............................................................................... 3-191
Figure 3.22-2 Logic diagram of stub differential protection ............................................... 3-194
Figure 3.23-1 Dead zone protection ...................................................................................... 3-197
Figure 3.24-1 Logic diagram of pole discrepancy protection............................................. 3-199
Figure 3.25-1 Logic diagram of broken conductor protection ........................................... 3-201
Figure 3.26-1 Logic diagram of stage 1 of reverse power protection................................ 3-204
Figure 3.26-2 Logic diagram of stage 2 of reverse power protection................................ 3-204
Figure 3.27-1 Relationship between reference voltage and synchronism voltage .......... 3-206
Figure 3.27-2 Voltage connection for single busbar arrangement..................................... 3-208
Figure 3.27-3 Voltage connection for single busbar arrangement..................................... 3-208
Figure 3.27-4 Voltage connection for double busbars arrangement ................................. 3-209
Figure 3.27-5 Voltage selection for double busbars arrangement ..................................... 3-209
Figure 3.27-6 Voltage connection for one and a half breakers arrangement ................... 3-210
Figure 3.27-7 Voltage selection for one and a half breakers arrangement ....................... 3-211
Figure 3.27-8 Voltage selection for one and a half breakers arrangement ....................... 3-212
Figure 3.27-9 Reference voltage circuit failure supervision logic ..................................... 3-213
Figure 3.27-10 Synchronism voltage circuit failure supervision logic .............................. 3-213
Figure 3.27-11 Synchrocheck mode selection ..................................................................... 3-217
Figure 3.27-12 Synchronism check ....................................................................................... 3-217
Figure 3.27-13 Dead charge check logic ............................................................................... 3-218
Figure 3.27-14 Synchrocheck logic ....................................................................................... 3-218
Figure 3.28-1 Logic diagram of AR block ............................................................................. 3-226
Figure 3.28-2 Logic diagram of AR ready ............................................................................. 3-227
Figure 3.28-3 Logic diagram of tripping condition output .................................................. 3-228
Figure 3.28-4 Single-phase tripping initiating AR ................................................................ 3-229
Figure 3.28-5 Three-phase tripping initiating AR ................................................................. 3-229
3-m
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
Figure 3.28-6 1-pole AR initiation .......................................................................................... 3-230
Figure 3.28-7 3-pole AR initiation .......................................................................................... 3-230
Figure 3.28-8 One-shot AR ..................................................................................................... 3-231
Figure 3.28-9 Extra time delay of AR ..................................................................................... 3-231
Figure 3.28-10 Reclosing output logic .................................................................................. 3-232
Figure 3.28-11 Wait to slave signal ........................................................................................ 3-232
Figure 3.28-12 Reclosing failure and success ..................................................................... 3-233
Figure 3.28-13 Single-phase transient fault .......................................................................... 3-236
Figure 3.28-14 Single-phase permanent fault ([CBx.79.N_Rcls]=2) ................................... 3-236
Figure 3.29-1 Logic diagram of transfer trip......................................................................... 3-240
Figure 3.30-1 Tripping logic.................................................................................................... 3-245
Figure 3.30-2 Breaker failure initiation logic ........................................................................ 3-246
Figure 3.30-3 Blocking AR logic ............................................................................................ 3-247
Figure 3.31-1 Logic of VT circuit supervision ...................................................................... 3-250
Figure 3.31-2 Logic of VT neutral point supervision ........................................................... 3-250
Figure 3.32-1 Logic diagram of CT circuit failure ................................................................ 3-252
Figure 3.33-1 Synchrocheck mode selection for manual closing...................................... 3-254
Figure 3.33-2 Logic diagram of closing circuit breaker 1 ................................................... 3-255
Figure 3.33-3 Logic diagram of closing circuit breaker 2 ................................................... 3-255
Figure 3.33-4 Logic diagram of closing switch (xx=02~15) ................................................ 3-256
Figure 3.33-5 Logic diagram of open circuit breaker .......................................................... 3-257
Figure 3.33-6 Logic diagram of open switch (xx=02~15) .................................................... 3-258
Figure 3.33-7 Configuration page of control output 01 (default configuration) ............... 3-260
Figure 3.33-8 Configuration page of control output 02 (default configuration) ............... 3-261
Figure 3.34-1 The region of faulty phase selection ............................................................. 3-271
Figure 3.34-2 The logic of faulty phase selection ................................................................ 3-273
Figure 3.35-1 Equivalent sequence network ........................................................................ 3-275
List of Tables
Table 3.1-1 System parameters .................................................................................................. 3-1
3-n
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
Table 3.2-1 Line parameters ....................................................................................................... 3-2
Table 3.3-1 I/O signals of frequency calculation ...................................................................... 3-3
Table 3.4-1 I/O signals of CB position supervision.................................................................. 3-5
Table 3.4-2 Internal settings of CB position supervision ........................................................ 3-8
Table 3.5-1 I/O signals of fault detector .................................................................................. 3-13
Table 3.5-2 Settings of fault detector ...................................................................................... 3-13
Table 3.6-1 I/O signals of auxiliary element ............................................................................ 3-17
Table 3.6-2 Settings of auxiliary element ................................................................................ 3-21
Table 3.7-1 I/O signals of DPFC distance protection ............................................................. 3-33
Table 3.7-2 Settings of DPFC distance protection ................................................................. 3-34
Table 3.7-3 I/O signals of load encroachment ........................................................................ 3-35
Table 3.7-4 Settings of load encroachment ............................................................................ 3-35
Table 3.7-5 I/O signals of distance protection (Mho) ............................................................. 3-42
Table 3.7-6 Settings of distance protection (Mho) ................................................................. 3-46
Table 3.7-7 I/O signals of distance protection (Quad) ........................................................... 3-50
Table 3.7-8 Settings of distance protection (Quad) ............................................................... 3-53
Table 3.7-9 Settings of pilot distance zone ............................................................................. 3-57
Table 3.7-10 I/O signals of out-of-step protection.................................................................. 3-63
Table 3.7-11 Settings of out-of-step protection ...................................................................... 3-65
Table 3.7-12 I/O signals of PSBR ............................................................................................. 3-69
Table 3.7-13 Settings of PSBR ................................................................................................. 3-72
Table 3.7-14 I/O signals of distance SOTF protection ........................................................... 3-73
Table 3.7-15 Settings of distance SOTF protection ............................................................... 3-78
Table 3.7-16 Internal settings of distance SOTF protection ................................................. 3-80
Table 3.8-1 I/O signals of pilot channel ................................................................................... 3-86
Table 3.8-2 Settings of pilot channel ....................................................................................... 3-87
Table 3.9-1 I/O signals of pilot distance protection ............................................................. 3-104
Table 3.9-2 Settings of pilot distance protection ................................................................. 3-106
Table 3.9-3 Internal settings of pilot distance protection.................................................... 3-107
Table 3.10-1 I/O signals of pilot directional earth-fault protection..................................... 3-116
3-o
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
Table 3.10-2 Settings of pilot directional earth-fault protection ......................................... 3-117
Table 3.10-3 Internal settings of pilot distance protection.................................................. 3-118
Table 3.11-1 Direction description ......................................................................................... 3-120
Table 3.11-2 I/O signals of current direction ......................................................................... 3-124
Table 3.11-3 Settings of current direction ............................................................................. 3-125
Table 3.13-1 Inverse-time curve parameters......................................................................... 3-127
Table 3.13-2 I/O signals of phase overcurrent protection ................................................... 3-128
Table 3.13-3 Settings of phase overcurrent protection ....................................................... 3-130
Table 3.14-1 Inverse-time curve parameters......................................................................... 3-133
Table 3.14-2 I/O signals of earth fault protection ................................................................. 3-134
Table 3.14-3 Settings of earth fault protection ..................................................................... 3-137
Table 3.15-1 Inverse-time curve parameters......................................................................... 3-141
Table 3.15-2 I/O signals of negative-sequence overcurrent protection............................. 3-142
Table 3.15-3 Settings of negative-sequence overcurrent protection................................. 3-144
Table 3.16-1 Inverse-time curve parameters......................................................................... 3-147
Table 3.16-2 I/O signals of overcurrent protection for VT circuit failure ........................... 3-148
Table 3.16-3 Settings of overcurrent protection for VT circuit failure ............................... 3-150
Table 3.17-1 I/O signals of residual SOTF protection .......................................................... 3-153
Table 3.17-2 Settings of phase current SOTF protection .................................................... 3-155
Table 3.16-1 I/O signals of residual SOTF protection .......................................................... 3-157
Table 3.16-2 Settings of residual current SOTF protection ................................................ 3-158
Table 3.17-1 Inverse-time curve parameters......................................................................... 3-161
Table 3.17-2 I/O signals of overvoltage protection .............................................................. 3-162
Table 3.17-3 Settings of overvoltage protection .................................................................. 3-164
Table 3.17-4 I/O signals of negative-sequence overvoltage protection ............................ 3-165
Table 3.17-5 Settings of negative-sequence overvoltage protection ................................ 3-166
Table 3.19-6 Inverse-time curve parameters of residual overvoltage protection ............. 3-167
Table 3.19-7 I/O signals of residual overvoltage protection ............................................... 3-168
Table 3.19-8 Settings of residual overvoltage protection ................................................... 3-170
Table 3.19-9 Inverse-time curve parameters of phase undervoltage protection .............. 3-173
3-p
PCS-902 Line Distance Relay
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3 Operation Theory
Table 3.19-10 I/O signals of undervoltage protection .......................................................... 3-173
Table 3.19-11 Settings of undervoltage protection .............................................................. 3-176
Table 3.18-1 I/O signals of overfrequency protection.......................................................... 3-179
Table 3.18-2 Settings of overfrequency protection.............................................................. 3-180
Table 3.18-3 I/O signals of underfrequency protection ....................................................... 3-181
Table 3.18-4 Settings of underfrequency protection ........................................................... 3-182
Table 3.21-1 I/O signals of breaker failure protection.......................................................... 3-185
Table 3.21-2 Settings of breaker failure protection.............................................................. 3-187
Table 3.20-1 I/O signals of thermal overload protection ..................................................... 3-189
Table 3.20-2 Settings of thermal overload protection ......................................................... 3-190
Table 3.21-1 I/O signals of stub differential protection ....................................................... 3-193
Table 3.21-2 Settings of stub differential protection ........................................................... 3-194
Table 3.22-1 I/O signals of dead zone protection ................................................................. 3-196
Table 3.22-2 Settings of dead zone protection ..................................................................... 3-197
Table 3.23-1 I/O signals of pole discrepancy protection ..................................................... 3-198
Table 3.23-2 Settings of pole discrepancy protection ......................................................... 3-199
Table 3.24-1 I/O signals of broken conductor protection .................................................... 3-201
Table 3.24-2 Settings of broken conductor protection ........................................................ 3-202
Table 3.25-1 I/O signals of reverse power protection .......................................................... 3-203
Table 3.25-2 Settings of broken conductor protection ........................................................ 3-205
Table 3.28-1 I/O signals of synchrocheck ............................................................................. 3-215
Table 3.28-2 Synchrocheck settings ..................................................................................... 3-219
Table 3.29-1 I/O signals of auto-reclosing ............................................................................ 3-223
Table 3.29-2 Reclosing number.............................................................................................. 3-235
Table 3.29-3 Auto-reclosing settings ..................................................................................... 3-237
Table 3.28-1 I/O signals of transfer trip ................................................................................. 3-240
Table 3.28-2 Settings of transfer trip ..................................................................................... 3-240
Table 3.29-1 I/O signals of trip logic ...................................................................................... 3-242
Table 3.29-2 Settings of trip logic .......................................................................................... 3-248
Table 3.30-1 I/O signals of VT circuit supervision ............................................................... 3-249
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PCS-902 Line Distance Relay
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3 Operation Theory
Table 3.30-2 VTS settings ....................................................................................................... 3-251
Table 3.31-1 I/O signals of CT circuit supervision ............................................................... 3-252
Table 3.32-1 I/O signals of control ......................................................................................... 3-265
Table 3.32-2 Function settings ............................................................................................... 3-266
Table 3.32-3 Synchrocheck settings ..................................................................................... 3-266
Table 3.32-4 Dual point binary input settings....................................................................... 3-269
Table 3.32-5 Control settings ................................................................................................. 3-269
Table 3.32-6 Interlock settings ............................................................................................... 3-269
Table 3.33-1 Relation between ΔUOΦMAX and faulty phase.............................................. 3-271
Table 3.33-2 I/O signals of faulty phase selection ............................................................... 3-273
Table 3.34-1 I/O signals of fault location ............................................................................... 3-278
3-r
PCS-902 Line Distance Relay
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3 Operation Theory
3.1 System Parameters
3.1.1 General Application
The device performs various protection functions by respective algorithms with the information
(currents and voltages) acquired from primary system through current transformer and voltage
transformer, so it is important to configure analog input channels correctly.
Further to correct configuration of analog input channels, other protected system information, such
as the parameters of voltage transformer and current transformer are also required.
3.1.2 Function Description
The device generally considers transmission line as its protected object, current flows from busbar
to line is considered as the forward direction.
The device uses a sampling rate of 24 samples per cycle, and the amplitudes of voltage and
current are calculated through fourier filter algorithm. The data window is 1 cycle, and the actual
amplitude can be achieved when the cycle is expired. Two cycles of pre-fault voltage are
memorized when three-phase voltage drops suddenly due to a close up symmetrical solid fault.
3.1.3 Settings
Table 3.1-1 System parameters
No.
Name
Range
Step
Unit
1
Active_Grp
1~20
1
2
Opt_SysFreq
50 or 60
3
PrimaryEquip_Name
4
U1n
10.00~65500.00
0.01
kV
5
U2n
80.00~220.00
0.01
V
6
CBx.I1n
100~30000
1
A
Remark
Active setting group
Hz
System frequency
The name of primary equipment
Primary rated value of VT (phase to
phase)
Secondary rated value of VT (phase to
phase)
Primary rated value of CT corresponding
to circuit breaker No.x
Primary calculation base rated current of
7
I1n_Base
100~30000
1
A
CT, and generally set as same as
[CB1.I1n]
8
I2n_Base
1 or 5
A
Secondary
calculation
base
rated
current of CT
Frequency upper limit setting
9
f_High_FreqAlm
50~65
1
Hz
The
device
will
issue
an
alarm
[Alm_Freq], when system frequency is
higher than the setting.
Frequency lower limit setting
10
f_Low_FreqAlm
45~60
1
Hz
The
device
will
issue
an
alarm
[Alm_Freq], when system frequency is
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PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
lower than the setting.
3.2 Line Parameters
3.2.1 General Application
When the device equips with line protection functions, line parameters of protected line are
required, especially for fault location, precise line parameters are the basic criterion for accurate
fault location.
3.2.2 Function Description
Line parameters mainly include positive-sequence reactance, positive-sequence resistance,
zero-sequence reactance, zero-sequence resistance, mutual zero-sequence reactance, mutual
zero-sequence resistance and line length.
The positive-sequence reactance, zero-sequence reactance, positive-sequence resistance and
zero-sequence resistance are the reactance and resistance value of the whole line. In general, the
device locates the fault through calculating the impedance value from the location of the device to
fault point.
3.2.3 Settings
Table 3.2-1 Line parameters
No.
Name
Range
Step
Unit
1
X1L
(0.000~4Unn)/In
0.001
ohm
2
R1L
(0.000~4Unn)/In
0.001
ohm
3
X0L
(0.000~4Unn)/In
0.001
ohm
4
R0L
(0.000~4Unn)/In
0.010
ohm
5
X0M
(0.000~4Unn)/In
0.001
ohm
6
R0M
(0.000~4Unn)/In
0.001
ohm
7
LineLength
0.00~655.35
0.01
km
Remark
Positive-sequence reactance of the whole
line (secondary value)
Positive-sequence resistance of the whole
line (secondary value)
Zero-sequence reactance of the whole line
(secondary value)
Zero-sequence resistance of the whole line
(secondary value)
Zero-sequence
mutual
reactance
(secondary value)
Zero-sequence mutual resistance of the
whole line (secondary value)
Total length of the whole line
3.3 Frequency Calculation
3.3.1 General Application
System frequency is an important parameter to characterize power system, and the measurement
and calculation of system frequency are the basis of many protection functions. The frequency
calculation module can accurately calculate the frequency of voltage component.
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3 Operation Theory
3.3.2 Function Description
The device can be applied to the power system within frequency range of 40Hz~63Hz, the
reference frequency can be set as 50Hz or 60Hz via the system setting [Opt_SysFreq].
The device provide frequency track function, which can improve the accuracy of protection
algorithms and the performance of protection functions. For the power system using 50Hz or 60Hz
as reference frequency, the frequency track function can be disabled if the fluctuation of the
frequency range is not great. For the power system that the fluctuation of the frequency range is
great, the frequency track function can be enabled to improve protection performance.
It adopts the positive-sequence voltage which derived from protection used voltage as the
calculation reference, the positive-sequence voltage can be calculated as following:
U1  (U a  U b e j120  U c e j 240) / 3
When no VT is connected to the device, the frequency track function is disabled automatically, and
then the device calculates protection algorithm using the system reference frequency. When the
device detects a fault happening to the power system or the voltage is smaller than 0.15Un, the
frequency track function is disabled.
3.3.3 Function Block Diagram
FreqCal
FreqTrack
fn
f
Alm_Freq
3.3.4 I/O Signal
Table 3.3-1 I/O signals of frequency calculation
No.
Input Signal
1
FreqTrack
2
fn
No.
Description
It is used to enabled or disable frequency track function by the configuration
software PCS-Explorer.
It is the system frequency, which is decided by the setting [Opt_SysFreq].
Output Signal
Description
1
f
Frequency calculation result
2
Alm_Freq
Frequency abnormality alarm
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3 Operation Theory
3.3.5 Logic
SIG U3P
Frequency
calculation
SIG fn
f
SIG FreqTrack
SIG f<[f_Low_FreqAlm]
>=1
Alm_Freq
SIG f>[f_High_FreqAlm]
Figure 3.3-1 Logic diagram of frequency calculation
3.4 Circuit Breaker Position Supervision
3.4.1 General Application
The status of circuit breaker (CB) position is applied for protection and control functions in this
device, such as, SOTF protection, auto-reclose and VT circuit supervision, etc. The status of CB
position can be applied as input signals for other features configured by user.
3.4.2 Function Description
The signal reflecting CB position is acquired via opto-coupler with settable delay pickup and
dropoff, and forms digital signal used by protection functions. CB position can reflect the status of
each phase by means of phase-segregated inputs.
In order to prevent that wrong status of CB position is input into the device via binary input,
appropriate monitor method is used to check the rationality of the binary input. When the binary
input of CB open position is detected, the status of CB position will be thought as incorrect and an
alarm [Alm_52b] will be issued if there is current detected in the line.
Together with the status of circuit breaker and the information of external circuit, this function can
be used to supervise control circuit of circuit breaker.
External manual closing binary input (ManCls) is only used for SOTF logic application, the control
of circuit breaker (CB) closing or opening should refer to section 3.29 (Control and Synchrocheck
for Manual Closing).
3.4.3 Function Block Diagram
1.
For phase-segregated circuit breaker
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3 Operation Theory
CB Position Supervision
CBx.52b_PhA
CBx.Alm_52b
CBx.52b_PhB
CBx.52b_PhC
CBx.ManCls
CBx.Test
2.
For non-phase segregated circuit breaker
CB Position Supervision
CBx.52b
CBx.Alm_52b
CBx.ManCls
CBx.Test
3.
Trip&closing circuit supervision (TCCS)
TCCS
CBx.52a
CBx.TCCS.Alm
CBx.52b
CBx.TCCS.Input
CBx.ManCls
CBx.Test
TCCS will be disabled automatically when it is used for phase-segregated circuit breaker. x=1 or 2
3.4.4 I/O Signals
Table 3.4-1 I/O signals of CB position supervision
No.
Input Signal
Description
1
CBx.52b_PhA
Normally closed contact of A-phase of circuit breaker No.x
2
CBx.52b_PhB
Normally closed contact of B-phase of circuit breaker No.x
3
CBx.52b_PhC
Normally closed contact of C-phase of circuit breaker No.x
Maintenance status binary input of circuit breaker No.x
4
CBx.Test
If any circuit breaker is in maintenance and out of service, CBx.52b or CBx.Test
should be set as “1” in fixed, and CB No.x will not be take effect in corresponding
protection logics. (CB position supervision is still kept.) It is only available for
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3 Operation Theory
double circuit breakers mode.
External manual closing binary input of circuit breaker No.x, it is only applied to
5
CBx.ManCls
6
CBx.52b
Normally closed contact of three-phase of circuit breaker No.x
7
CBx.52a
Normally open contact of three-phase of circuit breaker No.x
SOTF logic
Control circuit failure of circuit breaker No.x (normally closed contacts of tripping
8
CBx.TCCS.Input
position (52b) and closing position (52a) of three-phase circuit breaker are all
de-energized due to DC power loss of control circuit)
No.
Output Signal
Description
1
CBx.Alm_52b
Circuit breaker No.x position is abnormal
2
CBx.TCCS.Alm
Control circuit of circuit breaker No.x is abnormal
NOTICE!
The signal [CBx.52a] only take effect in the tripping/closing circuit supervision and not
affect any protection function. Only if tripping/closing circuit supervision is configured,
this signal needs to be connected to the device.
3.4.5 Logic
BI
[CBx.52b_PhA]
>=1
&
&
BI
[CBx.52b_PhB]
>=1
&
&
>=1
10s
BI
[CBx.52b_PhC]
BI
[CBx.52b]
>=1
>=1
10s
CBx.Alm_52b
&
&
SIG CBx.Ia>I_Line
&
>=1
SIG CBx.Ib>I_Line
&
SIG CBx.Ic>I_Line
Figure 3.4-1 Logic diagram of CB position supervision
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3 Operation Theory
BI
[CBx.52a]
BI
[CBx.52b]
BI
[CBx.TCCS.Input]
>=1
>=1
[CBx.TCCS.t_DPU]
[CBx.TCCS.t_DDO]
CBx.TCCS.Alm
Figure 3.4-2 Logic diagram of trip&closing circuit supervision
BI
[CB1.52b_PhA]
>=1
&
52b_PhA
BI
[CB1.52b_PhB]
BI
[CB1.52b_PhC]
BI
[CB1.52b]
BI
[CB1.Test]
BI
[CB2.52b_PhA]
>=1
BI
[CB2.52b_PhB]
>=1
BI
[CB2.52b_PhC]
BI
[CB2.52b]
BI
[CB2.Test]
>=1
>=1
&
52b_PhB
&
>=1
52b_PhC
Figure 3.4-3 Logic diagram of circuit breaker position
x=1 or 2
I_Line is threshold value used to determine whether line is on-load or no-load. Default value
0.06In.
If there is any single phase tripping or breaker status [52b_Phx]=1 (x can be A, B or C) and
corresponding phase current is smaller than 0.06IN, then single pole open state is confirmed by the
device.
If there is three pole tripping or breaker status of three phases are all open and three phase
currents are all smaller than 0.06IN, then three pole open state is confirmed by the device.
3-7
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3 Operation Theory
&
SIG 52b_PhA
50ms
0ms
50ms
0ms
50ms
0ms
SIG Ia<I_Line
SIG 52b_PhB
&
SIG Ib<I_Line
SIG 52b_PhC
&
SIG Ic<I_Line
>=1
SIG Trp A
S
SET
Pole A open
&
Q
50ms
SIG FD.Pkp
R
CLR
0ms
Q
SIG Ia<I_Line
>=1
SIG Trp B
S
SET
Q
Pole B open
&
50ms
R
CLR
0ms
Q
SIG Ib<I_Line
>=1
SIG Trp C
S
SET
Pole C open
&
Q
50ms
R
CLR
0ms
Q
SIG Ic<I_Line
Figure 3.4-4 Logic diagram of pole open states
Where:
TrpA, TrpB and TrpC are the tripping signals of the device.
3.4.6 Settings
Table 3.4-2 Internal settings of CB position supervision
No.
Name
Default Value
Unit
1
CBx.TCCS.t_DPU
0.5
s
2
CBx.TCCS.t_DDO
0.5
s
Remark
Pickup delay time of control circuit failure alarm for
circuit breaker No.x (x=1 or 2)
Dropoff delay time of control circuit failure alarm for
circuit breaker No.x (x=1 or 2)
3.5 Fault Detector (FD)
3.5.1 Application
The device has one DSP module with fault detector DSP and protection DSP for fault detector and
protection calculation respectively. Protection DSP with protection fault detector element is
responsible for calculation of protection elements, and fault detector DSP is responsible to
determine fault appearance on the protected power system. Fault detector in fault detector DSP
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PCS-902 Line Distance Relay
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3 Operation Theory
picks up to provide positive supply to output relays. The output relays can only operate when both
the fault detector in fault detector DSP and a protection element operate simultaneously.
Otherwise, the output relays would not operate. An alarm message will be issued with blocking
outputs if a protection element operates while the fault detector does not operate.
3.5.2 Fault Detector in Fault Detector DSP
Main part of FD is DPFC current detector element that detects the change of phase-to-phase
power frequency current, and residual current fault detector element that calculates the vector
sum of 3 phase currents as supplementary. They are continuously calculating the analog input
signals.
All fault detectors in this device include:
1.
Fault detector based on DPFC current: DPFC current is greater than the setting value
2.
Fault detector based on residual current: Residual current is greater than the setting value
3.
Fault detector based on negative-sequence current: Negative-sequence current is greater
than the setting value
4.
Fault detector based on phase current: Phase current is greater than the setting value
5.
Fault detector based on voltage: Phase voltage or phase-to-phase voltage is greater than the
setting value
6.
Fault detector based on circuit breaker position: Circuit breaker position discrepancy
7.
Fault detector based on thermal overload logic: Thermal overload pickup
8.
Fault detector based on protection elements: Frequency element pickup, broken conductor
element pickup, reverse power element pickup, power swing element pickup, breaker failure
element pickup, phase overcurrent with VT failure element pickup and transfer trip element
pickup.
If any of the above conditions is complied, FD will operate to activate the output circuit providing
DC power supply to the output relays. The fault detector based on DPFC current and the fault
detector based on residual current are always enabled, and all protection functions are permitted
to operate when they operate.
3.5.2.1 Fault Detector Based on DPFC Current
DPFC phase-to-phase current is obtained by subtracting the phase-to-phase current from that of a
cycle before.
I(k) is the sampling value at a point.
I(k-24) is the value of a sampling point before a cycle, 24 is the sampling points in one cycle.
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PCS-902 Line Distance Relay
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3 Operation Theory
200
100
0
-100
-200
0
20
40
60
Original Current
80
100
120
0
20
40
60
DPFC current
80
100
120
100
50
0
-50
-100
From above figures, it is concluded that DPFC can reflect the sudden change of current at the
initial stage of a fault and has a perfect performance of fault detection.
It is used to determine whether this pickup condition is met according to Equation 3.5-1.
For multi-phase short-circuit fault, DPFC phase-to-phase current has high sensitivity to ensure the
pickup of protection device. For usual single phase to earth fault, it also has sufficient sensitivity to
pick up except the earth fault with very large fault resistance. Under this condition, DPFC current is
relative small, however, residual current is also used to judge pickup condition.
This element adopts adaptive floating threshold varied with the change of load current
continuously. The change of load current is small and steady under normal or power swing
condition, the adaptive floating threshold with the ΔI Set is higher than the change of current under
these conditions and hence maintains the element stability.
The criterion is:
ΔIΦΦMAX>1.25ΔITh+ΔISet
Equation 3.5-1
Where:
ΔIΦΦMAX: The maximum half-wave integration value of phase-to-phase current (ΦΦ=AB, BC, CA)
ΔISet: The fixed threshold value (i.e. the setting [FD.DPFC.I_Set])
ΔITh: The floating threshold value
The coefficient, 1.25, is an empirical value which ensures the threshold always higher than the
unbalance output value of the system.
If operation condition is met, the fault detector based on DPFC current will operate to provide DC
power supply for output relays, the pickup signal will maintain 5s after the fault detector based on
DPFC current drops off.
3-10
PCS-902 Line Distance Relay
Date: 2019-03-01
3 Operation Theory
3.5.2.2 Fault Detector Based on Residual Current
The operation condition will be met when 3I0 is greater than the setting [FD.ROC.3I0_Set]. The
fault detector based on residual current is always in service.
Where:
3I0: residual current calculates from the vector sum of Ia, Ib and Ic
When the fault detector based on residual current operates and lasts for longer than 10 seconds,
an alarm [Alm_Pkp_I0] will be issued.
If operation condition is met, the fault detector based on residual current will operate to provide DC
power supply for output relay, and the pickup signal will maintain 5s after the fault detector based
on residual current drops off.
3.5.2.3 Fault Detector Based on Negative-sequence Current
The operation condition will be met when negative-sequence current (I2) is greater than the
setting [FD.NOC.I2_Set]. It can be enabled or disabled by the logic setting [FD.NOC.En].
If operation condition is met, the fault detector based on negative-sequence current will operate to
provide DC power supply for output relay, and the pickup signal will maintain 5s after the fault
detector based on negative-sequence current drops off.
3.5.2.4 Fault Detector Based on Phase Current
The fault detector based on phase current will operate to provide DC power supply for output relay
when phase overcurrent protection is enabled and meets the operation condition, and the pickup
signal will maintain 500ms after the fault detector based on phase current drops off.
3.5.2.5 Fault Detector Based on Voltage
This fault detector based on voltage includes the fault detectors of overvoltage protection,
undervoltage protection and frequency protection. The fault detector based on voltage will operate
to provide DC power supply for output relay when corresponding voltage element is enabled and
meets the operation condition, and the pickup signal will maintain 500ms after the fault detector
based on voltage drops off.
3.5.2.6 Fault Detector Based on Circuit Breaker Position
When pole discrepancy protection is enabled, i.e. the logic setting [62PD.En] is set as “1”, and if
three phases of circuit breaker are not in the same status, the fault detector based on circuit
breaker position will operate to provide DC power supply for output relays, and the pickup signal
will maintain 500ms after the fault detector based on circuit breaker position drops off.
3.5.2.7 Fault Detector Based on Thermal Overload Logic
The fault detector based on thermal overload logic will operate to provide DC power supply for
output relay when tripping logic of thermal overload protection meets the operation condition, and
the pickup signal will maintain 500ms after the fault detector based on thermal overload logic
drops off.
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3 Operation Theory
3.5.2.8 Fault Detector Based on Protection Element
The fault detector based on protection element will operate to provide DC power supply for output
relay when these protection element are enabled and meet the operation condition, and the pickup
signal will maintain 500ms after the fault detector based on protection element drops off.
3.5.3 Protection Fault Detector in Protection Calculation DSP
The protection device is running either of the two programs: one is “Regular program” for normal
state, and the other is “Fault calculation program” after protection fault detector picks up.
Under the normal state, the protection device will perform the following tasks:
1.
Calculate analog quantity
2.
Read binary input
3.
Hardware self-check
4.
Circuit breaker position supervision
5.
Analog quantity input supervision
6.
Channel supervision
Once the protection fault detector element in protection calculation DSP picks up, the protection
device will switch to fault calculation program, for example the calculation of distance protection,
and to determine logic. If the fault is within the protected zone, the protection device will send
tripping command.
The protection program flow chart is shown as Figure 3.5-1.
Main program
Sampling program
No
Regular program
Yes
Pickup?
Fault calculation program
Figure 3.5-1 Flow chart of protection program
The protection FD pickup conditions are the same as the FD in fault detector DSP as shown below.
The operation criteria for the conditions are also the same as that in fault detector DSP. Please
refer to section 3.5.2 for details.
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3 Operation Theory
3.5.4 Function Block Diagram
FD
FD.Pkp
FD.DPFC.Pkp
FD.ROC.Pkp
FD.NOC.Pkp
3.5.5 I/O Signals
Table 3.5-1 I/O signals of fault detector
No.
Output Signal
Description
1
FD.Pkp
The device picks up
2
FD.DPFC.Pkp
DPFC current fault detector element operates.
3
FD.ROC.Pkp
Residual current fault detector element operates.
4
FD.NOC.Pkp
Negative-sequence fault detector element operates.
3.5.6 Logic
SIG
Ia
SIG
Ib
SIG
Ic
Calculate DPFC phase-tophase current:
Δ Iab=Δ (Ia-Ib)
Δ Ibc=Δ (Ib-Ic)
Δ Ica=Δ (Ic-Ia)
Δ Iab>[FD.DPFC.I_Set]
>=1
Δ Ibc>[FD.DPFC.I_Set]
FD.DPFC.Pkp
Δ Ica>[FD.DPFC.I_Set]
>=1
0s
Calculate residual current:
3I0=Ia+Ib+Ic
3I0>[FD.ROC.3I0_Set]
Calculate negativesequence current: I2
I2>[FD.NOC.I2_Set]
5s
FD.Pkp
FD.ROC.Pkp
&
FD.NOC.Pkp
EN
FD.NOC.En
Figure 3.5-2 Logic diagram of fault detector
3.5.7 Settings
Table 3.5-2 Settings of fault detector
No.
Name
Range
Step
Unit
1
FD.DPFC.I_Set
(0.050~30.000)×In
0.001
A
2
FD.ROC.3I0_Set
(0.050~30.000)×In
0.001
A
3
FD.NOC.I2_Set
(0.050~30.000)×In
0.001
A
Remark
Current setting of DPFC current fault
detector element
Current setting of residual current fault
detector element
Current setting of negative-sequence
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3 Operation Theory
No.
Name
Range
Step
Unit
Remark
current fault detector element
Enabling/disabling negative-sequence
4
FD.NOC.En
current fault detector element
0 or 1
0: disable
1: enable
3.6 Auxiliary Element
3.6.1 General Application
Auxiliary element (AuxE) is mainly used to program logics to meet users’ applications or further
improve operating reliability of protection elements. Reliability of protective elements (such as
distance element or current differential element) is assured, auxiliary element is usually not
required to configure. Auxiliary elements including current change auxiliary element (AuxE.OCD),
residual current auxiliary element (AuxE.ROC), phase current auxiliary element (AuxE.OC),
voltage change auxiliary element (AuxE.UVD), phase under voltage auxiliary element (AuxE.UVG),
phase-to-phase under voltage auxiliary element (AuxE.UVS) and residual voltage auxiliary
element (AuxE.ROV), and they can be enabled or disabled by corresponding logic setting or
binary inputs. Users can configure them according to applications via PCS-Explorer software.
3.6.2 Function Description
1.
Current change auxiliary element AuxE.OCD
It shares DPFC current element of DPFC fault detector. If DPFC fault detector operates
(FD.DPFC.Pkp=1) and current change auxiliary element is enabled, current change auxiliary
element operates.
2.
Residual current auxiliary element AuxE.ROC
There are 3 stages for residual current auxiliary element (AuxE.ROC1, AuxE.ROC2 and
AuxE.ROC3). Each residual current auxiliary element will operate instantly if calculated residual
current amplitude is larger than corresponding current setting
The criteria are:
AuxE.ROC1: 3I0>[AuxE.ROC1.3I0_Set]
AuxE.ROC2: 3I0>[AuxE.ROC2.3I0_Set]
AuxE.ROC3: 3I0>[AuxE.ROC3.3I0_Set]
Where:
3I0: The calculated residual current
3.
Phase current auxiliary element AuxE.OC
There are 3 stages for phase current auxiliary element (AuxE.OC1, AuxE.OC2 and AuxE.OC3).
Each phase current auxiliary element will operate instantly if phase current amplitude is larger than
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corresponding current setting.
The criteria are:
AuxE.OC1: IΦMAX>[AuxE.OC1.I_Set]
AuxE.OC2: IΦMAX>[AuxE.OC2.I_Set]
AuxE.OC3: IΦMAX>[AuxE.OC3.I_Set]
Where:
IΦMAX: The maximum phase current among three phases
4.
Voltage change auxiliary element AuxE.UVD
AuxE.UVD is based on phase-to-ground voltage change measured in all three phases.
The criterion is:
Δ UΦMAX>[AuxE.UVD.U_Set]
Where:
ΔUΦMAX: The maximum phase-to-ground voltage change among three phases
5.
Phase under voltage auxiliary element AuxE.UVG
AuxE.UVG will operate instantly if any phase-to-ground voltage is lower than corresponding
voltage setting.
The criterion is:
UΦMIN<[AuxE.UVG.U_Set]
Where:
UΦMIN: The minimum value among three phase-to-ground voltages
6.
Phase-to-phase under voltage auxiliary element AuxE.UVS
AuxE.UVS will operate instantly if any phase-to-phase voltage is lower than corresponding voltage
setting.
The criterion is:
UΦΦMIN<[AuxE.UVS.U_Set]
Where:
UΦΦMIN: The minimum value among three phase-to-phase voltages
7.
Residual voltage auxiliary element AuxE.ROV
AuxE.ROV will operate instantly if calculated residual voltage is larger than corresponding voltage
setting.
The criterion is:
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3 Operation Theory
3U0>[AuxE.ROV.3U0_Set]
Where:
3U0: The calculated residual voltage
3.6.3 Function Block Diagram
AuxE
AuxE.OCD.En
AuxE.St
AuxE.OCD.Blk
AuxE.OCD.St_DDO
AuxE.ROCi.En
AuxE.OCD.On
AuxE.ROCi.Blk
AuxE.ROCi.St
AuxE.OCi.En
AuxE.ROCi.On
AuxE.OCi.Blk
AuxE.OCi.St
AuxE.UVD.En
AuxE.OCi.StA
AuxE.UVD.Blk
AuxE.OCi.StB
AuxE.UVG.En
AuxE.OCi.StC
AuxE.UVG.Blk
AuxE.OCi.On
AuxE.UVS.En
AuxE.UVD.St
AuxE.UVS.Blk
AuxE.UVD.St_DDO
AuxE.ROV.En
AuxE.UVD.On
AuxE.ROV.Blk
AuxE.UVG.St
AuxE.UVG.StA
AuxE.UVG.StB
AuxE.UVG.StC
AuxE.UVG.On
AuxE.UVS.St
AuxE.UVS.StAB
AuxE.UVS.StBC
AuxE.UVS.StCA
AuxE.UVS.On
AuxE.ROV.St
AuxE.ROV.On
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3.6.4 I/O Signals
Table 3.6-1 I/O signals of auxiliary element
No.
Input Signal
1
AuxE.OCD.En
2
AuxE.OCD.Blk
3
AuxE.ROCi.En
4
AuxE.ROCi.Blk
5
AuxE.OCi.En
6
AuxE.OCi.Blk
7
AuxE.UVD.En
8
AuxE.UVD.Blk
9
AuxE.UVG.En
10
AuxE.UVG.Blk
11
AuxE.UVS.En
12
AuxE.UVS.Blk
13
AuxE.ROV.En
14
AuxE.ROV.Blk
No.
Output Signal
Description
Current change auxiliary element enabling input, it is triggered from binary input
or programmable logic etc.
Current change auxiliary element blocking input, it is triggered from binary input
or programmable logic etc.
Stage i of residual current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc. (i=1, 2, 3)
Stage i of residual current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc. (i=1, 2, 3)
Stage 1 of phase current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc. (i=1, 2, 3)
Stage 1 of phase current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc. (i=1, 2, 3)
Voltage change auxiliary element enabling input, it is triggered from binary input
or programmable logic etc.
Voltage change auxiliary element blocking input, it is triggered from binary input
or programmable logic etc.
Phase-to-ground under voltage auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Phase-to-ground under voltage auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Residual voltage auxiliary element enabling input, it is triggered from binary
input or programmable logic etc.
Residual voltage auxiliary element blocking input, it is triggered from binary
input or programmable logic etc.
Description
1
AuxE.St
Any auxiliary element of the device operates.
2
AuxE.OCD.St_DDO
Current change auxiliary element operates.
3
AuxE.OCD.On
Current change auxiliary element is enabled.
4
AuxE.ROCi.St
Stage 1 of residual current auxiliary element operates. (i=1, 2, 3)
5
AuxE.ROCi.On
Stage 1 of residual current auxiliary element is enabled. (i=1, 2, 3)
6
AuxE.OCi.St
Stage 1 of phase current auxiliary element operates. (i=1, 2, 3)
7
AuxE.OCi.StA
Stage 1 of phase current auxiliary element operates (phase A). (i=1, 2, 3)
8
AuxE.OCi.StB
Stage 1 of phase current auxiliary element operates (phase B). (i=1, 2, 3)
9
AuxE.OCi.StC
Stage 1 of phase current auxiliary element operates (phase C). (i=1, 2, 3)
10
AuxE.OCi.On
Stage 1 of phase current auxiliary element is enabled. (i=1, 2, 3)
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11
AuxE.UVD.St
Voltage change auxiliary element operates.
12
AuxE.UVD.St_DDO
Voltage change auxiliary element operates.
13
AuxE.UVD.On
Voltage change auxiliary element is enabled.
14
AuxE.UVG.St
Phase-to-ground under voltage auxiliary element operates.
15
AuxE.UVG.StA
Phase-to-ground under voltage auxiliary element operates (phase A).
16
AuxE.UVG.StB
Phase-to-ground under voltage auxiliary element operates (phase B).
17
AuxE.UVG.StC
Phase-to-ground under voltage auxiliary element operates (phase C).
18
AuxE.UVG.On
Phase-to-ground under voltage auxiliary element is enabled.
19
AuxE.UVS.St
Phase-to-phase under voltage auxiliary element operates.
20
AuxE.UVS.StAB
Phase-to-phase under voltage auxiliary element operates (phase AB).
21
AuxE.UVS.StBC
Phase-to-phase under voltage auxiliary element operates (phase BC).
22
AuxE.UVS.StCA
Phase-to-phase under voltage auxiliary element operates (phase CA).
23
AuxE.UVS.On
Phase-to-phase under voltage auxiliary element is enabled.
24
AuxE.ROV.St
Residual voltage auxiliary element operates.
25
AuxE.ROV.On
Residual voltage auxiliary element is enabled.
3.6.5 Logic
SET 3I0>[AuxE.ROCi.3I0_Set]
SIG
AuxE.ROCi.En
SIG
AuxE.ROCi.Blk
EN
AuxE.ROCi.En
&
AuxE.ROCi.St
&
AuxE.ROCi.On
Figure 3.6-1 Logic diagram of auxiliary element (ROC)
SIG
3U0>[AuxE.ROV.3U0_Set]
SIG
AuxE.ROV.En
SIG
AuxE.ROV.Blk
EN
AuxE.ROV.En
&
AuxE.ROV.St
&
AuxE.ROV.On
Figure 3.6-2 Logic diagram of auxiliary element (ROV)
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SIG
AuxE.OCi.En
SIG
AuxE.OCi.Blk
EN
AuxE.OCi.En
&
AuxE.OCi.On
SET Ia>[AuxE.OCi.I_Set]
&
AuxE.OCi.StA
SET Ib>[AuxE.OCi.I_Set]
&
AuxE.OCi.StB
SET Ic>[AuxE.OCi.I_Set]
&
AuxE.OCi.StC
SET Ia>[AuxE.OCi.I_Set]
&
AuxE.OCi.St
>=1
SET Ib>[AuxE.OCi.I_Set]
SET Ic>[AuxE.OCi.I_Set]
Figure 3.6-3 Logic diagram of auxiliary element (OC)
SIG
AuxE.UVG.En
SIG
AuxE.UVG.Blk
EN
AuxE.UVG.En
SET
UA<[AuxE.UVG.U_Set]
&
AuxE.UVG.On
&
AuxE.UVG.StA
SET
UB<[AuxE.UVG.U_Set]
&
AuxE.UVG.StB
SET
UC<[AuxE.UVG.U_Set]
&
AuxE.UVG.StC
SET
UA<[AuxE.UVG.U_Set]
SET
UB<[AuxE.UVG.U_Set]
SET
UC<[AuxE.UVG.U_Set]
&
>=1
AuxE.UVG.St
Figure 3.6-4 Logic diagram of auxiliary element (UVG)
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3 Operation Theory
SIG
AuxE.UVS.En
SIG
AuxE.UVS.Blk
EN
AuxE.UVS.En
SET
UA<[AuxE.UVS.U_Set]
&
AuxE.UVS.On
&
AuxE.UVS.StA
SET
UB<[AuxE.UVS.U_Set]
&
AuxE.UVS.StB
SET
UC<[AuxE.UVS.U_Set]
&
AuxE.UVS.StC
SET
UA<[AuxE.UVS.U_Set]
SET
UB<[AuxE.UVS.U_Set]
SET
UC<[AuxE.UVS.U_Set]
&
AuxE.UVS.St
>=1
Figure 3.6-5 Logic diagram of auxiliary element (UVS)
SET
Δ Ua>[AuxE.UVD.U_Set]
SET
Δ Ub>[AuxE.UVD.U_Set]
SET
Δ Uc>[AuxE.UVD.U_Set]
SIG
AuxE.UVD.En
SIG
AuxE.UVD.Blk
EN
AuxE.UVD.En
>=1
&
AuxE.UVD.St
0s
[AuxE.UVD.t_DDO]
AuxE.UVD.St_DDO
&
AuxE.UVD.On
Figure 3.6-6 Logic diagram of auxiliary element (UVD)
SIG
AuxE.OCD.En
SIG
AuxE.OCD.Blk
AuxE.OCD.On
EN
AuxE.OCD.En
&
&
0s [AuxE.OCD.t_DDO]
SIG
AuxE.OCD.St_DDO
FD.DPFC.Pkp
Figure 3.6-7 Logic diagram of auxiliary element (OCD)
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3 Operation Theory
SIG
AuxE.OCD.St_DDO
SIG
AuxE.ROC1.St
SIG
AuxE.ROC2.St
SIG
AuxE.ROC3.St
SIG
AuxE.OC1.St
SIG
AuxE.OC2.St
SIG
AuxE.OC3.St
SIG
AuxE.UVD.St_DDO
SIG
AuxE.UVG.St
SIG
AuxE.UVS.St
SIG
AuxE.ROV.St
>=1
>=1
>=1
AuxE.St
>=1
>=1
>=1
>=1
Figure 3.6-8 Logic diagram of auxiliary element (Startup)
Where:
i=1, 2, 3
Calculate residual current: 3I0=Ia+Ib+Ic
Calculate DPFC phase voltage: △Ua=△(Ua-Ufa), △Ub=△(Ub-Ufb), △Uc=△(Uc-Ufc)
Calculate residual voltage: 3U0=Ua+Ub+Uc
3.6.6 Settings
Table 3.6-2 Settings of auxiliary element
No.
1
Name
AuxE.OCD.t_DDO
Range
0.000~10.000
Step
Unit
0.001
s
Remark
Drop-off time delay of current change
auxiliary element
Enabling/disabling
2
AuxE.OCD.En
current
change
auxiliary element
0 or 1
0: disable
1: enable
3
AuxE.ROCi.3I0_Set
(0.050~30.000)×In
0.001
A
Current setting of stage i residual
current auxiliary element (i=1, 2, 3)
Enabling/disabling
4
AuxE.ROCi.En
stage
i
residual
current auxiliary element (i=1, 2, 3)
0 or 1
0: disable
1: enable
5
AuxE.OCi.I_Set
(0.050~30.000)×In
Current setting of stage i phase current
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3 Operation Theory
No.
Name
Range
Step
Unit
Remark
auxiliary element (i=1, 2, 3)
Enabling/disabling
6
AuxE.OCi.En
stage
i
phase
current auxiliary element (i=1, 2, 3)
0 or 1
0: disable
1: enable
7
AuxE.UVD.U_Set
0~Un
0.001
V
8
AuxE.UVD.t_DDO
0.000~10.000
0.001
s
Voltage setting for voltage change
auxiliary element
Drop-off time delay of voltage change
auxiliary element
Enabling/disabling
9
AuxE.UVD.En
voltage
change
auxiliary element
0 or 1
0: disable
1: enable
10
AuxE.UVG.U_Set
0~Un
0.001
V
Voltage setting for phase-to-ground
under voltage auxiliary element
Enabling/disabling
11
AuxE.UVG.En
phase-to-ground
under voltage auxiliary element
0 or 1
0: disable
1: enable
12
AuxE.UVS.U_Set
0~Unn
0.001
V
Voltage setting for
under voltage auxiliary element
Enabling/disabling
13
AuxE.UVS.En
phase-to-phase
phase-to-phase
under voltage auxiliary element
0 or 1
0: disable
1: enable
14
AuxE.ROV.3U0_Set
0~Un
0.001
V
Voltage setting for residual voltage
auxiliary element
Enabling/disabling
15
AuxE.ROV.En
residual
voltage
auxiliary element
0 or 1
0: disable
1: enable
3.7 Distance Protection
3.7.1 General Application
When a fault happens on a power system, distance protection will trip circuit breaker to isolate the
fault from power system with its specific time delay if the fault is within the protected zone of
distance protection.
3.7.2 Function Description
The device provide various distance elements, including 1 DPFC distance zone with fixed forward
direction, 1 forward zones, 4 settable forward or reverse zone, and 1 forward zone and 1 reverse
zone dedicated for pilot distance protection. For each independent distance element zone, full
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3 Operation Theory
scheme design provides continuous measurement of impedance separately in each independent
phase-to-phase measuring loops as well as in each independent phase-to-ground measuring
loops. Selection of zone characteristic between mho and quadrilateral is available. Distance
protection includes:
1.
DPFC distance protection
It is independent fast protection providing extremely fast speed to clear close up fault
especially on long line and thus improves system stability.
2.
Mho phase-to-phase distance protection
Zone 1: forward direction
Zone 2~5: settable forward or reverse direction
3.
Mho phase-to-ground distance protection
Zone 1: forward direction
Zone 2~5: settable forward or reverse direction
4.
Quadrilateral phase-to-phase distance protection
Zone 1: forward direction
Zone 2~5: settable forward or reverse direction
5.
Quadrilateral phase-to-ground distance protection
Zone 1: forward direction
Zone 2~5: settable forward or reverse direction
6.
Pilot distance protection
The pilot zone is for PUTT, POTT and blocking scheme. The forward direction element is for
sending signal for POTT and tripping upon receiving permissive signal for both PUTT and
POTT scheme. The forward direction element for blocking scheme is used to stop sending
blocking signal. The reverse direction element is only for POTT scheme with weak infeed
condition.
7.
Load encroachment
It is used to prevent all distance elements from undesired trip due to load encroachment
under heavy load condition especially for long lines.
8.
Out-of-step protection (OOS)
9.
Power swing blocking releasing (PSBR)
For power swing with external fault, distance protection is always blocked, but for power
swing with internal fault, PSBR will operate to release the blocking for distance protection.
10. SOTF distance protection
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3 Operation Theory
For manual closing or automatic closing on to a fault, zone 2, 3 or 4 of distance protection will
accelerate to trip.
When VT circuit fails, VT circuit supervision logic will output a blocking signal to block all distance
protection except DPFC distance protection. The operating threshold will be increased to 1.5U N to
enhance stability.
Distance protection can select line VT or bus VT for protection algorithm by a setting
[VTS.En_LineVT]. When no VT is provided, logic setting [VTS.En_Out_VT] should be set as “1”,
all distance protection will be blocked automatically. The choice of impedance reach is as follow.
(only for reference)
The zone 1 impedance reach setting should be set to cover as much the protected line as possible
but not to respond faults beyond the protected line. The accuracy of the relay distance elements is
±2.5% in general applications, however, the error could be much larger due to errors of current
transformer, voltage transformer and inaccuracies of line parameter from which the relay settings
are calculated. It is recommended the zone 1 reach is set to 80%~85% of the protected line in
consideration the aforesaid errors and safety margin to prevent instantaneously tripping for faults
on adjacent lines. The remaining 20% of the protected line relies on the zone 2 distance elements.
With the pilot scheme distance protection, fast fault clearance could also be achieved for end zone
faults at both ends of the protected line.
The general rule for zone 2 impedance reach setting is set to cover the protected line plus 20% of
the adjacent line. However, the coverage of adjacent line should be extended in the presence of
additional infeed at the remote end of the protected line to ensure 20% coverage of adjacent line.
This assures the fast operation of zone 2 distance element for faults at the remote end of the
protected line since the fault is well within zone 2 reach. This is important for pilot protection as the
impedance reach of pilot zone is the same as that of zone 2 distance element. In a parallel line
situation, a fault cleared sequentially on a line may cause current reversal in the healthy line. If the
pilot zone settings are set to cover 50% of adjacent line and the POTT or Blocking scheme is used,
the current reversal in the healthy line could cause relay mal-operation. Therefore, current reversal
logic is required and explained in section 3.9.2.6.
For different system impedance ratio (SIR), the operating time of distance protection for different
fault location are shown as the following figures.
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3 Operation Theory
35
30
25
Operating Time (ms)
20
15
10
5
0
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Fault Location (% of relay setting)
Figure 3.7-1 Operating time of single-phase fault (50Hz, SIR=1)
30
25
Operating Time (ms)
20
15
10
5
0
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Fault Location (% of relay setting)
Figure 3.7-2 Operating time of single-phase fault (60Hz, SIR=1)
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3 Operation Theory
35
30
25
Operating Time (ms)
20
15
10
5
0
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Fault Location (% of relay setting)
Figure 3.7-3 Operating time of two-phase fault (50Hz, SIR=1)
30
25
Operating Time (ms)
20
15
10
5
0
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Fault Location (% of relay setting)
Figure 3.7-4 Operating time of two-phase fault (60Hz, SIR=1)
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3 Operation Theory
35
30
25
Operating Time (ms)
20
15
10
5
0
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Fault Location (% of relay setting)
Figure 3.7-5 Operating time of three-phase fault (50Hz, SIR=1)
30
25
Operating Time (ms)
20
15
10
5
0
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Fault Location (% of relay setting)
Figure 3.7-6 Operating time of three-phase fault (60Hz, SIR=1)
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33
32.5
32
Operating Time (ms)
31.5
31
30.5
30
29.5
29
0%
10%
20%
30%
40%
50%
60%
70%
80%
90% 100%
Fault Location (% of relay setting)
Figure 3.7-7 Operating time of single-phase fault (50Hz, SIR=30)
27.5
27
Operating Time (ms)
26.5
26
25.5
25
24.5
24
0%
10%
20%
30%
40%
50%
60%
70%
80%
90% 100%
Fault Location (% of relay setting)
Figure 3.7-8 Operating time of single-phase fault (60Hz, SIR=30)
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45
40
35
Operating Time (ms)
30
25
20
15
10
5
0
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Fault Location (% of relay setting)
Figure 3.7-9 Operating time of two-phase fault (50Hz, SIR=30)
35
30
Operating Time (ms)
25
20
15
10
5
0
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Fault Location (% of relay setting)
Figure 3.7-10 Operating time of two-phase fault (60Hz, SIR=30)
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3 Operation Theory
33
32
Operating Time (ms)
31
30
29
28
27
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Fault Location (% of relay setting)
Figure 3.7-11 Operating time of three-phase fault (50Hz, SIR=30)
27.5
27
Operating Time (ms)
26.5
26
25.5
25
24.5
24
23.5
0%
10%
20%
30%
40%
50%
60%
70%
80%
90% 100%
Fault Location (% of relay setting)
Figure 3.7-12 Operating time of three-phase fault (60Hz, SIR=30)
3.7.3 DPFC Distance Protection
The power system is normally treated as a balanced symmetrical three-phase network. When a
fault occurs in the power system, by applying the principle of superposition, the load current and
voltage can be calculated in the system prior to the fault and the pure fault component can be
calculated by fault current or voltage subtracted by pre-fault load current or voltage. DPFC
distance protection concerns change of current and voltage at power frequency, therefore, DPFC
distance protection is not influenced by load current.
As an independent fast protection, DPFC distance protection is mainly used to clear close up fault
of long line quickly, its protected range can set as 80%~85% of the whole line.
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Since DPFC distance protection only reflects fault component and is not influenced by current
change due to load variation and power swing, power swing blocking (PSB) is this not required.
Moreover, there is no transient overreaching due to infeed current from the remote power supply
because it is not influenced by load current.
DPFC distance protection may not overreach, and its protected zone will be inverse-proportion
reduced with system impedance behind it, i.e. the protected zone will be less than setting if the
system impedance is greater. The protected zone will be close to setting value if the system
impedance is smaller. Therefore, DPFC distance protection is usually used for long transmission
line with large power source and it is recommended to disable DPFC distance protection for short
line or the line with weak power source.
3.7.3.1 Impedance Characteristic
ZZD
M
EM
F
Z
N
EN
∆I
ZS
ZK
jX
Zzd
Zk
Φ
Zs+Zk
R
-Zs
Figure 3.7-13 Operation characteristic for forward fault
Where:
ZZD: the setting of DPFC distance protection
ZS: total impedance between local system and device location
ZK: measurement impedance
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Φ: positive-sequence sensitive angle, i.e. [21-1.phi1_Reach]
Figure 3.7-13 shows the operation characteristic of DPFC distance protection on R-X plane when
a fault occurs in forward direction, which is the circle with the –Zs as the center and the│Zs+Zzd│ as
the radius. When measured impedance Z k is in the circle, DPFC distance protection will operate.
DPFC distance protection has a larger capability of enduring fault resistance than distance
protection using positive-sequence as polarized voltage.
ZZD
F
M
EM
N
Z
EN
∆I
ZK
Z′S
jX
Z's
Zzd
Φ
R
-Zk
Figure 3.7-14 Operation characteristic for reverse fault
Z'S：total impedance between remote system and protective device location
Figure 3.7-14 shows the operation characteristic of the DPFC distance element on R-X plane
when a fault occurs in reverse direction, which is the circle with the Z′S as the center and
the│Z′S-Zzd│as the radius. The region of operation is in the quadrant 1 but the measured
impedance -Zk is always in the quadrant 3, the DPFC distance protection will not operate.
The DPFC distance protection can be enabled or disabled by logic setting and binary input.
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3.7.3.2 Function Block Diagram
21D
21D.En
21D.Op
21D.Blk
21D.On
3.7.3.3 I/O Signals
Table 3.7-1 I/O signals of DPFC distance protection
No.
Input Signal
1
21D.En
2
21D.Blk
No.
Description
DPFC distance protection enabling input, it is triggered from binary input or
programmable logic etc.
DPFC distance protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
1
21D.Op
DPFC distance protection operates.
2
21D.On
DPFC distance protection is enabled.
3.7.3.4 Logic
EN
[21D.En]
SIG
21D.En
SIG
21D.Blk
SIG
FD.Pkp
EN
[VTS.En_Out_VT]
SIG
Manual closing signal
SIG
3-pole reclosing signal
SET
[21D.Z_Set]<0.05Ω/In
SET
ZΦ<[21D.Z_Set]
SIG
UP<0.85Un
SET
ZΦΦ<[21D.Z_Set]
SIG
UPP<0.85Unn
SIG
Pole open
&
21D.On
&
>=1
&
>=1
&
&
21D.Op
&
Figure 3.7-15 Logic diagram of DPFC distance protection
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NOTICE!
Pole open signal blocks DPFC distance element of corresponding phase-to-earth and
phase-to-phase DPFC distance protection, and healthy phases (operation phases) are
not affected. For example, if phase A open is confirmed, DPFC distance element of
phase A, phase AB and phase AC are blocked.
3.7.3.5 Settings
Table 3.7-2 Settings of DPFC distance protection
No.
1
Name
21D.Z_Set
Range
Step
Unit
(0.000~4Unn)/In
0.001
ohm
Remark
Impedance setting of DPFC distance
protection
Enabling/disabling
2
21D.En
DPFC
distance
protection
0 or 1
0: disable
1: enable
3.7.4 Load Encroachment
3.7.4.1 Impedance Characteristic
When distance protection is used to protect long, heavily loaded lines, the risk of encroachment of
the load impedance into the tripping characteristic of the distance protection may exist. A load
trapezoid characteristic for all zones is used to exclude the risk of unwanted fault detection by the
distance protection during heavy load flow.
As shown below, if the measured impedance into the load area, distance elements need to be
blocked.
jX
φLoad
φLoad
Load Area
Load Area
R
RLoad
RLoad
Figure 3.7-16 Distance element with load trapezoid
Two settings are equipped to exclude the encroachment of the load impedance:
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RLoad: the minimum load resistance
φLoad: the load area angle
These values are common for all zones.
3.7.4.2 Function Block Diagram
LoadEnch
LoadEnch.En
LoadEnch.St
LoadEnch.Blk
LoadEnch.On
3.7.4.3 I/O Signals
Table 3.7-3 I/O signals of load encroachment
No.
Input Signal
1
LoadEnch.En
2
LoadEnch.Blk
No.
Description
Load trapezoid characteristic enabling input, it is triggered from binary input or
programmable logic etc.
Load trapezoid characteristic blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
Measured impedance is inside the load area.
If load trapezoid characteristic is enabled and measured impedance is inside the
1
LoadEnch.St
load area, LoadEnch.St=1
If load trapezoid characteristic is disabled or measured impedance is outside the
load area, LoadEnch.St=0
2
LoadEnch.On
Load trapezoid characteristic is enabled.
3.7.4.4 Settings
Table 3.7-4 Settings of load encroachment
No.
Name
Range
Step
Unit
Remark
Angle
setting
characteristic,
1
LoadEnch.phi
0~45
1
deg
of
it
load
should
trapezoid
be
set
according to the maximum load area
angle
(φLoad_Max),
φLoad_Max+5° is
recommended.
Impedance setting of load trapezoid
2
LoadEnch.Z_Set
(0.05~200)/In
0.01
ohm
characteristic,
it
according
the
to
should
be
minimum
set
load
resistance, 70%~90% minimum load
resistance is recommended.
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Enabling/disabling
3
LoadEnch.En
load
trapezoid
characteristic
0,1
0: disable
1: enable
3.7.5 Mho Distance Protection
3.7.5.1 Impedance Characteristic
1.
Phase-to-ground distance element
ZZD
M
EM
F
Z
N
IN
EN
I
ZS
ZK
jX
ZZD
ZK
Φ
R
-2ZS/3
Figure 3.7-17 Phase-to-ground operation characteristic for forward fault
Where:
ZZD: the setting of distance protection
ZS: total impedance between local system and protective device location
ZK: measurement impedance
Φ: positive-sequence sensitive angle, i.e. [21-i.phi1_Reach] (i=1, 2, 3, 4, 5)
Phase-to-neutral positive sequence voltage is used as polarized signal for phase-to-ground
distance protection. Phase-to-ground distance protection is controlled by the fault detector based
on residual current.
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Operation voltage:
Polarized voltage:
UPΦ uses phase positive-sequence voltage as polarized voltage. For earth fault, positive-sequence
voltage is mainly formed from healthy phases, basically retaining the phase of the
positive-sequence voltage before fault.
Phase comparison equation is:
The operation characteristic is shown in Figure 3.7-17. Operation characteristic of ZK on R-X plane
is a circle with line connecting ends of ZZD and -2ZS/3 as the diameter. The origin is enclosed in the
circle.
In short line, phase shift θ1 could be applied to the polarized voltage to improve the performance
against high resistance fault. The device provides an angle-shift setting, [21Mx.ZG.phi_Shift], to
set value of θ1 among 0°, 15°and 30°. Their impedance shift characteristics towards quadrant 1
are respectively shown as the impedance circle A, B and C in Figure 3.7-23.
The sensitivity of phase-to-ground distance element with Mho characteristic may be not enough
during ground fault with extreme high resistance. So additional quadrilateral characteristic for
phase-to-ground distance element is adopted in the equipment to compensate the sensitivity of
Mho characteristic. The logic relationship between quadrilateral distance element and Mho
distance element is OR. It means that any ground fault in one of the two operation zones will be
cleared. The quadrilateral phase-to-ground distance element can significantly improve the
sensitivity to clear ground fault with extreme high resistance. The five zones of quadrilateral
characteristic can be enabled or disabled by the logic setting [21Mi.ZGQ.En]. (i=1, 2, 3, 4, 5)
The operation characteristic of quadrilateral distance element is shown in Figure 3.7-18.
When the characteristic of mho & quadrilateral is enabled by PCS-Explorer, the settings
[21Mi.ZG.phi_Shift] will be hidden automatically. (i=1, 2, 3, 4, 5)
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jX
[21Mi.ZG.Z_Set]
[21Mi.ZGQ.RCA]
Φ
Φ
R
15°
[21Mi.ZGQ.R_Set]
Figure 3.7-18 Operation Characteristic of quadrilateral distance element
Where:
i=1, 2, 3, 4, 5
Φ is the phase angle of positive sequence line impedance
The quadrilateral characteristic is a supplement to Mho characteristic for phase-to-ground
distance protection. It is used to improve sensitivity for ground fault with high resistance.
2.
Phase-to-phase distance element
jX
ZZD
ZK
Φ
R
-ZS/2
Figure 3.7-19 Phase-to-phase operation characteristic for forward fault
Phase-to-phase positive sequence voltage is used as polarized signal for phase-to-phase
distance protection.
Operation voltage:
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Polarized voltage:
Phase comparison equation is:
The operation characteristic of phase-to-phase distance element is shown in Figure 3.7-19.
Operation characteristic of ZK on R-X plane is a circle with line connecting ends of Z ZD and -ZS/2 as
the diameter. The origin is enclosed in the circle.
Phase shift θ2 could be applied to polarized voltage just like θ1 in phase-to-ground distance
element. It is also used for improving performance against high resistance fault in short line. The
device provides an angle-shift setting, [21Mx.ZP.phi_Shift], to set value of θ2 among 0°, 15°and
30°. Their impedance shift characteristics towards quadrant 1 are respectively shown as the
impedance circle A, B and C in Figure 3.7-23.
Figure 3.7-20 shows operation characteristic of measured impedance -ZK on R-X plane when an
asymmetric reverse fault occurs. This characteristic is a circle with line connecting ends of Z ZD and
Z'S as the diameter. It will operate only when -ZK is in the circle. Therefore, directionality of the
distanced protection is achieved.
ZZD
F
EM
M
N
Z
EN
IΦ
ZK
Z′S
jX
Z'S
ZZD
Φ
R
-ZK
Figure 3.7-20 Operation characteristic for reverse fault
Z'S: total impedance between remote system and protective device location
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jX
ZZD
ZK
Φ
R
Figure 3.7-21 Steady-state characteristic of three-phase short-circuit fault
Phase-to-phase distance protection is also used for three-phase short-circuit fault. The operation
characteristic is shown in Figure 3.7-21. Operation characteristic of ZK on R-X plane is a circle with
setting impedance ZZD as the diameter.
jX
ZZD
ZK
Φ
R
Circle C
-ZS
Circle B
Circle A
Figure 3.7-22 Operation characteristic of three-phase close up short-circuit fault
Where:
ZZD: the setting of distance protection (zone i)
ZS: total impedance between local system and protective device location
ZK: measured impedance
Φ: positive-sequence characteristic angle, i.e. [21-i.phi1_Reach] (i=1, 2, 3, 4, 5)
Circle A: transient characteristic
Circle B: steady-state characteristic shifting towards quadrant Ⅲ
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Circle C: steady-state characteristic shifting towards quadrant Ⅰ
As shown in Figure 3.7-22, the characteristic of the distance protection for a three-phase fault on a
system is an impedance circle cross the origin, and there is a voltage dead zone around the origin.
In order to eliminate the dead zone of the distance protection for a close up three-phase fault
memorized positive-sequence voltage is adopted as polarized voltage when the
positive-sequence voltage drops down to 15%Un or below. The memorized positive-sequence
voltages adopts 2 cycles pre-fault positvie-sequence voltage.
The transient (during process of memory) operation characteristic is shown as the impedance
circle A in the above figure. The circle takes Z ZD and -ZZS as diameter and thus the origin is within
the impedance circle. When three-phase fault happens in reverse direction, its transient
characteristic is shown in Figure 3.7-20, i.e. the distance protection has a clearly defined
directionality and no dead zone during the process of memory.
For phase-to-phase distance protection, if distance protection operates with memorized polarizing
voltage, this means a close up forward fault. When the memory fades out, the operation
characteristic will be reverse offset a little to enclose the origin as impedance circle B shown in
Figure 3.7-22 to ensure keeping operating of distance protection until the fault being cleared. If
distance protection does not operate with memorized polarizing voltage, it will be a close up
reverse fault. When the memory fades out, the operation characteristic will be forward offset not to
enclose the origin as impedance circle C shown in Figure 3.7-22, and the distance protection will
not mal-operate even if voltage is zero.
The distance protection with such design thoroughly eliminates the dead zone when three-phase
close up fault occurs. It also has favorable directivity and will not operate for a reverse three-phase
fault at busbar.
When receiving manual closing signal or 3-pole reclosing signal, the operation characteristic of
phase to phase distance protection will always shift in reverse direction. It is ensured to enclose
the origin of impedance and without dead zone for three-phase fault, i.e. the reverse shift
impedance circle B shown in Figure 3.7-22.
jX
B: 15° C: 30°
ZZD
A: 0°
D
R
-ZS
Figure 3.7-23 Shift impedance characteristic of zone 1 and zone 2
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The impedance characteristic of phase-to-ground distance protection is the circle with line
connecting ends of ZZD and -2ZS/3 as the diameter and that of phase-to-phase distance is the
circle with line connecting ends of ZZD and -ZS/2 as the diameter.
In order to prevent the transient overreach caused by the infeed power supply from the remote
end, the zero-sequence reactance line D is added. These measures have enhanced the capacity
against fault resistance when using distance protection in short lines.
NOTICE!
Phase current direction element is used as auxiliary direction element of distance
protection. Hence, the setting [RCA_OC] should be set correctly according to actual
system parameters if distance protection is enabled even if phase overcurrent
protection is disabled.
Zero-sequence current direction element is used as auxiliary direction element of
phase-to-ground distance element (mho characteristic). In order to prevent
phase-to-ground distance element from undesired operation due to revese direction
fault, the setting [RCA_ROC] should be set correctly according to actual system
parameters if phase-to-ground distance element is enabled even if earth fault protection
is disabled.
3.7.5.2 Function Block Diagram
21M
21.En
21Mi.On
21.Blk
21Mi.Op
21Mi.ZG.En
21Mi.ZP.En
21Mi.ZG.Blk
21Mi.ZP.Blk
21Mi.En_ShortDly
21Mi.Blk_ShortDly
21M1.En_Instant
3.7.5.3 I/O Signals
Table 3.7-5 I/O signals of distance protection (Mho)
No.
Input Signal
1
21.En
2
21.Blk
Description
Distance protection enabling input, it is triggered from binary input or
programmable logic etc.
Distance protection blocking input, it is triggered from binary input or
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programmable logic etc.
Zone i of phase-to-ground distance protection enabling input, default value is
3
21Mi.ZG.En
4
21Mi.ZG.Blk
5
21Mi.ZP.En
6
21Mi.ZP.Blk
7
21Mi.En_ShortDly
Enable accelerating zone i of distance protection (i=2, 3, 4, 5)
8
21Mi.Blk_ShortDly
Accelerating zone i of distance protection is disabled (i=2, 3, 4, 5)
9
21M1.En_Instant
Enable zone 1 of distance protection operates without time delay
No.
“1” (i=1, 2, 3, 4, 5)
Zone i of phase-to-ground distance protection blocking input, default value is
“0” (i=1, 2, 3, 4, 5)
Zone i of phase-to-phase distance protection enabling input, default value is
“1” (i=1, 2, 3, 4, 5)
Zone i of phase-to-phase distance protection blocking input, default value is
“0” (i=1, 2, 3, 4, 5)
Output Signal
Description
1
21Mi.On
Zone i of distance protection is enabled (i=1, 2, 3, 4, 5)
2
21Mi.Op
Zone i of distance protection operates (i=1, 2, 3, 4, 5)
3.7.5.4 Logic
SIG
21.En
&
21.Enable
SIG
21.Blk
Figure 3.7-24 Logic diagram of enabling distance protection (Mho)
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SIG 21.Enable
EN
&
&
[21M1.ZG.En]
21M1.ZG.Enable
&
SIG 21M1.ZG.En
SIG 21M1.ZG.Blk
EN
>=1
21M1.On
&
[21M1.ZP.En]
&
SIG 21M1.ZP.En
SIG 21M1.ZP.Blk
&
SIG VTS.Alm
EN
21M1.ZP.Enable
>=1
[VTS.En_Out_VT]
SIG 21M1.Rls_PSBR
SIG FD.Pkp
&
&
[21M1.ZG.t_Op]
SIG 21M1.ZG.Enable
SIG Flag.21M1.ZG
&
SIG LoadEnch.St (PG)
21M1.ZG.Op
&
>=1
21M1.Flg_PSBR
&
SIG LoadEnch.St (PP)
SIG FD.Pkp
>=1
&
SET 3I0>[FD.ROC.3I0_Set]
SIG Flag.21M1.ZP
0
&
[21M1.ZP.t_Op]
&
0
>=1
21M1.ZP.Op
&
SIG 21M1.ZP.Enable
SIG 21M1.En_Instant
SIG 21M1.ZG.Op
>=1
21M1.Op
SIG 21M1.ZP.Op
Figure 3.7-25 Logic diagram of distance protection (Mho zone 1)
Where:
21M1.Rls_PSBR: is the signal of power swing blocking releasing signal, please refer to Figure
3.7-43.
Flag.21M1.ZG means that measured impedance by zone 1 of phase-to-ground distance
protection is within the range determined by the setting [21M1.ZG.Z_Set].
Flag.21M1.ZP means that measured impedance by zone 1 of phase-to-phase distance protection
is within the range determined by the setting [21M1.ZP.Z_Set].
LoadEnch.St (PG) means that load trapezoid characteristic for distance element is enabled and
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measured phase-to-ground impedance into the load area.
LoadEnch.St (PP) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-phase impedance into the load area.
SIG
21.Enable
EN
[21Mi.ZG.En]
SIG
21Mi.ZG.En
SIG
21Mi.ZG.Blk
EN
[21Mi.ZP.En]
SIG
21Mi.ZP.En
SIG
21Mi.ZP.Blk
SIG
VTS.Alm
EN
[VTS.En_Out_VT]
SIG
21Mi.En_ShortDly
SIG
21Mi.Blk_ShortDly
EN
[21Mi.En_ShortDly]
SIG
21Mi.On
SIG
21Mi.Enable_ShortDly
SIG
21Mi.Rls_PSBR
SIG
21Mi.ZG.Enable
SIG
FD.Pkp
SIG
Flag.21Mi.ZG
SIG
LoadEnch.St (PG)
SET
3I0>[FD.ROC.3I0_Set]
SIG
Flag.21Mi.ZP
SIG
LoadEnch.St (PP)
SIG
21Mi.ZP.Enable
&
&
21Mi.ZG.Enable
&
>=1
21Mi.On
&
&
&
21Mi.ZP.Enable
>=1
&
&
21Mi.Enable_ShortDly
&
[21Mi.ZG.t_ShortDly]
0
>=1
21Mi.ZG.Op
&
&
[21Mi.ZG.t_Op]
0
&
>=1
&
21Mi.Flg_PSBR
&
&
[21Mi.ZP.t_Op]
&
0
>=1
21Mi.ZP.Op
&
SIG
FD.Pkp
SIG
21Mi.Enable_ShortDly
SIG
21Mi.ZG.Op
SIG
21Mi.ZP.Op
[21Mi.ZP.t_ShortDly]
0
>=1
21Mi.Op
Figure 3.7-26 Logic diagram of distance protection (Mho zone i)
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Where:
i=2, 3, 4, 5
21Mi.Rls_PSBR: is the signal of power swing blocking releasing signal, please refer to Figure
3.7-43.
Flag.21Mi.ZG means that measured impedance by zone x of phase-to-ground distance protection
is within the range determined by the setting [21Mi.ZG.Z_Set].
Flag.21Mi.ZP means that measured impedance by zone x of phase-to-phase distance protection
is within the range determined by the setting [21Mi.ZP.Z_Set].
3.7.5.5 Settings
Table 3.7-6 Settings of distance protection (Mho)
No.
Name
Range
Step
Unit
Remark
Direction option for zone i of distance
1
21-i.DirMode
0 or 1
protection (i=2, 3, 4, 5)
0
0: Forward
1: Reverse
Real component of zero-sequence
2
21-i.Real_K0
-4.000~4.000
0.001
compensation coefficient for zone i
(i=1, 2, 3, 4, 5)
Imaginary
3
21-i.Imag_K0
-4.000~4.000
0.001
component
zero-sequence
of
compensation
coefficient for zone i (i=1, 2, 3, 4, 5)
4
21-i.phi1_Reach
30~89
1
deg
Phase angle of
impedance for zone i (i=1, 2, 3, 4, 5)
Downward
5
21Mi.ZGQ.RCA
0~45
1
deg
positive-sequence
reactance
offset
line
angle
for
of
zone
the
i
of
phase-to-ground distance protection
(i=1, 2, 3, 4, 5)
Phase
6
21Mi.ZG.phi_Shift
0, 15 or 30
deg
shift
of
phase-to-ground
distance protection for zone i (i=1, 2, 3,
4, 5)
7
21Mi.ZP.phi_Shift
0, 15 or 30
deg
Phase shift of phase-to-phase distance
protection for zone i (i=1, 2, 3, 4, 5)
Impedance
8
21Mi.ZG.Z_Set
(0.000~4Unn)/In
0.001
ohm
setting
of
zone
i
of
phase-to-ground distance protection
(i=1, 2, 3, 4, 5)
Resistance
9
21Mi.ZGQ.R_Set
(0.000~4Unn)/In
0.001
ohm
setting
of
zone
i
of
phase-to-ground distance protection
(i=1, 2, 3, 4, 5)
10
21Mi.ZG.t_Op
0.000~10.000
0.001
s
3-46
Time
delay
of
zone
i
of
phase-to-ground distance protection
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Date: 2019-03-01
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
(i=1, 2, 3, 4, 5)
Short
11
21Mi.ZG.t_ShortDly
0.000~10.000
0.001
s
time
delay
of
zone
i
of
phase-to-ground distance protection
(i=2, 3, 4, 5)
Enabling/disabling
zone
i
of
phase-to-ground distance protection
12
21Mi.ZG.En
0 or 1
(i=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling
zone
i
of
quadrilateral phase-to-ground distance
13
21Mi.ZGQ.En
0 or 1
protection (i=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling
phase-to-ground
zone i of distance protection operation
14
21Mi.ZG.En_BlkAR
0 or 1
to block AR (i=1, 2, 3, 4, 5)
0: disable
1: enable
Impedance
15
21Mi.ZP.Z_Set
(0.000~4Unn)/In
0.001
ohm
setting
phase-to-phase
of
zone
distance
i
of
protection
(i=1, 2, 3, 4, 5)
16
21Mi.ZP.t_Op
0.000~10.000
0.001
s
Time delay of zone i of phase-to-phase
distance protection (i=1, 2, 3, 4, 5)
Short
17
21Mi.ZP.t_ShortDly
0.000~10.000
0.001
s
time
delay
phase-to-phase
of
zone
distance
i
of
protection
(i=2, 3, 4, 5)
Enabling/disabling
phase-to-phase
18
21Mi.ZP.En
0 or 1
zone
distance
i
of
protection
(i=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling
phase-to-phase
zone i of distance protection operation
19
21Mi.ZP.En_BlkAR
0 or 1
to block AR (i=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling
fixed
accelerate
zone i of distance protection (i=2, 3, 4,
20
21Mi.En_ShortDly
0 or 1
5)
0: disable
1: enable
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3.7.6 Quadrilateral Distance Protection
3.7.6.1 Impedance Characteristic
Features available with quadrilateral distance protection include 1 forward zone (zone 1)
phase-to-ground or phase-to-phase distance elements and 4 settable forward or reverse zones
(zone 2~5) phase-to-ground or phase-to-phase distance element. Each zone can respectively
enable or disable power swing blocking releasing. Quadrilateral distance protection will be
disabled when VT circuit fails.
1.
Forward distance element
Quadrilateral forward distance element characteristic is shown as follows:
jX
A
ZZD
θ
B
α
φ
φ
O
β
RZD
C
R
Figure 3.7-27 Quadrilateral forward distance element characteristics
Where:
ZZD: impedance setting in forward direction
RZD: resistance setting in forward direction
φ: line positive-sequence characteristic angle
α: the angle of directional line in the second quadrant, set by the setting [21Q.Ang_Alpha]
β: the angle of directional line in the fourth quadrant, fixed at 15 °
θ: downward offset angle of the reactance line AB
2.
Reverse distance element
Zone 2, 3, 4, 5 can be set as reverse direction by the setting [21-i.DirMode] (i=2, 3, 4, 5). When a
fault occurs on the busbar at the back, reverse distance element is provided to clear it with definite
time delay and is used as backup protection for reverse busbar fault.
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jX
C
RZD
O
β
φ
R
φ
α
B
θ
ZZD
A
Figure 3.7-28 Quadrilateral reverse distance element characteristic
Where:
ZZD: impedance setting in reverse direction
RZD: resistance setting in reverse direction
φ: line positive-sequence characteristic angle
α: the angle of directional line, set by the setting [21Q.Ang_Alpha]
β: the angle of directional line, fixed at 15°
θ: downward offset angle of the reactance line AB
For quadrilateral distance protection, the reactance line should consider downward offset angle θ
as shown in Figure 3.7-27 and Figure 3.7-28. According to system status, the downward offset
angle can be independently set for phase-to-ground distance element and phase-to-phase
distance element. The downward offset angle of all zones can be settable by the corresponding
settings [21Qi.ZG.RCA] and [21Qi.ZP.RCA]. (i=1, 2, 3, 4, 5). Phase-to-ground distance protection
is controlled by the fault detector based on residual current.
NOTICE!
Phase current direction element is used as auxiliary direction element of distance
protection. Hence, the setting [RCA_OC] should be set correctly according to actual
system parameters if distance protection is enabled even if phase overcurrent
protection is disabled.
Zero-sequence current direction element is used as auxiliary direction element of zone
1 of phase-to-ground distance element (quad characteristic). In order to prevent zone 1
of phase-to-ground distance element from undesired operation due to revese direction
fault, the setting [RCA_ROC] should be set correctly according to actual system
parameters if zone 1 of phase-to-ground distance element is enabled even if earth fault
protection is disabled.
Negative-sequence current direction element is used as the direction element of
phase-to-ground and phase-to-phase distance element (quad characteristic) for
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asymmetric fault. In order to prevent phase-to-ground and phase-to-phase distance
element from undesired operation due to revese direction fault, the setting
[RCA_NegOC] should be set correctly according to actual system parameters.
3.7.6.2 Function Block Diagram
21Q
21.En
21Qi.On
21.Blk
21Qi.Op
21Qi.ZG.En
21Qi.ZP.En
21Qi.ZG.Blk
21Qi.ZP.Blk
21Qi.En_ShortDly
21Qi.Blk_ShortDly
21Q1.En_Instant
3.7.6.3 I/O Signals
Table 3.7-7 I/O signals of distance protection (Quad)
No.
Input Signal
Description
Distance protection enabling input, it is triggered from binary input or
1
21.En
2
21.Blk
3
21Qi.ZG.En
4
21Qi.ZG.Blk
5
21Qi.ZP.En
6
21Qi.ZP.Blk
7
21Qi.En_ShortDly
Enable accelerating zone i of distance protection (i=2, 3, 4, 5)
8
21Qi.Blk_ShortDly
Accelerating zone i of distance protection is disabled (i=2, 3, 4, 5)
9
21Q1.En_Instant
Enable zone 1 of distance protection operates without time delay
No.
programmable logic etc.
Distance protection blocking input, it is triggered from binary input or
programmable logic etc.
Zone i of phase-to-ground distance protection enabling input, default value is
“1” (i=1, 2, 3, 4, 5)
Zone i of phase-to-ground distance protection blocking input, default value is
“0” (i=1, 2, 3, 4, 5)
Zone i of phase-to-phase distance protection enabling input, default value is “1”
(i=1, 2, 3, 4, 5)
Zone i of phase-to-phase distance protection blocking input, default value is “0”
Output Signal
(i=1, 2, 3, 4, 5)
Description
1
21Qi.On
Zone i of distance protection is enabled (i=1, 2, 3, 4, 5)
2
21Qi.Op
Zone i of distance protection operates (i=1, 2, 3, 4, 5)
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3.7.6.4 Logic
SIG
21.En
&
21.Enable
SIG
21.Blk
Figure 3.7-29 Logic diagram of enabling distance protection (Quad)
SIG
21.Enable
EN
[21Q1.ZG.En]
SIG
21Q1.ZG.En
SIG
21Q1.ZG.Blk
&
&
21Q1.ZG.Enable
&
>=1
21Q1.On
&
EN
[21Q1.ZP.En]
SIG
21Q1.ZP.En
SIG
21Q1.ZP.Blk
SIG
VTS.Alm
EN
[VTS.En_Out_VT]
SIG
21Q1.ZG.Enable
SIG
FD.Pkp
SIG
LoadEnch.St (PG)
SET
3I0>[FD.ROC.3I0_Set]
SIG
Flag.21Q1.ZG
SIG
21Q1.Rls_PSBR
SIG
FD.Pkp
SIG
21Q1.ZP.Enable
SIG
LoadEnch.St (PP)
SIG
Flag.21Q1.ZP
SIG
21Q1.En_Instant
SIG
21Q1.ZG.Op
SIG
21Q1.ZP.Op
&
&
21Q1.ZP.Enable
>=1
&
&
&
[21Q1.ZG.t_Op]
&
0
>=1
21Q1.ZG.Op
&
>=1
21Q1.Flg_PSBR
&
&
&
&
[21Q1.ZP.t_Op]
0
>=1
&
21Q1.ZP.Op
>=1
21Q1.Op
Figure 3.7-30 Logic diagram of distance protection (Quad zone 1)
Where:
21Q1. Rls_PSBR: is the signal of power swing blocking releasing signal, please refer to Figure
3.7-43.
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Flag.21Q1.ZG means that measured impedance by zone 1 of phase-to-ground distance protection
is within the range determined by the settings [21Q1.ZG.Z_Set] and [21Q1.ZG.R_Set].
Flag.21Q1.ZP means that measured impedance by zone 1 of phase-to-phase distance protection
is within the range determined by the settings [21Q1.ZP.Z_Set] and [21Q1.ZP.R_Set].
LoadEnch.St (PG) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-ground impedance into the load area.
LoadEnch.St (PP) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-phase impedance into the load area.
SIG
21.Enable
EN
[21Qi.ZG.En]
SIG
21Qi.ZG.En
SIG
21Qi.ZG.Blk
EN
[21Qi.ZP.En]
SIG
21Qi.ZP.En
SIG
21Qi.ZP.Blk
SIG
VTS.Alm
EN
[VTS.En_Out_VT]
SIG
21Qi.En_ShortDly
SIG
21Qi.Blk_ShortDly
EN
[21Qi.En_ShortDly]
SIG
21Qi.On
&
&
21Qi.ZG.Enable
&
>=1
21Qi.On
&
&
&
21Qi.ZP.Enable
>=1
&
&
21Qi.Enable_ShortDly
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SIG 21Qi.Enable_ShortDly
SIG 21Qi.ZG.Enable
&
&
SIG FD.Pkp
[21Qi.ZG.t_ShortDly] 0
&
>=1
21Qi.ZG.Op
&
SET 3I0>[FD.ROC.3I0_Set]
&
[21Qi.ZG.t_Op]
0
SIG LoadEnch.St (PG)
SIG Flag.21Qi.ZG
>=1
SIG 21Qi.Rls_PSBR
21Qi.Flg_PSBR
SIG LoadEnch.St (PP)
&
&
SIG Flag.21Qi.ZP
&
[21Qi.ZP.t_ShortDly] 0
&
SIG 21Qi.ZP.Enable
>=1
21Qi.ZP.Op
&
[21Qi.ZP.t_Op]
0
SIG FD.Pkp
SIG 21Qi.ZG.Op
>=1
21Qi.Op
SIG 21Qi.ZP.Op
Figure 3.7-31 Logic diagram of distance protection (Quad zone i)
Where:
i=2, 3, 4, 5
21Qi.Z.Rls_PSBR: is the signal of power swing blocking releasing signal, please refer to Figure
3.7-43.
Flag.21Qi.ZG means that measured impedance by zone x of phase-to-ground distance protection
is within the range determined by the settings [21Qi.ZG.Z_Set] and [21Qi.ZG.R_Set].
Flag.21Qi.ZP means that measured impedance by zone x of phase-to-phase distance protection
is within the range determined by the settings [21Qi.ZP.Z_Set] and [21Qi.ZP.R_Set].
3.7.6.5 Settings
Table 3.7-8 Settings of distance protection (Quad)
No.
1
Name
21Q.Ang_Alpha
Range
5~30
Step
Unit
1
deg
Remark
The angle of directional line
Direction option for zone i of distance
2
21-i.DirMode
0 or 1
0
protection (i=2, 3, 4, 5)
0: Forward
1: Reverse
Real component of zero-sequence
3
21-i.Real_K0
-4.000~4.000
0.001
compensation coefficient for zone i
(i=1, 2, 3, 4, 5)
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No.
Name
Range
Step
Unit
Remark
Imaginary
4
21-i.Imag_K0
-4.000~4.000
0.001
component
zero-sequence
of
compensation
coefficient for zone i (i=1, 2, 3, 4, 5)
5
21-i.phi1_Reach
30~89
1
deg
Phase angle of positive-sequence
impedance for zone i (i=1, 2, 3, 4, 5)
Downward
6
21Qi.ZG.RCA
0~45
1
deg
reactance
offset
line
angle
for
of
zone
the
i
of
phase-to-ground distance protection
(i=1, 2, 3, 4, 5)
Impedance
7
21Qi.ZG.Z_Set
(0.000~4Unn)/In
0.001
ohm
setting
of
zone
i
of
phase-to-ground distance protection
(i=1, 2, 3, 4, 5)
Resistance
8
21Qi.ZG.R_Set
(0.000~4Unn)/In
0.001
ohm
setting
of
zone
i
of
phase-to-ground distance protection
(i=1, 2, 3, 4, 5)
Time
9
21Qi.ZG.t_Op
0.000~10.000
0.001
s
delay
of
zone
i
of
phase-to-ground distance protection
(i=1, 2, 3, 4, 5)
Short
10
21Qi.ZG.t_ShortDly
0.000~10.000
0.001
s
time
delay
of
zone
i
of
phase-to-ground distance protection
(i=2, 3, 4, 5)
Enabling/disabling
zone
i
of
phase-to-ground distance protection
11
21Qi.ZG.En
0 or 1
(i=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling
phase-to-ground
zone i of distance protection operation
12
21Qi.ZG.En_BlkAR
0 or 1
to block AR (i=1, 2, 3, 4, 5)
0: disable
1: enable
Downward
13
21Qi.ZP.RCA
0~45
1
deg
reactance
offset
line
phase-to-phase
angle
for
of
zone
distance
the
i
of
protection
(i=1, 2, 3, 4, 5)
Impedance
14
21Qi.ZP.Z_Set
(0.000~4Unn)/In
0.001
ohm
setting
phase-to-phase
of
distance
zone
i
of
protection
(i=1, 2, 3, 4, 5)
Resistance
15
21Qi.ZP.R_Set
(0.000~4Unn)/In
0.001
ohm
setting
phase-to-phase
of
distance
zone
i
of
protection
(i=1, 2, 3, 4, 5)
16
21Qi.ZP.t_Op
0.000~10.000
0.001
s
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Date: 2019-03-01
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
Short
17
21Qi.ZP.t_ShortDly
0.000~10.000
0.001
s
time
delay
of
zone
i
of
phase-to-ground distance protection
(i=2, 3, 4, 5)
Enabling/disabling
phase-to-phase
18
21Qi.ZP.En
0 or 1
zone
distance
i
of
protection
(i=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling
phase-to-phase
zone i of distance protection operation
19
21Qi.ZP.En_BlkAR
0 or 1
to block AR (i=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling
fixed
accelerate
zone i of distance protection (i=2, 3, 4,
20
21Qi.En_ShortDly
0 or 1
5)
0: disable
1: enable
3.7.7 Pilot Distance Zone
3.7.7.1 Impedance Characteristic
An independent pilot zone distance protection is used for PUTT and POTT scheme. There is also
a reverse pilot distance element available as an option for application of POTT on weak power
source system.
Pilot.Z_Rev_B
Pilot.Z_Set_B
M
EM
Pilot.Z_Rev_A
A
B
N
C
D
Pilot.Z_Set_A
Figure 3.7-32 Protected zone of pilot distance protection
The operation characteristic of pilot zone is same as that of zone 2, including mho and
quadrilateral characteristic.
When an internal fault occurs, distance protection at weak source end may not operate due to
small fault current. Thus, a reverse distance element is provided to coordinate with the
independent pilot distance protection to implement weak infeed logic, ensure pilot distance
protection can operate to send signal or trip in the weak end. The operation characteristic is shown
in Figure 3.7-33. The reverse weak infeed distance element is forward offset with 1/4 of the
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reverse setting to enclose the origin.
Operation characteristics of pilot reverse weak infeed element distance are shown as below.
jX
jX
B
β
21Q.Pilot.Z_Rev/4
21M.Pilot.Z_Rev/4
21Q.Pilot.R_Rev
o
Φ
φ
R
φ
R
α
C
θ
21Q.Pilot.Z_Rev
21M.Pilot.Z_Rev
A
Figure 3.7-33 Pilot reverse weak infeed element
Where:
Φ: positive-sequence characteristic angle, i.e. [21.Pilot.phi1_Reach]
α: the angle of directional line, set by the setting [21Q.Ang_Alpha]
β: the angle of directional line, fixed at 15°
θ: tilted angle of the reactance line AC, fixed at 12°
3.7.7.2 Logic
SIG
FD.Pkp
SIG
21.Enable
SIG
21M.Pilot.Rls_PSBR
SET
Flag.21M.Pilot.Z (PG)
SIG
LoadEnch.St (PG)
SET
Flag.21M.Pilot.Z (PP)
SIG
LoadEnch.St (PP)
&
&
&
ZPilotP
&
>=1
21M.Zpilot.Flag_PSBR
&
Figure 3.7-34 Logic diagram of pilot distance zone (Mho characteristic)
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SIG
FD.Pkp
SIG
21.Enable
SIG
21Q.Pilot.Rls_PSBR
SET
Flag.21Q.Pilot.Z (PG)
SIG
LoadEnch.St (PG)
SET
Flag.21Q.Pilot.Z (PP)
SIG
LoadEnch.St (PP)
&
&
&
ZPilotP
&
>=1
21Q.Zpilot.Flag_PSBR
&
Figure 3.7-35 Logic diagram of pilot distance zone (Quad characteristic)
Where:
21M.Pilot.Rls_PSBR, 21Q.Pilot.Rls_PSBR: Please refer to Figure 3.7-43.
LoadEnch.St (PG) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-ground impedance into the load area.
LoadEnch.St (PP) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-phase impedance into the load area.
Flag.21Q.Pilot.Z (PG) means that measured impedance by phase-to-ground distance element is
within the range determined by the setting [21Q.Pilot.Z_Set]. (Quad characteristic)
Flag.21Q.Pilot.Z (PP) means that measured impedance by phase-to-phase distance element is
within the range determined by the setting [21Q.Pilot.Z_Set]. (Quad characteristic)
Flag.21M.Pilot.Z (PG) means that measured impedance by phase-to-ground distance element is
within the range determined by the setting [21M.Pilot.Z_Set]. (Mho characteristic)
Flag.21M.Pilot.Z (PP) means that measured impedance by phase-to-phase distance element is
within the range determined by the setting [21M.Pilot.Z_Set]. (Mho characteristic)
3.7.7.3 Settings
Table 3.7-9 Settings of pilot distance zone
No.
Name
Range
Step
Unit
Remark
Real component of zero-sequence
1
21.Pilot.Real_K0
30.00~89.00
0.01
deg
compensation
coefficient
for
pilot
distance protection
Imaginary
2
21.Pilot.Imag_K0
-4.000~4.000
0.001
component
zero-sequence
of
compensation
coefficient for pilot distance protection
Phase angle of positive-sequence
3
21.Pilot.phi1_Reach
-4.000~4.000
0.001
impedance
for
pilot
distance
protection
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No.
Name
Range
Step
Unit
4
21M.Pilot.Z_Set
(0.000~4Unn)/In
0.001
ohm
5
21M.Pilot.R_Set_Quad
(0.000~4Unn)/In
0.001
ohm
6
21Q.Pilot.Z_Set
(0.000~4Unn)/In
0.001
ohm
Remark
Impedance setting of pilot distance
protection (Mho characteristic)
Resistance setting of pilot distance
protection (Mho characteristic)
Impedance setting of pilot distance
protection (Quad characteristic)
Impedance setting of pilot distance
7
21M.Pilot.Z_Rev
(0.000~4Unn)/In
0.001
ohm
protection in reverse direction (Mho
characteristic)
Enabling/disabling
characteristic
8
21M.Pilot.En_Z_Quad
0 or 1
of
quadrilateral
phase-to-ground
distance protection
0: disable
1: enable
Impedance setting of pilot distance
9
21Q.Pilot.Z_Rev
(0.000~4Unn)/In
0.001
ohm
protection in reverse direction (Quad
characteristic)
10
21Q.Pilot.R_Set
(0.000~4Unn)/In
0.001
ohm
Resistance setting of pilot distance
protection (Quad characteristic)
Resistance setting of pilot distance
11
21Q.Pilot.R_Rev
(0.000~4Unn)/In
0.001
ohm
protection in reverse direction (Quad
characteristic)
3.7.8 Out-of-step Protection
3.7.8.1 General Application
When the disturbance happens to the power system because of some reason (such as short
circuit, fault clear, power supply injecting or separating, etc.), the phase angle difference of the
electric potential between the synchronous generators of parallel operation will change with time,
and the voltage of each node and the current of each circuit in the system also change with time,
this phenomenon is called oscillation. The oscillation that can keep system stably and
synchronously operate is called synchronous oscillation, and that leads to lose synchronization
and that the system can't normally operate is called asynchronous oscillation.
For the power grid of loss synchronous, the voltage of each node in the tie line that synchronous or
asynchronous oscillation happens to will oscillate periodically, and where the voltage oscillation is
the most violent in each tie line is the center of synchronous or asynchronous oscillation. In
general, the voltage oscillation is more violent more close to the oscillation center. Out-of-step
center is the point where the lowest voltage appears in the tie line of asynchronous oscillation in
the process of out-of-step oscillation, i.e., the oscillation center of the tie line of asynchronous
oscillation. The phase angle of bus voltage difference on either side of out-of-step center will
change within 0°~180°~360° periodically. Considering the selectivity, the separation should be
performed within 2~3 out-of-step period or the corresponding time delay after the system is out of
step, otherwise the out-of-step oscillation among multiple generators may is developed, further
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expanding the accident, so as to cause system separation even collapse accident. So when the
out-of-step operation time or oscillation times is greater than specified value, out-of-step protection
should operate to separate.
3.7.8.2 Function Description
In the event that the interconnected system is out-of-step, the system can be reduced as a
dual-machine system as shown in Figure 3.7-36.
EM
U
EN
I
ZLine
Figure 3.7-36 Dual-machine equivalent system
For the sake of easy analysis, assumptions have to be made as follows:
1.
The potential of the two machines are E M and EN respectively, and their amplitude are both
equal to E1.
2.
The equivalent impedance angle of system is 90°
Taking EN as reference vector, whose initial phase angle is 0°and angle velocity is ω. At the side
M, the initial phase angle of equivalent potential E M is α (i.e., during normal operation condition,
the system′s power angle δ is α), whose increment of the angle velocity is Δω relative to side N, so
EN  E1  cos(  t )
EM  E1  cos((  )  t   )
Suppose the power angle between both sides of the system is
    t  
The equivalent system vector diagram of Figure 3.7-36 is illustrated in Figure 3.7-37.
I
U
EM
U cos 
EN
U SCV
E1
E1
 
2
Figure 3.7-37 Dual-machine equivalent system
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Where:
USCV is the voltage of oscillation center
U is the measured voltage by the device
As shown in Figure 3.7-37, the voltage of oscillation center USCV is:

U SCV  U cos   E1  cos( )
2
In the case that the system is in synchronous condition, Δω=0, the voltage of oscillation center
maintains be unchanged, that is:

U SCV  cos( )
2
Make calculus for the voltage of oscillation center,
d (U SCV )
E
 d ( )
  1  sin( ) 
dt
2
2
dt
The above equation describe the relationship between the voltage change rate of oscillation
center and system slip frequency
d ( )
, which indicates the voltage variation of oscillation center
dt
is independent of system impedance.
When the power angle is 180°, the voltage variation of oscillation center is maximum, and when
the power angle is 0°, the voltage variation of oscillation center is minimum.
In the case that the system is in out-of-step condition, the voltage of oscillation center varies
periodically with the oscillation cycle as 180°, that is:
If the value of Δω is larger than 0, namely accelerating out-of-step condition, the variation trend of
δ is 0°－360°(0°)－360°, the variation curve of oscillation center voltage is shown in Figure 3.7-38
(a)
If the value of Δω is less than 0, namely decelerating out-of-step condition, the variation trend of δ
is 360°－0°(360°)－0°, the variation curve of oscillation center voltage is shown in Figure 3.7-38
(b)
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U
U
1
1
t
0
-1
t
0
-1
(a)
(b)
Figure 3.7-38 Variation curve of oscillation center voltage
According to the above analysis, it can be shown that there is certain functional relation between
the oscillation center voltage and power angle δ, thus the oscillation center voltage (Ucosφ) can
be used to reflect the variation of power angle. Power angle varies continuously as an
electrical quantity. As a result, the oscillation center voltage varies continuously during
out-of-step oscillation, crossing the zero point. However, sudden variation or discontinuous
change is a distinguished feature of oscillation center voltage during fault occurrence or
clearance. During synchronous oscillation, the oscillation center voltage also varies
continuously but it does not cross the zero point. Therefore, the oscillation center voltage can
be used to discriminate among out-of-step oscillation, short-circuit fault and synchronous
oscillation.
The variation range of oscillation center voltage (Ucosφ) can be divided into seven zones on the
variation plane, as shown in Figure 3.7-39.
From the above analysis, the variation rules of oscillation center voltage (Ucosφ) during
out-of-step oscillation are as follows:
1. During accelerating out-of-step condition, the variation rule of Ucosφ is 0 – 1 – 2 – 3 – 4 – 5 –
6–0
2. During decelerating out-of-step condition, the variation rule of Ucosφ is 0 – 6 – 5 – 4 – 3 – 2 –
1–0
U
1
U
1
0
2
3
0
-1
4
0
1
1
2
3
t
0
5
5
6
6
0
-1
t
4
0
Figure 3.7-39 The variation rule of oscillation center voltage
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If the oscillation center voltage varies as the above mentioned rules, the relay consider it as
out-of-step condition and issues tripping command after the time delay (i.e., the setting
[78.N_Limit]), performing separation.
The above analysis is based on the assumption that system impedance angle is 90°, while in
practical system it is not, thus angle compensation is required. As shown in Figure 3.7-40, setting
the system impedance angle φ L in the device, the angle compensation is made to the oscillation
center voltage,
U SCV  U cos(  90   L )
I'
EM
EN
U
U cos 
 
2
Figure 3.7-40 Vector diagram of the oscillation center voltage
In order to locate the distance between the oscillation center and where the device is equipped,
setting impedance measurement element is used to confirm the operation range of separation
device, the operation characteristic of zone relay based on impedance discrimination is shown
in Figure 3.7-41.
EM
ZM
Z L ine
ZN
EN
I
Z Re v Relay
U
Z Fwd
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ZN
jX
Z Fwd

R
δ
Z Re v
O
ZM
Figure 3.7-41 Operation characteristic of zone detector element
Where:
ZM and ZN are respective system impedances.
ZFwd is the impedance from zone relay location to side-N system
ZRev is the impedance from zone relay location to side-M system
The measured impedance is the impedance of phase-BC, zone relay meet the operation criterion
when the measured impedance is within the range of operation characteristic. Out-of-step
protection will operate when both zone relay and out-of-step relay operate.
In order to prevent out-of-step protection from being initiated under normal conditions, the device
calculates in real-time the voltage vector of two points (ZFwd and ZRev) based on measured voltage
and current, so as to calculate the phase angle between two voltage (δ), which participates in logic
discrimination of out-of-step protection.
3.7.8.3 Function Block Diagram
78
78.En
78.On
78.Blk
78.St
78.Clr_Counter
78.St_Zone
78.Op
3.7.8.4 I/O Signals
Table 3.7-10 I/O signals of out-of-step protection
No.
1
Input Signal
78.En
Description
Out-of-step protection enabling input, it is triggered from binary input or
programmable logic etc.
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2
78.Blk
3
78.Clr_Counter
No.
Out-of-step protection blocking input, it is triggered from binary input or
programmable logic etc.
Clear the counter
Output Signal
Description
1
78.On
Out-of-step protection is enabled.
2
78.St
Out-of-step protection starts.
3
78.St_Zone
4
78.Op
Zone detector element of out-of-step protection starts, whose operation
characteristic is shown as Figure 3.7-41.
Out-of-step protection operates.
3.7.8.5 Logic
SIG
78.En
EN
[78.En]
SIG
78.Blk
SIG
VTS.Alm
SIG
Ia>0.12In
SIG
Ib>0.12In
SIG
Ic>0.12In
&
&
78.On
&
t1
t2
78.St
&
&
&
SIG |δ|>[78.phi_Start]
SIG
U1<0.95Un
SIG
8>dδ/dt>0.2
SIG
Ucosφ from + to -
&
&
Counter>[78.N_Limit]
>=1
SIG 78.Clr_Counter
&
Counter>[78.N_Limit]
SIG
Ucosφ - to +
EN
[78.En_Trp]
SIG
δ<[78.phi_Trp]
&
78.Op
&
>=1
SIG
78.St_Zone
SIG
78.St
&
Figure 3.7-42 Logic diagram of out-of-step protection
Where:
U1 is positive-sequence voltage.
t1 is the pickup time delay of discriminating oscillation, internal fixed value is 40ms
t2 is the dropoff time delay of discriminating oscillation, internal fixed value is 3s
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In order to prevent out-of-step protection from maloperation under normal conditions or faulty
conditions, the system will be think as oscillation only the following conditions are all met.
1.
Measured positive-sequence voltage (U1) is smaller than 0.95Un.
2.
Three phase currents are all greater than 0.12In.
3.
The change rate of power angle (dδ/dt) is within 0.2~8.
4.
The power angle (δ) is greater than the minimum start angle ([78.Phi_Start]).
3.7.8.6 Settings
Table 3.7-11 Settings of out-of-step protection
No.
Name
Range
Step
Unit
Remark
Enabling/disabling out-of-step protection
1
78.En
0 or 1
0: disable
1: enable
Enabling/disabling out-of-step protection
2
78.En_Trp
operate to trip
0 or 1
0: disable
1: enable
3
78.Z_Fwd
(0.000~4Unn)/In
0.001
ohm
4
78.Z_Rev
(0.000~4Unn)/In
0.001
ohm
5
78.phi1_Reach
30.00~89.00
0.01
deg
The forward impedance setting of zone
detector element
The reversal impedance setting of zone
detector element
The system impedance angle
The minimum start angle, which generally
6
78.phi_Start
0~180
1
deg
should be greater than maximum load
angle.
It is the maximum tripping angle after
out-of-step protection operating, which is
7
78.phi_Trp
0~180.00
0.01
deg
used to prevent the circuit breaker from
incorrect operation due to too large current
during tripping. It is generally set based on
the breaking capacity of circuit breaker.
8
78.N_Limit
1~20
The number setting of out-of-step cycle,
1
and it is set as 2~3 generally
3.7.9 Power Swing Blocking Releasing
When power swing occurs on the power system, the impedance measured by the distance
measuring element may vary from the load impedance area into the operating zone of the
distance element. The distance measuring element may operate due to the power swing occurs in
many points of interconnected power systems. To keep the stability of whole power system,
tripping due to operation of the distance measuring element during a power swing is generally not
allowed. Our distance protection adopts power swing blocking releasing to avoid maloperation
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resulting from power swing. In another word, distance protection is blocked all along under the
normal condition and power swing when the respective logic settings are enabled. Only when fault
(internal fault or power swing with internal fault) is detected, power swing blocking for distance
protection is released by PSBR element.
Power swing blocking for distance element will be released if any of the following PSBR elements
operates. Each distance zone elements has respective setting for selection this function.

Fault detector PSBR element (FD PSBR)

Unsymmetrical fault PSBR element (UF PSBR)

Symmetrical fault PSBR element (SF PSBR)
1.
Fault detector PSBR element
If any of the following condition is matched, FD PSBR will operate for 160ms.
Positive sequence current is lower than the setting [21M.I_PSBR] or [21Q.I_PSBR] before general
fault detector element operates.
As shown in figure below, assuming that normal load impedance locates at position 1 and the
impedance locates at position 2 when positive-sequence current is lower than the setting
[21M.I_PSBR] or [21Q.I_PSBR], it means FD operates between point 1 and point 2 if operation
condition for FD PSBR mentioned above is fulfilled (point 3 as an example), and then FD PSBR
will operate for 160ms.
[21.I_PSBR]
FD
Normal load
impedance
Point 1
Point 3
Point 2
2.
Unsymmetrical fault PSBR element
The operation criterion:
I0+I2>m×I1
The “m”, an empirical value, is internal fixed coefficient which can ensure UF PSBR operation
during power swing with internal unsymmetrical fault, while no operation during power swing or
power swing with external fault.
This decision mainly utilizes the "discrepancy" that there is no negative-sequence or
zero-sequence current during power swing, and there are negative-sequence and zero-sequence
currents in case of asymmetric fault. In addition, value of m is used to differentiate internal
asymmetric fault and external asymmetric fault in case of power swing.
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 In case of power swing or both power swing and external fault, asymmetric fault discriminating
element will not operate and distance protection will be blocked:
In case of power swing but no fault, I0 and I2 are near zero, but I1 is very large. Asymmetric fault
discriminating element will not operate.
In case of both power swing and external fault, if center of power swing is in scope of protection,
both phase-to-phase and grounding impedance relays may operate. At this time, selection of
value of m is used to ensure no operation of asymmetric fault discriminating element, blocking of
distance protection, and no incorrect operation without selectivity. If power swing center is not on
this line, distance protection will not operate incorrectly without selectivity due to power swing.
 In case of internal asymmetric fault, asymmetric fault discriminating element operates and
distance protection will be release to clear internal fault:
In case of both power swing and internal fault, if at the instant of short circuit, system electric
potential angle is not laid out, asymmetric fault discriminating element will operate at once. If at the
instant of short circuit, system electric potential angle is laid out, asymmetric fault discriminating
element will operate when system angle gradually decreases, or local side tripping may be
activated after immediate operation of opposite side asymmetric fault discriminating element and
releasing of distance protection tripping. In case of normal internal asymmetric phase-to-phase or
grounding fault in the system, relatively large zero-sequence or negative-sequence component will
exist. At this time, the above equation is true and distance protection will be released.
3.
Symmetrical fault PSBR element
If a three-phase fault occurs and FD PSBR is invalid (160ms after FD operates), neither FD PSBR
nor UF PSBR will be able to release the distance protection. Thus, SF PSBR is provided for this
case specially. This detection is based on measuring the voltage at power swing center, during
power swing, U1cosΦ will constantly change periodically.
UOS=U1×COSΦ
Where:
Φ: the angle between positive sequence voltage and current
U1: the positive sequence voltage
As shown in the figure below, assume system connection impedance angle of 90°, current vector
will be perpendicular to the line connecting E M and EN, and have the same phase as power swing
center voltage. During normal operation of system or power swing, U1cosΦ just reflects
positive-sequence voltage of power swing center. In case of 3-phase short circuit, U1cosΦ is
voltage drop on arc resistor, transition resistance is arc resistance, and voltage drop on arc resistor
is less than 5%UN. In actual system, line impedance angle is not 90°. Through compensation of
angle Φ, power swing center voltage can be measured accurately. After compensation, power
swing center voltage is U1cos(Φ＋90o－ΦL), where ΦL is line impedance angle.
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EM
I
U
EN
UOS
Φ
During power swing, power swing center voltage U 1cosΦ has the following characteristics: When
electric potential phase angle difference between power supplies at two sides is 180o, U1cosΦ＝0
and change rate dU1cosΦ/dt is the maximum. When this phase angle difference is near 0 o, power
swing center voltage change rate dU 1cosΦ/dt is the minimum. During short circuit, U 1cosΦ
remains unchanged and dU1cosΦ/dt＝0. However, in early stage of short circuit when normal state
enters short circuit state, dU1cosΦ/dt is very large. Therefore, use of dU 1cosΦ/dt solely to
differentiate power swing and short circuit is not complete.
For these reasons, the method to release distance protection on condition that power swing center
voltage U1cosΦ is less than a setting and after a short delay can be used as symmetric fault
discriminating element. This element can accurately differentiate power swing and 3-phase short
circuit fault, and constitute a complete power swing blocking scheme with other elements. The
element to open distance protection if U 1cosΦ is less than a certain setting and after a delay is
easy to realize and has short delay, and can trip fault more quickly and accurately trip 3-phase
short circuit fault during power swing.
The criterion of SF PSBR element comprises the following two parts:

when -0.03UN<UOS<0.08UN, the SF PSBR element will operate after 150ms.

when -0.1UN<UOS<0.25UN, the SF PSBR element will operate after 500ms.
The second criterion is a backup of the first criterion allowing longer monitoring period of voltage
variation.
To reduce the time delay for SF PSBR element during power swing, the change rate of voltage at
power swing center is also used which can release SF PSBR element quickly for the fault occurred
during power swing. The typical release time is less than 60ms.
3.7.9.1 Function Block Diagram
21Mi
21Mi.En_PSBR
21Mi.Rls_PSBR
21Mi.Blk_PSBR
21M.Pilot.Rls_PSBR
21M.Pilot.En_PSBR
21M.Pilot.Blk_PSBR
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21Qi
21Qi.En_PSBR
21Qi.Rls_PSBR
21Qi.Blk_PSBR
21Q.Pilot.Rls_PSBR
21Q.Pilot.En_PSBR
21Q.Pilot.Blk_PSBR
3.7.9.2 I/O Signals
Table 3.7-12 I/O signals of PSBR
No.
Input Signal
1
21Mi.En_PSBR
2
21Qi.En_PSBR
3
21Mi.Blk_PSBR
4
21Qi.Blk_PSBR
5
21M.Pilot.En_PSBR
6
21M.Pilot.Blk_PSBR
7
21Q.Pilot.En_PSBR
8
21Q.Pilot.Blk_PSBR
No.
Output Signal
Description
Enabling power swing blocking releasing of zone i (Mho characteristic, i=1, 2, 3,
4, 5)
Enabling power swing blocking releasing of zone i (Quad characteristic, i=1, 2,
3, 4, 5)
Blocking power swing blocking releasing of zone i (Mho characteristic, i=1, 2, 3,
4, 5)
Blocking power swing blocking releasing of zone i (Quad characteristic, i=1, 2,
3, 4, 5)
Enabling power swing blocking releasing of pilot distance zone (Mho
characteristic)
Blocking power swing blocking releasing of pilot distance zone (Mho
characteristic)
Enabling power swing blocking releasing of pilot distance zone (Quad
characteristic)
Blocking power swing blocking releasing of pilot distance zone (Quad
characteristic)
Description
1
21Mi.Rls_PSBR
PSBR operates to release zone i (Mho characteristic, i=1, 2, 3, 4, 5)
2
21Qi.Rls_PSBR
PSBR operates to release zone i (Quad characteristic, i=1, 2, 3, 4, 5)
3
21M.Pilot.Rls_PSBR
PSBR operates to release pilot distance zone (Mho characteristic)
4
21Q.Pilot.Rls_PSBR
PSBR operates to release pilot distance zone (Quad characteristic)
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3.7.9.3 Logic
SIG
21Mi.En_PSBR
SIG
21Mi.Blk_PSBR
SIG
FD.Pkp
SIG
21Mi.Flg_PSBR
SIG
21Mi.Enable_PSBR
EN
[21Mi.En_PSBR]
SIG
Symmetrical |U1cosΦ |<
&
21Mi.Enable_PSBR
&
&
>=1
&
t
0ms
Unblocking for SF
21Mi.Rls_PSBR
>=1
>=1
&
SIG
Unsymmetrical |I0|+|I2|>
Unblocking for UF
SIG
21Mi.Flg_PSBR
SET
I1>[21M.I_PSBR]
0
3s
&
&
0
SIG
FD.Pkp
SIG
21Qi.En_PSBR
SIG
21Qi.Blk_PSBR
SIG
FD.Pkp
SIG
21Qi.Flg_PSBR
SIG
21Qi.Enable_PSBR
EN
[21Qi.En_PSBR]
SIG
Symmetrical |U1cosΦ |<
160ms
>=1
&
21Qi.Enable_PSBR
&
&
>=1
&
t
0ms
Unblocking for SF
>=1
21Qi.Rls_PSBR
>=1
&
SIG
Unsymmetrical |I0|+|I2|>
Unblocking for UF
SIG
21Qi.Flg_PSBR
SET
I1>[21Q.I_PSBR]
0
3s
&
&
0
SIG
160ms
>=1
FD.Pkp
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SIG
21M.Pilot.En_PSBR
SIG
21M.Pilot.Blk_PSBR
SIG
FD.Pkp
SIG
21M.Pilot.Flg_PSBR
SIG
21M.Pilot.Enable_PSBR
EN
[21M.Pilot.En_PSBR]
SIG
Symmetrical |U1cosΦ |<
&
21M.Pilot.Enable_PSBR
&
&
>=1
&
t
0ms
Unblocking for SF
21M.Pilot.Rls_PSBR
>=1
>=1
&
SIG
Unsymmetrical |I0|+|I2|>
Unblocking for UF
SIG
21M.Pilot.Flg_PSBR
SET
I1>[21M.I_PSBR]
0
3s
&
&
0
SIG
FD.Pkp
SIG
21Q.Pilot.En_PSBR
SIG
21Q.Pilot.Blk_PSBR
SIG
FD.Pkp
SIG
21Q.Pilot.Flg_PSBR
SIG
21Q.Pilot.Enable_PSBR
EN
[21Q.Pilot.En_PSBR]
SIG
Symmetrical |U1cosΦ |<
160ms
>=1
&
21Q.Pilot.Enable_PSBR
&
&
>=1
&
t
0ms
Unblocking for SF
>=1
21Q.Pilot.Rls_PSBR
>=1
&
SIG
Unsymmetrical |I0|+|I2|>
Unblocking for UF
SIG
21Q.Pilot.Flg_PSBR
SET
I1>[21Q.I_PSBR]
0
3s
&
&
0
SIG
160ms
>=1
FD.Pkp
Figure 3.7-43 Logic diagram of PSBR
Where:
i=1, 2, 3, 4, 5
21Mi.Flg_PSBR: Please refer to Figure 3.7-25 and Figure 3.7-26
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21Qi.Flg_PSBR: Please refer to Figure 3.7-30 and Figure 3.7-31
21M.Pilot.Flg_PSBR and 21Q.Pilot.Flg_PSBR: Please refer to Figure 3.7-34 and Figure 3.7-35
3.7.9.4 Settings
Table 3.7-13 Settings of PSBR
No.
Name
Range
Step
Unit
Remark
Enabling/disabling zone i of distance
protection controlled by PSBR (Mho
1
21Mi.En_PSBR
0 or 1
characteristic, i=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling zone i of distance
protection controlled by PSBR (Quad
2
21Qi.En_PSBR
0 or 1
characteristic, i=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling
pilot
distance
zone controlled by PSBR (Mho
3
21M.Pilot.En_PSBR
0 or 1
characteristic)
0: disable
1: enable
Enabling/disabling
pilot
distance
zone controlled by PSBR (Quad
4
21Q.Pilot.En_PSBR
0 or 1
characteristic)
0: disable
1: enable
5
21M.I_PSBR
(0.050~30.000)×In
0.001
A
6
21Q.I_PSBR
(0.050~30.000)×In
0.001
A
Current setting for power swing
blocking (Mho characteristic)
Current setting for power swing
blocking (Quad characteristic)
3.7.10 Distance SOTF Protection
When the circuit breaker is closed manually or automatically, it is possible to switch on to a fault.
This is especially critical if the line in the remote station is grounded, since the distance protection
would not clear the fault until overreach zones (zone 2 and/or zone 3) time delays have elapsed. In
this situation, however, the fastest possible clearance is required. The SOTF (switch onto fault)
protection is a complementary function to the distance protection. With distance SOTF protection,
a fast trip is achieved for a fault on the whole line, when the line is being energized. It shall be
responsive to all types of faults anywhere within the protected line. Distance SOTF protection can
be initiated by several cases, including manual closing signal, 3-pole reclosing, 1-pole reclosing
and pole discrepancy conditions.
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3.7.10.1 Function Block Diagram
21SOTF
21SOTF.En
21SOTF.On
21SOTF.Blk
21SOTF.Op
21SOTF.Op_PDF
3.7.10.2 I/O Signals
Table 3.7-14 I/O signals of distance SOTF protection
No.
Input Signal
1
21SOTF.En
2
21SOTF.Blk
No.
Description
Distance SOTF protection enabling input, it is triggered from binary input or
programmable logic etc.
Distance SOTF protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
Accelerate distance protection to trip when manual closing or auto-reclosing to
1
21SOTF.Op
2
21SOTF.Op_PDF
3
21SOTF.On
fault
Accelerate distance protection to trip when another fault happened under pole
discrepancy conditions
Accelerate distance protection is enabled.
3.7.10.3 Logic
SIG
21SOTF.En
SIG
21SOTF.Blk
EN
[21SOTF.En]
&
&
21SOTF.On
Figure 3.7-44 Logic diagram of enabling distance SOTF protection
1.
For single circuit breaker mode
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SIG
CB1.52b_PhA
SIG
CB1.52b_PhB
SIG
CB1.52b_PhC
SIG
FD.Pkp
SET
[SOTF.Opt_Mode_ManCls]=CBPos
SET
[SOTF.Opt_Mode_ManCls]=ManClsBI/CBPos
SET
[SOTF.Opt_Mode_ManCls]=All
SET
[SOTF.Opt_Mode_ManCls]=ManClsBI
SET
[SOTF.Opt_Mode_ManCls]=ManClsBI/CBPos
SET
[SOTF.Opt_Mode_ManCls]=All
SIG
CB1.ManCls
SET
[SOTF.Opt_Mode_ManCls]=All
SET
[SOTF.Opt_Mode_ManCls]=AutoInit
SIG
Ua<[SOTF.U_Ddl]
SIG
Ub<[SOTF.U_Ddl]
SIG
Uc<[SOTF.U_Ddl]
SIG
FD.Pkp
>=1
&
>=1
>=1
&
>=1
0ms [SOTF.t_En]
Manual closing signal
>=1
&
&
>=1
&
[SOTF.t_DdL]
0ms
SIG
VTS.Alm
SIG
Ia<0.06In
SIG
Ib<0.06In
SIG
Ic<0.06In
SIG
79.Close (3P)
0ms
[SOTF.t_En]
3-pole reclosing signal
SIG
79.Close (1P)
0ms
[SOTF.t_En]
1-pole reclosing signal
Dead line
&
Figure 3.7-45 Logic diagram of manual closing signal
For double circuit breakers mode, the phase's open status corresponding to the line is invalid
unless both circuit breakers are in open position.
2.
For double circuit breakers mode
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BI
[CB1.52b_PhA]
BI
[CB2.52b_PhA]
BI
[CB1.52b_PhB]
BI
[CB2.52b_PhB]
BI
[CB1.52b_PhC]
BI
[CB2.52b_PhC]
SIG
FD.Pkp
SET
[SOTF.Opt_Mode_ManCls]=CBPos
SET
[SOTF.Opt_Mode_ManCls]=ManClsBI/CBPos
SET
[SOTF.Opt_Mode_ManCls]=All
SET
[SOTF.Opt_Mode_ManCls]=ManClsBI
SET
[SOTF.Opt_Mode_ManCls]=ManClsBI/CBPos
SET
[SOTF.Opt_Mode_ManCls]=All
SIG
CBx.ManCls
SET
[SOTF.Opt_Mode_ManCls]=All
SET
[SOTF.Opt_Mode_ManCls]=AutoInit
SIG
Ua<[SOTF.U_Ddl]
SIG
Ub<[SOTF.U_Ddl]
SIG
Uc<[SOTF.U_Ddl]
SIG
FD.Pkp
&
&
>=1
&
&
>=1
>=1
&
>=1
0ms
[SOTF.t_En]
Manual closing signal
>=1
&
&
>=1
&
[SOTF.t_DdL]
SIG
VTS.Alm
SIG
Ia<0.06In
SIG
Ib<0.06In
SIG
Ic<0.06In
0ms
Dead line
&
Figure 3.7-46 Logic diagram of manual closing signal
For accelerated tripping mode by manual closing signal, manual closing signal can be from circuit
breaker position, external binary signal of manual closing or dead line check.
When the circuit breaker is in open position while the device does not pick up, or external manual
closing binary input is energized, then manual closing signal will be kept for the setting
[SOTF.t_En], which will enable SOTF logic. When the initiation mode of SOTF protection is set as
“AutoInit” (i.e., [SOTF.Opt_Mode_ManCls] is set as “AutoInit”), distance SOTF protection will be
initiated by dead line check. When three phases currents are all smaller than 0.06In and no fault
detector element operates, SOTF logic will be enabled only for the setting [SOTF.t_En] if three
phase voltages are all smaller than the setting [SOTF.U_Ddl] with the time delay [SOTF.t_Ddl].
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It is selectable among zone 2, 3 or 4 of ditance protection which is accelerated to trip by manual
closing signal, and they are not controlled by power swing blocking.
SIG
Manual closing signal
SIG
21SOTF.On
SIG
FD.Pkp
EN
[21SOTF.En_ManCls]
EN
[21SOTF.Z2.En_ManCls]
SIG
21M(21Q)2.Flg_PSBR
EN
[21SOTF.Z3.En_ManCls]
SIG
21M(21Q)3.Flg_PSBR
EN
[21SOTF.Z4.En_ManCls]
SIG
21M(21Q)4.Flg_PSBR
&
&
&
[21SOTF.t_ManCls]
0
21SOTF.Op_ManCls
&
&
>=1
&
Figure 3.7-47 Logic diagram of distance SOTF protection by manual closing signal
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SIG
FD.Pkp
SIG
21SOTF.On
EN
[21SOTF.En_3PAR]
SIG
3-pole reclosing signal
EN
[21SOTF.Z2.En_3PAR]
SIG
21M(21Q)2.Flg_PSBR
EN
[21SOTF.Z2.En_PSBR]
SIG
21M(21Q)2.Rls_PSBR
EN
[21SOTF.Z3.En_3PAR]
SIG
21M(21Q)3.Flg_PSBR
EN
[21SOTF.Z3.En_PSBR]
SIG
21M(21Q)3.Rls_PSBR
EN
[21SOTF.Z4.En_3PAR]
SIG
21M(21Q)4.Flg_PSBR
EN
[21SOTF.Z4.En_PSBR]
SIG
21M(21Q)4.Rls_PSBR
EN
[21SOTF.En_1PAR]
SIG
52b_PhA
SIG
21M(21Q)2.Rls_PSBR(A)
SIG
52b_PhB
SIG
21M(21Q)2.Rls_PSBR(B)
SIG
52b_PhC
SIG
21M(21Q)2.Rls_PSBR(C)
&
&
[21SOTF.t_3PAR]
0
>=1
21SOTF.Op_AR
&
&
>=1
&
&
&
>=1
>=1
&
&
>=1
&
&
[21SOTF.t_1PAR]
50ms
0
&
50ms
0
&
50ms
0
&
0
>=1
Figure 3.7-48 Logic diagram of distance SOTF protection by 1-pole or 3-pole AR
It is selectable among zone 2, 3 or 4 of ditance protection which is accelerated to trip by 3-pole AR
signal, and it is settable whether they are controlled by power swing blocking. Zone 2 of distance
protection is always accelerated to trip by 1-pole AR signal, and it is controlled by power swing
blocking.
For single-phase permanent fault, distance SOTF protection for 1-pole reclosing onto the faulty
phase will trip three-phase circuit breaker.
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SIG
52b_PhA
SIG
21M(21Q)2.Rls_PSBR(A)
SIG
52b_PhB
SIG
21M(21Q)2.Rls_PSBR(B)
SIG
52b_PhC
SIG
21M(21Q)2.Rls_PSBR(C)
50ms
0
&
50ms
0
&
50ms
0
&
>=1
>=1
SIG
21M(21Q)2.Rls_PSBR
SIG
21SOTF.On
SIG
FD.Pkp
EN
[21SOTF.En_PDF]
&
&
&
[21SOTF.t_PDF]
0
21SOTF.Op_PDF
Figure 3.7-49 Logic diagram of distance SOTF protection by PD condition
Under pole discrepancy condition after single-phase tripping, distance SOTF protection will
accelerate to operate if another fault happens to the healthy phase.
SIG
21SOTF.Op_ManCls
>=1
21SOTF.Op
SIG
21SOTF.Op_AR
Figure 3.7-50 Logic diagram of distance SOTF protection
3.7.10.4 Settings
Table 3.7-15 Settings of distance SOTF protection
No.
Name
Range
Step
Unit
Remark
Time delay of enabling SOTF
protection (shared by distance
1
SOTF.t_En
0.000~10.000
0.001
s
SOTF protection, phase current
SOTF protection and residual
current SOTF protection)
Enabling/disabling distance SOTF
2
21SOTF.En
protection
0 or 1
0: disable
1: enable
Enabling/disabling
distance
3
21SOTF.Zi.En_ManCls
0 or 1
SOTF
i
of
protection
zone
for
manual closing (i=2, 3, 4)
1: enable
0: disable
4
21SOTF.t_ManCls
0.000~10.000
0.001
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No.
Name
Range
Step
Unit
Remark
accelerating to trip when manual
closing
Enabling/disabling
distance
5
21SOTF.Zi.En_3PAR
0 or 1
SOTF
zone
i
of
protection
for
3-pole reclosing (i=2, 3, 4)
1: enable
0: disable
Enabling/disabling
zone
i
controlled by PSB of distance
6
21SOTF.Zi.En_PSBR
SOTF
0 or 1
protection
for
3-pole
reclosing (i=2, 3, 4)
1: enable
0: disable
Time delay of distance protection
7
21SOTF.t_3PAR
0.000~10.000
0.001
s
accelerating to trip when 3-pole
reclosing
Enabling/disabling distance SOTF
8
21SOTF.En_1PAR
0 or 1
protection for 1-pole reclosing
1
0: disable
1: enable
Time delay of distance protection
9
21SOTF.t_1PAR
0.000~10.000
0.001
s
accelerating to trip when 1-pole
reclosing
Enabling/disabling distance SOTF
protection under pole discrepancy
10
21SOTF.En_PDF
0 or 1
conditions
1: enable
0: disable
Time delay of distance protection
11
21SOTF.t_PDF
0.000~10.000
0.001
s
operating under pole discrepancy
conditions
12
SOTF.U_Ddl
0~Unn
0.001
V
13
SOTF.t_Ddl
0.000~600.000
0.001
s
Undervoltage setting of deadline
detection
Time delay of deadline detection
Option of manual SOTF mode
ManClsBI: initiated by input signal
ManClsBI
of manual closing
CBPos
14
SOTF.Opt_Mode_ManCls
CBPos: initiated by CB position
ManClsBI/
ManClsBI/CBPos:
CBPos
initiated
by
either input signal of manual
AutoInit
closing or CB position
All
AutoInit: initiated by no voltage
detection
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No.
Name
Range
Step
Unit
Remark
All: initiated by both binary input
and no voltage detection
Table 3.7-16 Internal settings of distance SOTF protection
No.
Name
Default Value
Unit
Remark
Enabling/disabling distance SOTF protection for
1
21SOTF.En_ManCls
manual closing
1
0: disable
1: enable
Enabling/disabling distance SOTF protection for
2
21SOTF.En_3PAR
3-pole reclosing
1
0: disable
1: enable
3.8 Optical Pilot Channel (Option)
3.8.1 General Application
When fibre optical channel is available between the devices at both ends, the devices have an
optional module to transmit permissive signal or blocking signal (subject to the scheme selected),
transfer signal and transfer trip via the fibre ports of the module. The communication rate can be
64kbits/s or 2048kbits/s via optional dedicated optical fibre channel or multiplex channel. By the
setting [FO.Protocol], the device can support G.703 or C37.94.
3.8.2 Function Description
12 digital bits are integrated in each frame of transmission message for various applications. Each
received message frame via fibre optical channel will pass through security check to ensure the
integrity of the message consistently.
The last four digital bits of the 12 have been assigned for pilot scheme protection. The
communication channel can be configured as single channel mode or as dual channels mode.
(FOx, x can be 1 or 2) according to the optical pilot channel module selected.
3.8.2.1 Channel Interface
The modules can communicate in two modes via multiplexer or dedicated optical fibre.
Communication through dedicated fibre is usually recommended unless the received power does
not meet with the requirement. Channel of 64kbits/s or 2048kbits/s via dedicated fibre is shown in
Figure 3.8-1 and Figure 3.8-2. Two fibre cores of optical cable are dedicated to pilot scheme
protection. For dual firbre optical channels application, two fibre cores of optical cable are normally
in service, and all data are exchanged via the other healthy core if one core is failed.
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Max 2km for 62.5/125um multi-mode FO C37.94 (N*64kbits/s)
TX
RX
RX
TX
PCS-902
PCS-902
ST connectors
ST connectors
Max 2km for 62.5/125um multi-mode FO C37.94 (N*64kbits/s)
ST connectors (FO1)
PCS-902
ST connectors (FO1)
TX
RX
RX
TX
TX
RX
RX
TX
PCS-902
ST connectors (FO2)
ST connectors (FO2)
Figure 3.8-1 Direct optical link up to 2km with 850nm
Max 60km/110km for 9/125um single-mode FO
TX
RX
RX
TX
PCS-902
PCS-902
FC connectors
FC connectors
Max 60km/110km for 9/125um single-mode FO
FC connectors (FO1)
FC connectors (FO1)
TX
RX
RX
TX
TX
RX
RX
TX
PCS-902
PCS-902
FC connectors (FO2)
FC connectors (FO2)
Figure 3.8-2 Direct optical link up to 60km with1310nm or 110km with 1550nm
Channel of 64kbits/s or 2048kbits/s via multiplexer is shown in Figure 3.8-3, Figure 3.8-4 and
Figure 3.8-5.
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C37.94 (N*64kbits/s)
Multi-mode FO
Communication convertor
TX
RX
RX
TX
E
Interface
Link to
communicate
device
PCS-902
ST connectors
ST connectors
Multi-mode FO
ST connectors (FO1)
O
C37.94 (N*64kbits/s)
ST connectors (FO1) Communication convertor
TX
RX
RX
TX
TX
RX
RX
TX
E
Interface
Link to
communicate
device
PCS-902
ST connectors (FO2)
O
ST connectors (FO2)
Figure 3.8-3 Connect to a communication network via communication convertor
G.703 (64kbits/s)
Single-mode FO
MUX-64
TX
RX
RX
TX
E
Interface
Link to
communicate
device
PCS-902
FC connectors
O
FC connectors
G.703 (64kbits/s)
Single-mode FO
FC connectors (FO1)
FC connectors (FO1)
TX
RX
RX
TX
TX
RX
RX
TX
MUX-64
E
Interface
Link to
communicate
device
PCS-902
FC connectors (FO2)
O
FC connectors (FO2)
Figure 3.8-4 Connect to a communication network via MUX-64
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G.703-E1 (2048kbits/s)
MUX-2M
Single-mode FO
TX
RX
RX
TX
E
Interface
Link to
communicate
device
PCS-902
FC connectors
O
FC connectors
Single-mode FO
G.703-E1 (2048kbits/s)
FC connectors (FO1)
MUX-2M
TX
RX
E
RX
TX
TX
RX
RX
TX
FC connectors (FO1)
Interface
Link to
communicate
device
PCS-902
FC connectors (FO2)
O
FC connectors (FO2)
Figure 3.8-5 Connect to a communication network via MUX-2M
The protection transmission data format is shown as following table.
Bit
High
low
Data Frame
Description
Format
The header of transmission data format
LocID
The identity code of local device
Time
Time for synchronizing
FOx.Send1~FOx.Send12
The twelve signals sent by channel No.x
CRC
3.8.2.2 Communication Clock
Valid messages exchange is key factor for digital pilot scheme protection.
The device transmits and receives messages based on respective clocks, which are called
transmit clock (i.e. clock TX) and receive clock (i.e. clock RX) respectively. Clock RX is fixed to be
extracted from message frame, which can ensure no slip frame and no error message received.
Clock TX has two options:
1. Use internal crystal clock, which is called internal clock. (master clock)
2. Use external clock. (slave clock)
Depend on the clock used by the device at both ends, there are three modes.
1.
Master-master mode
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Both ends use internal clock.
2.
Slave-slave mode
Both ends use external clock.
3.
Master-slave mode
One of them uses internal clock, the other uses external clock
The logic setting [FOx.En_IntClock] is used in pilot scheme protection to select the communication
clock. The internal clock is enabled automatically when the logic setting [FOx.En_IntClock] is set
as “1”. Contrarily, the external clock is enabled automatically when the logic setting
[FOx.En_IntClock] is set to “0”.
If the device uses multiplex PCM channel, logic setting [FOx.En_IntClock] at both ends should be
set as “0” (Mode 2). If the device uses dedicated optical fibre channel, clock Mode 1 and Mode 3
can be used. Mode 1 is recommended in considering simplification to user, i.e. logic setting
[FOx.En_IntClock] at both ends should be set as “1”.
3.8.2.3 Identity Code
In order to ensure reliability of the device when digital communication channel is applied, settings
[FO.LocID] and [FO.RmtID] are provided as identity code to distinguish uniquely the device at
remote end using same channel.
Under normal conditions, the identity code of the device at local end should be different with that at
remote end. In addition, it is recommended that the identity code of all devices, i.e., the setting
[FO.LocID], should be unique in the power grid. The setting range is from 0 to 65535. Only for loop
test, they are set as the same.
The setting [FO.LocID] of the device at an end should be the same as the setting [FO.RmtID] of
the device at opposite end and the greater [FO.LocID] between the two ends is chosen as a
master end for sampling synchronism, the smaller [FO.LocID] is slave end. If the setting [FO.LocID]
is set the same as [FO.RmtID], that implies the device in loopback testing state.
The setting [FO.LocID] is packaged in the message frame and transmitted to the remote end.
When the [FO.LocID] of the device at remote end received by local device is same to the setting
[FO.RmtID] of local device, the message received from the remote end is valid, and protection
information involved in message is read. When these settings are not matched, the message is
considered as invalid and protection information involved in message is ignored, corresponding
alarms will be issued.
3.8.2.4 Channel Statistics
The device has the function of on-line channel monitoring and channel statistics. It can produce
channel statistic report automatically at 9:00 every day and the report can be printed for operator
to check the channel quality. The monitoring contents of channel status are shown as follows, and
they can be viewed by the menu “Main Menu→Test→Prot Ch Counter→Chx Counter”.
1.
FOx.StartTime (starting time)
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It shows the starting time of the channel status statistics of the device at local end.
2.
FO.RmtID (ID code of the remote end)
It shows the ID information received by the device at local end now.
3.
FOx.t_ChLag (propagation delay of channel x)
It shows the calculated communication channel time delay of the device at local end now (unit: us).
The calculation is based on the assumption of same channel path for to and from remote end. The
device measures propagation delay of communication channel based on the below principle.
Side S transmits a frame of message to side M, and meanwhile records the transmitting time “tss”
on the basis of clock on side S. When side M receives the message, it will record receiving time
“tmr” of the message with its own clock, and return a frame of message to side S at next fixed
transmitting time, meanwhile data of “tms-tmr” is included in the frame of message. Side S will
receive the message from side M at the time “tsr” and obtain the data of “tms-tmr”.
Therefore, the propagation delay of the channel “Td” is obtained through calculation:
Td 
(ts r  t s s )  (tms  t mr )
2
By using the above calculated “Td”, the device automatically compensate time synchronization of
sampling data at each end and transmission time lag.
T1
tss
tsr
tmr
Td
tms
"S"
"M"
T2
Figure 3.8-6 Schematic diagram of communication channel time
4.
FOx.N_CRCFail (total number of error frame of channel x)
It shows the total number of the error frames of the device at local end from starting time of
channel statistics until now. Error frame means that this frame fails in CRC check.
5.
FOx.N_FramErr (total number of abnormal messages of channel x)
It shows the total number of abnormal messages of the device at local end from starting time of
channel statistics until now.
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6.
FOx.N_FramLoss (total number of lost frames of channel x)
It shows the total number of the lost frames of the device at local end from starting time of channel
statistics until now.
7.
FOx.N_RmtAbnor (total number of abnormal messages from the remote end of channel x)
It shows the total number of abnormal messages received from the remote end from starting time
of channel statistics until now.
8.
FOx.N_CRCFailSec (total number of serious error frames of channel x)
It shows the total number of serious error frame seconds of the device at local end from starting
time of the channel statistics until now.
9.
FOx.N_LossSyn (total number of loss synchronous of channel x)
It shows the total number of loss synchronous of the device at local end from starting time of the
channel statistics until now.
3.8.3 Function Block Diagram
FOx
FOx.En
FOx.On
FOx.Sendi
FOx.Recvi
FOx.Alm
FOx.Alm_ID
3.8.4 I/O Signals
Table 3.8-1 I/O signals of pilot channel
No.
Input Signal
Description
1
FOx.En
Enabling channel x
2
FOx.Sendi
Sending signal i of channel x (i=1, 2, 3, ......, 8)
3
FOx.Send9
Sending signal 9 of channel x (it is configured by default as sending permissive
signal 1 or sending A-phase permissive signal (only for phase-segregated
command scheme))
4
FOx.Send10
5
FOx.Send11
Sending signal 10 of channel x (it is configured by default as sending B-phase
permissive signal (only for phase-segregated command scheme))
Sending signal 11 of channel x (it is configured by default as sending C-phase
permissive signal (only for phase-segregated command scheme))
Sending signal 12 of channel x (it is configured by default as sending
6
FOx.Send12
permissive signal 2 only for pilot directional earth-fault protection adopting
independent pilot channel 2)
No.
Output Signal
Description
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1
FOx.On
Channel x is enabled.
2
FOx.Recvi
Receiving signal i of channel x (i=1, 2, 3, ......, 8)
Receiving signal 9 of channel x (it is configured by default as receiving
3
FOx.Recv9
permissive signal via pilot channel 1, or receiving permissive signal of A-phase
via channel No.1 (only for phase-segregated command scheme))
Receiving signal 10 of channel x (it is configured by default as receiving
4
FOx.Recv10
permissive signal of B-phase via pilot channel 1 (only for phase-segregated
command scheme))
Receiving signal 11 of channel x (it is configured by default as receiving
5
FOx.Recv11
permissive signal of C-phase via pilot channel 1 (only for phase-segregated
command scheme))
Receiving signal 12 of channel x (it is configured by default as receiving
6
FOx.Recv12
permissive signal 2 only for pilot directional earth-fault protection adopting
independent pilot channel 2)
7
FOx.Alm
Channel x is abnormal
8
FOx.Alm_ID
Received ID from the remote end is not as same as the setting [FO.RmtID] of
the device in local end
3.8.5 Logic
SIG Receiving transfer signal i from remote side
&
FOx.Recvi
SIG FOx.Alm
>=1
SIG FOx.Alm_ID
SIG FOx.En
&
FOx.On
EN
FOx.En
Figure 3.8-7 Logic diagram of receiving signal i
i can be 1, 2, 3, ......, 12
3.8.6 Settings
Table 3.8-2 Settings of pilot channel
No.
Name
Range
Step
Unit
Remark
1
FO.LocID
0-65535
1
Identity code of the device at local end
2
FO.RmtID
0-65535
1
Identity code of the device at remote end
3
FO.BaudRate
64 or 2048
4
FO.Protocol
5
FOx.Nx64k_C37.94
kbps
Baud rate of optical pilot channel
G.703
It is used to select protocol type, G.703 or
C37.94
C37.94
1-12
1
The setting for the times of 64kbits/s, which
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No.
Name
Range
Step
Unit
Remark
is an N*64kbits/s standard defined by IEEE
C37.94 standard
Option of internal clock or external clock
6
FOx.En_IntClock
0 or 1
0: external clock
1: internal clock
Enabling/disabling channel x
7
FOx.En
0: disable
0 or 1
1: enable
3.9 Pilot Distance Protection
3.9.1 General Application
The instant distance protection with underreaching setting is impossible to isolate the fault at
remote end of the line, while distance protection with overreaching setting needs a time delay to
grade with downstream protection to maintain discrimination. Pilot distance protection that
exchanges distance protection information at both ends of the line can remove the fault within this
line quickly, and will not operate for external fault.
Pilot distance protection requires communication channel to exchange protection information at
both ends. The channel may be dedicated or multiplexed channel through optical fiber or any other
communication media. Pilot distance protection has schemes of permissive underreaching
transfer trip (PUTT), permissive overreaching transfer trip (POTT) and blocking. The device
provides duplicated pilot distance protections with dual channels. The communication media and
mode can be independent each other.
3.9.2 Function Description
Pilot distance protection determines whether it will send the signal to the remote end according to
the discrimination result of the distance element or direction element. Pilot distance protection can
be divided into permissive scheme and blocking scheme according to whether the signal sent is
used to permit tripping or block tripping. For permissive scheme, it can be divided into
overreaching mode or underreaching mode according to the setting of distance element and
scheme selected, furthermore, it will provide the unblocking scheme as auxiliary function. For
overreaching mode, current reversal logic and weak infeed logic are available for parallel line
operation and weak power source situation respectively.
Pilot distance protection is used to protect the whole line, and its setting is set as 1.2 times the line
length at least, so the problem of overreaching does not exist and pilot distance protection,
compared with the distance protection, it is not required to coordinate with other zones. In order to
simplify setting calculation, the downward offset angle of the reactance of pilot distance protection
with quadrilateral characteristic is fixed 12 °without setting, which has been well proved to be a
reliable angle by large project experience and test data. The angle of directional line in the second
quadrant (α) and the angle of directional line in the fourth quadrant (β) are as same as those of
distance protection with quadrilateral characteristic.
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Pilot distance protection with permissive scheme receives permissive signal from the remote end,
so as to combine with local discrimination condition to accelerate tripping, so it has high security.
Blocking scheme will operate with a short time delay [85.t_DPU_Blocking1] if forward pilot zone
element operates and not receiving blocking signal before the short time delay expired.
Pilot distance protection can be enabled or disabled by input signals, logic setting and blocking
signal, as shown in Figure 3.9-1.
SIG 85-x.Z.En1
SIG
85-x.Z.En2
EN
[85.Z.En]
SIG
85-x.Z.Blk
&
&
85-x.Z.On
Figure 3.9-1 Enabling/disabling logic of pilot distance protection
Pilot distance protection receives and sends signals via pilot channel, and the logic of receiving
signal is shown in Figure 3.9-2.
NOTICE!
For non-phase segregation mode, "85-x.Recv1" means that permissive signal of any
phase is received from the remote end. However, for phase segregation mode,
"85-x.Recv1" means that permissive signal of phase A is received from the remote end.
1.
Non-phase segregated mode
SET
[85.Opt_PilotMode]=Blocking
&
>=1
2.
SIG
85-x.Recv1
SIG
85-x.Abnor_Ch1
SIG
85-x.Unblocking1 Valid
SET
[85.Opt_PilotMode]=PUTT
SET
[85.Opt_PilotMode]=POTT
SET
[85.Opt_Ch_PhSeg]=0
&
>=1
&
>=1
&
85-x.Valid_Recv1
Phase segregated mode
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SIG
85-x.Recv1
SIG
85-x.Abnor_Ch1
SIG
85-x.Unblocking1 Valid (Phase A)
SET
[85.Opt_PilotMode]=PUTT
SET
[85.Opt_PilotMode]=POTT
SET
[85.Opt_Ch_PhSeg]=1
SIG
85-x.RecvB
SIG
85-x.Abnor_Ch1
SIG
85-x.Unblocking1 Valid (Phase B)
SET
[85.Opt_PilotMode]=PUTT
SET
[85.Opt_PilotMode]=POTT
SET
[85.Opt_Ch_PhSeg]=1
SIG
85-x.RecvC
SIG
85-x.Abnor_Ch1
SIG
85-x.Unblocking1 Valid (Phase C)
SET
[85.Opt_PilotMode]=PUTT
SET
[85.Opt_PilotMode]=POTT
SET
[85.Opt_Ch_PhSeg]=1
&
>=1
&
>=1
&
85-x.Valid_Recv1 (Phase A)
&
>=1
&
>=1
&
85-x.Valid_RecvB (Phase B)
&
>=1
&
>=1
&
85-x.Valid_RecvC (Phase C)
Figure 3.9-2 Logic diagram of receiving signal
Pilot distance protection has the following application modes:
3.9.2.1 Zone Extension
When pilot scheme protection is out of service due to pilot channel failure or no pilot scheme
protection is provided. The fault outside zone 1 only can be cleared by zone 2 with a time delay. It
can not ensure that all faults within protected line are cleared instantaneously. As a supplement of
pilot scheme protection, zone extension can clear the fault within the whole line instantaneously.
Different with pilot distance protection, zone extension can also operate for external close up fault
in parallel line, but power supply can be restored by AR. So zone extension should be blocked
when AR is out of service and is not ready.
In order to prevent too many lines from disconnecting with system due to zone extension operate
when the circuit breaker is closed into permanent fault, zone extension should be blocked when
AR operates. For temporary fault, the line can be into service again after AR operates successfully.
For permanent fault in either local line or parallel line, distance protection with a time delay will
operate.
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SIG FD.Pkp
&
SIG 85-x.ZX.En1
&
SIG 85-x.ZX.En2
EN
&
85-x.ZX.On
[85.ZX.En]
SIG 85-x.ZX.Blk1
>=1
SIG 85-x.ZX.Blk2
&
SIG 79.Ready
[85.t_DPU_ZX]
&
0ms
85-x.Op_ZX
SIG Zpilot
Figure 3.9-3 Zone extension
Zone extension uses the setting of pilot zone (ZPilot), and its operation characteristic can be Mho
or Quad.
3.9.2.2 Permissive Underreaching Transfer Trip (PUTT)
Distance elements zone 1 (Z1) with underreaching setting and pilot zone (ZPilot) with
overreaching setting are used for this scheme. Z1 element will send permissive signal to the
remote end and release tripping after Z1 time delay expired. After receiving permissive signal with
ZPilot element pickup, a tripping signal will be released.
The signal transmission element for PUTT is set according to underreaching mode, so current
reversal need not be considered.
For PUTT, there may be a dead zone under weak power source condition. If the fault occurs
outside Z1 zone at strong power source side, Z1 at weak power supply side may not operate to trip
and transmit permissive signal, and pilot distance protection will not operate. Therefore, the
system fault can only be removed by Z2 at strong power source side with time delay.
ZPilot
Z2
Z1
EM
M
A
Fault
B
Z1
EN
N
Z2
ZPilot
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Relay A
Relay B
Z1
Z1
&
&
85-x.Op_Z
85-x.Op_Z
ZPilot
ZPilot
Figure 3.9-4 Simple schematic of PUTT
Pilot distance protection always adopts pilot channel 1, and the logic of PUTT is shown in Figure
3.9-5.
NOTICE!
For non-phase segregation mode, "85-x.Send1" means that permissive signal of any
phase is sent to the remote end. However, for phase segregation mode, "85-x.Send1"
means that permissive signal of phase A is sent to the remote end.
1.
Non-phase segregated mode
SIG 21M1(21Q1).Op
0ms
100ms
SIG 85-x.ExTrp
0ms
150ms
>=1
&
SET [85.Opt_PilotMode]=PUTT
85-x.Send1
&
&
SIG 85-x.Z.On
SIG FD.Pkp
SIG 85-x.Valid_Recv1
&
&
8ms
0ms
85-x.Op_Z
SET [85.Opt_Ch_PhSeg]=0
SIG ZPilot
2.
Phase segregated mode
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SIG 21M1(21Q1).Op (Phase A)
0ms
100ms
SIG 85-x.ExTrp
0ms
150ms
>=1
&
SET [85.Opt_PilotMode]=PUTT
85-x.Send1 (Phase A)
&
SIG 85-x.Z.On
&
SIG FD.Pkp
SIG 85-x.Valid_Recv (Phase A)
&
&
8ms
0ms
85-x.Op_Z (Phase A)
SET [85.Opt_Ch_PhSeg]=1
SIG Zpilot (Phase A)
SIG 21M1(21Q1).Op (Phase B)
0ms
100ms
SIG 85-x.ExTrp
0ms
150ms
>=1
&
SET [85.Opt_PilotMode]=PUTT
85-x.SendB (Phase B)
&
SIG 85-x.Z.On
&
SIG FD.Pkp
SIG 85-x.Valid_Recv (Phase B)
&
&
8ms
0ms
85-x.Op_Z (Phase B)
SET [85.Opt_Ch_PhSeg]=1
SIG Zpilot (Phase B)
SIG 21M1(21Q1).Op (Phase C)
0ms
100ms
SIG 85-x.ExTrp
0ms
150ms
>=1
&
SET [85.Opt_PilotMode]=PUTT
85-x.SendC (Phase C)
&
SIG 85-x.Z.On
&
SIG FD.Pkp
SIG 85-x.Valid_Recv (Phase C)
&
&
8ms
0ms
85-x.Op_Z (Phase C)
SET [85.Opt_Ch_PhSeg]=1
SIG Zpilot (Phase C)
Figure 3.9-5 Logic diagram of pilot distance protection (PUTT)
3.9.2.3 Permissive Overreaching Transfer Trip (POTT)
ZPilot will send permissive signal to remote end once it picks up and release tripping signal upon
receiving permissive signal from the remote end.
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When POTT is applied on parallel lines arrangement and the ZPilot setting covers 50% of the
parallel line, there may be a problem under current reversal condition, settings for current reversal
condition should be considered, please refer to section 3.9.2.6 for details.
Under weak power source condition, the problem of dead zone at weak power source end is
eliminated by the weak infeed logic, please refers to section 3.9.2.7 for details.
ZPilot
Z2
M
EM
Zpilot_Rev
A
Fault
B
EN
N
Zpilot_Rev
Z2
ZPilot
Relay A
ZPilot
&
>=1
Relay B
&
85-x.Op_Z
85-x.Op_Z
WI
>=1
ZPilot
WI
Figure 3.9-6 Simple schematic of POTT
1.
Non-phase segregated mode
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SIG Trp
0ms
100ms
SIG 85-x.ExTrp
0ms
150ms
SIG 52b_PhA
>=1
&
SIG 52b_PhB
&
&
SIG 52b_PhC
SET [85.Opt_Ch_PhSeg]=0
200ms
&
>=1
0ms
SIG 85-x.Valid_Recv1
&
SIG FD.Pkp
85-x.Send1
SET [85.Opt_PilotMode]=POTT
SIG 85-x.Z.FwdDir
&
&
>=1
8ms
&
SIG 85-x.Z.On
0ms
85-x.Op_Z
&
SIG WI
SIG Current reversal blocking
2.
Phase segregated mode
SIG Trp
0ms
150ms
SIG 85-x.ExTrp
0ms
150ms
SIG 52b_PhA
>=1
&
SIG 52b_PhB
&
>=1
&
200ms
0ms
SIG 52b_PhC
SET [85.Opt_Ch_PhSeg]=1
&
SIG 85-x.Valid_Recv(Phase A)
&
SIG FD.Pkp
85-x.Send1 (Phase A)
SET [85.Opt_PilotMode]=POTT
SIG 85-x.Z.FwdDir (Phase A)
&
&
>=1
SIG 85-x.Z.On
&
8ms
0ms
85-x.Op_Z (Phase A)
&
SIG WI (Phase A)
SIG Current reversal blocking (Phase A)
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SIG Trp
0ms
150ms
SIG 85-x.ExTrp
0ms
150ms
SIG 52b_PhA
>=1
&
SIG 52b_PhB
&
>=1
&
200ms
0ms
SIG 52b_PhC
SET [85.Opt_Ch_PhSeg]=1
&
SIG 85-x.Valid_Recv(Phase B)
&
SIG FD.Pkp
85-x.SendB (Phase B)
SET [85.Opt_PilotMode]=POTT
SIG 85-x.Z.FwdDir (Phase B)
&
&
>=1
SIG 85-x.Z.On
8ms
&
0ms
85-x.Op_Z (Phase B)
&
SIG WI (Phase B)
SIG Current reversal blocking (Phase B)
SIG Trp
0ms
150ms
SIG 85-x.ExTrp
0ms
150ms
SIG 52b_PhA
>=1
&
SIG 52b_PhB
&
>=1
&
200ms
0ms
SIG 52b_PhC
SET [85.Opt_Ch_PhSeg]=1
&
SIG 85-x.Valid_Recv(Phase C)
&
SIG FD.Pkp
85-x.SendB (Phase C)
SET [85.Opt_PilotMode]=POTT
SIG 85-x.Z.FwdDir (Phase C)
&
&
>=1
SIG 85-x.Z.On
&
8ms
0ms
85-x.Op_Z (Phase C)
&
SIG WI (Phase C)
SIG Current reversal blocking (Phase C)
Figure 3.9-7 Logic diagram of pilot distance protection (POTT)
For current reversal blocking, please refer to section 3.9.2.6 for detail.
3.9.2.4 Blocking
Permissive scheme has high security, but it relies on pilot channel seriously. Pilot distance
protection will not operate when there is an internal fault with abnormal channel. Blocking scheme
could be considered as an alternative.
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Blocking scheme takes use of pilot distance element Zpilot operation to terminate sending of
blocking signal. Blocking signal will be sent once fault detector picks up without pilot zone Zpilot
operation. Pilot distance protection will operate with a short time delay if pilot distance element
operates and not receiving blocking signal after timer expired.
The setting of pilot zone element Zpilot in Blocking scheme is overreaching, so current reversal
condition should be considered. However, the short time delay of pilot distance protection has an
enough margin for current reversal, that this problem has been resolved.
The short time delay must consider channel delay and with a certain margin to set. As shown in
Figure 3.9-8, an external fault happens to line MN. The fault is behind the device at M side, for
blocking scheme, the device at M side will send blocking signal to the device at N side. If channel
delay is too long, the device at side N has operated before receiving blocking signal. Hence, the
time delay of pilot distance protection adopted in blocking scheme should be set according to
channel delay.
Blocking signal
EM
Fault
M
A
N
B
EN
Figure 3.9-8 Simple schematic of system fault
For blocking scheme, pilot distance protection will operate when there is an internal fault with
abnormal channel, however, it is possible that pilot distance protection issue an undesired trip
when there is an external fault with abnormal channel.
ZPilot
EM
M
Zpilot_Rev
A
Fault
B
EN
N
Zpilot_Rev
ZPilot
Relay A
Relay B
FD.Pkp
&
Zpilot
&
[85.t_DPU_Blocking1]
85-x.Op_Z
85-x.Op_Z
&
FD.Pkp
&
Zpilot
[85.t_DPU_Blocking1]
Figure 3.9-9 Simple schematic of blocking
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SIG Trp
0ms
100ms
SIG
0ms
150ms
85-x.ExTrp
SIG 52b_PhB
>=1
&
SIG 52b_PhA
&
>=1
&
SIG 52b_PhC
200ms
0ms
&
SIG 85-x.Valid_Recv1
85-x.Send1
&
SIG 85-x.Z.FwdDir
>=1
SIG WI
&
[85.t_DPU_Blocking1]
SIG FD.Pkp
SET [85.Opt_PilotMode]=Blocking
85-x.Op_Z
&
SIG 85-x.Z.On
Figure 3.9-10 Logic diagram of pilot distance protection (Blocking)
Current reversal logic is only used for permissive scheme. For blocking scheme, the time delay of
pilot distance protection has enough margin for current reversal, so current reversal need not be
considered.
3.9.2.5 Unblocking
Permissive scheme will trip only when it receives permissive signal from the remote end. However,
it may not receive permissive signal from the remote end when pilot channel fails. For this case,
pilot distance protection can adopt unblocking scheme. Under normal conditions, the signaling
equipment works in the pilot frequency, and when the device operates to send permissive signal,
the signaling equipment will be switched to high frequency. While pilot channel is blocked, the
signaling equipment will receive neither pilot frequency signal nor high frequency signal. The
signaling equipment will provide a contact to the device as unblocking signal. When the device
receives unblocking signal from the signaling equipment, it will recognize channel failure, and
unblocking signal will be taken as permissive signal temporarily.
The unblocking function can only be used together with PUTT and POTT.
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EN
[85.En_Unblocking1]
SIG 85-x.Unblocking1
&
&
[85.t_Unblocking1] 0ms
SIG Detecting multi-phase fault
>=1
&
SET [85.Opt_PilotCh1]
85-x.Unblocking1 Valid
SIG Pilot distance forward element
Figure 3.9-11 Logic diagram of pilot distance protection (Unblocking)
3.9.2.6 Current Reversal
When there is a fault in one of the parallel lines, the direction of the fault current may change
during the sequence tripping of the circuit breaker at both ends as shown in Figure 3.9-12: When a
fault occurs on line C–D near breaker D, the fault current through line A-B to D will flow from A to B.
When breaker D is tripped, but breaker C is not tripped, the fault current in line A-B will then flow
from B to A. This process is the current reversal.
M
Strong
source
EM
N
A
B
C
M
Weak
source
EN
N
A
B
EN
EM
D
C
Direction of fault current
flow before CB‘D’open
D
Direction of fault current
flow after CB‘D’open
Figure 3.9-12 Current reversal
As shown above, the device A judges a forward fault while the device B judges a reverse fault
before break D is tripped. However, the device A judges a reverse fault while the device B judges a
forward fault after breaker D is tripped. There is a competition between pickup and drop off of pilot
zones in the device A and the device B when the fault measured by the device A changes from
forward direction into reverse direction and vice versa for the device B. There may be
maloperation for the device in line A-B if the forward direction of the device B has operated but the
forward direction of the device A drops off slightly slower or the forward direction of the device B
has operated but the forward direction information of the device A is still received due to the
channel delay (the permissive signal is received).
In general, the following two methods shall be adopted to solve the problem of current reversal:
1.
The fault shall be measured by means of the reverse element of the device B. Once the
reverse element of the device B operates, the send signals and the tripping circuit will be
blocked for a period of time after a short time delay. This method can effectively solve the
problem of competition between the device A and the device B, but there shall be a
precondition. The reverse element of the device B must be in cooperation with the forward
element of the device A, i.e. in case of a fault in adjacent lines, if the forward element of the
device A operates, and the reverse element of the device B must also operate. Once the
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bilateral cooperation fails, the anticipated function cannot be achieved. In addition, the
blocking time for sending signals and the tripping circuit after the reverse element of the
device B operates shall be set in combination with the channel time delay.
2.
Considering the pickup and drop off time difference of distance elements and the channel time
delay between the device A and the device B, the maloperation due to current reversal shall
be eliminated by setting the time delay. The reverse direction element of the device is not
required for this method, the channel time delay and the tripping time of adjacent breaker
shall be taken into account comprehensively.
This protection device adopts the second method to eliminate the maloperation due to current
reversal.
SIG Pilot forward zone start condition
&
t1
t2
Current reversal blocking
SIG Signal received conditon
Figure 3.9-13 Logic diagram of current reversal blocking
t1: [85.t_DPU_CR1]
t2: [85.t_DDO_CR1]
Referring to above figure, when signal from the remote end is received without pilot forward zone
pickup, the current reversal blocking logic is enabled after t1 delay.
The time delay of t1 [85.t_DPU_CR1] shall be set the shortest possible but allowing sufficient time
for pilot forward zone pickup, generally set as 25ms.
Once the current reversal logic is enabled, the healthy line device B transfer tripping is blocked.
The logic will be disabled by either the dropoff of signal or the pickup of pilot forward zone. A time
delay t2 [85.t_DDO_CR1] is required to avoid maloperation for the case that the pilot forward zone
(or forward element of pilot directional earth-fault protection) of device B picks up before the signal
from device A drops off. Considering the channel propagation delay and the pickup and drop-off
time difference of pilot forward zone (or pilot directional earth-fault element) with margin, t2 is
generally set between 25ms~40ms.
Because the time delay of pilot distance protection has an enough margin to current reversal,
current reversal blocking only used for permissive scheme not blocking scheme.
3.9.2.7 Weak Infeed
In case of a fault in line at one end of which there is a weak power source, the fault current
supplied to the fault point from the weak power source is very small or even nil, and the
conventional distance element could not operate. The weak infeed logic combines the protection
information from the strong power source end and the electric feature of the local end to cope with
the case.
The weak infeed logic can be only applied for BOTT and POTT. The weak infeed logic has options
for echo or both echo and tripping.
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ZPilot
Z1
M
EM
Zpilot_Rev
A
Fault
Zpilot_Rev
B
Z1
EN
N
ZPilot
Load
Figure 3.9-14 Line fault description
Both forward direction element and reverse direction element of pilot distance protection are used
to discriminate weak infeed logic. When the weak infeed logic is enabled, distance forward and
reverse element and direction element of directional earth-fault protection do not operate with the
voltage lower than the setting [85.U_UV_WI] after the device picks up, upon receiving signal from
remote end, the weak infeed logic will echo the signal back to remote end for 200ms if the weak
infeed echo is enabled, the weak infeed end will echo signal and release tripping according to the
logic.
ZPilot_Rev at weak source end must coordinate with ZPilot_Set of the remote end. The coverage
of ZPilot_Rev must exceed that of ZPilot_Set of the remote end. ZPilot_Rev only activates in the
protection calculation when the weak infeed logic is enabled. In case of the weak infeed logic not
enabled, the setting coordination is not required.
If the device does not pick up, and the weak infeed logic is enabled, upon receiving signal from
remote end with the voltage lower than the setting [85.U_UV_WI], the weak infeed logic will echo
back to remote end for 200ms. When either weak infeed echo or weak infeed tripping is enabled,
then the weak infeed logic is deemed to be enabled. During the device picking up, the weak infeed
logic is shown in Figure 3.9-15.
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SIG
FwdDir_ROC
&
85-x.DEF.FwdDir
SET
3I0>[85.DEF.3I0_Set]
SIG
RevDir_ROC
SIG
FD.ROC.Pkp
SIG
Pilot distance forward direction
85-x.Z.FwdDir
SIG
Pilot distance reverse direction
85-x.Z.RevDir
&
85-x.DEF.RevDir
>=1
>=1
SIG
Valid_Recv1
SIG
FD.Pkp
EN
[85.En_WI]
SET
Up<[85.U_UV_WI]
&
&
85-x.WI
>=1
&
200ms
SET
0ms
85-x.UV_WI
Upp<[85.U_UV_WI]
Figure 3.9-15 Weak infeed logic during pickup
For weak infeed end, the device may not pick up when a fault happens to the protected line. If the
device does not pick up, the logic setting [85.En_WI_Pkp] is used to determine that weak infeed
echo logic without pickup (as shown in Figure 3.9-16) or weak infeed trip logic without pickup (as
shown in Figure 3.9-17) is executed.
EN
[85.En_WI_Pkp]
SIG
Signal receive condition
EN
[85.En_WI]
&
SET Up<[85.U_UV_WI]
WI echo
>=1
&
200ms
0ms
85-x.UV_WI
SET Upp<[85.U_UV_WI]
Figure 3.9-16 Weak infeed echo logic without pickup
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SIG
FwdDir_ROC
&
85-x.DEF.FwdDir
SET
3I0>[85.DEF.3I0_Set]
SIG
RevDir_ROC
SIG
FD.ROC.Pkp
SIG
Pilot distance forward direction
SIG
Pilot distance reverse direction
&
85-x.DEF.RevDir
85-x.Z.FwdDir
85-x.Z.RevDir
>=1
>=1
SIG
Signal receive condition
EN
[85.En_WI_Pkp]
EN
[85.En_WI]
SET
Up<[85.U_UV_WI]
&
85-x.WI
>=1
&
200ms
SET
&
0ms
85-x.UV_WI
Upp<[85.U_UV_WI]
Figure 3.9-17 Weak infeed trip logic without pickup
For permissive scheme, the signal receive condition means that the permissive signal is received
or the unblocking signal is valid.
3.9.2.8 CB Echo
A feature is also provided which enables fast tripping to be maintained along the whole length of
the protected line, even when one terminal is open. The device will initiate sending a pulse of
200ms permissive signal when signal receive condition is met during CB is in open position.
SIG FD.Pkp
&
&
SIG 52b_PhA
200ms
>=1
0ms
&
SIG 52b_PhB
Send permissive signal
SIG 52b_PhC
SIG 85-x.Valid_Recv1
&
SET [85.Opt_PilotMode]=POTT
Figure 3.9-18 Simplified CB echo logic for POTT
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CB Echo logic is only applied to permissive overreach mode not underreach mode, and it is
processed without the device pickup. This logic will be terminated immediately once the device
picks up.
3.9.3 Function Block Diagram
85
85-x.Z.En1
85-x.Z.On
85-x.Z.En2
85-x.ZX.On
85-x.Z.Blk
85.Op_Z
85-x.Abnor_Ch1
85.Z.On
85-x.Rcv1
85.ZX.On
85-x.RcvB
85-x.Op_Z
85-x.RcvC
85-x.Send1
85-x.ExTrp
85-x.SendB
85-x.Unblocking1
85-x.SendC
85-x.ZX.En1
85-x.Op_ZX
85-x.ZX.En2
85-x.ZX_St
85-x.ZX.Blk1
85-x.Z.FwdDir
85-x.ZX.Blk2
85-x.Z.RevDir
79.Ready
85-x.DEF.FwdDir
85-x.DEF.RevDir
85-x.WI
85-x.UV_WI
3.9.4 I/O Signals
Table 3.9-1 I/O signals of pilot distance protection
No.
Input Signal
1
85-x.Z.En1
2
85-x.Z.En2
3
85-x.Z.Blk
4
85-x.Abnor_Ch1
Description
Pilot distance protection x enabling input 1, it is triggered from binary input or
programmable logic etc. (x=1 or 2)
Pilot distance protection x enabling input 2, it is triggered from binary input or
programmable logic etc. (x=1 or 2)
Pilot distance protection x blocking input, it is triggered from binary input or
programmable logic etc. (x=1 or 2)
Input signal of indicating that pilot channel 1 is abnormal for pilot distance
protection x (x=1 or 2)
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Input signal of receiving permissive signal via channel No.1 for pilot distance
5
85-x.Recv1
protection x, or input signal of receiving permissive signal of A-phase via channel
No.1 for pilot distance protection x (only for phase-segregated command scheme,
x=1 or 2)
6
85-x.RecvB
7
85-x.RecvC
8
85-x.ExTrp
9
85-x.Unblocking1
10
85-x.ZX.En1
11
85-x.ZX.En2
12
85-x.ZX.Blk1
13
85-x.ZX.Blk2
14
79.Ready
No.
Input signal of receiving permissive signal of B-phase via channel No.1 for pilot
distance protection x (only for phase-segregated command scheme, x=1 or 2)
Input signal of receiving permissive signal of C-phase via channel No.1 for pilot
distance protection x (only for phase-segregated command scheme, x=1 or 2)
Input signal of initiating sending permissive signal from external tripping signal for
pilot distance protection x (x=1 or 2)
Unblocking signal 1 of pilot distance protection x (x=1 or 2)
Zone Extension enabling input 1 of pilot distance protection x, it is triggered from
binary input or programmable logic etc. (x=1 or 2)
Zone Extension enabling input 2 of pilot distance protection x, it is triggered from
binary input or programmable logic etc. (x=1 or 2)
Zone Extension blocking input 1 of pilot distance protection x, it is triggered from
binary input or programmable logic etc. (x=1 or 2)
Zone Extension blocking input 2 of pilot distance protection x, it is triggered from
binary input or programmable logic etc. (x=1 or 2)
AR has been ready for reclosing cycle.
Output Signal
Description
1
85-x.Z.On
Pilot distance protection x is enabled. (x=1 or 2)
2
85-x.ZX.On
Zone extension protection of pilot distance protection x is enabled. (x=1 or 2)
3
85-x.Op_Z
Pilot distance protection x operates. (x=1 or 2)
4
85.Z.On
5
85.ZX.On
6
85.Op_Z
General pilot distance protection is enabled. Which is OR operation between
85-1.Z.On and 85-2.Z.On
General zone extension protection is enabled, which is OR operation between
85-1.ZX.On and 85-2.ZX.On
General pilot distance protection operates, which is OR operation between
85-1.Op_Z and 85-2.Op_Z
Output signal of sending permissive signal 1 or sending A-phase permissive
7
85-x.Send1
signal of pilot distance protection x (only for phase-segregated command scheme,
x=1 or 2)
Output signal of sending B-phase permissive signal of pilot distance protection x
8
85-x.SendB
9
85-x.SendC
10
85-x.Op_ZX
Zone extension protection of pilot distance protection x operates. (x=1 or 2)
11
85-x.ZX_St
Zone extension protection of pilot distance protection x starts (x=1 or 2)
12
85-x.Z.FwdDir
Forward direction signal of pilot distance protection x (x=1 or 2)
13
85-x.Z.RevDir
Reverse direction signal of pilot distance protection x (x=1 or 2)
14
85-x.DEF.FwdDir
Forward direction signal of pilot directional earth-fault protection x (x=1 or 2)
15
85-x.DEF.RevDir
Reverse direction signal of pilot directional earth-fault protection x (x=1 or 2)
(only for phase-segregated command scheme, x=1 or 2)
Output signal of sending C-phase permissive signal of pilot distance protection x
(only for phase-segregated command scheme, x=1 or 2)
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16
85-x.WI
Operation signal of weak infeed logic of pilot distance protection x (x=1 or 2)
17
85-x.UV_WI
Undervoltage signal of weak infeed logic of pilot distance protection x (x=1 or 2)
3.9.5 Settings
Table 3.9-2 Settings of pilot distance protection
No.
Name
Range
Step
Unit
Remark
POTT
1
85.Opt_PilotMode
PUTT
1
Option of pilot scheme
Blocking
Option of
phase-segregated
signal scheme or single signal
2
85.Opt_Ch_PhSeg
scheme
0 or 1
0: single signal scheme
1:
phase-segregated
signal
scheme
Enabling/disabling weak infeed
3
85.En_WI
scheme
0 or 1
0: disable
1: enable
For weak infeed end, If the
device does not pick up for
4
85.En_WI_Pkp
internal fault, it is used to
0 or 1
enable the device pick up.
0: disable
1: enable
5
85.U_UV_WI
0~Unn
0.001
V
Undervoltage setting of weak
infeed logic
Enabling/disabling
6
85.Z.En
pilot
distance protection
0 or 1
0: disable
1: enable
Enabling/disabling unblocking
7
85.En_Unblocking1
scheme
0 or 1
0: disable
1: enable
Time
8
85.t_DPU_Blocking1
0.000~1.000
0.001
s
scheme
delay
of
for
blocking
pilot
distance
protection operation
9
85.t_DDO_CR1
0.000~1.000
0.001
s
10
85.t_DPU_CR1
0.000~1.000
0.001
s
11
85.ZX.En
0 or 1
Time delay dropoff for current
reversal logic
Time delay pickup for current
reversal logic
Enabling/disabling
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No.
Name
Range
Step
Unit
Remark
extension protection
0: disable
1: enable
12
85.t_DPU_ZX
0.000~10.000
0.001
s
Pickup time delay for zone
extension protection operation
Table 3.9-3 Internal settings of pilot distance protection
No.
1
Name
85.t_Unblocking1
Default Value
0.1
Unit
s
Remark
Pickup time delay of unblocking scheme for pilot
channel 1
Option of PLC channel for pilot channel 1
2
85.Opt_PilotCh1
1
0: phase-to-phase channel
1: phase-to-ground channel
3.10 Pilot Directional Earth-fault Protection
3.10.1 General Application
Directional earth fault protection needs to coordinate with downstream protection with definite or
inverse time delay so it cannot clear an internal fault quickly. Pilot directional earth-fault protection
takes use of directional earth fault elements on both ends, it can detect high resistance fault and
maintain high-speed operation.
Pilot protection requires communication channel to exchange the protection information at both
ends. The channel may be dedicated or multiplexed channel through optical fiber or any other
communication media.
Pilot directional earth-fault protection can be used independently, for example, no distance
protection is equipped with the device but fast operation is required for the whole line, or it is used
as backup protection of pilot distance protection to enhance the sensitivity for an earth fault with
high fault resistance.
3.10.2 Function Description
Sending permissive signal (or terminating sending signal) to the opposite end is controlled by
forward direction element. Current reversal logic is available for parallel line operation and CB
echo logic is provided once pilot directional earth fault protection is enabled. Current reversal logic
is only used for permissive scheme. For blocking scheme, current reversal need not be considered
because there is a settable time delay in pilot directional earth-fault protection.
Pilot directional earth-fault protection can be enabled or disabled by input signals, logic setting and
blocking signal, as shown in Figure 3.10-1.
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SIG 85-x.DEF.En1
SIG
85-x.DEF.En2
EN
[85.DEF.En]
SIG
85-x.DEF.Blk
&
&
85-x.DEF.On
Figure 3.10-1 Enabling/disabling logic of pilot directional earth-fault protection
Pilot directional earth-fault protection comprises permissive scheme and blocking scheme. It can
share pilot channel 1 ([85.DEF.En_IndepCh]=0) with pilot distance protection, or uses independent
pilot channel 2 ([85.DEF.En_IndepCh]=1) by setting logic setting [85.DEF.En_IndepCh]. For
underreach mode, pilot directional earth-fault always adopts independent pilot channel 2. The
logic of receiving signal is shown in Figure 3.10-2.
SET [85.Opt_PilotMode]=Blocking
&
>=1
SIG 85-x.Recv1
&
SIG 85-x.Abnor_Ch1
SIG 85-x.Unblocking1 Valid
&
SET [85.Opt_PilotMode]=PUTT
>=1
>=1
85-x.Valid_Recv_DEF
EN
[85.DEF.En_IndepCh]
SET [85.Opt_PilotMode]=Blocking
&
&
>=1
SIG 85-x.Recv2
&
SIG 85-x.Abnor_Ch2
SIG 85-x.Unblocking2 Valid
Figure 3.10-2 Logic diagram of receiving signal
SIG
FwdDir_ROC
&
85-x.FwdDir_DEF_Pilot
SIG
3I0>[85.DEF.3I0_Set]
SIG
RevDir_ROC
&
85-x.RevDir_DEF_Pilot
SIG
FD.ROC.Pkp
Figure 3.10-3 Forward/reverse direction of zero-sequence power
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3.10.2.1 Permissive Transfer Trip (PTT)
Pilot protection with permissive scheme receives permissive signal from the device of remote end,
so as to combine with local discrimination condition to accelerate tripping, so it has high security.
Operation of forward directional earth fault element is used to send permissive signal to the
remote end when the protection is enabled and will release tripping signal upon receiving
permissive signal from the remote end with further guarded by no operation of reverse directional
earth fault element. This ensures the security of the protection.
The following figure shows the schematic of permissive transfer trip.
85-x.FwdDir_DEF_Pilot
M
EM
85-x.RevDir_DEF_Pilot
A
Fault
B
EN
N
85-x.RevDir_DEF_Pilot
85-x.FwdDir_DEF_Pilot
Relay A
85-x.FwdDir_DEF_Pilot
&
&
[85.DEF.t_DPU]
85-x.Op_DEF
85-x.Op_DEF
[85.DEF.t_DPU]
85-x.FwdDir_DEF_Pilot
Relay B
Figure 3.10-4 Simple schematic of DEF (permissive scheme)
1.
Independent channel mode
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0ms
SIG Trp
[85.DEF.t_DPU]+200ms
0ms
SIG 85-x.ExTrp
SIG 52b_PhA
>=1
150ms
&
SIG 52b_PhB
&
>=1
&
&
[85.DEF.t_DPU]+200ms
0ms
85-x.Send2
SIG 52b_PhC
SIG 85-x.Valid_Recv2
EN
&
[85.DEF.En_IndepCh]=1
SIG FD.Pkp
&
SET [85.Opt_PilotMode]=PUTT
>=1
&
SET [85.Opt_PilotMode]=POTT
SIG 85-x.DEF.On
&
SIG 85-x.FwdDir_DEF_Pilot
&
[85.DEF.t_DPU]
&
85-x.Op_DEF
&
SIG 85-x.RevDir_DEF_Pilot
SIG Current reversal blocking
2.
Shared channel mode
0ms
SIG Trp
[85.DEF.t_DPU]+200ms
0ms
SIG 85-x.ExTrp
SIG 52b_PhA
150ms
&
SIG 52b_PhB
>=1
&
>=1
&
[85.DEF.t_DPU]+200ms
0ms
SIG 52b_PhC
SIG 85-x.Valid_Recv1
EN
&
[85.DEF.En_IndepCh]=0
&
SIG FD.Pkp
SET [85.Opt_PilotMode]=POTT
85-x.Send1
&
SIG 85-x.DEF.On
&
SIG 85-x.FwdDir_DEF_Pilot
&
&
85-x.Op_DEF
&
SIG 85-x.RevDir_DEF_Pilot
SIG Current reversal blocking
Figure 3.10-5 Logic diagram of DEF (permissive scheme)
For current reversal blocking, please refer to section 3.10.2.4 for detail.
3.10.2.2 Blocking
Permissive scheme has high security, but it relies on pilot channel seriously. Pilot directional
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earth-fault protection will not operate when there is an internal fault with abnormal channel.
Blocking scheme could be considered as an alternative.
Blocking scheme sends blocking signal when fault detector picks up and zero-sequence forward
element does not operate or both zero-sequence forward element and zero-sequence reverse
element do not operate. Pilot directional earth-fault protection will operate if forward directional
zero-sequence overcurrent element operates and not receiving blocking signal.
85-x.FwdDir_DEF_Pilot
EM
85-x.RevDir_DEF_Pilot
M
A
Fault
B
EN
N
85-x.RevDir_DEF_Pilot
85-x.FwdDir_DEF_Pilot
Relay A
Relay B
FD.Pkp
FD.Pkp
&
85-x.RevDir_DEF_Pilot
&
&
&
85-x.FwdDir_DEF_Pilot
85-x.RevDir_DEF_Pilot
85-x.FwdDir_DEF_Pilot
&
&
85-x.Op_DEF
&
85-x.Op_DEF
[85.DEF.t_DPU]
&
[85.DEF.t_DPU]
Figure 3.10-6 Simple schematic of blocking
1.
Independent channel mode
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SIG Trp
0ms
[85.DEF.t_DPU]+200ms
SIG 85-x.ExTrp
0ms
150ms
SIG 52b_PhA
>=1
&
>=1
SIG 52b_PhB
&
SIG 52b_PhC
85-x.Send2
SIG 85-x.FwdDir_DEF_Pilot
&
SIG 85-x.RevDir_DEF_Pilot
&
SIG 85-x.Valid_Recv2
&
EN [85.DEF.En_IndepCh]=1
&
[85.DEF.t_DPU]
SIG FD.Pkp
SET [85.Opt_PilotMode]=Blocking
85-x.Op_DEF
&
SIG 85-x.DEF.On
2.
Shared channel mode
SIG Trp
0ms
[85.DEF.t_DPU]+200ms
SIG 85-x.ExTrp
0ms
150ms
SIG 52b_PhA
>=1
&
>=1
SIG 52b_PhB
&
SIG 52b_PhC
85-x.Send1
SIG 85-x.FwdDir_DEF_Pilot
&
SIG 85-x.RevDir_DEF_Pilot
&
SIG 85-x.Valid_Recv1
&
EN [85.DEF.En_IndepCh]=0
&
[85.t_DPU_Blocking1]
SIG FD.Pkp
SET [85.Opt_PilotMode]=Blocking
85-x.Op_DEF
&
SIG 85-x.DEF.On
Figure 3.10-7 Logic diagram of DEF (Blocking scheme)
When DEF shares pilot channel 1 with pilot distance protection, time delay of pilot directional
earth-fault protection will change from the setting [85.DEF.t_DPU] to the setting
[85.t_DPU_Blocking1].
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Because the time delay of pilot directional earth-fault protection has enough margin for current
reversal, so blocking scheme should not consider the current reversal condition.
For blocking scheme, pilot directional earth-fault protection will operate when there is an internal
fault with abnormal channel, however, it is possible that pilot directional earth-fault protection issue
an undesired trip when there is an external fault with abnormal channel.
3.10.2.3 Unblocking
Permissive scheme will operate only when it receives permissive signal from the remote end.
However, it may not receive permissive signal from the remote end when pilot channel fails. For
this case, pilot directional earth-fault protection can adopt unblocking scheme. Under normal
conditions, the signaling equipment works in the pilot frequency, and when the device operates to
send permissive signal, the signaling equipment will be switched to high frequency. While the
channel is blocked, the signaling equipment will receive neither pilot frequency signal nor high
frequency signal. The signaling equipment will provide a contact to the device as unblocking signal.
When the device receives unblocking signal from the signaling equipment, it will recognize
channel failure, and unblocking signal will be taken as permissive signal temporarily.
The unblocking scheme can only be used together with permissive scheme.
EN
[85.En_Unblocking2]
&
&
SIG 85-x.Unblocking2
&
[85.t_Unblocking2]
SIG Selection of multi-phase
EN
85-x.Unblocking2 Valid
0ms
>=1
[85.Opt_PilotCh2]
SIG Pilot DEF forward detection
Figure 3.10-8 Logic diagram for unblocking
3.10.2.4 Current Reversal
The reach of directional earth-fault protection is difficult to define. There may have problem for
pilot direction earth-fault protection applied on parallel line arrangement due to current reversal
phenomenon.
When there is a fault in one of the parallel lines, the direction of the fault current may change
during the sequence tripping of the circuit breaker at both ends as shown in Figure 3.10-9: When a
fault occurs on line C–D near breaker D, the fault current through line A-B to D will flow from A to B.
When breaker D is tripped, but breaker C is not tripped, the fault current in line A-B will then flow
from B to A. This process is the current reversal.
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M
Strong
source
EM
N
A
B
C
M
Weak
source
EN
N
A
B
EN
EM
D
C
Direction of fault current
flow before CB‘D’open
D
Direction of fault current
flow after CB‘D’open
Figure 3.10-9 Current reversal
As shown above, the device A judges a forward fault while the device B judges a reverse fault
before break D is tripped. However, the device A judges a reverse fault while the device B judges a
forward fault after breaker D is tripped. There is a competition between pickup and drop off of pilot
zones in the device A and the device B when the fault measured by the device A changes from
forward direction into reverse direction and vice versa for the device B. There may be
maloperation for the device in line A-B if the forward direction of the device B has operated but the
forward direction of the device A drops off slightly slower or the forward direction of the device B
has operated but the forward direction information of the device A is still received due to the
channel delay (the permissive signal is received).
In general, the following two methods shall be adopted to solve the problem of current reversal:
1.
The fault shall be measured by means of the reverse element of the device B. Once the
reverse element of the device B operates, the send signals and the tripping circuit will be
blocked for a period of time after a short time delay. This method can effectively solve the
problem of competition between the device A and the device B, but there shall be a
precondition. The reverse element of the device B must be in cooperation with the forward
element of the device A, i.e. in case of a fault in adjacent lines, if the forward element of the
device A operates, and the reverse element of the device B must also operate. Once the
bilateral cooperation fails, the anticipated function cannot be achieved. In addition, the
blocking time for sending signals and the tripping circuit after the reverse element of the
device B operates shall be set in combination with the channel time delay.
2.
Considering the pickup and drop off time difference of distance elements and the channel time
delay between the device A and the device B, the maloperation due to current reversal shall
be eliminated by setting the time delay. The reverse direction element of the device is not
required for this method, the channel time delay and the tripping time of adjacent breaker
shall be taken into account comprehensively.
This protection device adopts the second method to eliminate the maloperation due to current
reversal.
SIG
85-x.FwdDir_DEF_Pilot
&
t1
SIG
t2
Current reversal blocking
Signal received conditon
Figure 3.10-10 Logic diagram of current reversal blocking
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t1: pickup time delay of current reversal
t2: dropoff time delay of current reversal
When adopting independent pilot channel 2, t1 and t2 are the settings [85.t_DPU_CR2] and
[85.t_DDO_CR2] respectively, which should be considered individually from channel 1.
When sharing pilot channel 1 with pilot distance protection, t1 and t2 are the settings
[85.t_DPU_CR1] and [85.t_DDO_CR1] respectively.
Referring to above figure, when signal from the remote end is received without the operation of
forward element of pilot directional earth-fault protection, the current reversal blocking logic is
enabled after t1. t1 shall be set the shortest possible but allowing sufficient time for the operation
of forward element of pilot directional earth-fault protection, generally set as 25ms.
Once the current reversal logic is enabled, the healthy line device B transfer tripping is blocked.
The logic will be disabled by either the dropoff of signal or the operation of forward element of pilot
directional earth-fault protection. t2 is required to avoid maloperation for the case that the forward
element of pilot directional earth-fault protection of device B picks up before the signal from device
A drops off. Considering the channel propagation delay and the pickup and drop-off time difference
of the forward element of pilot directional earth-fault protection with margin, t2 is generally set
between 25ms~40ms.
Because the time delay of pilot directional earth-fault protection has an enough margin to current
reversal, current reversal blocking only used for permissive scheme not blocking scheme.
3.10.2.5 CB Echo
When CB Echo logic is applied for DEF, the device will initiate sending a pulse of permissive signal
if signal receive condition is met during CB is in open position.
SIG
FD.Pkp
SIG
52b_PhA
SIG
52b_PhB
SIG
52b_PhC
SIG
85-x Valid_Recv_DEF
EN
85-x.DEF.On
EN
85.DEF.En_IndepCh
&
>=1
&
&
[85.DEF.t_DPU]+200ms
0ms
&
85-x Send_DEF
Figure 3.10-11 Simplified CB Echo logic for POTT
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3.10.3 Function Block Diagram
85
85-x.DEF.En1
85-x.DEF.On
85-x.DEF.En2
85-x.Op_DEF
85-x.DEF.Blk
85-x.DEF_BlkAR
85-x.Abnor_Ch1
85.DEF.On
85-x.Abnor_Ch2
85.Op_DEF
85-x.Rcv1
85.DEF_BlkAR
85-x.Rcv2
85-x.Send1
85-x.ExTrp
85-x.Send2
85-x.Unblocking1
85-x.Unblocking2
3.10.4 I/O Signals
Table 3.10-1 I/O signals of pilot directional earth-fault protection
No.
Input Signal
Description
Pilot directional earth-fault protection x enabling input 1, it is triggered from binary
1
85-x.DEF.En1
2
85-x.DEF.En2
3
85-x.DEF.Blk
4
85-x.Abnor_Ch1
5
85-x.Abnor_Ch2
6
85-x.Recv1
7
85-x.Recv2
8
85-x.ExTrp
9
85-x.Unblocking1
Unblocking signal 1 for pilot directional earth-fault protection x (x=1 or 2)
10
85-x.Unblocking2
Unblocking signal 2 for pilot directional earth-fault protection x (x=1 or 2)
No.
Output Signal
input or programmable logic etc. (x=1 or 2)
Pilot directional earth-fault protection x enabling input 2, it is triggered from binary
input or programmable logic etc. (x=1 or 2)
Pilot directional earth-fault protection x blocking input, it is triggered from binary
input or programmable logic etc. (x=1 or 2)
Input signal of indicating that pilot channel 1 is abnormal for pilot directional
earth-fault protection x (x=1 or 2)
Input signal of indicating that pilot channel 2 is abnormal for pilot directional
earth-fault protection x (x=1 or 2)
Input signal of receiving permissive signal via channel 1 for pilot directional
earth-fault protection x (x=1 or 2)
Input signal of receiving permissive signal via channel 2 for pilot directional
earth-fault protection x (x=1 or 2)
Input signal of initiating sending permissive signal from external tripping signal
(x=1 or 2)
Description
1
85-x.DEF.On
Pilot directional earth-fault protection x is enabled. (x=1 or 2)
2
85-x.Op_DEF
Pilot directional earth-fault protection x operates. (x=1 or 2)
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3
85-x.DEF_BlkAR
4
85.DEF.On
5
85.Op_DEF
6
85.DEF_BlkAR
Pilot directional earth-fault protection x operates to block AR. (x=1 or 2)
General pilot directional earth-fault protection is enabled. It is OR operation
between 85-1.DEF.On and 85-2.DEF.On
General pilot directional earth-fault protection operates. It is OR operation
between 85-1.Op_DEF and 85-2.Op_DEF
General pilot directional earth-fault protection operates to block AR. It is OR
operation between 85-1.DEF_BlkAR and 85-2.DEF_BlkAR
Output signal of sending permissive signal 1 for pilot directional earth-fault
7
85-x.Send1
protection x when pilot directional earth-fault protection sharing pilot channel 1
with pilot distance protection (x=1 or 2)
Output signal of sending permissive signal 2 for pilot directional earth-fault
8
85-x.Send2
protection x when pilot directional earth-fault protection adopting independent pilot
channel 2 (x=1 or 2)
3.10.5 Settings
Table 3.10-2 Settings of pilot directional earth-fault protection
No.
Name
Range
Step
Unit
Remark
Enabling/disabling pilot directional
1
85.DEF.En
earth-fault protection
0 or 1
0: disable
1: enable
Enabling/disabling pilot directional
earth-fault protection operate to
block AR
2
85.DEF.En_BlkAR
0 or 1
0: selective phase tripping and not
blocking AR
1: three-phase tripping and blocking
AR
Enabling/disabling
channel
for
pilot
independent
directional
earth-fault protection
3
85.DEF.En_IndepCh
0:
0 or 1
pilot
directional
earth-fault
protection sharing same channel
with pilot distance protection
1:
pilot
directional
earth-fault
adopting independent pilot channel
Enabling/disabling
unblocking
scheme for pilot DEF via pilot
4
85.En_Unblocking2
0 or 1
channel 2
0: disable
1: enable
5
85.DEF.3I0_Set
(0.050~30.000)×In
0.001
A
Current setting of pilot directional
earth-fault protection
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No.
6
Name
Range
85.DEF.t_DPU
Step
0.001~10.000
Unit
0.001
s
Remark
Time delay of
85.t_DPU_CR2
0.000~1.000
0.001
s
directional
earth-fault protection
Time
7
pilot
delay
pickup for
current
reversal logic when pilot directional
earth-fault
protection
adopts
independent pilot channel 2
Time delay dropoff for current
8
85.t_DDO_CR2
0.000~1.000
0.001
s
reversal logic when pilot directional
earth-fault
protection
adopts
independent pilot channel 2
Table 3.10-3 Internal settings of pilot distance protection
No.
1
Name
Default Value
85.t_Unblocking2
Unit
0.2
s
Remark
Pickup time delay of unblocking scheme for pilot
channel 2
Option of PLC channel for pilot channel 2
2
85.Opt_PilotCh2
1
0: phase-to-phase channel
1: phase-to-ground channel
3.11 Current Direction
3.11.1 General Application
Overcurrent protection is widely used in the power system as backup protection, but in some
cases, the direction of current is necessary to aid to complete the selective tripping. As shown
below:
L
EM
M
C
Fault
D
N
A
B
EN
Figure 3.11-1 Line fault description
When line LM has an earth fault, the fault currents flowing through the relay A and the relay D are
of similar magnitude in most cases. It is desirable that the fault is isolated from the power system
by tripping the circuit breaker C and circuit breaker D. Hence, the overcurrent protection of relay A
and relay D require to associate with current direction to fulfill selective tripping.
Directional earth fault protection has a time delay due to coordinate with that of downstream so it
cannot clear the fault quickly. Pilot directional earth-fault protection, which is fulfilled by directional
earth fault element on both ends, it can maintain fast operation and achieve high sensitivity to
detect high resistance fault.
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3.11.2 Function Description
The module computes direction of phase current and phase-to-phase current, zero-sequence
current and negative-sequence current.
The direction of phase current and phase-to-phase current equips with an under-voltage direction
function to ensure that phase or phase-to-phase overcurrent protection has explicit directionality
when the polarized voltage is too low for close up fault.
The direction of zero-sequence current and negative-sequence current direction equips with an
impedance compensation function to ensure that zero-sequence or negative-sequence
overcurrent protection has explicit directionality when the zero-sequence voltage or the
negative-sequence voltage is too low.
3.11.2.1 Phase/Phase-to-phase Current Direction
By setting the characteristic angle [RCA_OC] to determine the most sensitive forward angle of
phase current and phase-to-phase current, power value is calculated using phase current with
phase polarized voltage or phase-to-phase current with phase-to-phase polarized voltage to
determine the direction of phase current or phase-to-phase current respectively in forward
direction or reverse direction. When the power value is zero, neither forward direction nor reverse
direction is considered. As shown below:
jX
U
φ
θ
I
R
O
Forward direction
Reverse direction
Figure 3.11-2 Vector diagram of current and voltage
Where:
φ is the setting [RCA_OC]
θ is the phase angle between polarized voltage and current
The power value is calculated as below:
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P=U×[I×COS(θ-φ)]
1.
If P>0, the current direction polarized by U is forward direction
2.
If P<0, the current direction polarized by U is reverse direction
From above diagram can be seen, when θ=φ, P reaches to the maximum value. It is considered
as the most sensitive forward direction. Hence, φ is called as sensitivity angle of phase
overcurrent protection.
1.
Polarized voltage of phase or phase-to-phase current direction
In the event of asymmetrical fault, because phase or phase-to-phase voltage may decrease to
very low voltage whereas positive-sequence voltage does not, the polarized voltage of phase or
phase-to-phase current direction uses positive-sequence voltage to avoid wrong direction due to
too low polarized voltage. Therefore, using positive-sequence voltage as polarized voltage can
ensure that the direction determination has no dead zone for asymmetrical fault. For symmetric
fault, if positive-sequence voltage decreases to 15%Un, the device uses memorized
positive-sequence voltage as polarized voltage, the memorized positive-sequence voltage is 1.5
cycles pre-fault positive-sequence voltage.
2.
Phase or phase-to-phase current direction under normal polarized voltage condition
When using normal polarized voltage to calculate phase and phase-to-phase current direction,
there are total twelve direction determination algorithm including forward direction and reverse
direction.
Table 3.11-1 Direction description
Direction
Phase A
Phase B
Phase C
Phase AB
Phase BC
Phase CA
3.
Polarized Voltage
Current
Forward direction
U1a
Ia
Reverse direction
U1a
Ia
Forward direction
U1b
Ib
Reverse direction
U1b
Ib
Forward direction
U1c
Ic
Reverse direction
U1c
Ic
Forward direction
U1ab
Iab
Reverse direction
U1ab
Iab
Forward direction
U1bc
Ibc
Reverse direction
U1bc
Ibc
Forward direction
U1ca
Ica
Reverse direction
U1ca
Ica
Phase or phase-to-phase current direction for under-voltage conditions
When the symmetrical fault occurs on a power system, positive-sequence voltage may reduce to
less than 0.15Un, the device will switch to phase or phase-to-phase current direction for
under-voltage condition. The 1.5 cycle pre-fault positive-sequence voltage is used as polarized
voltage with reverse threshold to ensure stable direction decision when three-phase voltage goes
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to approximately zero due to close up fault.
At first, the threshold is forward offset before direction is determined, and the threshold will be
reversed offset after direction is determined.
3.11.2.2 Zero-sequence/Negative-sequence Current Direction
By setting the characteristic angle [RCA_ROC] and [RCA_NegOC] to determine the most
sensitive forward angle of zero-sequence current and negative-sequence current, power value is
calculated using zero-sequence current with zero-sequence voltage or negative-sequence current
with negative-sequence voltage to determine the direction of zero-sequence current and
negative-sequence current respectively in forward direction or reverse direction.
When the power value is between 0 and -0.1In, neither forward direction nor reverse direction is
considered.
jX
3U0
θ-180°
-3I0
φ
R
O
3I0
θ
Reverse direction
Forward direction
Figure 3.11-3 Vector diagram of zero-sequence power
Vector diagram of negative-sequence power is similar to that of zero-sequence power.
Where:
φ is the setting [RCA_ROC] or the setting [RCA_NegOC]
θ is the phase angle between zero/negative-sequence voltage and zero/negative-sequence
current
3I0: calculated zero-sequence current by vector sum of Ia, Ib and Ic
The power value is calculated as below:
P=U×[I×COS(θ-φ)]

If P>0, the direction of zero /negative-sequence current is reverse direction
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
If P<-0.1InVA, the direction of zero /negative-sequence current is forward direction
1.
The direction of zero-sequence current
Calculating the power value using zero-sequence current (3I0) and zero-sequence voltage (3U0)
to determine the direction of zero-sequence current
According to the equation:
The zero-sequence current and the zero-sequence voltage can be gained by calculation
Zero-sequence power is: P=3U0×[3I0×COS(θ-φ)]
2.
The direction of negative-sequence current
Calculating the power value using negative-sequence current (3I2) and negative-sequence
voltage (3U2) to determine the direction of negative-sequence current
According to the equation:
The negative-sequence current and the negative-sequence voltage can be gained by calculation
Negative-sequence power is: P=3U2×[3I2×COS(θ-φ)]
3.
The direction of zero-sequence/negative-sequence current with impedance compensation
When zero-sequence impedance or negative-sequence impedance behind the device is very
small, if the fault in forward direction happens, the measured zero-sequence voltage or
negative-sequence voltage by the device may be relatively small to determine correct direction. In
order to solve this problem, compensated zero-sequence voltage and negative-sequence voltage
are used for power calculation.
The compensation formula is as follows:
is the setting [Z0_Comp], which cannot exceed the total zero-sequence impedance of
the protected line, and a half of the total zero-sequence impedance of the protected line is
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recommended.
is the setting [Z2_Comp], which cannot exceed the total negative-sequence impedance
of the protected line.
NOTICE!
Phase current direction element is used as the direction element of phase overcurrent
protection and auxiliary direction element of distance protection. It is required to set
according to actual system parameters. Hence, the setting [RCA_OC] should be set
correctly according to actual system parameters if distance protection is enabled even if
phase overcurrent protection is disabled.
Zero-sequence current direction element is used as the direction element of earth fault
protection and auxiliary direction element of zone 1 of distance protection. It is required
to set according to actual system parameters. Hence, the setting [RCA_ROC] should
be set correctly according to actual system parameters if distance protection is enabled
even if earth fault protection is disabled.
Negative-sequence current direction element is used as the direction element of
negative-sequence overcurrent protection and auxiliary direction element of distance
protection and phase overcurrent protection for asymmetric fault. It is required to set
according to actual system parameters. Hence, the setting [RCA_NegOC] should be
set correctly according to actual system parameters if any of distance protection and
phase overcurrent protection is enabled even if negative-sequence overcurrent
protection is disabled.
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3.11.3 Function Block Diagram
DIR
FwdDir_ROC
RevDir_ROC
FwdDir_NegOC
RevDir_NegOC
FwdDir_A
FwdDir_B
FwdDir_C
RevDir_A
RevDir_B
RevDir_C
FwdDir_AB
FwdDir_BC
FwdDir_CA
RevDir_AB
RevDir_BC
RevDir_CA
3.11.4 I/O Signals
Table 3.11-2 I/O signals of current direction
No.
Output Signal
Description
1
FwdDir_ROC
The forward direction of zero-sequence power
2
RevDir_ROC
The reverse direction of zero-sequence power
3
FwdDir_NegOC
The forward direction of negative-sequence power
4
RevDir_NegOC
The reverse direction of negative-sequence power
5
FwdDir_A
The forward direction of phase-A current
6
FwdDir_B
The forward direction of phase-B current
7
FwdDir_C
The forward direction of phase-C current
8
RevDir_A
The reverse direction of phase-A current
9
RevDir_B
The reverse direction of phase-B current
10
RevDir_C
The reverse direction of phase-C current
11
FwdDir_AB
The forward direction of phase-AB current
12
FwdDir_BC
The forward direction of phase-BC current
13
FwdDir_CA
The forward direction of phase-CA current
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14
RevDir_AB
The reverse direction of phase-AB current
15
RevDir_BC
The reverse direction of phase-BC current
16
RevDir_CA
The reverse direction of phase-CA current
3.11.5 Settings
Table 3.11-3 Settings of current direction
No.
Name
Range
Step
Unit
1
RCA_OC
30.00~89.00
0.01
deg
2
RCA_ROC
30.00~89.00
0.01
deg
3
RCA_NegOC
30.00~89.00
0.01
deg
4
Z0_Comp
(0.000~4Unn)/In
0.001
ohm
5
Z2_Comp
(0.000~4Unn)/In
0.001
ohm
Remark
The characteristic angle of directional
phase overcurrent element
The characteristic angle of directional earth
fault element
The characteristic angle of directional
negative-sequence overcurrent element
The
compensated
zero-sequence
impedance
The
compensated
negative-sequence
impedance
3.12 Phase Overcurrent Protection
3.12.1 General Application
When a fault occurs in power system, usually the fault current would be very large and phase
overcurrent protection operates monitoring fault current is then adopted to avoid further damage to
protected equipment. Directional element can be selected to improve the sensitivity and selectivity
of the protection. For application on feeder-transformer circuits, second harmonic can also be
selected to block phase overcurrent protection to avoid the effect of inrush current on the
protection.
3.12.2 Function Description
Phase overcurrent protection has following functions:
1.
Four-stage phase overcurrent protection with independent logic, current and time delay
settings.
2.
All stages can be selected as definite-time or inverse-time characteristic. The inverse-time
characteristic is selectable among IEC and ANSI/IEEE standard inverse-time characteristics,
and a user-defined inverse-time curve is available for stage 1 of phase overcurrent protection.
3.
Direction control element can be selected to control each stage phase overcurrent protection
with three options: no direction, forward direction and reverse direction.
4.
Second harmonic can be selected to block each stage of phase overcurrent protection.
3.12.2.1 Overview
Phase overcurrent protection consists of following three elements:
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1.
Overcurrent element: each stage is independent overcurrent element.
2.
Direction control element: one direction control element shared by all overcurrent elements,
and each overcurrent element can individually select protection direction. When phase
overcurrent protection is controlled by direction control element, negative-sequence current
direction element is also effective to ensure correct operation, especially for phase-to-phase
fault.
3.
Harmonic blocking element: one harmonic blocking element shared by all overcurrent
elements and each phase overcurrent element can individually enable the output signal from
harmonic element as a blocking input.
3.12.2.2 Phase Overcurrent Element
The operation criterion for each stage of overcurrent element is:
Ip> [50/51Pi.I_Set]
Equation 3.12-1
Where:
Ip is measured phase current.
[50/51Pi.I_Set] is the current setting of stage i of overcurrent element. (i=1, 2, 3, or 4)
3.12.2.3 Direction Control Element
In order to prevent phase current direction element from overreaching operation characteristic for
phase-to-phase fault, negative-sequence current direction element is also used as auxiliary
direction criterion of phase overcurrent protection for asymmetric fault. Please refer to section 3.11
for details.
3.12.2.4 Harmonic Blocking Element
When phase overcurrent protection is used to protect feeder-transformer circuits harmonic
blocking function can be selected for each stage of phase overcurrent element by configuring logic
setting [50/51Pi.En_Hm2_Blk] to prevent maloperation due to inrush current.
When the percentage of second harmonic component to fundamental component of any phase
current is greater than the setting [50/51P.K_Hm2], harmonic blocking element operates to block
stage x overcurrent element if corresponding logic setting [50/51Pi.En_Hm2_Blk] enabled.
Operation criterion:
IP_2nd>[50/51P. K_Hm2]×IP
Equation 3.12-2
Where:
is second harmonic of phase current
is fundamental component of phase current.
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[50/51P.K_Hm2] is harmonic blocking coefficient.
If fundamental component of any phase current is lower than the minimum operating current
(0.1In), then harmonic calculation is not carried out and harmonic blocking element does not
operate.
3.12.2.5 Characteristic Curve
All stages can be selected as definite-time or inverse-time characteristic, inverse-time operating
characteristic is as follows.
Equation 3.12-3
Where:
Iset is current setting [50/51Pi.I_Set].
Tp is time multiplier setting [50/51Pi.TMS].
α is a constant.
K is a constant.
C is a constant.
I is measured phase current from line CT
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50/51Pi.Opt_Curve], and parameters of available characteristics for selection are shown in
the following table.
Table 3.12-1 Inverse-time curve parameters
50/51Pi.Opt_Curve
α
K
Time Characteristic
C
DefTime
Definite time
IECN
IEC Normal inverse
0.14
0.02
0
IECV
IEC Very inverse
13.5
1.0
0
IECE
IEC Extremely inverse
80.0
2.0
0
IECST
IEC Short-time inverse
0.05
0.04
0
IECLT
IEC Long-time inverse
120.0
1.0
0
ANSIE
ANSI Extremely inverse
28.2
2.0
0.1217
ANSIV
ANSI Very inverse
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
ANSI Moderately inverse
0.0515
0.02
0.114
ANSILTE
ANSI Long-time extremely inverse
64.07
2.0
0.25
ANSILTV
ANSI Long-time very inverse
28.55
2.0
0.712
ANSILT
ANSI Long-time inverse
0.086
0.02
0.185
UserDefine
Programmable user-defined
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If all available curves do not comply with user application, user may set [50/51Pi.Opt_Curve] as
“UserDefine” to customize the inverse-time curve characteristic with constants α, K and C. (only
stage 1)
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50/51Pi.tmin], then the operating time of the protection changes to the value of setting
[50/51Pi.tmin] automatically.
Define-time or inverse-time phase overcurrent protection drops off instantaneously after fault
current disappears.
3.12.3 Function Block Diagram
50/51Pi
50/51Pi.En1
50/51Pi.On
50/51Pi.En2
50/51Pi.StA
50/51Pi.Blk
50/51Pi.StB
50/51Pi.StC
50/51Pi.St
50/51Pi.Op
3.12.4 I/O Signals
Table 3.12-2 I/O signals of phase overcurrent protection
No.
Input Signal
1
50/51Pi.En1
2
50/51Pi.En2
3
50/51Pi.Blk
No.
Output Signal
Description
Stage i of phase overcurrent protection enabling input 1, it is triggered from binary
input or programmable logic etc. (i=1, 2, 3, 4)
Stage i of phase overcurrent protection enabling input 2, it is triggered from binary
input or programmable logic etc. (i=1, 2, 3, 4)
Stage i of phase overcurrent protection blocking input, it is triggered from binary
input or programmable logic etc. (i=1, 2, 3, 4)
Description
1
50/51Pi.On
Stage i of phase overcurrent protection is enabled. (i=1, 2, 3, 4)
2
50/51Pi.Op
Stage i of phase overcurrent protection operates. (i=1, 2, 3, 4)
3
50/51Pi.St
Stage i of phase overcurrent protection starts. (i=1, 2, 3, 4)
4
50/51Pi.StA
Stage i of phase overcurrent protection starts (A-Phase, i=1, 2, 3, 4).
5
50/51Pi.StB
Stage i of phase overcurrent protection starts (B-Phase, i=1, 2, 3, 4).
6
50/51Pi.StC
Stage i of phase overcurrent protection starts (C-Phase, i=1, 2, 3, 4).
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3.12.5 Logic
EN
[50/51Pi.En]
&
SIG 50/51Pi.En1
&
50/51Pi.On
SIG 50/51Pi.En2
>=1
SIG 50/51Pi.Blk
50/51Pi.St
SET Ia>[50/51Pi.I_Set]
&
50/51Pi.StA
SET Ib>[50/51Pi.I_Set]
&
50/51Pi.StB
SET Ic>[50/51Pi.I_Set]
&
50/51Pi.StC
SET [50/51Pi.Opt_Dir]=Forward
&
SIG Forward DIR
SET [50/51Pi.Opt_Dir]=Reverse
&
>=1
>=1
SIG Reverse DIR
SIG VTS.Alm
EN
&
[50/51Pi.En_VTS_Blk]
SET [50/51Pi.Opt_Dir]=Non_Directional
SIG Three phase currents
2nd Hm Detect
&
&
SIG IP_2nd>[ 50/51P.K_Hm2]×IP
SET [50/51Pi.En_Hm2_Blk]
SIG 50/51Pi.On
&
SIG FD.Pkp
SET [50/51Pi.Opt_Curve]=DefTime
&
[50/51Pi.t_Op]
0
>=1
50/51Pi.Op
&
Timer
t
SIG 50/51Pi.St
Figure 3.12-1 Logic diagram of phase overcurrent protection
i=1, 2, 3, 4
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3.12.6 Settings
Table 3.12-3 Settings of phase overcurrent protection
No.
Name
Range
Step
Unit
Remark
Setting
1
50/51P.K_Hm2
0.000~1.000
0.001
of
component
second
for
harmonic
blocking
phase
overcurrent elements
2
50/51Pi.I_Set
(0.050~30.000)×In
0.001
A
3
50/51Pi.t_Op
0.000~20.000
0.001
s
Current setting for stage i of phase
overcurrent protection (i=1, 2, 3, 4)
Time delay for stage i of phase
overcurrent protection (i=1, 2, 3, 4)
Enabling/disabling stage i of phase
4
50/51Pi.En
overcurrent protection (i=1, 2, 3, 4)
0 or 1
0: disable
1: enable
Enabling/Disabling
auto-reclosing
blocked when stage i of phase
5
50/51Pi.En_BlkAR
overcurrent protection operates (i=1,
0 or 1
2, 3, 4)
0: disable
1: enable
Enabling/Disabling stage i of phase
overcurrent protection is blocked by
6
50/51Pi.En_VTS_Blk
0 or 1
VT circuit failure (i=1, 2, 3, 4)
0: disable
1: enable
Non_Directional
7
50/51Pi.Opt_Dir
Direction option for stage i of phase
Forward
overcurrent protection (i=1, 2, 3, 4)
Reverse
Enabling/disabling second harmonic
blocking for
8
50/51Pi.En_Hm2_Blk
0 or 1
stage i
of
phase
overcurrent protection (i=1, 2, 3, 4)
0: disable
1: enable
DefTime
IECN
IECV
IECE
9
50/51Pi.Opt_Curve
Option of characteristic curve for
IECST
stage
IECLT
i
of
phase
overcurrent
protection (i=1, 2, 3, 4)
ANSIE
ANSIV
ANSI
ANSIM
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No.
Name
Range
Step
Unit
Remark
ANSILTE
ANSILTV
ANSILT
UserDefine
Time multiplier setting for stage i of
10
50/51Pi.TMS
0.010~200.000
0.001
inverse-time
phase
overcurrent
protection (i=1, 2, 3, 4)
Minimum operating time for stage i
11
50/51Pi.tmin
0.000~20.000
0.001
s
of inverse-time phase overcurrent
protection (i=1, 2, 3, 4)
Constant
12
50/51P1.Alpha
0.010~5.000
0.001
“α”
for
customized
stage
1
of
inverse-time
characteristic
phase
overcurrent
protection
Constant
13
50/51P1.C
0.000~20.000
0.001
“C”
for
customized
stage
1
of
inverse-time
characteristic
phase
overcurrent
protection
Constant
14
50/51P1.K
0.050~20.000
0.001
“K”
for
customized
characteristic
stage
1
of
inverse-time
phase
overcurrent
protection
3.13 Earth Fault Protection
3.13.1 General Application
During normal operation of power system, there is trace residual current, whereas a fault current
flows to earth will result in greater residual current. Therefore, residual current is adopted for the
calculation of earth fault protection.
In order to improve the selectivity of earth fault protection in power grid with multiple power
sources, directional element can be selected to control earth fault protection. For application on
line-transformer unit, second harmonic also can be selected to block earth fault protection to avoid
the effect of sympathetic current on the protection.
3.13.2 Function Description
Earth fault protection has following functions:
1.
Four-stage earth fault protection with independent logic, current and time delay settings.
2.
All stages can be selected as definite-time or inverse-time characteristic. The inverse-time
characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time characteristics,
and a user-defined inverse-time curve is available for stage 1 of earth fault protection.
3.
Directional element can be selected to control each stage of earth fault protection with three
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options: no direction, forward direction and reverse direction.
4.
Second harmonic can be selected to block each stage of earth fault protection.
5.
Stage 2, 3, 4 of earth fault protection can enable short time delay to improve operation speed.
3.13.2.1 Overview
Earth fault protection consists of following three elements:
1.
Overcurrent element: each stage equipped with one independent overcurrent element.
2.
Directional control element: one direction control element shared by all overcurrent elements,
and each overcurrent element can individually select protection direction.
3.
Harmonic blocking element: one harmonic blocking element shared by all overcurrent
elements and each overcurrent element can individually enable the output signal of harmonic
blocking element as a blocking input.
3.13.2.2 Zero-sequence Overcurrent Element
The operation criterion for each stage of earth fault protection is:
3I0>[50/51Gi.3I0_Set]
Equation 3.13-1
Where:
3I0 is the calculated residual current.
[50/51Gi.3I0_Set] is the current setting of stage i of earth fault protection. (i=1, 2, 3, or 4)
3.13.2.3 Direction Control Element
Please refer to section 3.11 for details.
3.13.2.4 Harmonic Blocking Element
In order to prevent effects of inrush current on earth fault protection, harmonic blocking function
can be selected for each stage of earth fault element by configuring logic setting
[50/51Gx.En_Hm2_Blk].
When the percentage of second harmonic component to fundamental component of residual
current is greater than the setting [50/51G.K_Hm2], harmonic blocking element operates to block
stage x of earth fault protection if corresponding logic setting [50/51Gx.En_Hm2_Blk] is enabled.
Operation criterion:
I0_2nd>[50/51G. K_Hm2]×I0
Equation 3.13-2
Where:
is second harmonic of residual current
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is fundamental component of residual current.
[50/51G.K_Hm2] is harmonic blocking coefficient.
If fundamental component of residual current is lower than the minimum operating current (0.1In)
then harmonic calculation is not carried out and harmonic blocking element does not operate.
3.13.2.5 Characteristic Curve
All 4 stages earth fault protection can be selected as definite-time or inverse-time characteristic,
and inverse-time operating time curve is as follows.
Equation 3.13-3
Where:
Iset is residual current setting [50/51Gi.3I0_Set].
Tp is time multiplier setting [50/51Gi.TMS].
K is a constant
C is a constant.
α is a constant.
3I0 is the calculated residual current.
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50/51Gi.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.
Table 3.13-1 Inverse-time curve parameters
50/51Gi.Opt_Curve
Time Characteristic
α
K
C
DefTime
Definite time
IECN
IEC Normal inverse
0.14
0.02
0
IECV
IEC Very inverse
13.5
1.0
0
IECE
IEC Extremely inverse
80.0
2.0
0
IECST
IEC Short-time inverse
0.05
0.04
0
IECLT
IEC Long-time inverse
120.0
1.0
0
ANSIE
ANSI Extremely inverse
28.2
2.0
0.1217
ANSIV
ANSI Very inverse
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
ANSI Moderately inverse
0.0515
0.02
0.114
ANSILTE
ANSI Long-time extremely inverse
64.07
2.0
0.25
ANSILTV
ANSI Long-time very inverse
28.55
2.0
0.712
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50/51Gi.Opt_Curve
K
Time Characteristic
ANSILT
ANSI Long-time inverse
UserDefine
Programmable User-defined
0.086
α
0.02
C
0.185
If all available curves do not comply with user application, user may set [50/51Gi.Opt_Curve] as
“UserDefine” to customize the inverse-time curve characteristic, and constants K, α and C with
configuration tool software. (only stage 1)
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50/51Gi.tmin], then the operating time of the protection changes to the value of setting
[50/51Gi.tmin] automatically.
Define-time or inverse-time directional earth-fault protection drops off instantaneously after fault
current disappears.
3.13.3 Function Block Diagram
50/51Gi
50/51Gi.En1
50/51Gi.On
50/51Gi.En2
50/51Gi.On_ShortDly
50/51Gi.Blk
50/51Gi.St
50/51Gi.En_ShortDly
50/51Gi.Op
50/51Gi.Blk_ShortDly
3.13.4 I/O Signals
Table 3.13-2 I/O signals of earth fault protection
No.
Input Signal
1
50/51Gi.En1
2
50/51Gi.En2
3
50/51Gi.Blk
4
50/51Gi.En_ShortDly
5
50/51Gi.Blk_ShortDly
No.
Output Signal
Description
Stage i of earth fault protection enabling input 1, it is triggered from binary
input or programmable logic etc. (i=1, 2, 3, 4)
Stage i of earth fault protection enabling input 2, it is triggered from binary
input or programmable logic etc. (i=1, 2, 3, 4)
Stage i of earth fault protection blocking input, it is triggered from binary input
or programmable logic etc. (i=1, 2, 3, 4)
Short time delay for stage i of earth fault protection enabling input, it is
triggered from binary input or programmable logic etc. (i=2, 3, 4)
Short time delay for stage i of earth fault protection blocking input, it is
triggered from binary input or programmable logic etc. (i=2, 3, 4)
Description
1
50/51Gi.On
Stage i of earth fault protection is enabled. (i=1, 2, 3, 4)
2
50/51Gi.On_ShortDly
Short time delay for stage i of earth fault protection is enabled. (i=2, 3, 4)
3
50/51Gi.St
Stage i of earth fault protection starts. (i=1, 2, 3, 4)
4
50/51Gi.Op
Stage i of earth fault protection operates. (i=1, 2, 3, 4)
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3.13.5 Logic
EN
[50/51G1.En]
&
SIG 50/51G1.En1
&
50/51G1.On
SIG 50/51G1.En2
&
SIG 50/51G1.Blk
SIG FD.Pkp
SET 3I0>[50/51G1.3I0_Set]
EN
[50/51G1.En_Abnor_Blk]
>=1
SIG No abnormal conditions
&
SET [50/51G1.Opt_Dir]=Forward
&
SIG Forward DIR
SET [50/51G1.Opt_Dir]=Reverse
&
>=1
>=1
&
&
&
50/51G1.St
SIG Reverse DIR
SET [50/51G1.Opt_Dir]=Non_Directional
&
EN
[50/51G1.En_VTS_Blk]
>=1
SIG VTS.Alm
&
SIG CTS.Alm
&
EN [50/51G1.En_CTS_Blk]
SIG I3P
>=1
2nd Hm Detect
&
SET [50/51G1.En_Hm2_Blk]
&
SIG 50/51G1.St
Timer
t
>=1
&
50/51G1.Op
[50/51G1.t_Op]
0
SET [50/51G1.Opt_Curve]=DefTime
Figure 3.13-1 Logic diagram of stage 1 of earth fault protection
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EN
[50/51Gi.En_ShortDly]
&
SIG 50/51Gi.En_ShortDly
50/51Gi.On_ShortDly
SIG 50/51Gi.Blk_ShortDly
EN
[50/51Gi.En]
&
&
SIG 50/51Gi.En1
50/51Gi.On
SIG 50/51Gi.En2
&
SIG 50/51Gi.Blk
SIG FD.Pkp
SET 3I0>[50/51Gi.3I0_Set]
EN
[50/51Gi.En_Abnor_Blk]
>=1
SIG No abnormal conditions
&
SET [50/51Gi.Opt_Dir]=Forward
&
SIG Forward DIR
SET [50/51Gi.Opt_Dir]=Reverse
&
>=1
>=1
&
&
&
50/51Gi.St
SIG Reverse DIR
SET [50/51Gi.Opt_Dir]=Non_Directional
EN
&
[50/51Gi.En_VTS_Blk]
>=1
SIG VTS.Alm
&
SIG CTS.Alm
EN
&
[50/51Gi.En_CTS_Blk]
SIG I3P
>=1
2nd Hm Detect
&
SET [50/51Gi.En_Hm2_Blk]
&
SIG 50/51Gi.St
Timer
t
&
>=1
[50/51Gi.t_Op]
0
[50/51Gi.t_ShortDly]
0
50/51Gi.Op
SET [50/51Gi.Opt_Curve]=DefTime
&
SIG 50/51Gi.On_ShortDly
Figure 3.13-2 Logic diagram of stage i of earth fault protection
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i=2, 3, 4
Abnormal condition 1: when the system is under pole disagreement condition, for 1-pole AR, earth
fault protection will operate. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “1”, the stage x of
earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is set as “0”,
earth fault protection is not controlled by direction element.
Abnormal condition 2: When manually closing circuit breaker, three phases of the circuit breaker
maybe not operate simultaneously, and SOTF protection should operate. If the logic setting
[50/51Gx.En_Abnor_Blk] is set as “1”, the stage x of earth fault protection will be blocked. If the
logic setting [50/51Gx.En_Abnor_Blk] is set as “0”, earth fault protection is not controlled by
direction element.
VTS.Alm (VT circuit failure): If the logic setting [50/51Gx.En_VTS_Blk] is set as “1”, the stage x of
earth fault protection will be blocked. If the logic setting [50/51Gx.En_VTS_Blk] is set as “0”, earth
fault protection is not controlled by direction element.
3.13.6 Settings
Table 3.13-3 Settings of earth fault protection
No.
Name
Range
Step
Unit
Remark
Setting
1
50/51G.K_Hm2
0.000~1.000
0.001
of
second
harmonic
component for blocking earth fault
elements
2
50/51Gi.3I0_Set
(0.050~30.000)×In
0.001
A
3
50/51Gi.t_Op
0.000~20.000
0.001
s
Current setting for stage i of earth
fault protection (i=1, 2, 3, 4)
Time delay for stage i of earth
fault protection (i=1, 2, 3, 4)
Enabling/disabling stage i of earth
4
50/51Gi.En
fault protection (i=1, 2, 3, 4)
0 or 1
0: disable
1: enable
Enabling/Disabling auto-reclosing
blocked when stage i of earth fault
5
50/51Gi.En_BlkAR
0 or 1
protection operates (i=1, 2, 3, 4)
0: disable
1: enable
Non_Directional
6
50/51Gi.Opt_Dir
Forward
Direction option for stage i of
earth fault protection (i=1, 2, 3, 4)
Reverse
Enabling/disabling
second
harmonic blocking for stage i of
7
50/51Gi.En_Hm2_Blk
0 or 1
earth fault protection (i=1, 2, 3, 4)
0: disable
1: enable
8
50/51Gi.En_Abnor_Blk
0 or 1
Enabling/disabling
blocking
for
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No.
Name
Range
Step
Unit
Remark
stage i of earth fault protection
under abnormal conditions (i=1, 2,
3, 4)
0: disable
1: enable
Enabling/disabling
blocking
for
stage i of earth fault protection
9
50/51Gi.En_VTS_Blk
under VT failure conditions (i=1,
0 or 1
2, 3, 4)
0: disable
1: enable
Enabling/disabling
blocking
for
stage i of earth fault protection
10
50/51Gi.En_CTS_Blk
under CT failure conditions (i=1,
0 or 1
2, 3, 4)
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
11
50/51Gi.Opt_Curve
Option of characteristic curve for
ANSIE
stage i of earth fault protection
ANSIV
(i=1, 2, 3, 4)
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Time multiplier setting for stage i
12
50/51Gi.TMS
0.010~200.000
0.001
of
inverse-time
earth
fault
protection (i=1, 2, 3, 4)
Minimum operating time for stage
13
50/51Gi.tmin
0.050~20.000
0.001
s
i
of
inverse-time
earth
fault
protection (i=1, 2, 3, 4)
Constant “α” for stage 1 of
14
50/51G1.Alpha
0.010~5.000
0.001
customized
characteristic
inverse-time
earth
fault
protection
15
50/51G1.C
0.000~20.000
0.001
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Constant “C” for stage 1 of
customized
inverse-time
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3 Operation Theory
No.
Name
Range
Step
Unit
Remark
characteristic
earth
fault
protection
Constant “K” for stage 1 of
16
50/51G1.K
0.050~20.000
customized
0.001
characteristic
inverse-time
earth
fault
protection
17
50/51Gi.t_ShortDly
0.000~20.000
0.001
s
Short time delay for stage i of
earth fault protection (i=2, 3, 4)
Enabling/disabling
short
time
delay for stage i of earth fault
18
50/51Gi.En_ShortDly
0 or 1
protection (i=2, 3, 4)
0: disable
1: enable
3.14 Negative-sequence Overcurrent Protection
3.14.1 General Application
When an asymmetric short-circuit fault happens to the power system or the power system is under
asymmetrical three-phase operation, the power system will generate negative-sequence current.
Negative-sequence overcurrent will cause generator, motor and other equipments serious
damage, so negative-sequence overcurrent protection is used to prevent them. In order to make
negative-sequence overcurrent protection own selectivity in multiplex power supply system,
negative-sequence overcurrent protection can be controlled by direction control element.
3.14.2 Function Description
Negative-sequence overcurrent has following functions:
1.
Four-stage negative-sequence overcurrent protection with independent logic, current and
time delay settings.
2.
Each stage can be selected to block AR by the setting and stage 4 of negative-sequence
overcurrent protection can be selected to operate to trip or alarm.
3.
All stages can be selected as definite-time or inverse-time characteristic. The inverse-time
characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time characteristics,
and a user-defined inverse-time curve is available for stage 1 of negative-sequence
overcurrent protection.
4.
Directional element can be selected to control each stage of negative-sequence overcurrent
protection with three options: no direction, forward direction and reverse direction.
5.
CT circuit failure can be selected to block each stage of negative-sequence overcurrent
protection.
6.
Each stage can select independent releasing threshold based on the ratio of
negative-sequence current to positive-sequence current to prevent negative-sequence
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overcurrent protection from undesired operation for three-phase fault with asymmetrical
position exchange of three-phase.
3.14.2.1 Overview
Negative-sequence overcurrent protection consists of following three elements:
1.
Fault detector: each stage is controlled by the fault detector based on negative-sequence
current. Negative-sequence overcurrent protection can operate when the fault detector based
on negative-sequence current operate and it is enabled.
2.
Overcurrent element: each stage is equipped with one independent overcurrent element.
3.
Directional control element: one direction control element is shared by all overcurrent
elements, and each overcurrent element can individually select protection direction.
4.
Ratio element: each stage is equipped with one independent ratio element (I2/I1), usually the
same setting is applied for all stages.
3.14.2.2 Negative-sequence Overcurrent Element
The operation criterion for each stage of negative-sequence overcurrent protection is:
I2>[50/51Qi.I2_Set]
&
Equation 3.14-1
I2/I1>[50/51Qi.I2/I1_Set]
Where:
I2 is the calculated negative-sequence current.
I1 is the calculated positive-sequence current.
[50/51Qi.I2_Set] is the current setting of stage i of negative-sequence overcurrent protection. (i=1,
2, 3 or 4)
3.14.2.3 Direction Control Element
Please refer to section 3.11 for details.
3.14.2.4 Characteristic Curve
All 4 stages negative-sequence overcurrent protection can be selected as definite-time or
inverse-time characteristic, and inverse-time operating time curve is as follows.
Equation 3.14-2
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Where:
Iset is negative-sequence current setting [50/51Qi.I2_Set].
Tp is time multiplier setting [50/51Qi.TMS].
K is a constant
C is a constant.
α is a constant.
I2 is the calculated negative-sequence current.
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50/51Qi.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.
Table 3.14-1 Inverse-time curve parameters
50/51Qi.Opt_Curve
Time Characteristic
α
K
C
DefTime
Definite time
IECN
IEC Normal inverse
0.14
0.02
0
IECV
IEC Very inverse
13.5
1.0
0
IECE
IEC Extremely inverse
80.0
2.0
0
IECST
IEC Short-time inverse
0.05
0.04
0
IECLT
IEC Long-time inverse
120.0
1.0
0
ANSIE
ANSI Extremely inverse
28.2
2.0
0.1217
ANSIV
ANSI Very inverse
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
ANSI Moderately inverse
0.0515
0.02
0.114
ANSILTE
ANSI Long-time extremely inverse
64.07
2.0
0.25
ANSILTV
ANSI Long-time very inverse
28.55
2.0
0.712
ANSILT
ANSI Long-time inverse
0.086
0.02
0.185
UserDefine
Programmable User-defined
If all available curves do not comply with user application, user may set [50/51Qi.Opt_Curve] as
“UserDefine” to customize the inverse-time curve characteristic, and constants K, α and C with
configuration tool software. (only stage 1)
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50/51Qi.tmin], then the operating time of the protection changes to the value of setting
[50/51Qi.tmin] automatically.
Define-time or inverse-time directional negative-sequence overcurrent protection drops off
instantaneously after fault current disappears.
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3.14.3 Function Block Diagram
50/51Qi
50/51Gi.En1
50/51Qi.On
50/51Gi.En2
50/51Qi.St
50/51Qi.Blk
50/51Qi.Op
50/51Q4.Alm
3.14.4 I/O Signals
Table 3.14-2 I/O signals of negative-sequence overcurrent protection
No.
Input Signal
1
50/51Qi.En1
2
50/51Qi.En2
3
50/51Qi.Blk
No.
Output Signal
Description
Stage i of negative-sequence overcurrent protection enabling input 1, it is
triggered from binary input or programmable logic etc. (i=1, 2, 3, 4)
Stage i of negative-sequence overcurrent protection enabling input 2, it is
triggered from binary input or programmable logic etc. (i=1, 2, 3, 4)
Stage i of negative-sequence overcurrent protection blocking input, it is triggered
from binary input or programmable logic etc. (i=1, 2, 3, 4)
Description
1
50/51Qi.On
Stage i of negative-sequence overcurrent protection is enabled. (i=1, 2, 3, 4)
2
50/51Qi.St
Stage i of negative-sequence overcurrent protection starts. (i=1, 2, 3, 4)
3
50/51Qi.Op
Stage i of negative-sequence overcurrent protection operates. (i=1, 2, 3, 4)
4
50/51Q4.Alm
Stage 4 of negative-sequence overcurrent protection operates to alarm.
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3.14.5 Logic
EN
[50/51Qx.En]
SIG
50/51Qx.En1
SIG
50/51Qx.En2
SIG
50/51Qx.Blk
SET
I2/I1>[50/51Qx.I2/I1_Set]
SET
I2>[50/51Qx.I2_Set]
EN
[50/51Qx.En_Abnor_Blk]
SIG
No abnormal conditions
&
&
50/51Qx.On
&
>=1
&
SET
[50/51Qx.Opt_Dir]=Forward
SIG
Forward DIR
SET
[50/51Qx.Opt_Dir]=Reverse
SIG
Reverse DIR
SET
[50/51Qx.Opt_Dir]=Non_Directional
&
&
>=1
>=1
&
&
&
50/51Qx.St
Timer
t
50/51Qx.Op
t
&
EN
[50/51Qx.En_VTS_Blk]
SIG
VTS.Alm
SIG
CTS.Alm
EN
[50/51Qx.En_CTS_Blk]
SIG
FD.NOC.Pkp
>=1
&
Figure 3.14-1 Logic diagram of stage i of negative-sequence overcurrent protection
i=1, 2, 3
Abnormal condition 1: when the system is under pole disagreement condition, for 1-pole AR,
negative-sequence overcurrent protection will operate. If the logic setting [50/51Qx.En_Abnor_Blk]
is set as “1”, the stage x of negative-sequence overcurrent protection will be blocked. If the logic
setting [50/51Qx.En_Abnor_Blk] is set as “0”, negative-sequence overcurrent protection is not
controlled by direction element.
Abnormal condition 2: When manually closing circuit breaker, three phases of the circuit breaker
maybe not operate simultaneously, and SOTF protection should operate. If the logic setting
[50/51Qx.En_Abnor_Blk] is set as “1”, the stage x of negative-sequence overcurrent protection will
be blocked. If the logic setting [50/51Qx.En_Abnor_Blk] is set as “0”, negative-sequence
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overcurrent protection is not controlled by direction element.
VTS.Alm (VT circuit failure): If the logic setting [50/51Qx.En_VTS_Blk] is set as “1”, the stage x of
negative-sequence overcurrent protection will be blocked. If the logic setting
[50/51Qx.En_VTS_Blk] is set as “0”, negative-sequence overcurrent protection is not controlled by
direction element.
EN
[50/51Q4.En]
SIG
50/51Q4.En1
SIG
50/51Q4.En2
SIG
50/51Q4.Blk
SET
I2/I1>[50/51Q4.I2/I1_Set]
SET
I2>[50/51Q4.I2_Set]
EN
[50/51Q4.En_Abnor_Blk]
SIG
No abnormal conditions
&
&
50/51Q4.On
&
>=1
&
SET
[50/51Q4.Opt_Dir]=Forward
SIG
Forward DIR
SET
[50/51Q4.Opt_Dir]=Reverse
SIG
Reverse DIR
SET
[50/51Q4.Opt_Dir]=Non_Directional
&
&
>=1
>=1
&
&
&
50/51Q4.St
&
EN
[50/51Q4.En_VTS_Blk]
SIG
VTS.Alm
SIG
CTS.Alm
EN
[50/51Q4.En_CTS_Blk]
SIG
FD.NOC.Pkp
EN
[50/51Q4.En_Trp]
>=1
Timer
t
&
50/51Q4.Alm
t
&
Timer
t
&
50/51Q4.Op
t
Figure 3.14-2 Logic diagram of stage 4 of negative-sequence overcurrent protection
3.14.6 Settings
Table 3.14-3 Settings of negative-sequence overcurrent protection
No.
1
Name
50/51Qi.I2_Set
Range
Step
Unit
(0.050~30.000)×In
0.001
A
3-144
Remark
Current setting for stage i of
negative-sequence
overcurrent
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3 Operation Theory
No.
Name
Range
Step
Unit
Remark
protection (i=1, 2, 3, 4)
Ratio coefficient (I2/I1) for stage i of
2
50/51Qi.I2/I1_Set
0.00~1.00
0.01
negative-sequence
overcurrent
protection (i=1, 2, 3, 4)
Time
3
50/51Qi.t_Op
0.000~20.000
0.001
s
delay
for
stage
negative-sequence
i
of
overcurrent
protection (i=1, 2, 3, 4)
Enabling/disabling
stage
negative-sequence
4
50/51Qi.En
0 or 1
i
of
overcurrent
protection (i=1, 2, 3, 4)
0: disable
1: enable
Enabling/Disabling
blocked
5
50/51Qi.En_BlkAR
when
auto-reclosing
stage
negative-sequence
0 or 1
i
of
overcurrent
protection operates (i=1, 2, 3, 4)
0: disable
1: enable
6
50/51Qi.Opt_Dir
Non_Directional
Direction option for stage i of
Forward
negative-sequence
Reverse
protection (i=1, 2, 3, 4)
Enabling/disabling
stage
7
50/51Qi.En_Abnor_Blk
i
of
overcurrent
0 or 1
overcurrent
blocking
for
negative-sequence
protection
under
abnormal conditions (i=1, 2, 3, 4)
0: disable
1: enable
Enabling/disabling
stage
8
50/51Qi.En_VTS_Blk
i
of
blocking
for
negative-sequence
overcurrent protection under VT
0 or 1
failure conditions (i=1, 2, 3, 4)
0: disable
1: enable
Enabling/disabling
stage
9
50/51Qi.En_CTS_Blk
i
of
blocking
for
negative-sequence
overcurrent protection under CT
0 or 1
failure conditions (i=1, 2, 3, 4)
0: disable
1: enable
DefTime
10
50/51Qi.Opt_Curve
Option of characteristic curve for
IECN
stage
IECV
i
of
negative-sequence
overcurrent protection (i=1, 2, 3, 4)
IECE
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No.
Name
Range
Step
Unit
Remark
IECST
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Time multiplier setting for stage i of
11
50/51Qi.TMS
0.010~200.000
0.001
inverse-time
negative-sequence
overcurrent protection (i=1, 2, 3, 4)
Minimum operating time for stage i
12
50/51Qi.tmin
0.050~20.000
0.001
s
of inverse-time negative-sequence
overcurrent protection (i=1, 2, 3, 4)
“α”
Constant
13
50/51Q1.Alpha
0.010~5.000
0.001
for
stage
customized
1
of
inverse-time
characteristic
negative-sequence
overcurrent protection
Constant
14
50/51Q1.C
0.000~20.000
0.001
“C”
for
stage
customized
1
of
inverse-time
characteristic
negative-sequence
overcurrent protection
Constant
15
50/51Q1.K
0.050~20.000
0.001
“K”
for
stage
customized
characteristic
1
of
inverse-time
negative-sequence
overcurrent protection
Enabling/Disabling
negative-sequence
16
50/51Q4.En_Trp
0 or 1
stage
4
of
overcurrent
protection operate to trip or alarm.
0: alarm
1: trip
3.15 Overcurrent Protection for VT Circuit Failure
3.15.1 General Application
When protection VT circuit fails, distance protection will be disabled. As a substitute, definite-time or
inverse-time phase overcurrent protection and ground overcurrent protection will be enabled
automatically, if selected, as backup protection of distance protection.
3.15.2 Function Description
Two stages phase overcurrent protection and two stages ground overcurrent protection with
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independent logic, current and time delay settings. Stage 2 of phase overcurrent protection and
two stages ground overcurrent protection can be selected as definite-time or inverse-time
characteristic. The inverse-time characteristic is selectable among IEC and ANSI/IEEE standard
inverse-time characteristics, and a user-defined inverse-time curve. Define-time or inverse-time
phase overcurrent protection drops off instantaneously after fault current disappears.
The inverse-time operating characteristic is as follows.
Equation 3.15-1
Where:
Iset is current setting [50PVT2.I_Set] or [50GVT2.3I0_Set].
Tp is time multiplier setting [50PVT2.TMS] or [50GVT2.TMS].
α is a constant.
K is a constant.
C is a constant.
I is measured phase current from line CT
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50PVT2.Opt_Curve] and [50GVT2.Opt_Curve], and parameters of available
characteristics for selection are shown in the following table.
Table 3.15-1 Inverse-time curve parameters
[50PVT2.Opt_Curve]/[50GVT2.Opt_Curve]
Time Characteristic
K
α
C
DefTime
Definite time
IECN
IEC Normal inverse
0.14
0.02
0
IECV
IEC Very inverse
13.5
1.0
0
IECE
IEC Extremely inverse
80.0
2.0
0
IECST
IEC Short-time inverse
0.05
0.04
0
IECLT
IEC Long-time inverse
120.0
1.0
0
ANSIE
ANSI Extremely inverse
28.2
2.0
0.1217
ANSIV
ANSI Very inverse
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
ANSI Moderately inverse
0.0515
0.02
0.114
ANSILTE
ANSI Long-time extremely inverse
64.07
2.0
0.25
ANSILTV
ANSI Long-time very inverse
28.55
2.0
0.712
ANSILT
ANSI Long-time inverse
0.086
0.02
0.185
UserDefine
Programmable user-defined
If all available curves do not comply with user application, user may set [50PVT2.Opt_Curve] and
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[50GVT2.Opt_Curve] as “UserDefine” to customize the inverse-time curve characteristic with
constants α, K and C.
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50PVT2.tmin] or [50GVT2.tmin], then the operating time of the protection changes to the value of
setting [50PVT2.tmin] or [50GVT2.tmin] automatically.
3.15.3 Function Block Diagram
50PVTi/50GVTi
50PVTi.En1
50PVTi.On
50PVTi.En2
50PVTi.Op
50PVTi.Blk
50PVTi.St
50GVTi.En1
50PVTi.StA
50GVTi.En2
50PVTi.StB
50GVTi.Blk
50PVTi.StC
50GVTi.On
50GVTi.Op
50GVTi.St
3.15.4 I/O Signals
Table 3.15-2 I/O signals of overcurrent protection for VT circuit failure
No.
Input Signal
1
50PVTi.En1
2
50PVTi.En2
3
50PVTi.Blk
4
50GVTi.En1
5
50GVTi.En2
6
50GVTi.Blk
No.
Output Signal
Description
Stage i of phase overcurrent protection for VT circuit failure enabling input 1, it is
triggered from binary input or programmable logic etc. (i=1, 2)
Stage i of phase overcurrent protection for VT circuit failure enabling input 2, it is
triggered from binary input or programmable logic etc. (i=1, 2)
Stage i of phase overcurrent protection for VT circuit failure blocking input, it is
triggered from binary input or programmable logic etc. (i=1, 2)
Stage i of ground overcurrent protection for VT circuit failure enabling input 1, it is
triggered from binary input or programmable logic etc. (i=1, 2)
Stage i of ground overcurrent protection for VT circuit failure enabling input 2, it is
triggered from binary input or programmable logic etc. (i=1, 2)
Stage i of ground overcurrent protection for VT circuit failure blocking input, it is
triggered from binary input or programmable logic etc. (i=1, 2)
Description
1
50PVTi.On
Stage i of phase overcurrent protection for VT circuit failure is enabled. (i=1, 2)
2
50PVTi.Op
Stage i of phase overcurrent protection for VT circuit failure operates. (i=1, 2)
3
50PVTi.St
Stage i of phase overcurrent protection for VT circuit failure starts. (i=1, 2)
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Stage i of phase overcurrent protection for VT circuit failure starts (A-Phase). (i=1,
4
50PVTi.StA
5
50PVTi.StB
6
50PVTi.StC
7
50GVTi.On
Stage i of ground overcurrent protection for VT circuit failure is enabled. (i=1, 2)
8
50GVTi.Op
Stage i of ground overcurrent protection for VT circuit failure operates. (i=1, 2)
9
50GVTi.St
Stage i of ground overcurrent protection for VT circuit failure starts. (i=1, 2)
2)
Stage i of phase overcurrent protection for VT circuit failure starts (B-Phase). (i=1,
2)
Stage i of phase overcurrent protection for VT circuit failure starts (C-Phase). (i=1,
2)
3.15.5 Logic
SIG 50PVTx.En1
&
SIG 50PVTx.En2
EN
&
50PVTx.On
[50PVTx.En]
>=1
&
SIG 50PVTx.Blk
50PVTx.St
&
SIG FD.Pkp
&
SIG VTS.Alm
50PVTx.StA
SET Ia>[50PVTx.I_Set]
&
50PVTx.StB
SET Ib>[50PVTx.I_Set]
&
50PVTx.StC
SET Ic>[50PVTx.I_Set]
SIG 50PVT1.St
[50PVT1.t_Op]
SIG 50PVT2.St
0ms
&
50PVT1.Op
Timer
t
>=1
&
50PVT2.Op
[50PVT2.t_Op]
0
SET [50PVT2.Opt_Curve]=DefTime
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SIG 50GVTx.En1
&
SIG 50GVTx.En2
EN
&
50GVTx.On
[50GVTx.En]
&
SIG 50GVTx.Blk
SIG FD.Pkp
&
SET 3I0>[50GVTx.3I0_Set]
50GVTx.St
SIG FD.ROC.Pkp
&
SIG VTS.Alm
[50GVT1.t_Op]
SIG 50GVT1.St
&
SIG 50GVT2.St
0ms
50GVT1.Op
Timer
t
>=1
&
50GVT2.Op
[50GVT2.t_Op]
0
SET [50GVT2.Opt_Curve]=DefTime
Figure 3.15-1 Logic diagram of overcurrent protection for VT circuit failure
3.15.6 Settings
Table 3.15-3 Settings of overcurrent protection for VT circuit failure
No.
Name
Range
Step
Unit
Remark
Current setting for stage i of phase
1
50PVTi.I_Set
(0.050~30.000)×In
0.001
A
overcurrent protection when VT
circuit failure (i=1, 2)
Time delay for stage i of phase
2
50PVTi.t_Op
0.000~10.000
0.001
s
overcurrent protection when VT
circuit failure (i=1, 2)
Enabling/disabling stage i of phase
overcurrent protection when VT
3
50PVTi.En
0 or 1
circuit failure (i=1, 2)
0: disable
1: enable
DefTime
IECN
Option of inverse-time characteristic
IECV
4
50PVT2.Opt_Curve
curve
IECE
for
stage
2
of
phase
overcurrent protection when VT
IECST
circuit failure
IECLT
ANSIE
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No.
Name
Range
Step
Unit
Remark
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 2
5
50PVT2.TMS
0.010~200.000
0.001
of
phase overcurrent
protection
when VT circuit failure
Minimum operating time for stage 2
6
50PVT2.tmin
0.000~20.000
0.001
s
of
phase overcurrent
protection
when VT circuit failure
Constant
7
50PVT2.Alpha
0.010~5.000
“α”
for
stage
customized
0.001
2
of
inverse-time
characteristic
phase
overcurrent
protection when VT circuit failure
Constant
8
50PVT2.C
0.000~20.000
“C”
for
stage
customized
0.001
2
of
inverse-time
characteristic
phase
overcurrent
protection when VT circuit failure
Constant
9
50PVT2.K
0.050~20.000
“K”
for
stage
customized
0.001
2
of
inverse-time
characteristic
phase
overcurrent
protection when VT circuit failure
Current setting for stage i of ground
10
50GVTi.3I0_Set
(0.050~30.000)×In
0.001
A
overcurrent protection when VT
circuit failure (i=1, 2)
Time delay for stage i of ground
11
50GVTi.t_Op
0.000~10.000
0.001
s
overcurrent protection when VT
circuit failure (i=1, 2)
Enabling/disabling stage i of ground
overcurrent protection when VT
12
50GVTi.En
0 or 1
circuit failure (i=1, 2)
0: disable
1: enable
DefTime
IECN
13
50GVT2.Opt_Curve
IECV
Option of inverse-time characteristic
IECE
curve
IECST
overcurrent protection when VT
IECLT
circuit failure
for
stage
2
of
ground
ANSIE
ANSIV
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No.
Name
Range
Step
Unit
Remark
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 2 of
14
50GVT2.TMS
0.010~200.000
0.001
ground overcurrent protection when
VT circuit failure
Minimum operating time for stage 2
15
50GVT2.tmin
0.000~20.000
0.001
s
of ground overcurrent protection
when VT circuit failure
Constant
16
50GVT2.Alpha
0.010~5.000
0.001
“α”
for
customized
stage
2
of
inverse-time
characteristic ground overcurrent
protection when VT circuit failure
Constant
17
50GVT2.C
0.000~20.000
0.001
“C”
for
customized
stage
2
of
inverse-time
characteristic ground overcurrent
protection when VT circuit failure
Constant
18
50GVT2.K
0.050~20.000
0.001
customized
“K”
for
stage
2
of
inverse-time
characteristic ground overcurrent
protection when VT circuit failure
3.16 Phase Current SOTF Protection
3.16.1 General Application
When the circuit breaker is closed manually or automatically, it is possible to switch on to an
existing fault. This is especially critical if the line in the remote station is grounded, since earth fault
protection would not clear the fault until their time delays had elapsed. In this situation, however,
the fastest possible clearance is desired. For application on line-transformer unit, second
harmonic also can be selected to block phase overcurrent protection to avoid the effect of inrush
current on the protection.
With phase current SOTF protection, a fast trip is achieved for a fault on the line when the line is
being energized. It shall be responsive to all types of earth faults anywhere within the protected
line, and it shall be enabled for the setting [SOTF.t_En] when the circuit is energized either
manually or via an auto-reclosing system.
3.16.2 Function Description
Phase current SOTF protection will operate to trip three-phase circuit breaker with a time delay of
[50PSOTF.t_Op] when auto-reclosing or closing manually.
Second harmonic can be selected to block phase overcurrent SOTF protection. When phase
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overcurrent SOTF protection is used to protect line-transformer unit, harmonic blocking function
can be selected by configuring logic setting [50PSOTF.En_Hm2_Blk] to prevent maloperation due
to inrush current.
When the percentage of second harmonic component to fundamental component of any phase
current is greater than the setting [50/51P.K_Hm2], harmonic blocking element operates to block
phase overcurrent SOTF element if corresponding logic setting [50PSOTF.En_Hm2_Blk] enabled.
Operation criterion:
IP_2nd=[50/51P.K_Hm2]×IP
Equation 3.16-1
Where:
IP_2nd is second harmonic of phase current
IP is fundamental component of phase current.
[50/51P.K_Hm2] is harmonic blocking coefficient.
If fundamental component of any phase current is lower than the minimum operating current
(0.1In), then harmonic calculation is not carried out and harmonic blocking element does not
operate.
3.16.3 Function Block Diagram
50PSOTF
50PSOTF.En1
50PSOTF.On
50PSOTF.En2
50PSOTF.Op
50PSOTF.Blk
50PSOTF.St
3.16.4 I/O Signals
Table 3.16-1 I/O signals of residual SOTF protection
No.
Input Signal
1
50PSOTF.En1
2
50PSOTF.En2
3
50PSOTF.Blk
No.
Description
Phase current SOTF protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Phase current SOTF protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Phase current SOTF protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
1
50PSOTF.On
Phase current SOTF protection is enabled.
2
50PSOTF.Op
Phase current SOTF protection operates.
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3
50PSOTF.St
Phase current SOTF protection starts.
3.16.5 Logic
SIG I3P
2nd Hm Detect
&
SET [50PSOTF.En_Hm2_Blk]
SIG 3-pole reclosing signal
&
>=1
SIG 1-pole reclosing signal
SIG Manual closing signal
SET Ia>[50PSOTF.I_Set]
>=1
SET Ib>[50PSOTF.I_Set]
SET Ic>[50PSOTF.I_Set]
SET Ua<[50PSOTF.Up_Set]
>=1
SET Ub<[50PSOTF.Up_Set]
&
SET Uc<[50PSOTF.Up_Set]
EN
[50PSOTF.En_Up_UV]
SET Uab<[50PSOTF.Upp_Set]
>=1
SET Ubc<[50PSOTF.Upp_Set]
>=1
&
>=1
&
>=1
SET Uca<[50PSOTF.Upp_Set]
EN
[50PSOTF.En_Upp_UV]
SET U2>[50PSOTF.U2_Set]
EN
[50PSOTF.En_U2_OV]
SET 3U0>[50PSOTF.3U0_Set]
EN
&
&
[50PSOTF.En_3U0_OV]
>=1
>=1
EN
[50PSOTF.En_Up_UV]
EN
[50PSOTF.En_Upp_UV]
&
[50PSOTF.t_Op]
SIG FD.Pkp
SIG 50PSOTF.En1
50PSOTF.St
0ms
50PSOTF.Op
&
SIG 50PSOTF.En2
SIG 50PSOTF.Blk
EN
&
50PSOTF.On
[50PSOTF.En]
Figure 3.16-1 Logic diagram of phase current SOTF protection
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3.16.6 Settings
Table 3.16-2 Settings of phase current SOTF protection
No.
Name
Range
Step
Unit
1
50PSOTF.I_Set
(0.050~30.000)×In
0.001
A
2
50PSOTF.t_Op
0.000~10.000
0.001
s
Remark
Current setting of phase current
SOTF protection
Time delay for phase current
SOTF protection
Enabling/disabling
3
50PSOTF.En
phase
current SOTF protection
0 or 1
0: disable
1: enable
Enabling/disabling
second
harmonic blocking for phase
4
50PSOTF.En_Hm2_Blk
0 or 1
overcurrent SOTF protection
0: disable
1: enable
5
50PSOTF.Up_Set
(0~1) ×Un
0.001
V
6
50PSOTF.Upp_Set
(0~1) ×Un
0.001
V
Voltage
setting
50PSOTF.U2_Set
(0~1) ×Un
0.001
V
phase
Voltage setting for phase-phase
undervoltage supervision logic
Voltage
7
for
undervoltage supervision logic
setting
for
negative-sequence overvoltage
supervision logic
Voltage
8
50PSOTF.3U0_Set
(0~1) ×Un
0.001
V
setting
zero-sequence
for
overvoltage
supervision logic
Enabling/disabling
phase
undervoltage supervision logic
9
50PSOTF.En_Up_UV
for
0 or 1
phase
current
SOTF
protection
0: disable
1: enable
Enabling/disabling phase-phase
undervoltage supervision logic
10
50PSOTF.En_Upp_UV
for
0 or 1
phase
current
SOTF
protection
0: disable
1: enable
Enabling/disabling
negative-sequence overvoltage
11
50PSOTF.En_U2_OV
0 or 1
supervision
logic
for
phase
current SOTF protection
0: disable
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No.
Name
Range
Step
Unit
Remark
1: enable
Enabling/disabling
12
50PSOTF.En_3U0_OV
0 or 1
zero-sequence
overvoltage
supervision
for
logic
phase
current SOTF protection
0: disable
1: enable
3.17 Residual Current SOTF Protection
3.17.1 General Application
When the circuit breaker is closed manually or automatically, it is possible to switch on to an
existing fault. This is especially critical if the line in the remote station is grounded, since earth fault
protection would not clear the fault until their time delays had elapsed. In this situation, however,
the fastest possible clearance is desired. For application on line-transformer unit, second
harmonic also can be selected to block earth fault protection to avoid the effect of inrush current
on the protection.
Residual current SOTF (switch onto fault) protection is a complementary function to earth fault
protection. With residual current SOTF protection, a fast trip is achieved for a fault on the line,
when the line is being energized. It shall be responsive to all types of earth faults anywhere within
the protected line, and it shall be enabled for the setting [SOTF.t_En] when the circuit is energized
either manually or via an auto-reclosing system.
3.17.2 Function Description
Residual current SOTF protection will operate to trip three-phase circuit breaker with a time delay
of [50GSOTF.t_Op_1P] when 1-pole auto-reclosing.
Residual current SOTF protection will operate to trip three-phase circuit breaker with a time delay of
[50GSOTF.t_Op_3P] when 3-pole auto-reclosing or closing manually.
Second harmonic can be selected to block residual current SOTF protection. When residual
current SOTF protection is used to protect line-transformer unit, harmonic blocking function can be
selected by configuring logic setting [50GSOTF.En_Hm2_Blk] to prevent maloperation due to
inrush current.
When the percentage of second harmonic component to fundamental component of residual
current is greater than the setting [50/51G.K_Hm2], harmonic blocking element operates to block
residual overcurrent SOTF element if corresponding logic setting [50GSOTF.En_Hm2_Blk]
enabled.
Operation criterion:
I0_2nd=[50/51G.K_Hm2]×I0
Equation 3.17-1
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Where:
I0_2nd is second harmonic of residual current
I0 is fundamental component of residual current.
[50/51G.K_Hm2] is harmonic blocking coefficient.
If fundamental component of residual current is lower than the minimum operating current (0.1In)
then harmonic calculation is not carried out and harmonic blocking element does not operate.
3.17.3 Function Block Diagram
50GSOTF
50GSOTF.En1
50GSOTF.On
50GSOTF.En2
50GSOTF.Op
50GSOTF.Blk
50GSOTF.St
3.17.4 I/O Signals
Table 3.17-1 I/O signals of residual SOTF protection
No.
Input Signal
1
50GSOTF.En1
2
50GSOTF.En2
3
50GSOTF.Blk
No.
Description
Residual current SOTF protection enabling input 1, it is triggered from binary input
or programmable logic etc.
Residual current SOTF protection enabling input 2, it is triggered from binary input
or programmable logic etc.
Residual current SOTF protection blocking input, it is triggered from binary input
or programmable logic etc.
Output Signal
Description
1
50GSOTF.On
Residual current SOTF protection is enabled.
2
50GSOTF.Op
Residual current SOTF protection operates.
3
50GSOTF.St
Residual current SOTF protection starts.
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3.17.5 Logic
SIG I3P
2nd Hm Detect
&
SET [50/51G1.En_Hm2_Blk]
SIG 3-pole AR signal
>=1
&
[50GSOTF.t_Op_3P]
SIG Manual closing signal
SET 3I0>[50GSOTF.3I0_Set]
&
>=1
50GSOTF.Op
&
SIG FD.ROC.Pkp
[50GSOTF.t_Op_1P]
SIG 1-pole AR signal
0ms
>=1
SIG 50GSOTF.En1
50GSOTF.St
&
SIG 50GSOTF.En2
&
50GSOTF.On
SIG 50GSOTF.Blk
EN
0ms
[50GSOTF.En]
Figure 3.17-1 Logic diagram of residual current SOTF protection
3.17.6 Settings
Table 3.17-2 Settings of residual current SOTF protection
No.
1
Name
50GSOTF.3I0_Set
Range
Step
Unit
(0.050~30.000)×In
0.001
A
Remark
Current
setting
of
residual
current SOTF protection
Time delay for residual current
2
50GSOTF.t_Op_3P
0.000~10.000
0.001
s
SOTF protection when 3 pole
closed
Time delay for residual current
3
50GSOTF.t_Op_1P
0.000~10.000
0.001
s
SOTF protection when 1 pole
closed
Enabling/disabling
4
50GSOTF.En
residual
current SOTF protection
0 or 1
0: disable
1: enable
Enabling/disabling
current
5
50GSOTF.En_Hm2_Blk
0 or 1
SOTF
residual
protection
blocked by harmonic
0: disable
1: enable
3.18 Voltage Protection
Voltage protection has the function of protecting device against undervoltage and overvoltage.
Both operational states are unfavorable as overvoltage may cause insulation breakdown while
undervoltage may cause stability problem. Each voltage protection function has three individual
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stages with respective time delay, but only one stage negative-sequence overvoltage protection is
available. These voltage protection functions can be switched on or off separately. Selectable
definite-time characteristic and multiple inverse-time characteristics are available.
3.18.1 Overvoltage Protection
3.18.1.1 General Application
Abnormal high voltages often occur e.g. in low loaded, long distance transmission lines, in
islanded systems when generator voltage regulation fails, or load rejection of a generator. Even if
compensation reactors are provided to avoid line overvoltage by compensation of the line
capacitance and thus reduction of the overvoltage, the overvoltage will endanger the insulation if
the reactors fail. The line must be de-energized within a very short time.
The overvoltage protection in this device detects the phase voltages Ua, Ub and Uc or the
phase-to-phase voltages Uab, Ubc and Uca with an option of any phase or all phases operation
for output. The overvoltage protection can be used for tripping purpose as well as to initiate
transfer trip, which selectable controlled by local circuit breaker.
3.18.1.2 Function Description
Phase overvoltage protection has following functions:
1.
Three stages phase overvoltage protection with independent logic, voltage and time delay
settings.
2.
Overvoltage protection can be selected as definite-time or inverse-time characteristic. The
inverse-time characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time
characteristics.
3.
Phase voltage or phase-to-phase voltage can be selected for protection calculation.
4.
“1-out-of-3” or “3-out-of-3” logic can be selected for protection criterion. (1-out-of-3 means any
of three phase voltages, 3-out-of-3 means all three phase voltages)
1.
Operation Criterion
Users can select phase voltage or phase-to-phase voltage for the protection calculation. If setting
[59Pi.Opt_Up/Upp] is set to “0”, phase voltage criterion is selected and if [59Pi.Opt_Up/Upp] is set
to “1”, phase-to-phase voltage criterion is selected.
When phase voltage or phase-to-phase voltage is greater than any enabled stage voltage setting,
the stage protection picks up and operates after delay, which will drop off instantaneously when
fault voltage disappears.

Phase voltage criterion
Two operation criteria of definite-time overvoltage protection are shown as follows, which of them
is applied depending on the logic setting [59Pi.Opt_1P/3P].
UΦ_max>[ 59Pi.U_Set]
Equation 3.18-1
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or
Ua>[59Pi.U_Set] & Ub>[59Pi.U_Set] & Uc>[59Pi.U_Set]
Equation 3.18-2
Where:
UΦ_max is the maximum value among three phase-voltage.
Ua, Ub, Uc are three phase voltages.
[59Pi.U_Set] is the setting of stage i of overvoltage protection. (i=1, 2, 3)
When [59Pi.Opt_1P/3P] is set as “1”, “1-out-of-3” logic (Equation 3.18-1) is selected as operation
criterion, and when set as “0”, “3-out-of-3” logic (Equation 3.18-2) is selected.

Phase-to-phase voltage criterion
Two operation criteria of definite-time overvoltage protection are shown as follows, which of them
is applied depending on the logic setting [59Pi.Opt_1P/3P].
UΦΦ_max>[ 59Pi.U_Set]
Equation 3.18-3
or
Uab>[59Pi.U_Set] & Ubc>[59Pi.U_Set] & Uca>[59Pi.U_Set]
Equation 3.18-4
[59Pi.U_Set] is the setting of stage i of overvoltage protection.
When [59Pi.Opt_1P/3P] is set as “1”, “1-out-of-3” logic (Equation 3.18-3) is selected as operation
criterion, and when set as “0”, “3-out-of-3” logic (Equation 3.18-4) is selected.
2.
Characteristic Curve
Phase overvoltage protection can be selected as definite-time or inverse-time characteristic, and
inverse-time operating time curve is as follows.
Equation 3.18-5
Where:
Uset is the voltage setting [59Pi.U_Set].
Tp is time multiplier setting [59Pi.TMS].
K is a constant.
C is a constant.
α is a constant.
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U is the measured voltage
Operating characteristic of overvoltage protection, can be chosen from definite-time characteristic
and 12 inverse-time characteristics by setting the logic setting [59Pi.Opt_Curve]. The parameters
of each characteristic are listed in the following table.
Table 3.18-1 Inverse-time curve parameters
59Pi.Opt_Curve
α
K
Time Characteristic
C
DefTime
Definite time
IECN
IEC Normal inverse
0.14
0.02
0
IECV
IEC Very inverse
13.5
1.0
0
IECE
IEC Extremely inverse
80.0
2.0
0
IECST
IEC Short-time inverse
0.05
0.04
0
IECLT
IEC Long-time inverse
120.0
1.0
0
ANSIE
ANSI Extremely inverse
28.2
2.0
0.1217
ANSIV
ANSI Very inverse
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
ANSI Moderately inverse
0.0515
0.02
0.114
ANSILTE
ANSI Long-time extremely inverse
64.07
2.0
0.25
ANSILTV
ANSI Long-time very inverse
28.55
2.0
0.712
ANSILT
ANSI Long-time inverse
0.086
0.02
0.185
When inverse-time characteristic is selected, if calculated operating time is less than setting
[59Pi.tmin], then the operating time changes to the value of setting [59Pi.tmin] automatically.
Define-time or inverse-time phase overvoltage protection drops off instantaneously when
measured voltage is lower than reset voltage.
3.18.1.3 Function Block Diagram
59Pi
59Pi.En1
59Pi.On
59Pi.En2
59Pi.St
59Pi.Blk
59Pi.St1
59Pi.St2
59Pi.St3
59Pi.Op
59Pi.Alm
59Pi.Op_InitTT
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3.18.1.4 I/O Signals
Table 3.18-2 I/O signals of overvoltage protection
No.
Input Signal
1
59Pi.En1
2
59Pi.En2
3
59Pi.Blk
No.
Output Signal
Description
Stage i of overvoltage protection enabling input 1, it is triggered from binary input
or programmable logic etc. (i=1, 2, 3)
Stage i of overvoltage protection enabling input 2, it is triggered from binary input
or programmable logic etc. (i=1, 2, 3)
Stage i of overvoltage protection blocking input, it is triggered from binary input or
programmable logic etc. (i=1, 2, 3)
Description
1
59Pi.On
Stage i of overvoltage protection is enabled. (i=1, 2, 3)
2
59Pi.Op
Stage i of overvoltage protection operates. (i=1, 2, 3)
3
59Pi.St
Stage i of overvoltage protection starts. (i=1, 2, 3)
4
59Pi.St1
Stage i of overvoltage protection starts (A or AB). (i=1, 2, 3)
5
59Pi.St2
Stage i of overvoltage protection starts (B or BC). (i=1, 2, 3)
6
59Pi.St3
Stage i of overvoltage protection starts (C or CA). (i=1, 2, 3)
7
59Pi.Op_InitTT
Stage i of overvoltage protection operates to initiate transfer trip. (i=1, 2, 3)
8
59Pi.Alm
Stage i of overvoltage protection alarms. (i=1, 2, 3)
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3.18.1.5 Logic
EN
[59Pi.En]
&
SIG 59Pi.En1
&
59Pi.On
SIG 59Pi.En2
SIG 59Pi.Blk
SIG 52b_PhA
&
SIG 52b_PhB
&
&
>=1
SIG 52b_PhC
EN
[59Pi.En_52b_TT]
EN
[59Pi.En_TT]
EN
[59Pi.Opt_1P/3P]
SIG
FD.Pkp
59Pi.Op_InitTT
&
&
SIG 59Pi.On
EN
[59Pi.Opt_Up/Upp]
&
&
>=1
Timer
t
&
t
SET UA>[59Pi.U_Set]
&
&
SET UAB>[59Pi.U_Set]
&
&
>=1
Timer
t
t
SET UB>[59Pi.U_Set]
&
SET UBC>[59Pi.U_Set]
>=1
&
&
>=1
SET UC>[59Pi.U_Set]
Timer
t
t
&
59Pi.St1
59Pi.Op
59Pi.St3
[59Pi.En_Alm]
SIG 59Pi.St1
&
59Pi.St2
SET UCA>[59Pi.U_Set]
EN
>=1
&
&
59Pi.Alm
>=1
SIG 59Pi.St2
59Pi.St
SIG 59Pi.St3
Figure 3.18-1 Logic diagram of stage i of overvoltage protection
Where:
i=1, 2, 3
52b_PhA, 52b_PhB and 52b_PhC: Please refer to section 3.4.
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3.18.1.6 Settings
Table 3.18-3 Settings of overvoltage protection
No.
Name
Range
Step
Unit
1
59Pi.U_Set
Un~2Unn
0.001
V
2
59Pi.t_Op
0.000~30.000
0.001
s
Remark
Voltage setting for stage i of overvoltage
protection (i=1, 2, 3)
Time delay for stage i of overvoltage
protection (i=1, 2, 3)
Enabling/disabling stage i of overvoltage
3
59Pi.En
protection (i=1, 2, 3)
0 or 1
0: disable
1: enable
Option of 1-out-of-3 mode or 3-out-of-3
mode for stage i of overvoltage protection
4
59Pi.Opt_1P/3P
0 or 1
(i=1, 2, 3)
0: 3-out-of-3 mode
1: 1-out-of-3 mode
Option of phase-to-phase voltage or phase
voltage for stage i of overvoltage protection
5
59Pi.Opt_Up/Upp
0 or 1
(i=1, 2, 3)
0: phase voltage
1: phase-to-phase voltage
Enabling/disabling stage i of overvoltage
6
59Pi.En_Alm
protection for alarm purpose (i=1, 2, 3)
0 or 1
0: disable
1: enable
Enabling/disabling transfer trip controlled
by CB open position for stage i of
7
59Pi.En_52b_TT
0 or 1
overvoltage protection (i=1, 2, 3)
0: disable
1: enable
Enabling/disabling stage i of overvoltage
protection operate to initiate transfer trip
8
59Pi.En_TT
0 or 1
(i=1, 2, 3)
0: disable
1: enable
DefTime
IECN
IECV
9
59Pi.Opt_Curve
IECE
Option of characteristic curve for stage i of
IECST
overvoltage protection (i=1, 2, 3)
IECLT
ANSIE
ANSIV
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No.
Name
Range
Step
Unit
Remark
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage i of
10
59Pi.TMS
0.010~200.000
0.001
inverse-time overvoltage protection (i=1, 2,
3)
11
59Pi.tmin
0.050~20.000
0.001
Minimum delay for stage i of inverse-time
s
overvoltage protection (i=1, 2, 3)
3.18.2 Negative-sequence Overvoltage Protection
3.18.2.1 General Application
On a healthy three-phase power system, negative-sequence voltage is nominally zero. However,
when an unbalance situation occurs on the primary system, the negative-sequence voltage is
produced. The device provides a one-stage negative-sequence overvoltage protection with
definite time delay characteristic.
3.18.2.2 Function Block Diagram
59Q
59Q.En1
59Q.On
59Q.En2
59Q.Op
59Q.Blk
59Q.St
3.18.2.3 I/O Signals
Table 3.18-4 I/O signals of negative-sequence overvoltage protection
No.
Input Signal
1
59Q.En1
2
59Q.En2
3
59Q.Blk
No.
Description
Negative-sequence overvoltage protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Negative-sequence overvoltage protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Negative-sequence overvoltage protection blocking input, it is triggered from
binary input or programmable logic etc.
Output Signal
Description
1
59Q.On
Negative-sequence overvoltage protection is enabled.
2
59Q.Op
Negative-sequence overvoltage protection operates.
3
59Q.St
Negative-sequence overvoltage protection starts.
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3.18.2.4 Logic
SIG
59Q.En1
SIG
59Q.En2
EN
[59Q.En]
SIG
59Q.Blk
&
&
59Q.On
[59Q.t_Op]
59Q.Op
&
59Q.St
SET U2>[59Q.U_Set]
Figure 3.18-2 Logic diagram of negative-sequence overvoltage protection
3.18.2.5 Settings
Table 3.18-5 Settings of negative-sequence overvoltage protection
No.
Name
Range
Step
Unit
1
59Q.U_Set
0~Un
0.001
V
2
59Q.t_Op
0.000~30.000
0.001
s
Remark
Voltage setting for negative-sequence
overvoltage protection
Time
delay
for
overvoltage protection
Enabling/disabling
3
59Q.En
negative-sequence
negative-sequence
overvoltage protection
0 or 1
0: disable
1: enable
3.18.3 Residual Overvoltage Protection
3.18.3.1 General Application
A single phase earth fault occurrence in ungrounded system or Peterson coil grounded system will
result in residual overvoltage, so residual overvoltage protection is equipped to prevent protected
equipment being damaged by residual overvoltage in this condition.
3.18.3.2 Function Description
Residual overvoltage protection has following functions
1.
Three-stage residual overvoltage protection with independent logic, voltage and time delay
settings.
2.
Stage 1 is definite-time characteristic, stage 2 and 3 can be selected as definite-time or
inverse-time characteristic, only stage 3 can be defined for trip purpose or alarm purpose. The
inverse-time characteristic is selectable among IEC and ANSI/IEEE standard inverse-time
characteristics and a user-defined inverse-time curve.
3.
Define-time or inverse-time residual overvoltage protection drops off instantaneously.
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1. Operation Criterion
3U0> [59Gi.3U0_Set]
Equation 3.18-6
Where:
3U0 is calculated residual voltage.
[59Gi.3U0_Set] is the voltage setting of stage i of residual overvoltage protection. (i=1, 2 or 3)
If residual voltage is greater than the setting of any stage enabled residual overvoltage protection,
the stage residual overvoltage protection will operate after time delay and the stage protection will
drop off instantaneously after fault voltage disappears.
2. Time Curve
Stage 1 of residual overvoltage protection is definite-time characteristic and can perform
instantaneous operation with the corresponding time delay being set as “0”. Stage 2 and 3 can be
selected as definite-time or inverse-time characteristic, and inverse-time operating time curve is as
follows.
Equation 3.18-7
Where:
Uset is residual voltage setting [59Gi.3U0_Set].
Tp is time setting [59Gi.TMS].
K and C are constants.
α is a constant.
U is actual measured residual voltage.
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [59Gi.Opt_Curve], and parameters of available characteristics for selection are shown in
the following table.
Table 3.18-6 Inverse-time curve parameters of residual overvoltage protection
59Gi.Opt_Curve (i=2 or 3)
α
K
Time Characteristic
C
DefTime
Definite time
IECN
IEC Normal inverse
0.14
0.02
0
IECV
IEC Very inverse
13.5
1.0
0
IECE
IEC Extremely inverse
80.0
2.0
0
IECST
IEC Short-time inverse
0.05
0.04
0
IECLT
IEC Long-time inverse
120.0
1.0
0
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59Gi.Opt_Curve (i=2 or 3)
α
K
Time Characteristic
C
ANSIE
ANSI Extremely inverse
28.2
2.0
0.1217
ANSIV
ANSI Very inverse
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
ANSI Moderately inverse
0.0515
0.02
0.114
ANSILTE
ANSI Long-time extremely inverse
64.07
2.0
0.25
ANSILTV
ANSI Long-time very inverse
28.55
2.0
0.712
ANSILT
ANSI Long-time inverse
0.086
0.02
0.185
UserDefine
Programmable user-defined
If all available curves do not comply with user application, user may configure setting
[59Gi.Opt_Curve] to “UserDefine” to customize the inverse-time curve characteristic, and
constants K, α and C.
3.18.3.3 Function Block Diagram
59Gi
59Gi.En1
59Gi.On
59Gi.En2
59Gi.St
59Gi.Blk
59Gi.Op
59G3.Alm
3.18.3.4 I/O Signals
Table 3.18-7 I/O signals of residual overvoltage protection
No.
Signal
1
59Gi.En1
2
59Gi.En2
3
59Gi.Blk
No.
Signal
Description
Stage i of residual overvoltage protection enabling input 1, it is triggered from binary
input or programmable logic etc. (i=1, 2, 3)
Stage i of residual overvoltage protection enabling input 2, it is triggered from binary
input or programmable logic etc. (i=1, 2, 3)
Stage i of overvoltage protection blocking input, it is triggered from binary input or
programmable logic etc. (i=1, 2, 3)
Description
1
59Gi.On
Stage i of residual overvoltage protection is enabled. (i=1, 2, 3)
2
59Gi.Op
Stage i of residual overvoltage protection operates. (i=1, 2, 3)
3
59Gi.St
Stage i of residual overvoltage protection start. (i=1, 2, 3)
4
59G3.Alm
Stage 3 of residual overvoltage protection operates to alarm.
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3.18.3.5 Logic
EN
[59G1.En]
SIG
59G1.En1
SIG
59G1.En2
SIG
59G1.Blk
SET
3U0>[59G1.3U0_Set]
&
&
59G1.On
59G1.St
&
[59G1.t_Op]
0
59G1.Op
Figure 3.18-3 Logic diagram of stage 1 of residual overvoltage protection
EN
[59G2.En]
SIG
59G2.En1
SIG
59G2.En2
SIG
59G2.Blk
SET
3U0>[59G2.3U0_Set]
&
&
59G2.On
&
59G2.St
Timer
t
&
t
>=1
59G2.Op
&
[59G2.t_Op]
SET
0
[59G2.Opt_Curve]=DefTime
Figure 3.18-4 Logic diagram of stage 2 of residual overvoltage protection
EN
[59G3.En]
SIG
59G3.En1
SIG
59G3.En2
SIG
59G3.Blk
SET
3U0>[59G3.3U0_Set]
&
&
59G3.On
&
59G3.St
&
Timer
t
t
>=1
&
[59G3.t_Op]
SET
[59G3.Opt_Curve]=DefTime
EN
[59G3.En_Trp]
0
&
59G3.Op
&
59G3.Alm
Figure 3.18-5 Logic diagram of stage 3 of residual overvoltage protection
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3.18.3.6 Settings
Table 3.18-8 Settings of residual overvoltage protection
No.
Name
Range
Step
Unit
1
59Gi.3U0_Set
0~2Unn
0.001
V
2
59Gi.t_Op
0.000~3600.000
0.001
s
Remark
Voltage setting of stage i of residual
overvoltage protection. (i=1, 2, 3)
Time delay of stage i of residual
overvoltage protection. (i=1, 2, 3)
Enabling/disabling stage i of residual
3
59Gi.En
overvoltage protection (i=1, 2, 3)
0 or 1
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
4
59Gi.Opt_Curve
ANSIE
Option of characteristic curve for stage i
ANSIV
of residual overvoltage protection (i=2, 3)
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
5
59Gi.TMS
0.050~3.200
0.001
6
59Gi.tmin
0.000~20.000
0.001
Time multiplier setting for stage i of
residual overvoltage protection (i=2, 3)
s
Minimum operating time for stage i of
residual overvoltage protection (i=2, 3)
Constant “α” for stage i of customized
7
59Gi.Alpha
0.020~5.000
0.001
inverse-time
characteristic
residual
overvoltage protection (i=2, 3)
Constant “C” for stage i of customized
8
59Gi.C
0.000~20.000
0.001
inverse-time
characteristic
residual
overvoltage protection (i=2, 3)
Constant “K” for stage i of customized
9
59Gi.K
0.000~120.000
0.001
inverse-time
characteristic
residual
overvoltage protection (i=2, 3)
Enabling/disabling stage 3 of residual
10
59G3.En_Trp
overvoltage protection for trip purpose
0 or 1
0: disable
1: enable
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3.18.4 Undervoltage Protection
3.18.4.1 General Application
The undervoltage protection can be applied to trip when fault occurs in a system. Two stages of
undervoltage protection are available measuring phase voltages U A, UB and UC or phase-to-phase
voltages UAB, UBC and UCA. The protection output can be selected for either any phase or all
phases operation. The undervoltage protection is normally used as decoupling system rather than
load shedding.
3.18.4.2 Function Description
Phase undervoltage protection has following functions:
1.
Three stages phase undervoltage protection with independent logic, voltage and time delay
settings.
2.
Undervoltage protection can be selected as definite-time or inverse-time characteristic. The
inverse-time characteristic is selectable, among IEC and ANSI/IEEE standard inverse-time
characteristics.
3.
Phase voltage or phase-to-phase voltage can be selected for protection calculation.
4.
“1-out-of-3” or “3-out-of-3” logic can be selected for protection criterion. (1-out-of-3 means any
of three phase voltages, 3-out-of-3 means all three phase voltages)
1.
Operation Criterion
Users can select phase voltage or phase-to-phase voltage for the protection calculation. If setting
[27Pi.Opt_Up/Upp] is set to “0”, phase voltage criterion is selected and if [27Pi.Opt_Up/Upp] is set
to “1”, phase-to-phase voltage criterion is selected.
When phase voltage or phase-to-phase voltage is less than any enabled stage voltage setting, the
stage protection picks up and operates after delay, which will drop off instantaneously when fault
voltage disappears.

Phase voltage criterion
Two operation criteria of definite-time undervoltage protection are shown as follows, which of them
is applied depending on the logic setting [27Pi.Opt_1P/3P].
UΦ_min<[ 27Pi.U_Set]
Equation 3.18-8
or
Ua<[ 27Pi.U_Set] & Ub<[27Pi.U_Set] & Uc<[27Pi.U_Set]
Equation 3.18-9
Where:
UΦ_min is the minimum value among three phase voltages.
Ua, Ub and Uc are three phase voltages.
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[27Pi.U_Set] is the setting of stage i of undervoltage protection.
When [27Pi.Opt_1P/3P] is set as “1”, “1-out-of-3” logic (Equation 3.18-8) is selected as operation
criterion, and when set as “0”, “3-out-of-3” logic (Equation 3.18-9) is selected.

Phase-to-phase voltage criterion
Two operation criteria of definite-time undervoltage protection are shown as follows, which of them
is applied depending on the logic setting [27Pi.Opt_Up/Upp].
UΦΦ_min<[ 27Pi.U_Set]
Equation 3.18-10
or
Uab<[27Pi.U_Set] & Ubc<[27Pi.U_Set] & Uca<[27Pi.U_Set]
Equation 3.18-11
Where:
UΦΦ_min is the minimum value among three phase-to-phase voltages.
Uab, Ubc and Uca are three phase-to-phase voltages.
[27Pi.U_Set] is the setting of stage i of undervoltage protection.
When the setting [27Pi.Opt_1P/3P] is set as “1”, “1-out-of-3” logic (Equation 3.18-10) is selected
as operation criterion, and when it is set as “0”, “3-out-of-3” logic (Equation 3.18-11) is selected.
2.
Characteristic Curve
Undervoltage protection can be selected as definite-time or inverse-time characteristic, and
inverse-time operating time curve is as follows.
Equation 3.18-12
Where:
Uset is the setting [27Pi.U_Set].
Tp is time multiplier setting [27Pi.TMS].
K is a constant.
C is a constant.
α is a constant.
U is the measured voltage
Operating characteristic of undervoltage protection can be chosen from definite-time characteristic
and twelve inverse-time characteristics by setting the logic setting [27Pi.Opt_Curve]. The
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parameters of each characteristic are listed in the following table.
Table 3.18-9 Inverse-time curve parameters of phase undervoltage protection
27Pi.Opt_Curve
α
K
Time Characteristic
C
DefTime
Definite time
IECN
IEC Normal inverse
0.14
0.02
0
IECV
IEC Very inverse
13.5
1.0
0
IECE
IEC Extremely inverse
80.0
2.0
0
IECST
IEC Short-time inverse
0.05
0.04
0
IECLT
IEC Long-time inverse
120.0
1.0
0
ANSIE
ANSI Extremely inverse
28.2
2.0
0.1217
ANSIV
ANSI Very inverse
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
ANSI Moderately inverse
0.0515
0.02
0.114
ANSILTE
ANSI Long-time extremely inverse
64.07
2.0
0.25
ANSILTV
ANSI Long-time very inverse
28.55
2.0
0.712
ANSILT
ANSI Long-time inverse
0.086
0.02
0.185
When inverse-time characteristic is selected, if calculated operating time is less than setting
[27Pi.tmin], then the operating time changes to the value of setting [27Pi.tmin] automatically.
Define-time or inverse-time phase under voltage protection drops off instantaneously when
measured voltage is higher than reset voltage.
3.18.4.3 Function Block Diagram
27Pi
27Pi.En1
27Pi.On
27Pi.En2
27Pi.Alm
27Pi.Blk
27Pi.Op
27Pi.St
27Pi.St1
27Pi.St2
27Pi.St3
27Pi.U_Absent
3.18.4.4 I/O Signals
Table 3.18-10 I/O signals of undervoltage protection
No.
1
Input Signal
27Pi.En1
Description
Stage i of undervoltage protection enabling input 1, it is triggered from binary input
or programmable logic etc. (i=1, 2, 3)
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2
27Pi.En2
3
27Pi.Blk
No.
Stage i of undervoltage protection enabling input 2, it is triggered from binary input
or programmable logic etc. (i=1, 2, 3)
Stage i of undervoltage protection blocking input, it is triggered from binary input
or programmable logic etc. (i=1, 2, 3)
Output Signal
Description
1
27Pi.On
Stage i of undervoltage protection is enabled. (i=1, 2, 3)
2
27Pi.Op
Stage i of undervoltage protection operates. (i=1, 2, 3)
3
27Pi.Alm
Stage i of undervoltage protection alarms. (i=1, 2, 3)
4
27Pi.St
Stage i of undervoltage protection starts. (i=1, 2, 3)
5
27Pi.St1
Stage i of undervoltage protection starts (A or AB). (i=1, 2, 3)
6
27Pi.St2
Stage i of undervoltage protection starts (B or BC). (i=1, 2, 3)
7
27Pi.St3
Stage i of undervoltage protection starts (C or CA). (i=1, 2, 3)
8
27Pi.U_Absent
No AC voltage input after the device powered on for stage i of undervoltage
protection (i=1, 2, 3)
3.18.4.5 Logic
In order to prevent undervoltage protection from undesired operation, after the device powered on,
if any phase current is greater than 0.06In or circuit breaker is in closed position, undervoltage
protection will be in service with a time delay of 100ms when the corresponding phase voltage is
greater than 0.1Un. Otherwise, undervoltage protection will be blocked by the signal
“27Pi.U_Absent”
Through settings these logic settings [27Pi.En_FD_Ctrl], [27Pi.En_Curr_Ctrl] and
[27Pi.En_VTS_Blk], undervoltage protection optionally can be controlled by FD element reflecting
current (including DPFC current element and residual current element), current condition and VT
circuit failure
When the setting [27Pi.En_FD_Ctrl] is set as “1”, undervoltage protection will be blocked if FD
element reflecting current does not operate.
When the setting [27Pi.En_Curr_Ctrl] is set as “1”, undervoltage protection will be blocked if
current condition (>0.06In) is not met.
When the setting [27Pi.En_VTS_Blk] is set as “1”, undervoltage protection will be blocked if VT
circuit fails.
If any phase of circuit breaker is open (binary input of normal close contact of breaker is energized)
and the corresponding phase current is smaller than 0.06In, undervoltage protection will be
blocked.
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SIG
VTS.Alm
>=1
&
SIG
VTS.Inst
EN
[27Pi.En_VTS_Blk]
EN
[27Pi.En_FD_Ctrl]
SIG
FD.Pkp
SIG
CB Open
SIG
27Pi.U_Absent
&
>=1
Block UV
>=1
Figure 3.18-6 Blocking logic of undervoltage protection
EN
[27Pi.En]
&
SIG 27Pi.En1
&
27Pi.On
SIG 27Pi.En2
SIG 27Pi.Blk
Figure 3.18-7 Enabling logic of undervoltage protection
SIG Ia>0.06In
>=1
UV_PhA_Curr_Rls
SIG Ib>0.06In
>=1
UV_PhB_Curr_Rls
SIG Ic>0.06In
>=1
UV_PhC_Curr_Rls
&
>=1
UV_PhAB_Curr_Rls
&
>=1
UV_PhBC_Curr_Rls
&
>=1
UV_PhCA_Curr_Rls
EN
[27Pi.En_Curr_Ctrl]
Figure 3.18-8 Current releasing logic of undervoltage protection
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EN
[27Pi.En_Alm]
SET [27Pi.Opt_1P/3P]
SIG 27Pi.On
SIG Block UV
SET [27Pi.Opt_Up/Upp]
&
Timer
t
&
SIG UV_PhA_Curr_Rls
>=1
&
&
t
SET UA<[27Pi.U_Set]
&
SIG UV_PhAB_Curr_Rls
SET UAB<[27Pi.U_Set]
&
SIG UV_PhB_Curr_Rls
&
Timer
t
&
>=1
27Pi.Op
t
SET UB<[27Pi.U_Set]
&
&
>=1
SIG UV_PhBC_Curr_Rls
27Pi.Alm
&
SET UBC<[27Pi.U_Set]
>=1
&
Timer
t
&
SIG UV_PhC_Curr_Rls
>=1
t
SET UC<[27Pi.U_Set]
27Pi.St1
&
27Pi.St2
SIG UV_PhCA_Curr_Rls
27Pi.St3
SET UCA<[27Pi.U_Set]
>=1
27Pi.St
Figure 3.18-9 Logic diagram of stage i of undervoltage protection
i=1, 2, 3
3.18.4.6 Settings
Table 3.18-11 Settings of undervoltage protection
No.
Name
Range
Step
Unit
1
27Pi.U_Set
0~Unn
0.001
V
2
27Pi.t_Op
0.000~30.000
0.001
s
Remark
Voltage setting for stage i of undervoltage
protection (i=1, 2, 3)
Time delay for stage i of undervoltage
protection (i=1, 2, 3)
Enabling/disabling stage i of undervoltage
3
27Pi.En
protection (i=1, 2, 3)
0 or 1
0: disable
1: enable
Enabling/disabling stage i of undervoltage
protection controlled by FD element
4
27Pi.En_FD_Ctrl
0 or 1
reflecting current (i=1, 2, 3)
0: disable
1: enable
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No.
Name
Range
Step
Unit
Remark
Enabling/disabling stage i of undervoltage
protection controlled by current condition
5
27Pi.En_Curr_Ctrl
0 or 1
(i=1, 2, 3)
0: disable
1: enable
Enabling/disabling stage i of undervoltage
protection controlled by VT circuit failure
6
27Pi.En_VTS_Blk
0 or 1
(i=1, 2, 3)
0: disable
1: enable
Option of 1-out-of-3 mode or 3-out-of-3
mode
7
27Pi.Opt_1P/3P
0 or 1
for
stage
i
of
undervoltage
protection (i=1, 2, 3)
0: 3-out-of-3 mode
1: 1-out-of-3 mode
Option
of
voltage
criterion
adopting
phase-to-phase voltage or phase voltage
8
27Pi.Opt_Up/Upp
for stage i of undervoltage protection (i=1,
0 or 1
2, 3)
0: phase voltage
1: phase-to-phase voltage
Enabling/disabling stage i of undervoltage
9
27Pi.En_Alm
protection operate to alarm (i=1, 2, 3)
0 or 1
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
10
27Pi.Opt_Curve
Option of characteristic curve for stage i of
ANSIE
undervoltage protection (i=1, 2, 3)
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage i of
11
27Pi.TMS
0.010~200.000
0.001
inverse-time undervoltage protection (i=1,
2, 3)
12
27Pi.tmin
0.050~20.000
0.001
s
Minimum delay for stage i of inverse-time
undervoltage protection (i=1, 2, 3)
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3.19 Frequency Protection
3.19.1 Overfrequency Protection
3.19.1.1 General Application
If the power frequency of regional rises due to the active power excess demand, overfrequency
protection operates to perform generator rejection to shed part of the generators automatically
according to the rising frequency so that power supply and the load are re-balanced.
3.19.1.2 Function Description
The device provides four stages overfrequency protection. When system frequency is greater than
the setting [81O.f_Pkp], overfrequency protection will put into service.
In order to prevent possible maloperation of overfreqency protection in conditions of high
harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:
1.
Blocking in undervoltage condition
If the positive voltage U1<0.15Un, the calculation of protection is not carried out and the output
relay will be blocked.
2.
Frequency abnormality condition
When f<40Hz or f>65Hz, overfrequency protection will be blocked
Operation criteria of overfrequency protection is shown in the following equation.
f>[81O.OFi.f_Set]
Equation 3.19-1
Where:
f is system frequency.
[81O.OFi.f_Set] is the frequency setting of stage i of overfrequency protection. (i=1, 2, 3, 4)
3.19.1.3 Function Block Diagram
81O.OFi
81O.En1
81O.OFi.On
81O.En2
81O.St
81O.Blk
81O.OFi.Op
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3.19.1.4 I/O Signals
Table 3.19-1 I/O signals of overfrequency protection
No.
Input Signal
1
81O.En1
2
81O.En2
3
81O.Blk
No.
Description
Overfrequency protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Overfrequency protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Overfrequency protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
1
81O.OFi.On
Stage i of overfrequency protection is enabled (i=1, 2, 3, 4).
2
81O.OFi.Op
Stage i of overfrequency protection operates (i=1, 2, 3, 4).
3
81O.St
Overfrequency protection starts.
3.19.1.5 Logic
SIG
81O.St1
SIG
81O.St2
SIG
81O.St3
SIG
81O.St4
>=1
>=1
81O.St
>=1
Figure 3.19-1 Logic diagram of overfrequency protection (start)
SIG
81O.En1
SIG
81O.En2
EN
[81O.OFi.En]
SIG
81O.Blk
SIG
FD.Pkp
SIG
U1<0.15Un
SIG
f<40 or f>65
SET f>[81O.f_Pkp]
&
&
81O.OFi.On
&
>=1
&
50ms
0ms
81O.Sti
&
SET f>[81O.OFi.f_Set]
EN
[81O.OFi.En]
SIG
VTS.Alm
[81O.OFi.t_Op]
&
0ms
81O.OFi.Op
Figure 3.19-2 Logic diagram of stage i of overfrequency protection
i=1, 2, 3, 4
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3.19.1.6 Settings
Table 3.19-2 Settings of overfrequency protection
No.
1
Name
81O.f_Pkp
Range
50.000~65.000
Step
Unit
0.001
Hz
Remark
Frequency
pickup
setting
for
overfrequency protection
Frequency setting for stage i of
2
81O.OFi.f_Set
50.000~65.000
0.001
Hz
overfrequency protection (i=1, 2, 3,
4)
Time
3
81O.OFi.t_Op
0.000~20.000
0.001
s
delay
for
stage
i
of
overfrequency protection (i=1, 2, 3,
4)
Enabling/disabling
stage
i
of
overfrequency protection (i=1, 2, 3,
4
81O.OFi.En
0 or 1
4)
0: disable
1: enable
3.19.2 Underfrequency Protection
3.19.2.1 General Application
In case of frequency decline due to lack of active power in the power system, underfrequency
protection operates to shed part of the load according to the declined value of frequency to
re-balance the power supply and the load.
3.19.2.2 Function Description
The device provides four stages underfrequency protection. When system frequency is smaller
than the setting [81U.f_Pkp], underfrequency protection will put into service.
In order to prevent possible maloperation of underfrequency protection in conditions of high
harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:
1.
Blocking in undervoltage condition
If the positive voltage U1<0.15Un, the calculation of protection is not carried out and the output
relay will be blocked.
2.
df/dt blocking element
If －df/dt≥[81U.df/dt_Blk], the calculation of protection is not carried out and the output relay will
be blocked. The blocking element will not be released automatically until the system frequency
recovers to be greater than the setting [81U.f_Pkp].
3.
Frequency abnormality condition
When f<40Hz or f>65Hz, underfrequency protection will be blocked
Operation criteria of underfrequency protection is shown in the following equation.
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f<[81U.UFi.f_Set]
Equation 3.19-2
Where:
f is system frequency.
[81U.UFi.f_Set] is the frequency settings of stage i of underfrequency protection. (i=1, 2, 3, 4)
The equation of df/dt blocking function is as follows.
-df/dt>[81U.df/dt_Blk]
Equation 3.19-3
Where:
df/dt is the frequency slip speed and the time step (i.e. dt) for the calculation is equal to 5 cycle.
[81U.df/dt_Blk] is the setting of df/dt blocking underfrequency protection.
Underfrequency protection can be blocked by the frequency slip speed (df/dt). If the logic setting
[81U.UFi.En_df/dt_Blk] is set as “1”, when Equation 3.19-2 and Equation 3.19-3 are met, it is
decided that a fault occurred and the corresponding stage underfrequency protection is blocked at
the same time for the purpose of waiting for operation of other related protection. The blocking
signal will not reset until the system frequency recovers, i.e. the system frequency is greater than
the setting [81U.f_Pkp]. If the logic setting is set as “0”, when Equation 3.19-2 and Equation 3.19-3
are met, the stage underfrequency protection will be released to operate.
3.19.2.3 Function Block Diagram
81U.UFi
81U.En1
81U.UFi.On
81U.En2
81U.St
81U.Blk
81U.UFi.Op
3.19.2.4 I/O Signals
Table 3.19-3 I/O signals of underfrequency protection
No.
Input Signal
1
81U.En1
2
81U.En2
3
81U.Blk
No.
Description
Underfrequency protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Underfrequency protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Underfrequency protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
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1
81U.UFi.On
Stage i of underfrequency protection is enabled (i=1, 2, 3, 4).
2
81U.UFi.Op
Stage i of underfrequency protection operates (i=1, 2, 3, 4).
3
81U.St
Underfrequency protection starts.
3.19.2.5 Logic
SIG
81U.St1
SIG
81U.St2
SIG
81U.St3
SIG
81U.St4
>=1
>=1
81U.St
>=1
Figure 3.19-3 Logic diagram of underfrequency protection (start)
SIG 81U.En1
&
SIG 81U.En2
EN
&
[81U.UFi.En]
81U.UFi.On
SIG 81U.Blk
&
SIG FD.Pkp
&
SIG U1<0.15Un
>=1
SIG f<40 or f>65
SET f<[81U.f_Pkp]
50ms
SET -df/dt<[81U.df/dt_Blk]
>=1
EN
[81U.UFi.En_df/dt_Blk]
SET f<[81U.UFi.f_Set]
EN
0ms
&
81U.Sti
&
[81U.UFi.t_Op]
&
0ms
81U.UFi.Op
[81U.UFi.En]
SIG VTS.Alm
Figure 3.19-4 Logic diagram of stage i of underfrequency protection
i=1, 2, 3, 4
3.19.2.6 Settings
Table 3.19-4 Settings of underfrequency protection
No.
Name
Range
Step
Unit
1
81U.f_Pkp
45.000~60.000
0.01
Hz
2
81U.df/dt_Blk
0.200~20.000
0.01
Hz/s
3
81U.UFi.f_Set
45.000~60.000
0.001
Hz
3-182
Remark
Frequency
pickup
setting
for
underfrequency protection
Rate
of
frequency
change
for
blocking underfrequency protection
Frequency setting for stage i of
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Date: 2019-03-01
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
underfrequency protection (i=1, 2, 3,
4)
Time
4
81U.UFi.t_Op
0.000~30.000
0.01
s
delay
for
stage
i
of
underfrequency protection (i=1, 2, 3,
4)
Enabling/disabling
stage
i
of
underfrequency protection (i=1, 2, 3,
5
81U.UFi.En
0 or 1
4)
0: disable
1: enable
Enabling/disabling rate of frequency
change
6
81U.UFi.En_df/dt_Blk
to
block
stage
i
of
underfrequency protection (i=1, 2, 3,
0 or 1
4)
0: disable
1: enable
3.20 Breaker Failure Protection
3.20.1 General Application
Duplicated protection configurations are usually adopted for EHV power system, but the primary
equipment, circuit breaker, is not duplicated. Breaker failure protection is adopted to cater circuit
breaker tripping failure.
Breaker failure protection issues a back-up trip command to trip adjacent circuit breakers in case
of a tripping failure of the circuit breaker, and clears the fault as requested by the device. To utilize
the protection information of faulty equipment and the electrical information of failure circuit
breaker to constitute the criterion of breaker failure protection, it can ensure that the adjacent
circuit breakers of failure circuit breaker are tripped with a shorter time delay, so that the affected
area is minimized, and ensure stable operation of the entire power grid to prevent generators,
transformers and other components from seriously damaged.
NOTICE!
For double circuit breakers mode, the device will provide independent breaker failure
protection for CB1 and CB2 respectively. Both breaker failure protections have the
same logic. The difference is that the prefix “CBx.” is added to all signals and settings
for circuit breaker No.x (x=1 or 2).
3.20.2 Function Description
The instantaneous re-tripping function, after receiving tripping signal from other device and the
corresponding phase overcurrent element operating, is available and provides phase-segregated
binary output contact, which can ensure the circuit breaker is still tripped in case the secondary
circuit between the device and the circuit breaker is abnormal, to avoid undesired tripping of
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breaker failure protection and the expansion of the affected area. Instantaneous re-tripping
function does not block AR.
When both the phase-segregated tripping contact from line protection and the corresponding
phase overcurrent element operate, or both the three-phase tripping contact and any phase
overcurrent element operate, breaker failure protection will send three-phase tripping command to
trip local circuit breaker after time delay of [CBx.50BF.t1_Op] and trip all adjacent circuit breakers
after time delay of [CBx.50BF.t2_Op].
When the protection element except undervoltage element within this device operates and issues
tripping signal, breaker failure protection will also be initiated.
Taking into account that the faulty current is too small for generator or transformer fault, the
sensitivity of phase current element may not meet the requirements, zero-sequence current
criterion and negative-sequence current criterion are provided in addition to the phase overcurrent
element for breaker failure protection initiated by input signal [CBx.50BF.ExTrp3P_GT] from
generator and transformer protection. They can be enabled or disabled by logic settings
[CBx.50BF.En_3I0_3P] and [CBx.50BF.En_I2_3P] respectively.
For some special fault (for example, mechanical protection or overvoltage protection operating),
maybe faulty current is very small and current criterion of breaker failure protection is not met, in
order to make breaker failure protection can also operate under the above situation, an input
signal [CBx.50BF.ExTrp_WOI] is equipped to initiate breaker failure protection, once the input
signal is energized, normally closed auxiliary contact of circuit breaker is chosen in addition to
breaker failure current check to trigger breaker failure timer. The device takes current as priority
with CB auxiliary contact (52b) as an option criterion for breaker failure check.
3.20.3 Function Block Diagram
50BF
CBx.50BF.ExTrp3P_L
CBx.50BF.On
CBx.50BF.ExTrp3P_GT
CBx.50BF.Op_ReTrpA
CBx.50BF.ExTrp_WOI
CBx.50BF.Op_ReTrpB
CBx.50BF.ExTrpA
CBx.50BF.Op_ReTrpC
CBx.50BF.ExTrpB
CBx.50BF.Op_ReTrp3P
CBx.50BF.ExTrpC
CBx.50BF.Op_t1
CBx.50BF.En
CBx.50BF.Op_t2
CBx.50BF.Blk
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3.20.4 I/O Signals
Table 3.20-1 I/O signals of breaker failure protection
No.
Input Signal
Description
1
CBx.50BF.ExTrp3P_L
Input signal of three-phase tripping contact from line protection
2
CBx.50BF.ExTrp3P_GT
3
CBx.50BF.ExTrpA
Input signal of phase-A tripping contact from external device
4
CBx.50BF.ExTrpB
Input signal of phase-B tripping contact from external device
5
CBx.50BF.ExTrpC
Input signal of phase-C tripping contact from external device
Input signal of three-phase tripping contact from generator or transformer
protection
Input signal of three-phase tripping contact from external device. Once it is
6
CBx.50BF.ExTrp_WOI
energized, normally closed auxiliary contact of circuit breaker is chosen in
addition to breaker failure current check to trigger breaker failure timers.
7
CBx.50BF.En
Input signal of enabling breaker failure protection
Breaker failure protection blocking input, such as function blocking binary
8
CBx.50BF.Blk
input.
When the input is 1, breaker failure protection is reset and time delay is
cleared.
No.
Output Signal
Description
1
CBx.50BF.On
Breaker failure protection is enabled
2
CBx.50BF.Op_ReTrpA
Breaker failure protection operates to re-trip phase-A circuit breaker
3
CBx.50BF.Op_ReTrpB
Breaker failure protection operates to re-trip phase-B circuit breaker
4
CBx.50BF.Op_ReTrpC
Breaker failure protection operates to re-trip phase-C circuit breaker
5
CBx.50BF.Op_ReTrp3P
Breaker failure protection operates to re-trip three-phase circuit breaker
6
CBx.50BF.Op_t1
Stage 1 of breaker failure protection operates
7
CBx.50BF.Op_t2
Stage 2 of breaker failure protection operates
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3.20.5 Logic
SIG CBx.50BF.En
EN
&
[CBx.50BF.En]
CBx.50BF.On
SIG CBx.50BF.Blk
SIG CBx.50BF.On
&
SIG FD.Pkp
EN [CBx.50BF.En_ReTrp]
EN [CBx.50BF.En_3I0_1P]
>=1
SET 3I0>[CBx.50BF.3I0_Set]
SIG CBx.BFI_A
BI
&
>=1
&
>=1
&
>=1
&
SIG CBx.BFI_B
[CBx.50BF.t_ReTrp] 0ms
CBx.50BF.Op_ReTrpB
[CBx.50BF.t_ReTrp] 0ms
CBx.50BF.Op_ReTrpC
&
[CBx.50BF.ExTrpB]
SET IB>[CBx.50BF.I_Set]
SIG CBx.BFI_C
BI
CBx.50BF.Op_ReTrpA
[CBx.50BF.ExTrpA]
SET IA>[CBx.50BF.I_Set]
BI
[CBx.50BF.t_ReTrp] 0ms
&
[CBx.50BF.ExTrpC]
>=1
SET IC>[CBx.50BF.I_Set]
SIG CBx.BFI_3P
BI
[CBx.50BF.ExTrp3P_L]
BI
[CBx.50BF.ExTrp3P_GT]
BI
[CBx.50BF.ExTrp_WOI]
EN [CBx.50BF.En_3I0_3P]
>=1
>=1
>=1
[CBx.50BF.t_ReTrp] 0ms
>=1
>=1
[CBx.50BF.Op_ReTrp3P]
&
&
&
SET 3I0>[CBx.50BF.3I0_Set]
EN [CBx.50BF.En_I2_3P]
&
&
&
&
>=1
>=1
[CBx.50BF.t1_Op]
0ms
CBx.50BF.Op_t1
[CBx.50BF.t2_Op]
0ms
CBx.50BF.Op_t2
&
SET I2>[CBx.50BF.I2_Set]
&
EN [CBx.50BF.En_CB_Ctrl]
BI
[CBx.52b_PhA]
BI
[CBx.52b_PhB]
BI
[CBx.52b_PhC]
SIG CBx.50BF.On
&
&
SIG FD.Pkp
Figure 3.20-1 Logic diagram of breaker failure protection
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3.20.6 Settings
Table 3.20-2 Settings of breaker failure protection
No.
Name
Range
Step
Unit
Remark
Current setting of phase current
criterion for BFP
1
CBx.50BF.I_Set
(0.050~30.000 )×In
0.001
A
2
CBx.50BF.3I0_Set
(0.050~30.000 )×In
0.001
A
3
CBx.50BF.I2_Set
(0.050~30.000 )×In
0.001
A
4
CBx.50BF.t_ReTrp
0.000~10.000
0.001
s
Time delay of re-tripping for BFP
5
CBx.50BF.t1_Op
0.000~10.000
0.001
s
Time delay of stage 1 for BFP
6
CBx.50BF.t2_Op
0.000~10.000
0.001
s
Time delay of stage 2 for BFP
7
CBx.50BF.En
0 or 1
8
CBx.50BF.En_ReTrp
0 or 1
9
CBx.50BF.En_3I0_1P
0 or 1
10
CBx.50BF.En_3I0_3P
0 or 1
11
CBx.50BF.En_I2_3P
0 or 1
12
CBx.50BF.En_CB_Ctrl
0 or 1
Current setting of zero-sequence
current criterion for BFP
Current
setting
of
negative-sequence
current
criterion for BFP
Enabling/disabling breaker failure
protection
0: disable
1: enable
Enabling/disabling re-trip function
for BFP
0: disable
1: enable
Enabling/disabling
zero-sequence current criterion
for BFP initiated by single-phase
tripping contact
0: disable
1: enable
Enabling/disabling
zero-sequence current criterion
for BFP initiated by three-phase
tripping contact
0: disable
1: enable
Enabling/disabling
negative-sequence
current
criterion for BFP initiated by
three-phase tripping contact
0: disable
1: enable
Enabling/disabling breaker failure
protection can be initiated by
normally closed contact of circuit
breaker
0: disable
1: enable
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3.21 Thermal Overload Protection
3.21.1 General Application
During overload operation of a transmission line (specially for cable), great current results in
greater heat to lead temperature increase and if the temperature reaches too high values the
equipment might be damaged.
Thermal overload protection estimates the internal heat content (temperature) continuously. This
estimation is made by using a thermal model with two time constants, which is based on current
measurement.
When the temperature increases to the alarm value, the protection issues alarm signals to remind
the operator for attention, and if the temperature continues to increase to the trip value, the
protection sends trip command to disconnect the protected line.
3.21.2 Function Description
Thermal overload protection has following functions:

Thermal time characteristic adopting IEC 60255-8

Two stages for alarm purpose and two stages for trip purpose

Thermal accumulation can be cleared by external input signal
The device provides a thermal overload model which is based on the IEC60255-8 standard. The
thermal overload formulas are shown as below.
1.
Cold start characteristic:
2.
Hot start characteristic:
Where:
T = Time to operate (in seconds)
 = Thermal time constant of the equipment to be protected, the setting [49.Tau]
IB = Full load current rating, the setting [49.Ib_Set]
I = The RMS value of the largest phase current
IP = Steady state pre-loading before application of the overload
k = Factor associated to the thermal state formula, the setting [49.K]
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ln = Natural logarithm
The characteristic curve of thermal overload model is shown in Figure 3.21-1.
Refer to IEC60255-8
t
Ip
P=—
IB
P = 0.0
P = 0.6
P = 0.8
P = 0.9
kIB
I
Figure 3.21-1 Characteristic curve of thermal overload model
The hot start characteristic is adopted in the device. The calculation is carried out at zero of Ip, so
users need not to set the value of Ip.
Tripping outputs of the protection is controlled by current, even if the thermal accumulation value is
greater than the setting for tripping, the protection drops off instantaneously when current
disappears. Alarm outputs of the protection is not controlled by current, and only if the thermal
accumulation value is greater than the setting for alarm, alarm output contacts, which can be
connected to block the auto-reclosure, will operate.
3.21.3 Function Block Diagram
49
49.Clr_Cmd
49.On
49.En
49.St
49.Blk
49-i.Alm
49-i.Op
3.21.4 I/O Signals
Table 3.21-1 I/O signals of thermal overload protection
No.
Input Signal
1
49.Clr_Cmd
2
49.En
3
49.Blk
Description
Input signal of clear thermal accumulation value
Thermal overload protection enabling input, it is triggered from binary input or
programmable logic etc.
Thermal overload protection blocking input, it is triggered from binary input or
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programmable logic etc.
No.
Output Signal
Description
1
49.On
Thermal overload protection is enabled.
2
49.St
Thermal overload protection starts.
3
49-i.Op
Stage i of thermal overload protection operates to trip. (i=1, 2)
4
49-i.Alm
Stage i of thermal overload protection operates to alarm. (i=1, 2)
3.21.5 Logic
SIG 49.En
&
&
SIG 49.Blk
49.On
EN
[49-i.En_Trp]
EN
[49-i.En_Alm]
>=1
&
SIG FD.Pkp
49.St
Timer
t
&
49-i.Op
t
SIG I3P
Timer
t
&
SET [49.Ib_Set]
BI
49-i.Alm
t
[49.Clr_Cmd]
Figure 3.21-2 Logic diagram of stage i of thermal overload protection
i=1, 2
3.21.6 Settings
Table 3.21-2 Settings of thermal overload protection
No.
Name
Range
Step
Unit
Remark
The factor setting for stage i of
1
49-i.K
1.000~3.000
0.001
%
thermal overload protection which is
associated to the thermal state
formula (i=1, 2)
2
49.Ib_Set
(0.050~30.000 )×In
0.001
A
3
49.Tau
0.100~100.000
0.001
min
The reference current setting of the
thermal overload protection
The time constant setting of the
IDMT overload protection
Enabling/disabling stage i of thermal
overload
4
49-i.En_Alm
0 or 1
protection
for
alarm
purpose (i=1, 2)
0: disable
1: enable
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No.
Name
Range
Step
Unit
Remark
Enabling/disabling stage i of thermal
overload protection for trip purpose
5
49-i.En_Trp
0 or 1
(i=1, 2)
0: disable
1: enable
3.22 Stub Differential Protection
3.22.1 General Application
Stub differential protection is mainly designed for one and a half breakers arrangement. When line
disconnector is open and transmission line is put into maintenance, line VT is no voltage. Distance
protection is disabled, and stub differential protection is enabled. It is used to protect stub section
among two circuit breakers and line disconnector. Usually, stub differential protection is enabled
automatically by normally closed auxiliary contact of line disconnector.
CT1
CT2
Bus
Bus
To the device
Line
Line
Figure 3.22-1 3/2 breakers arrangement
3.22.2 Function Description
3.22.2.1 Stub Differential Element
Stub differential element is composed of percentage differential principle. Stub differential element
can be controlled by normally closed auxiliary contact of line disconnector to enabled or disabled.
The normally closed auxiliary contact of line disconnector is closed when line disconnector is open.
The operation criterion is:


 I 1  I  2  [87STB.I_Pkp]





I  I
1
 2  [87STB.Slop e]  I 1  I  2


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Where:


I 1 、 I  2 are secondary phase currents corresponding to both circuit breakers, are formed by
phase A, B, C
3.22.2.2 Differential Current Alarm
Under normal conditions, when stub differential protection is enabled, the device will issue the
alarm signal [87STB.Alm_Diff] with the time delay if the following operation criterion is met.


 I 1  I  2  [87STB.I_Alm]





I  I
1
 2  0.15  I 1  I  2


3.22.2.3 Disconnector Position Alarm
The device will issue the alarm signal [87STB.Alm_89b_DS] with the time delay of 10s if the signal
[87STB.89b_DS] is energized and the line is live, and the alarm signal will drop off with the time
delay of 10s after the abnormality disappears.
When the alarm signal of disconnector position appears, the operator should confirm the status of
disconnector position in time. The user can use programmable logic to determine whether the
disconnector position alarm will blocked stub differential protection.
3.22.2.4 CT Saturation
When there is an external fault, transient CT saturation may be happened. In order to prevent stub
differential protection from undesired operation, the floating technology of adaptive restraint
current is adopted to ensure that the device does not maloperate due to the serious saturation.
3.22.3 Function Block Diagram
87STB
87STB.En1
87STB.On
87STB.En2
87STB.On_Local
87STB.Blk
87STB.Op
87STB.89b_DS
87STB.St
87STB.89b_DS_Rmt
87STB.StA
87STB.StB
87STB.StC
87STB.Alm_Diff
87STB.Alm_89b_DS
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3.22.4 I/O Signals
Table 3.22-1 I/O signals of stub differential protection
No.
Input Signal
1
87STB.En1
2
87STB.En2
3
87STB.Blk
4
87STB.89b_DS
Description
Stub differential protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Stub differential protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Stub differential protection blocking input, it is triggered from binary input or
programmable logic etc.
Normally closed auxiliary contact of line disconnector
Normally closed auxiliary contact of line disconnector in remote end
5
87STB.89b_DS_Rmt
In general, it is configured as receiving the signal [87STB.On_Local] from the
remote end.
No.
Output Signal
Description
Stub differential protection is enabled. (Based on disconnector position signal
1
87STB.On
2
87STB.On_Local
3
87STB.Op
Stub differential protection operates.
4
87STB.St
Stub differential protection starts.
5
87STB.StA
Phase A of stub differential protection starts.
6
87STB.StB
Phase B of stub differential protection starts.
7
87STB.StC
Phase C of stub differential protection starts.
8
87STB.Alm_Diff
The alarm signal of differential current abnormality
9
87STB.Alm_89b_DS
The alarm signal of disconnector position abnormality
in both local end and remote end)
Stub differential protection is enabled. (Based on disconnector position signal
in local end)
3.22.5 Logic
Based on calculating vector summation of currents from dual CTs, the logic scheme of stub
differential protection is shown as Figure 3.22-2.
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SIG
Idiff>0.06In
SIG
87STB.89b_DS
SIG
87STB.En1
SIG
87STB.En2
EN
[87STB.En]
SIG
87STB.Blk
SIG
Enable 87STB
SIG
87STB.89b_DS
&
10s
10s
87STB.Alm_89b_DS
&
&
Enable 87STB
&
87STB.On_Local
>=1
&
SIG
87STB.89b_DS_Rmt
SET
Idiffa>[87STB.I_Alm]
SET
IdiffA>0.15×IBiasA
SET
Idiffb>[87STB.I_Alm]
SET
IdiffB>0.15×IBiasB
SET
Idiffc>[87STB.I_Alm]
SET
IdiffC>0.15×IBiasC
EN
[87STB.En_Alm]
SIG
87STB.Alm_Diff
SIG
87STB.En_CTS_Blk
SET
Idiffa>[87STB.I_Pkp]
SET
IdiffA>[87STB.Slope]×IBiasA
SET
Idiffb>[87STB.I_Pkp]
SET
IdiffB>[87STB.Slope]×IBiasB
SET
Idiffc>[87STB.I_Pkp]
SET
IdiffC>[87STB.Slope]×IBiasC
87STB.On
&
&
&
>=1
&
&
10s
10s
87STB.Alm_Diff
&
&
>=1
>=1
87STB.St
[87STB.t_Op]
87STB.Op
&
87STB.StA
&
&
87STB.StB
&
&
87STB.StC
&
Figure 3.22-2 Logic diagram of stub differential protection
3.22.6 Settings
Table 3.22-2 Settings of stub differential protection
No.
1
Name
87STB.I_Pkp
Range
Step
Unit
(0.050~30.000)×In
0.001
A
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No.
Name
Range
Step
Unit
A
2
87STB.I_ Alm
(0.050~30.000)×In
0.001
3
87STB.Slope
0.5~1
0.001
4
87STB.t_Op
0.000~10.000
0.001
Remark
Current
setting
of
differential
current
differential
current alarm
Slope
of
protection
s
Time delay of stub differential
protection
Enabling/disabling stub differential
5
87STB.En
protection
0 or 1
1: enable
0: disable
Enabling/disabling
6
87STB.En_Alm
differential
current alarm function
0 or 1
1: enable
0: disable
Enabling/disabling stub differential
protection controlled by CT circuit
7
87STB.En_CTS_Blk
0 or 1
failure
1: enable
0: disable
3.23 Dead Zone Protection
3.23.1 General Application
Generally, fault current is very large when multi-phase fault occurs between CT and circuit breaker
(i.e. dead zone) and it will have a greater impact on the system. Breaker failure protection can
operate after a longer time delay, in order to clear the dead zone fault quickly and improve the
system stability, dead zone protection with shorter time delay (compared with breaker failure
protection) is adopted.
NOTICE!
For double circuit breakers mode, the device will provide independent dead zone
protection for CB1 and CB2 respectively. Both dead zone protections have the same
logic. The difference is that the prefix “CBx.” is added to all signals and settings for
circuit breaker No.x (x=1 or 2).
3.23.2 Function Description
For some wiring arrangement (for example, circuit breaker is located between CT and the line), if
fault occurs between CT and circuit breaker, line protection can operate to trip circuit breaker
quickly, but the fault have not been cleared since local circuit breaker is tripped. Here dead zone
protection is needed in order to trip relevant circuit breaker.
The criterion for dead zone protection is: when dead zone protection is enabled, binary input of
initiating dead zone protection is energized (by default, three-phase tripping signal is used to
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initiate dead zone protection), if overcurrent element for dead zone protection operates, then
corresponding circuit breaker is tripped and three phases normally closed contact of the circuit
breaker are energized, dead zone protection will operate to trip adjacent circuit breaker after a
time delay.
3.23.3 Function Block Diagram
50DZ
CBx.50DZ.En1
CBx.50DZ.On
CBx.50DZ.En2
CBx.50DZ.Op
CBx.50DZ.Blk
CBx.50DZ.St
CBx.50DZ.Init
3.23.4 I/O Signal
Table 3.23-1 I/O signals of dead zone protection
No.
Input Signal
Description
1
CBx.50DZ.En1
Dead zone protection enabling input 1, it can be binary inputs or logic link.
2
CBx.50DZ.En2
Dead zone protection enabling input 2, it can be binary inputs or logic link.
3
CBx.50DZ.Blk
4
CBx.50DZ.Init
No.
Dead zone protection blocking input, such as function blocking binary input. When
the input is 1, dead zone protection is reset and time delay is cleared.
Initiation signal input of the dead zone protection.
Output Signal
Description
1
CBx.50DZ.On
Dead zone protection is enabled.
2
CBx.50DZ.St
Dead zone protection starts.
3
CBx.50DZ.Op
Dead zone protection operates.
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3.23.5 Logic
EN
[CBx.50DZ.En]
SIG
CBx.50DZ.En1
SIG
CBx.50DZ.En2
SIG
CBx.50DZ.Blk
&
&
CBx.50DZ.On
&
CBx.50DZ.St
&
[CBx.50DZ.t_Op]
SIG
FD.Pkp
SIG
CBx.52b_PhA
SIG
CBx.52b_PhB
SIG
CBx.52b_PhC
SET
Ia > [CBx.50DZ.I_Set]
SET
Ib > [CBx.50DZ.I_Set]
SET
Ic > [CBx.50DZ.I_Set]
SIG
CBx.50DZ.Init
SIG
CBx.Trp
0ms
CBx.50DZ.Op
&
>=1
&
>=1
Figure 3.23-1 Dead zone protection
3.23.6 Settings
Table 3.23-2 Settings of dead zone protection
No.
Name
Range
Step
Unit
Remark
Current
1
CBx.50DZ.I_Set
(0.050~30.000)×In
0.001
A
setting
for
dead
zone
protection. This setting shall ensure the
protection being sensitive enough if
dead zone fault occurs.
2
CBx.50DZ.t_Op
0.000~10.000
0.001
s
Time delay of dead zone protection.
Enabling/disabling
3
CBx.50DZ.En
0 or 1
-
dead
zone
protection.
1: enable
0: disable
3.24 Pole Discrepancy Protection
3.24.1 General Application
The pole discrepancy of circuit breaker may occur during operation of a breaker with segregated
operating gears for the three phases. The reason could be an interruption in the tripping/closing
circuits, or mechanical failure. A pole discrepancy can only be tolerated for a limited period. When
there is loading, zero-sequence or negative-sequence current will be generated in the power
system, which will result in overheat of the generator or the motor. With the load current increasing,
overcurrent elements based on zero-sequence current or negative-sequence current may operate.
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Pole discrepancy protection is required to operate before the operation of these overcurrent
elements.
NOTICE!
For double circuit breakers mode, the device will provide independent pole discrepancy
protection for CB1 and CB2 respectively. Both pole discrepancy protections have the
same logic. The difference is that the prefix “CBx.” is added to all signals and settings
for circuit breaker No.x (x=1 or 2).
3.24.2 Function Description
Pole discrepancy protection determines three-phase breaker pole discrepancy condition by its
phase segregated CB auxiliary contacts. In order to improve the reliability of pole discrepancy
protection, the asymmetrical current component can be selected as addition criteria when needed.
3.24.3 Function Block Diagram
62PD
CBx.62PD.En1
CBx.62PD.On
CBx.62PD.En2
CBx.62PD.Op
CBx.62PD.Blk
CBx.62PD.St
3.24.4 I/O Signals
Table 3.24-1 I/O signals of pole discrepancy protection
No.
Input Signal
1
CBx.62PD.En1
2
CBx.62PD.En2
3
CBx.62PD.Blk
No.
Description
Pole discrepancy protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Pole discrepancy protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Pole discrepancy protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
1
CBx.62PD.On
Pole discrepancy protection is enabled.
2
CBx.62PD.Op
Pole discrepancy protection operates to trip
3
CBx.62PD.St
Pole discrepancy protection starts
3.24.5 Logic
Phase-segregated circuit breaker auxiliary contacts are connected to the device. When the state
of three phase-segregated circuit breaker auxiliary contacts are inconsistent, pole discrepancy
protection will be started and initiate output after a time delay [CBx.62PD.t_Op].
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Pole discrepancy protection can be blocked by external input signal [62PD.Blk]. In general, this
input signal is usually from the output of 1-pole AR initiation, so as to prevent pole discrepancy
protection from operation during 1-pole AR initiation.
SIG
CBx.62PD.En1
SIG
CBx.62PD.En2
EN
[CBx.62PD.En]
&
&
62PD.On
&
SIG CBx.62PD.Blk
SIG
FD.Pkp
EN
[CBx.62PD.En_3I0/I2_Ctrl]
SET 3I0>[CBx.62PD.3I0_Set]
>=1
>=1
SET I2>[CBx.62PD.I2_Set]
BI
[CBx.52b_PhA]
&
&
SIG
CBx.Ia<0.06In
BI
[CBx.52b_PhB]
SIG
CBx.Ib<0.06In
BI
[CBx.52b_PhC]
SIG
CBx.Ic<0.06In
&
62PD.St
[62PD.t_Op]
&
0ms
62PD.Op
&
>=1
&
Figure 3.24-1 Logic diagram of pole discrepancy protection
Where:
CBx.52b_PhA, CBx.52b_PhB and CBx.52b_PhC: Please refer to section 3.4.
3.24.6 Settings
Table 3.24-2 Settings of pole discrepancy protection
No.
Name
Range
Step
Unit
1
CBx.62PD.3I0_Set
(0.050~30.000 )×In
0.001
A
2
CBx.62PD.I2_Set
(0.050~30.000 )×In
0.001
A
3
CBx.62PD.t_Op
0.000~600.000
0.001
s
4
CBx.62PD.En
0 or 1
Remark
Current setting of residual
current
criterion
for
pole
discrepancy protection
Current
setting
of
negative-sequence
current
criterion for pole discrepancy
protection
Time delay of pole discrepancy
protection
Enabling/disabling
pole
discrepancy protection
0: disable
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No.
5
Name
CBx.62PD.En_3I0/I2_Ctrl
Range
Step
Unit
Remark
1: enable
Enabling/disabling
residual
current
criterion
and
negative-sequence
current
criterion for pole discrepancy
protection
0: disable
1: enable
0 or 1
3.25 Broken Conductor Protection
3.25.1 General Application
Single-phase earthing fault and two-phases earthing fault are the most common fault on circuits,
the fault is easy to detect because the fault current will increase obviously.
Broken-conductor fault is difficult to detect since there is no increase of current but
negative-sequence current, so negative-sequence overcurrent protection can be considered to
clear broken-conductor fault. However, under heavy load condition, negative-sequence current is
relative large due to unbalance loading, but negative-sequence current because of
broken-conductor fault under light load condition is relative small. If negative-sequence current
protection is set larger than maximum negative-sequence current under loading, the protection
may be failure to operate if broken-conductor fault happens under light load condition,
negative-sequence overcurrent protection is therefore not suitable to apply for broken-conductor
fault.
The network of single-phase broken condition is similar to that of two-phases earthing fault,
positive-sequence, negative-sequence and zero-sequence network is connected in parallel, I2/I1=
Z0/(Z0+Z2), generally, zero-sequence impedance is larger than positive-sequence impedance, i.e.
I2/I1>0.5. The network of two-phases broken condition is similar to that of single-phase earthing
fault, positive-sequence, negative-sequence and zero-sequence network is connected in series,
so I2/I1=1.
3.25.2 Function Description
Broken-conductor fault mainly is single-phase broken or two-phases broken. According to the ratio
of negative-sequence current to positive-sequence current (I2/I1), it is used to judge whether there
is an broken-conductor fault. Negative-sequence current under normal operating condition (i.e.
unbalance current) is due to CT error and unbalance load, so the ratio of negative-sequence
current to positive-sequence current (amplitude) is relative steady. The value with margin can then
be used as the setting of broken conductor protection. It is mainly used to detect broken-conductor
fault and CT circuit failure as well.
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3.25.3 Function Block Diagram
46BC
46BC.En1
46BC.On
46BC.En2
46BC.St
46BC.Blk
46BC.Op
46BC.Alm
3.25.4 I/O Signals
Table 3.25-1 I/O signals of broken conductor protection
No.
Input Signal
1
46BC.En1
2
46BC.En2
3
46BC.Blk
No.
Description
Enable broken conductor protection input 1, it is triggered from binary input or
programmable logic etc.
Enable broken conductor protection input 2, it is triggered from binary input or
programmable logic etc.
Broken conductor protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
1
46BC.On
Broken-conductor protection is enabled.
2
46BC.St
Broken-conductor protection starts.
3
46BC.Op
Broken-conductor protection operates to trip.
4
46BC.Alm
Broken-conductor protection operates to alarm.
3.25.5 Logic
SIG
46BC.En1
SIG
46BC.En2
SIG
46BC.Blk
&
&
46BC.On
46BC.St
&
[46BC.t_Op] 0ms
SET Ia>[46BC.I_Min]
>=1
SET Ib>[46BC.I_Min]
SET Ic>[46BC.I_Min]
&
SET I2/I1>[46BC.I2/I1_Set]
EN
46BC.Op
[46BC.En_Trp]
&
46BC.Alm
EN
[46BC.En_Alm]
Figure 3.25-1 Logic diagram of broken conductor protection
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3.25.6 Settings
Table 3.25-2 Settings of broken conductor protection
No.
Name
Range
1
46BC.I2/I1_Set
0.20~1.00
0.001
2
46BC.t_Op
0.000~600.000
0.001
s
3
46BC.I_Min
(0.050~30.000)×In
0.001
A
4
46BC.En_Trp
0 or 1
5
46BC.En_Alm
0 or 1
Step
Unit
Remark
Ratio setting (negative-sequence
current to positive-sequence current)
of broken conductor protection
Time delay of broken conductor
protection
Minimum operation current of broken
conductor protection
Enabling/disabling broken conductor
protection to operate to trip
0: disable
1: enable
Enabling/disabling broken conductor
protection to operate to alarm
0: disable
1: enable
3.26 Reverse Power Protection
3.26.1 General Application
Due to various reasons lead to lose motivity, synchronous generator is changed to run as a motor
state, Absorbing energy from the power grid to drive a turbine (gas turbine) operation. In order to
prevent turbine blade or gas turbine gear from being damaged, reverse power protection (reversal
direction) should be configured.
3.26.2 Function Description
Reverse power protection provides two stages: stage 1 can be set as alarm purpose or tripping
purpose, and stage 2 is only for tripping purpose. When reverse power value of the generator
detected is greater than reverse power protection setting ([32R1.P_Set]), reverse power protection
can operate to alarm or trip with the time delay. After overload protection, over-excitation
protection or loss-of-excitation protection, such as abnormal operation protection operates, the
generator needs sequential tripping. The steam valve of turbine has to be closed firstly, and
sequential tripping reverse power protection blocked by position contact of steam valve and circuit
breaker operates to trip with the time delay.
Generator power is calculated by three-phase voltage and three-phase current of generator
terminal. Positive sequence component of active power is calculated by fundamental wave of the
voltage and current. The benefits is that reverse power protection is independent of the
asymmetric component, so as to truly reflect the load of the engine power system.
The level of generator absorbing the active power will depend on the need to overcome the friction
loss, according to different types of generator units, the settings of reverse power protection will be
different. During testing in the primary side of the generator unit, the active power absorbed by the
generator can be measured by the device.
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When the device is equipped with power plant side, reverse power is negative value, and reverse
power is positive value when it is equipped with substation side.
The operation criterion:
[32R.Opt_Dir]=Reverse & P<-[32Ri.P_Set]
or
[32R.Opt_Dir]=Forward & P>[32Ri.P_Set]
3.26.3 Function Block Diagram
32R
32Ri.En
P1
32Ri.Blk
32Ri.On
32Ri.St
32Ri.Op
32R1.Alm
3.26.4 I/O Signals
Table 3.26-1 I/O signals of reverse power protection
No.
Input Signal
1
32Ri.En
2
32Ri.Blk
No.
Description
Enable stage i of reverse power protection input 1, it is triggered from binary
input or programmable logic etc. (i=1, 2)
Stage i of reverse power protection blocking input, it is triggered from binary
input or programmable logic etc. (i=1, 2)
Output Signal
Description
1
P1
Positive-sequence active power
2
32Ri.On
Stage i of reverse power protection is enabled. (i=1, 2)
3
32Ri.St
Stage i of reverse power protection starts. (i=1, 2)
4
32Ri.Op
Stage i of reverse power protection operates to trip. (i=1, 2)
5
32R1.Alm
Stage 1 of reverse power protection operates to alarm. (i=1, 2)
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3.26.5 Logic
SIG 32R1.En
&
SIG 32R1.Blk
&
EN
[32R1.En_Alm]
EN
[32R1.En_Trp]
32R1.On
>=1
SIG 32R1.On
SET [32R.Opt_Dir]=Reverse
&
&
SIG P1<-[32R1.P_Set]
SET [32R.Opt_Dir]=Forward
32R1.St
>=1
&
SIG P1>[32R1.P_Set]
&
EN
[32R1.t_Alm]
0s
32R1.Alm
[32R1.t_Trp]
0s
32R1.Op
[32R1.En_Alm]
&
EN
[32R1.En_Trp]
Figure 3.26-1 Logic diagram of stage 1 of reverse power protection
SIG 32R2.En
&
&
SIG 32R2.Blk
EN
32R2.On
[32R2.En_Trp]
SIG 32R2.On
&
SET [32R.Opt_Dir]=Reverse
32R2.St
&
>=1
SIG P1<-[32R2.P_Set]
SET [32R.Opt_Dir]=Forward
&
SIG P1>[32R2.P_Set]
&
[32R2.t_Trp]
EN
0s
32R2.Op
[32R2.En_Trp]
Figure 3.26-2 Logic diagram of stage 2 of reverse power protection
When stage 2 of reverse power protection is used as sequential tripping reverse power protection,
it can be selectable to be controlled by position contact of steam valve and circuit breaker
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3.26.6 Settings
Table 3.26-2 Settings of broken conductor protection
No.
Name
Range
Step
Unit
Remark
Power setting of stage i of reverse
1
32Ri.P_Set
(0.100~50.000)×In
0.01
W
power protection (i=1, 2)
It should be greater 0.5 times the
measured value of reverse power.
2
32Ri.t_Trp
0.100~3000.000
0.01
s
3
32R1.t_Alm
0.100~3000.000
0.01
s
Time delay of stage i of reverse power
protection for tripping purpose (i=1, 2)
Time delay of stage 1 of reverse power
protection for alarm purpose
Enabling/disabling stage i of reverse
power protection to operate to trip (i=1,
4
32Ri.En_Trp
0 or 1
2)
0: disable
1: enable
Enabling/disabling stage 1 of reverse
5
32R1.En_Alm
power protection to operate to alarm
0 or 1
0: disable
1: enable
6
32R.Opt_Dir
The
Forward
directionality
direction
Reverse
or
option
reverse
(forward
direction)
of
reverse power protection
3.27 Synchrocheck
3.27.1 General Application
The purpose of synchrocheck is to ensure two systems are synchronism before they are going to
be connected.
When two asynchronous systems are connected together, due to phase difference between the
two systems, larger impact will be led to the system during closing. Thus auto-reclosing and
manual closing are applied with the synchrocheck to avoid this situation and maintain the system
stability. The synchrocheck includes synchronism check and dead charge check.
NOTICE!
For double circuit breakers mode, the device will provide independent synchrocheck
function for CB1 and CB2 respectively. Both synchrocheck functions have the same
logic. The difference is that the prefix “CBx.” is added to all signals and settings for
circuit breaker No.x (x=1 or 2).
3.27.2 Function Description
The synchronism check function is mainly to measure the electrical quantities between both sides
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of the circuit breaker and compares them with the corresponding settings. The output is only given
if all measured quantities are simultaneously within their set limits.
The dead charge check function measures the amplitude of line voltage and bus voltage between
both sides of the circuit breaker, and then compare them with the live check setting [CBx.25.U_Lv]
and the dead check setting [CBx.25.U_Dd]. The output is only given when the measured
quantities comply with the criteria.
The synchrocheck in this device can be used for auto-reclosing and manual closing for both single
circuit breaker and dual circuit breakers. When applied for single circuit breaker, the comparison
relationship between reference voltage (CBx.Uref) and synchronism voltage (CBx.Usyn) for
synchronism check is as shown in Figure 3.27-1.
CBx.Uref
CBx.Usyn
Figure 3.27-1 Relationship between reference voltage and synchronism voltage
When both line and busbar are live, the synchronism check element operates if voltage difference,
phase angle difference and frequency difference are all within their setting values.
1.
The voltage difference is checked by the following equations.
CBx.Usyn≥[CBx.25.U_Lv]
CBx.Uref≥[CBx.25.U_Lv]
[CBx.25.U_Diff]≥|CBx.Usyn-CBx.Uref|
2.
The phase difference is checked by the following equations.
CBx.Usyn×CBx.Uref×cosØ≥0
CBx.Usyn×CBx.Uref×sin([CBx.25.phi_Diff])≥CBx.Usyn×CBx.Uref×|sinØ|
Where,
Ø is phase difference between Usyn and Uref
3.
The frequency difference is checked by the following equations.
|f(CBx.Usyn)-f(CBx.Uref)|≤[CBx.25.f_Diff]
If frequency check is disabled (i.e. [CBx.25.En_fDiffChk] is set as “0”), a detected maximum slip
cycle can also be determined by the following equation based on phase difference setting and the
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synchronism check time setting:
f =[CBx.25.phi_Diff]/(180×[CBx.25.t_SynChk])
Where:
f is slip cycle
If frequency check is enabled (i.e. [CBx.25.En_fDiffChk] is set as “1”), [CBx.25.t_SynChk] can be
set to be a very small value (default value is 50ms).
This function module supports voltage switching. In general, voltage switching is fulfilled by
external circuit, and the busbar arrangement should be determined, including three options, single
busbar arrangement, double busbars arrangement and 1½ breakers arrangement, if using this
module to fulfill voltage switching.
Analog input defines four voltage inputs, UL1, UB1, UL2, UB2, and their usage are as follow:
UL1: it connects with three-phase protection voltages (from line or busbar), which mainly are used
by distance protection, voltage protection and so on.
UB1: it connects with single synchronism voltage (from line or busbar).
UL2: it connects with single synchronism voltage (from the other line of the same diameter in 1½
breakers arrangement). When voltage switching is available, it is only used by 1½ breakers
arrangement.
UB2: it connects with single synchronism voltage (from busbar). When voltage switching is
available, it is only used by double busbars arrangement and 1½ breakers arrangement.
The reference voltage (Uref) is determined to use phase voltage or phase-to-phase voltage (UL1)
from three-phase protection voltages and by the setting [CBx.25.Opt_Source_UL1].
The synchronism voltage (Usyn) always connects with UB1 if not adopting voltage switching. It
connects with one of UB1, UL2 and UB2 according to the result of voltage switching if adopting
voltage switching.
3.27.2.1 Single Busbar Arrangement
Voltage selection function is not required for this busbar arrangement, the connection of the
voltage signals and respective VT MCB auxiliary contacts to the device is shown in the Figure
3.27-2 and Figure 3.27-3.
1.
Three-phase bus voltage used for protection ([VTS.En_LineVT]=0)
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Bus
Ua
UL1
CB
Ub
Uc
25.MCB_VT_UL1
UB1
25.MCB_VT_UB1
Line
Figure 3.27-2 Voltage connection for single busbar arrangement
2.
Three-phase line voltage used for protection ([VTS.En_LineVT]=1)
Bus
CB
UB1
25.MCB_VT_UB1
Ua
UL1
Ub
Uc
25.MCB_VT_UL1
Line
Figure 3.27-3 Voltage connection for single busbar arrangement
In the figures, the setting [VTS.En_LineVT] is used to determine protection voltage signals (Ua, Ub,
Uc) from line VT or bus VT according to the condition.
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3.27.2.2 Double Busbars Arrangement
Bus2
Bus1
B1D B2D
UB1
25.MCB_VT_UB1
UB2
25.MCB_VT_UB2
25.NC_UB1DS
25.NO_UB1DS
CB
25.NC_UB2DS
25.NO_UB2DS
Ua
UL1
Ub
Line
Uc
25.MCB_VT_UL1
Figure 3.27-4 Voltage connection for double busbars arrangement
For double busbars arrangement, selection of appropriate voltage signals from Bus 1 and Bus 2
for synchronizing are required. Line VT signal is taken as reference to check synchronizing with
the voltage after voltage selection function. Selection approach is as follows.
For the disconnector positions, the normally open (NO) and normally closed (NC) contacts of the
disconnector for bus 1 and bus 2 are required to determine the disconnector open and closed
positions. The voltage selection logic is as follows.
BI
25.NO_UB1DS
&
CBx.UB1_Sel
BI
25.NC_UB1DS
BI
25.NO_UB2DS
BI
25.NC_UB2DS
&
CBx.UB2_Sel
&
CBx.Alm_Invalid_Sel
UB1
CBx.Usyn
UB2
Figure 3.27-5 Voltage selection for double busbars arrangement
After acquiring the disconnector open and closed positions of double busbars, use the following
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logic to acquire the feeder voltage of double busbars.
DS2 CLOSED
DS2 OPEN
DS1 CLOSED
Keep original value
Voltage from Bus 1 VT (CBx.UB1_Sel=1)
DS1 OPEN
Voltage from Bus 2 VT (CBx.UB2_Sel=1)
Keep original value
DS1 is disconnector of Bus 1
DS2 is disconnector of Bus 2
If voltage selection is invalid (CBx.Alm_Invalid_Sel=1), keep original selection and without
switchover.
3.27.2.3 One and A Half Breakers Arrangement
For one and a half breakers arrangement, selection of appropriate voltage signals among Line1
VT, Line2 VT and Bus 2 VT as reference voltage to check synchronizing with Bus 1 voltage signal
for closing breaker at Bus 1 side.
Bus1
UB1
25.MCB_VT_UB1
25.NC_UB1DS
B1D
25.NO_UB1DS
Ua
UL1
Line 1
Ub
Uc
25.MCB_VT_UL1
L1D
25.NC_UL1DS
25.NO_UL1DS
Line 2
UL2
25.MCB_VT_UL2
25.NC_UL2DS
25.NO_UL2DS
L2D
25.NC_UB2DS
25.NO_UB2DS
UB2
25.MCB_VT_UB2
B2D
Bus2
Figure 3.27-6 Voltage connection for one and a half breakers arrangement
For the circuit breaker at bus side (take bus breaker of bus 1 as an example), the device acquires
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the disconnector open and closed positions of two feeders and bus 2. The voltage selection logic
is as follows.
BI
25.NO_UL1DS
&
CBx.UL1_Sel
BI
25.NC_UL1DS
BI
25.NO_UL2DS
BI
25.NC_UL2DS
BI
25.NO_UB2DS
BI
25.NC_UB2DS
&
CBx.UL2_Sel
&
&
CBx.UB2_Sel
&
&
CBx.Alm_Invalid_Sel
UL1
CBx.Uref
UL2
UB2
UB1
CBx.Usyn
Figure 3.27-7 Voltage selection for one and a half breakers arrangement
For the tie breaker, the device acquires the disconnector open and closed positions of two feeders
and two busbars. Either Line 1 VT or Bus 1 VT signal is selected as reference voltage to check
synchronizing with the selected voltage between Line 2 VT and Bus 2 VT. The voltage selection
logic is as follows.
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BI
25.NO_UL1DS
&
CBx.UL1_Sel
BI
25.NC_UL1DS
BI
25.NO_UB1DS
BI
25.NC_UB1DS
&
CBx.UB1_Sel
&
&
UL1
CBx.Uref
UB1
BI
25.NO_UL2DS
BI
25.NC_UL2DS
BI
25.NO_UB2DS
BI
25.NC_UB2DS
&
CBx.UL2_Sel
&
CBx.UB2_Sel
&
>=1
&
UL2
CBx.Alm_Invalid_Sel
CBx.Usyn
UB2
Figure 3.27-8 Voltage selection for one and a half breakers arrangement
When the voltage selection fails (including VT circuit failure and MCB failure), the device will issue
the corresponding failure signal. If the voltage selection is invalid (CBx.Alm_Invalid_Sel=1), keep
original selection and without switchover.
In order to simplify description, one of the two voltages used in the synchrocheck (synchronism check
and dead charge check) which obtained after voltage selection function is regarded as line voltage,
and another is bus voltage.
3.27.2.4 Synchronism Voltage Circuit Failure Supervision
If synchronism voltage and reference voltage are used for auto-reclosing with synchronism or
dead line or busbar check, the VT circuit of synchronism voltage and reference voltage are
monitored.
Under normal conditions, the circuit breaker is in closed position but the synchronism voltage is
lower than the setting [CBx.25.U_Lv], it means that synchronism voltage circuit fails and an alarm
[CBx.25.Alm_VTS_Usyn] or [CBx.25.Alm_VTS_Uref] will be issued with a time delay [VTS.t_DPU].
If MCB of synchronism voltage or reference voltage is open, an alarm [CBx.25.Alm_VTS_Usyn] or
[CBx.25.Alm_VTS_Uref] will be issued instantaneously. After synchronism voltage reverted to
normal condition, the alarm will be reset automatically with a time delay [VTS.t_DDO]. When
synchronism voltage circuit failure is detected, dead check in auto-reclosing logic will be disabled.
If the logic setting [CBx.25.En_NoChk] is set as “1”, synchronism voltage circuit failure supervision
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will be disabled.
&
SIG FD.Pkp
>=1
SIG CBx.79.Inprog
>=1
SIG CBx.52b_PhA
>=1
&
SIG CBx.52b_PhB
SIG CBx.52b_PhC
If the signal [FD.Pkp] or [CBx.79.Inprog] operates,
the circuit of time delay will be interrupted.
SIG CBx.Uref<[CBx.25.U_Lv]
[VTS.t_DPU] [VTS.t_DDO]
>=1
>=1
CBx.25.Alm_VTS_Uref
&
BI
25.MCB_VT_Uref
SIG CBx.25.On_NoChk
&
SIG CBx.25.On_SynChk
>=1
SIG CBx.25.On_DdL_DdB
>=1
SIG CBx.25.On_DdL_LvB
&
SIG CBx.25.On_LvL_DdB
SIG CBx.25.Blk_VTS_UL
Figure 3.27-9 Reference voltage circuit failure supervision logic
&
SIG FD.Pkp
>=1
SIG CBx.79.Inprog
>=1
SIG CBx.52b_PhA
>=1
&
SIG CBx.52b_PhB
If the signal [FD.Pkp] or [CBx.79.Inprog] operates,
the circuit of time delay will be interrupted.
SIG CBx.52b_PhC
[VTS.t_DPU] [VTS.t_DDO]
SIG CBx.Usyn<[CBx.25.U_Lv]
>=1
>=1
&
CBx.25.Alm_VTS_Usyn
BI 25.MCB_VT_Usyn
SIG CBx.25.On_NoChk
&
SIG CBx.25.On_SynChk
SIG CBx.25.On_DdL_DdB
>=1
>=1
SIG CBx.25.On_DdL_LvB
&
SIG CBx.25.On_LvL_DdB
SIG CBx.25.Blk_VTS_UL
Figure 3.27-10 Synchronism voltage circuit failure supervision logic
As shown in Figure 3.27-9 and Figure 3.27-10, 25.MCB_VT_Uref is MCB signal corresponding to
reference voltage after switching and 25.MCB_VT_Usyn is MCB signal corresponding to
synchronism voltage after switching.
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3.27.3 Function Block Diagram
25
CBx.25.Blk_Chk
CBx.UL1_Sel
CBx.25.Blk_SynChk
CBx.UL2_Sel
CBx.25.Blk_DdChk
CBx.UB1_Sel
CBx.25.Start_Chk
CBx.UB2_Sel
CBx.25.Start_3PLvChk
CBx.25.Sel_SynChk
CBx.Alm_Invalid_Sel
CBx.25.Ok_fDiffChk
CBx.25.Sel_DdL_DdB
CBx.25.Ok_UDiffChk
CBx.25.Sel_DdL_LvB
CBx.25.Ok_phiDiffChk
CBx.25.Sel_LvL_DdB
CBx.25.Ok_DdL_DdB
CBx.25.Sel_NoChk
CBx.25.Ok_DdL_LvB
CBx.25.Blk_VTS_Uref
CBx.25.Ok_LvL_DdB
CBx.25.Blk_VTS_Usyn
CBx.25.Chk_LvL
25.MCB_VT_UL1
CBx.25.Chk_DdL
25.MCB_VT_UL2
CBx.25.Chk_LvB
25.MCB_VT_UB1
CBx.25.Chk_DdB
25.MCB_VT_UB2
CBx.25.Ok_DdChk
25.NC_UL1DS
CBx.25.Ok_SynChk
25.NO_UL1DS
CBx.25.Ok_Chk
25.NC_UB1DS
CBx.25.Ok_3PLvChk
25.NO_UB1DS
CBx.25.Alm_VTS_Uref
25.NC_UL2DS
CBx.25.Alm_VTS_Usyn
25.NO_UL2DS
CBx.25.f_Ref
25.NC_UB2DS
CBx.25.f_Syn
25.NO_UB2DS
CBx.25.U_Diff
CBx.25.f_Diff
CBx.25.Phi_Diff
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3.27.4 I/O Signals
Table 3.27-1 I/O signals of synchrocheck
No.
Input Signal
Description
1
CBx.25.Blk_Chk
2
CBx.25.Blk_SynChk
3
CBx.25.Blk_DdChk
4
CBx.25.Start_Chk
5
CBx.25.Start_3PLvChk
6
CBx.25.Sel_SynChk
Synchronism check is selected.
7
CBx.25.Sel_DdL_DdB
Dead line and dead bus check is selected.
8
CBx.25.Sel_DdL_LvB
Dead line and live bus check is selected.
9
CBx.25.Sel_LvL_DdB
Live line and live bus check is selected.
10
CBx.25.Sel_NoChk
No check is selected.
11
CBx.25.Blk_VTS_Usyn
VT circuit supervision (Usyn) is blocked
12
CBx.25.Blk_VTS_Uref
VT circuit supervision (Uref) is blocked
13
25.MCB_VT_UL1
Binary input for VT MCB auxiliary contact (UL1)
14
25.MCB_VT_UL2
Binary input for VT MCB auxiliary contact (UL2)
15
25.MCB_VT_UB1
Binary input for VT MCB auxiliary contact (UB1)
16
25.MCB_VT_UB2
Binary input for VT MCB auxiliary contact (UB2)
17
25.NC_UL1DS
Normally closed contact of disconnector (UL1)
18
25.NO_UL1DS
Normally open contact of disconnector (UL1)
19
25.NC_UB1DS
Normally closed contact of disconnector (UB1)
20
25.NO_UB1DS
Normally open contact of disconnector (UB1)
21
25.NC_UL2DS
Normally closed contact of disconnector (UL2)
22
25.NO_UL2DS
Normally open contact of disconnector (UL2)
23
25.NC_UB2DS
Normally closed contact of disconnector (UB2)
24
25.NO_UB2DS
Normally open contact of disconnector (UB2)
No.
Input signal of blocking synchrocheck function for AR.
Input signal of blocking synchronism check for AR. If the value is “1”, the
output of synchronism check is “0”.
Input signal of blocking dead charge check for AR.
Input signal of starting synchronism check, usually it was starting signal of
AR from auto-reclosing module.
Input signal of starting live three-phase check, usually it was starting signal
of 1-pole AR
Output Signal
Description
1
CBx.UL1_Sel
To select voltage of Line 1
2
CBx.UL2_Sel
To select voltage of Line 2
3
CBx.UB1_Sel
To select voltage of Bus 1
4
CBx.UB2_Sel
To select voltage of Bus 2
5
CBx.Alm_Invalid_Sel
Voltage selection is invalid.
6
CBx.25.Ok_fDiffChk
7
CBx.25.Ok_UDiffChk
8
CBx.25.Ok_phiDiffChk
To indicate that frequency difference condition for synchronism check of AR
is met, frequency difference between UB and UL is smaller than [25.f_Diff].
To indicate that voltage difference condition for synchronism check of AR is
met, voltage difference between UB and UL is smaller than [25.U_Diff]
To indicate phase difference condition for synchronism check of AR is met,
phase difference between UB and UL is smaller than [25.phi_Diff].
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9
CBx.25.Ok_DdL_DdB
Dead line and dead bus condition is met
10
CBx.25.Ok_DdL_LvB
Dead line and live bus condition is met
11
CBx.25.Ok_LvL_DdB
Live line and dead bus condition is met
12
CBx.25.Chk_LvL
Line voltage is greater than the voltage setting [25.U_Lv]
13
CBx.25.Chk_DdL
Line voltage is smaller than the voltage setting [25.U_Dd]
14
CBx.25.Chk_LvB
Bus voltage is greater than the voltage setting [25.U_Lv]
15
CBx.25.Chk_DdB
Bus voltage is smaller than the voltage setting [25.U_Dd]
16
CBx.25.Ok_DdChk
To indicate that dead charge check condition of AR is met
17
CBx.25.Ok_SynChk
To indicate that synchronism check condition of AR is met
18
CBx.25.Ok_Chk
To indicate that synchrocheck condition of AR is met
19
CBx.25.Ok_3PLvChk
To indicate that live three-phase check condition is met
20
CBx.25.Alm_VTS_Uref
Reference voltage circuit is abnormal
21
CBx.25.Alm_VTS_Usyn
Synchronism voltage circuit is abnormal
22
CBx.25.f_Ref
Frequency of the voltage used by protection calculation
23
CBx.25.f_Syn
Frequency of the voltage used by synchrocheck
24
CBx.25.U_Diff
Voltage difference for synchronism check
25
CBx.25.f_Diff
Frequency difference for synchronism check
26
CBx.25.phi_Diff
Phase difference for synchronism check
3.27.5 Logic
3.27.5.1 Synchronism Check Logic
The frequency difference, voltage difference, and phase difference of voltages from both sides of
the circuit breaker are calculated in the device, they are used as input conditions of the
synchronism check. When the synchronism check function is enabled and the voltages of both
ends meets the requirements of the voltage difference, phase difference, and frequency difference,
and there is no synchronism check blocking signal, it is regarded that the synchronism check
conditions are met.
Synchronism check logic is usually used for 3-pole AR, and 1-pole AR usually adopts no check
logic. However, the circuit breaker at local end can not reclosed unless the circuit breaker at
remote end is reclosed successfully. In order to meet this requirement, live three-phase check can
be used for 1-pole AR, determined by the setting [CBx.25.En_3PLvChk], ensure that three-phase
voltages is restored to normal at local end after the circuit breaker at remote end is reclosed.
Synchrocheck mode can be determined by the setting [CBx.25.SetOpt] or external signal. As
shown in Figure 3.27-11, when the setting [CBx.25.SetOpt] is set as “1”, synchrocheck mode is
determined by the setting. Otherwise, synchrocheck mode is determined by external signal.
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1
EN
[CBx.25.En_SynChk]
SIG
CBx.25.Sel_SynChk
EN
[CBx.25.SetOpt]
EN
[CBx.25.En_DdL_DdB]
SIG
CBx.25.Sel_SynChk
EN
[CBx.25.SetOpt]
EN
[CBx.25.En_LvL_DdB]
SIG
CBx.25.Sel_LvL_DdB
EN
[CBx.25.SetOpt]
EN
[CBx.25.En_DdL_LvB]
CBx.25.On_SynChk
0
1
CBx.25.On_DdL_DdB
0
1
CBx.25.On_LvL_DdB
0
1
CBx.25.On_DdL_LvB
SIG
CBx.25.Sel_DdL_LvB
EN
[CBx.25.SetOpt]
EN
[CBx.25.En_NoChk]
SIG
CBx.25.Sel_NoChk
EN
[CBx.25.SetOpt]
0
1
CBx.25.On_NoChk
0
Figure 3.27-11 Synchrocheck mode selection
EN
[CBx.25.En_3PLvChk]
SIG CBx.Uref.a>[CBx.25.U_Lv]
>=1
&
SIG CBx.Uref.b>[CBx.25.U_Lv]
SIG CBx.Uref.c>[CBx.25.U_Lv]
&
200ms
SIG CBx.25.Start_3PLvChk
SIG CBx.25.Blk_Chk
0ms
CBx.25.Ok_3PLvChk
>=1
&
SIG CBx.25.Blk_SynChk
&
SIG CBx.25.On_SynChk
SIG CBx.25.Start_Chk
SIG CBx.Usyn>[CBx.25.U_Lv]
SIG CBx.Uref>[CBx.25.U_Lv]
&
&
50ms
0ms
&
[CBx.25.t_SynChk]
0ms
CBx.25.Ok_SynChk
SIG CBx.25.Ok_UdiffChk
SIG CBx.25.Ok_phiDiffChk
SIG CBx.25.Ok_fDiffChk
Figure 3.27-12 Synchronism check
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3.27.5.2 Dead Charge Check Logic
The dead charge check conditions have three types, namely, live-bus and dead-line check,
dead-bus and live-line check and dead-bus and dead-line check. The above three modes can be
enabled and disabled by the corresponding logic settings. The device can calculate the measured
bus voltage and line voltage at both sides of the circuit breaker and compare them with the
settings [CBx.25.U_Lv] and [CBx.25.U_Dd]. When the voltage is higher than [CBx.25.U_Lv], the
bus/line is regarded as live. When the voltage is lower than [CBx.25.U_Dd], the bus/line is
regarded as dead.
SIG
CBx.25.Blk_Chk
SIG
CBx.25.Blk_DdChk
SIG
CBx.25.Start_Chk
SIG
CBx.25.On_DdL_DdB
SIG
CBx.Uref<[CBx.25.U_Dd]
SIG
CBx.Usyn<[CBx.25.U_Dd]
SIG
CBx.25.On_DdL_LvB
SIG
CBx.Uref<[CBx.25.U_Dd]
SIG
CBx.Usyn>[CBx.25.U_Lv]
SIG
CBx.25.On_LvL_DdB
SIG
CBx.Uref>[CBx.25.U_Lv]
SIG
CBx.Usyn<[CBx.25.U_Dd]
SIG
CBx.25.Alm_VTS_Usyn
SIG
CBx.25.Alm_VTS_Uref
>=1
&
>=1
&
[CBx.25.t_DdChk]
0
CBx.25.Ok_DdChk
&
CBx.25.Ok_DdL_DdB
&
&
CBx.25.Ok_DdL_LvB
&
&
CBx.25.Ok_LvL_DdB
&
>=1
Figure 3.27-13 Dead charge check logic
3.27.5.3 Synchrocheck Logic
SIG
CBx.25.Ok_SynChk
SIG
CBx.25.On_NoChk
SIG
CBx.25.Ok_DdChk
>=1
CBx.25.Ok_Chk
Figure 3.27-14 Synchrocheck logic
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3.27.6 Settings
Table 3.27-2 Synchrocheck settings
No.
Name
Range
Step
Ua: A-phase voltage
Ub
CBx.25.Opt_Source_UL1
Ub: B-phase voltage
Uc
Uc: C-phase voltage
Uab
Uab: AB-phase voltage
Ubc
Ubc: BC-phase voltage
Uca
Uca: CA-phase voltage
Voltage selecting mode of bus 1.
Ua
Ua: A-phase voltage
Ub
2
CBx.25.Opt_Source_UB1
Ub: B-phase voltage
Uc
Uc: C-phase voltage
Uab
Uab: AB-phase voltage
Ubc
Ubc: BC-phase voltage
Uca
Uca: CA-phase voltage
Voltage selecting mode of line 2.
Ua
Ua: A-phase voltage
Ub
3
CBx.25.Opt_Source_UL2
Ub: B-phase voltage
Uc
Uc: C-phase voltage
Uab
Uab: AB-phase voltage
Ubc
Ubc: BC-phase voltage
Uca
Uca: CA-phase voltage
Voltage selecting mode of bus 2.
Ua
Ua: A-phase voltage
Ub
4
CBx.25.Opt_Source_UB2
Remark
Voltage selecting mode of line 1.
Ua
1
Unit
Ub: B-phase voltage
Uc
Uc: C-phase voltage
Uab
Uab: AB-phase voltage
Ubc
Ubc: BC-phase voltage
Uca
Uca: CA-phase voltage
Option
of
circuit
breaker
configuration, and it should be
set as “NoVoltSel” if no voltage
selection is adopted.
NoVoltSel
DblBusOneCB
5
CBx.CBConfigMode
DblBusOneCB:
one
circuit
breaker for double busbar
3/2BusCB
3/2BusCB:
3/2TieCB
bus
side
circuit
breaker for one and a half
breakers
3/2TieCB:
line
side
circuit
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No.
Name
Range
Step
Unit
Remark
breaker for one and a half
breakers
6
CBx.25.U_Dd
0.05Un~0.8Un
0.001
V
Voltage threshold of dead check
7
CBx.25.U_Lv
0.5Un~Un
0.001
V
Voltage threshold of live check
8
CBx.25.K_Usyn
0.20-5.00
9
CBx.25.phi_Diff
0~ 89
1
deg
10
CBx.25.phi_Comp
0~359
1
deg
Compensation
coefficient
for
synchronism voltage
Phase
difference
limit
of
synchronism check for AR
Compensation
difference
for
phase
between
two
synchronism voltages
11
CBx.25.f_Diff
0.02~1.00
0.01
Hz
12
CBx.25.U_Diff
0.02Un~0.8Un
V
13
CBx.25.t_DdChk
0.010~25.000
s
14
CBx.25.t_SynChk
0.010~25.000
s
Frequency difference limit of
synchronism check for AR
Voltage
difference
CBx.25.En_fDiffChk
of
synchronism check for AR
Time delay to confirm dead
check condition
Time
delay
to
confirm
synchronism check condition
Enabling/disabling
15
limit
frequency
difference check
0 or 1
0: disable
1: enable
Synchrocheck mode selection
16
CBx.25.SetOpt
0, 1
1
0: determined by external signal
1: determined by the setting
Enabling/disabling synchronism
17
CBx.25.En_SynChk
check
0 or 1
0: disable
1: enable
Enabling/disabling dead line and
18
CBx.25.En_DdL_DdB
dead bus (DLDB) check
0 or 1
0: disable
1: enable
Enabling/disabling dead line and
19
CBx.25.En_DdL_LvB
live bus (DLLB) check
0 or 1
0: disable
1: enable
Enabling/disabling live line and
20
CBx.25.En_LvL_DdB
dead bus (LLDB) check
0 or 1
0: disable
1: enable
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No.
Name
Range
Step
Unit
Remark
Enabling/disabling AR without
21
CBx.25.En_NoChk
any check
0 or 1
0: disable
1: enable
Enabling/disabling
22
CBx.25.En_3PLvChk
live
three-phase check of line
0 or 1
0: disable
1: enable
3.28 Automatic Reclosure
3.28.1 General Application
To maintain the integrity of the overall electrical transmission system, the device is installed on the
transmission system to isolate faulted segments during system disturbances. Faults caused by
lightning, wind, or tree branches could be transient in nature and may disappear once the circuit is
de-energized. According to statistics, for overhead transmission line, 80%~90% of the faults on
overhead lines are the transient faults. Auto-reclosing systems are installed to restore the faulted
section of the transmission system once the fault is extinguished (providing it is a transient fault).
For certain transmission systems, auto-reclosure is used to improve system stability by restoring
critical transmission paths as soon as possible.
Besides overhead lines, other equipment failure, such as cables, busbar, transformer fault and so
on, are generally permanent fault, and auto-reclosing is not initiated after faulty feeder is tripped.
For some mixed circuits, such as overhead line with a transformer unit, hybrid transmission lines,
etc., it is required to ensure that auto-reclosing is only initiated for faults overhead line section, or
make a choice according to the situation.
NOTICE!
For double circuit breakers mode, the device will provide independent automatic
reclosure function for CB1 and CB2 respectively. Both automatic reclosure functions
have the same logic. The difference is that the prefix “CBx.” is added to all signals and
settings for circuit breaker No.x (x=1 or 2).
3.28.2 Function Description
This auto-reclosing logic can be used with either integrated device or external device. When the
auto-reclosure is used with integrated device, the internal protection logic can initiate AR,
moreover, a tripping contact from external device can be connected to the device via opto-coupler
input to initiate integrated AR function.
When external auto-reclosure is used, the device can output some configurable output to initiate
external AR, such as, contact of initiating AR, phase-segregated tripping contact, single-phase
tripping contact, three-phase tripping contact and contact of blocking AR. According to
requirement, these contacts can be selectively connected to external auto-reclosure device to
initiate AR.
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For phase-segregated circuit breaker, AR mode can be 1-pole AR for single-phase fault and
3-pole AR for multi-phase fault, or always 3-pole AR for any kinds of fault according to system
requirement. For persistent fault or multi-shot AR number preset value is reached, the device will
send final tripping command. The device will provide appropriate tripping command based on
faulty phase selection if adopting 1-pole AR.
AR can be enabled or disabled by logic setting or external signal via binary input. When AR is
enabled, the device will output contact [CBx.79.On], otherwise, output contact [CBx.79.Off]. After
some reclosing conditions, such as, CB position, CB pressure and so on, is satisfied, the device
will output contact [CBx.79.Ready].
According to requirement, the device can be set as one-shot or multi-shot AR. When adopting
multi-shot AR, the AR mode of first time reclosing can be set as 1-pole AR, 3-pole AR or 1/3-pole
AR. The rest AR mode is only 3-pole AR and its number is determined by the maximum 3-pole
reclosing number.
For one-shot AR or first reclosing of multi-shot AR, AR mode can be selected by logic setting
[CBx.79.En_1PAR], [CBx.79.En_3PAR] and [CBx.79.En_1P/3PAR] or external signal via binary
inputs. When 3-pole or 1/3-pole AR mode is selected, the following three types of check modes
can be selected: dead charge check, synchronism check and no check.
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3.28.3 Function Block Diagram
79
CBx.79.En
CBx.79.On
CBx.79.Blk
CBx.79.Off
CBx.79.Sel_1PAR
CBx.79.Close
CBx.79.Sel_3PAR
CBx.79.Ready
CBx.79.Sel_1P/3PAR
CBx.79.AR_Blkd
CBx.79.Trp
CBx.79.Active
CBx.79.Trp3P
CBx.79.Inprog
CBx.79.TrpA
CBx.79.Inprog_1P
CBx.79.TrpB
CBx.79.Inprog_3P
CBx.79.TrpC
CBx.79.Inprog_3PS1
CBx.79.LockOut
CBx.79.Inprog_3PS2
CBx.79.PLC_Lost
CBx.79.Inprog_3PS3
CBx.79.WaitMaster
CBx.79.Inprog_3PS4
CBx.79.CB_Healthy
CBx.79.WaitToSlave
CBx.79.Clr_Counter
CBx.79.Perm_Trp1P
CBx.79.Ok_Chk
CBx.79.Perm_Trp3P
CBx.79.Ok_3PLvChk
CBx.79.Rcls_Status
CBx.79.Fail_Rcls
CBx.79.Succ_Rcls
CBx.79.Fail_Chk
CBx.79.Mode_1PAR
CBx.79.Mode_3PAR
CBx.79.Mode_1/3PAR
3.28.4 I/O Signals
Table 3.28-1 I/O signals of auto-reclosing
No.
Input Signal
1
CBx.79.En
2
CBx.79.Blk
Description
Binary input for enabling AR. If the logic setting [79.En_ExtCtrl]=1,
enabling AR will be controlled by the external signal via binary input
Binary input for disabling AR. If the logic setting [79.En_ExtCtrl]=1,
disabling AR will be controlled by the external input
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Input signal for selecting 1-pole AR mode of corresponding circuit
3
CBx.79.Sel_1PAR
4
CBx.79.Sel_3PAR
5
CBx.79.Sel_1P/3PAR
6
CBx.79.Trp
Input signal of single-phase tripping from line protection to initiate AR
7
CBx.79.Trp3P
Input signal of three-phase tripping from line protection to initiate AR
8
CBx.79.TrpA
Input signal of A-phase tripping from line protection to initiate AR
9
CBx.79.TrpB
Input signal of B-phase tripping from line protection to initiate AR
10
CBx.79.TrpC
Input signal of C-phase tripping from line protection to initiate AR
breaker
Input signal for selecting 3-pole AR mode of corresponding circuit
breaker
Input signal for selecting 1/3-pole AR mode of corresponding circuit
breaker
Input signal of blocking reclosing, usually it is connected with the
11
CBx.79.LockOut
operating signals of definite-time protection, transformer protection
and busbar differential protection, etc.
12
CBx.79.PLC_Lost
13
CBx.79.WaitMaster
14
CBx.79.CB_Healthy
15
CBx.79.Clr_Counter
Clear the reclosing counter
16
CBx.79.Ok_Chk
Synchrocheck condition of AR is met
17
CBx.79.Ok_3PLvChk
Live three-phase check condition of AR is met
No.
Input signal of indicating the alarm signal that signal channel is lost
Input signal of waiting for reclosing permissive signal from master
AR (when reclosing multiple circuit breakers)
The input for indicating whether circuit breaker has enough energy to
perform the close function
Output Signal
Description
1
CBx.79.On
Automatic reclosure is enabled
2
CBx.79.Off
Automatic reclosure is disabled
3
CBx.79.Close
Output of auto-reclosing signal
4
CBx.79.Ready
Automatic reclosure have been ready for reclosing cycle
5
CBx.79.AR_Blkd
Automatic reclosure is blocked
6
CBx.79.Active
Automatic reclosing logic is actived
7
CBx.79.Inprog
Automatic reclosing cycle is in progress
8
CBx.79.Inprog_1P
The first 1-pole AR cycle is in progress
9
CBx.79.Inprog_3P
3-pole AR cycle is in progress
10
CBx.79.Inprog_3PS1
First 3-pole AR cycle is in progress
11
CBx.79.Inprog_3PS2
Second 3-pole AR cycle is in progress
12
CBx.79.Inprog_3PS3
Third 3-pole AR cycle is in progress
13
CBx.79.Inprog_3PS4
Fourth 3-pole AR cycle is in progress
14
CBx.79.WaitToSlave
15
CBx.79.Perm_Trp1P
16
CBx.79.Perm_Trp3P
17
CBx.79.Rcls_Status
Waiting signal of automatic reclosing which will be sent to slave
(when reclosing multiple circuit breakers)
Single-phase circuit breaker will be tripped once protection device
operates
Three-phase circuit breaker will be tripped once protection device
operates
Automatic reclosure status
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0: AR is ready.
1: AR is in progress.
2: AR is successful.
18
CBx.79.Fail_Rcls
Auto-reclosing fails
19
CBx.79.Succ_Rcls
Auto-reclosing is successful
20
CBx.79.Fail_Chk
Synchrocheck for AR fails
21
CBx.79.Mode_1PAR
Output of 1-pole AR mode
22
CBx.79.Mode_3PAR
Output of 3-pole AR mode
23
CBx.79.Mode_1/3PAR
Output of 1/3-pole AR mode
Automatic reclosure counter
24
CBx.79.N_Total_Rcls
Recorded number of all reclosing attempts
25
CBx.79.N_1PS1
Recorded number of first 1-pole reclosing attempts
26
CBx.79.N_3PS1
Recorded number of first 3-pole reclosing attempts
27
CBx.79.N_3PS2
Recorded number of second 3-pole reclosing attempts
28
CBx.79.N_3PS3
Recorded number of third 3-pole reclosing attempts
29
CBx.79.N_3PS4
Recorded number of fourth 3-pole reclosing attempts
3.28.5 Logic
3.28.5.1 AR Ready
For the first reclosing of multi-shot AR, AR mode can be 1-pole AR or 3-pole AR, however, the
selection is valid only to the first reclosing, after that it can only be 3-pole AR. When logic setting
[CBx.79.SetOpt] is set as “1”, AR mode is determined by logic settings. When logic setting
[CBx.79.SetOpt] is set as “0”, AR mode is determined by external signal via binary inputs.
An auto-reclosure must be ready to operate before performing reclosing. The output signal
[CBx.79.Ready] means that the auto-reclosure can perform at least one time of reclosing function,
i.e., breaker open-close-open.
When the device is energized or after the settings are modified, AR can not be ready unless the
following conditions are met:
1.
AR function is enabled.
2.
The circuit breaker is ready, such as, normal storage energy and no low pressure signal.
3.
The duration of the circuit breaker in closed position before fault occurrence is not less than
the setting [CBx.79.t_CBClsd].
4.
There is no block signal of auto-reclosing.
After the auto-reclosure operates, the auto-reclosure must reset, i.e., [CBx.79.Active]=0, in
addition to the above conditions for reclosing again.
When there is a fault on an overhead line, the concerned circuit breakers will be tripped normally.
After fault is cleared, the tripping command will drop off immediately. In case the circuit breaker is
in failure, etc., and the tripping signal of the circuit breaker maintains and in excess of the time
delay [CBx.79.t_PersistTrp], AR will be blocked, as shown in Figure 3.28-1.
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SIG
Any tripping signal
SIG
CBx.79.LockOut
SIG
1-pole AR Initiation
SIG
Any tripping signal
EN
[CBx.79.En_PDF_Blk]
SIG
CBx.79.Sel_1PAR
EN
[CBx.79.N_Rcls]=1
SIG
Three phase trip
SIG
Phase A open
SIG
Phase B open
[CBx.79.t_PersistTrp]
0ms
>=1
0ms [CBx.79.t_DDO_BlkAR]
[CBx.79.t_SecFault] 0ms
>=1
CBx.79.AR_Blkd
&
&
&
>=1
&
&
>=1
&
SIG
Phase C open
Figure 3.28-1 Logic diagram of AR block
The input signal [CBx.79.CB_Healthy] must be energized before auto-reclosure gets ready.
Because most circuit breakers can finish one complete process: open-closed-open, it is necessary
that circuit breaker has enough energy before reclosing. When the time delay of AR is exhausted,
AR will be blocked if the input signal [CBx.79.CB_Healthy] is still not energized within time delay
[CBx.79.t_CBReady]. If this function is not required, the input signal [CBx.79.CB_Healthy] can be
not to configure, and its state will be thought as “1” by default.
In order to block AR reliably even if the signal of manually open circuit breaker not connected to
the input of blocking AR, when the circuit breaker is open by manually and there is CB position
input under normal conditions, AR will be blocked with the time delay of 100ms if AR is not initiated
and no any trip signal.
When auto-reclosure is blocked, auto-reclosing failure, synchrocheck failure or last shot is
reached, or when the internal blocking condition of AR is met (such as, zone 3 of distance
protection operates, the device operates for multi-phase fault, three-phase fault and so on. These
flags of blocking AR have been configured in the device, additional configuration is not required.),
auto-reclosure will be discharged immediately and next auto-reclosing will be disabled.
When the input signal [CBx.79.LockOut] is energized, auto-reclosure will be blocked immediately.
The blocking flag of AR will be also controlled by the internal blocking condition of AR. When the
blocking flag of AR is valid, auto-reclosure will be blocked immediately. The logic of AR ready is
shown in Figure 3.28-2.
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>=1
SIG
3 CB closed
[CBx.79.t_CBClsd]
SIG
CBx.79.Active
>=1
SIG
Any tripping signal
100ms
&
&
&
100ms
SIG
CBx.79.Inprog
SIG
[CBx.79.CB_Healthy]
0ms
SIG
CBx.79.AR_Blkd
>=1
SIG
CBx.TRP.BlkAR
SIG
CBx.79.Fail_Rcls
SIG
CBx.79.Fail_Chk
SIG
Last shot is made
EN
[CBx.79.En]
EN
[CBx.79.En_ExtCtrl]
SIG
CBx.79.En
SIG
CBx.79.Blk
[CBx.79.t_CBReady]
0
CBx.79.Ready
&
>=1
&
>=1
&
>=1
CBx.79.On
&
&
Figure 3.28-2 Logic diagram of AR ready
When a fault occurs under pole disagreement condition, blocking AR can be enabled or disabled.
The time delay [CBx.79.t_SecFault] is used to discriminate another fault which begins after 1-pole
AR initiated. AR will be blocked if another fault happens after this time delay if the logic setting
[CBx.79.En_PDF_Blk] is set as “1”, and 3-pole AR will be initiated if [CBx.79.En_PDF_Blk] is set
as “1”.
AR will be blocked immediately once the blocking condition of AR appears, but the blocking
condition of AR will drop off with a time delay [CBx.79.t_DDO_BlkAR] after blocking signal
disappears.
When one-shot and 1-pole AR is enabled, auto-reclosure will be blocked immediately if there are
binary inputs of multi-phase CB position is energized.
When any protection element operates to trip, the device will output a signal [CBx.79.Active] until
AR drop off (Reset Command). Any tripping signal can be from external protection device or
internal protection element.
AR function can be enabled by internal logic settings of AR mode or external signal via binary
inputs in addition to internal logic setting [CBx.79.En]. When logic setting [CBx.79.En_ExtCtrl] is
set as “1”, AR enable are determined by external signal via binary inputs and logic settings. When
logic setting [CBx.79.En_ExtCtrl] set as “0”, AR enable are determined only by logic settings.
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For one-shot reclosing, if 1-pole AR mode is selected, auto-reclosure will reset when there is
three-phase tripping signal or input signal of multi-phase open position.
SIG
CBx.79.On
SIG
CBx.79.Mode_3PAR
SIG
CBx.79.Ready
SIG
CBx.79.Trp
SIG
CBx.79.Trp3P
SIG
CBx.79.TrpA
SIG
CBx.79.TrpB
SIG
CBx.79.TrpC
SIG
Phase A open
SIG
Phase B open
SIG
Phase C open
Logic
CBx.79.Perm_Trp3P
CBx.79.Perm_Trp1P
Figure 3.28-3 Logic diagram of tripping condition output
When AR is enabled, the device will output the signal [CBx.79.Perm_Trp3P] if AR is not ready, or
AR mode is set as 3-Pole AR, or another fault occurs after the circuit breaker is open.
3.28.5.2 AR Initiation
AR mode can be selected by external signal via binary inputs or internal logic settings. If the logic
setting [CBx.79.SetOpt] set as “1”, AR mode is determined by the internal logic settings. If the logic
settings [CBx.79.SetOpt] set as “0”, AR mode is determined by the external inputs.
1.
AR initiated by tripping signal of line protection
AR can be initiated by tripping signal of line protection, and the tripping signal may be from internal
trip signal or external trip signal.
When selecting 1-pole AR or 1/3-pole AR, line single-phase fault will trigger 1-pole AR. When AR
is ready to reclosing (“CBx.79.Ready”=1) and the single-phase tripping command is received, this
single-phase tripping command will be kept in the device, and 1-pole AR will be initiated after the
single-phase tripping command drops off. The single-phase tripping command kept in the device
will be cleared after the completion of auto-reclosing sequence (Reset Command). Its logic is
shown in Figure 3.28-4.
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SIG
Reset Command
&
>=1
SIG
Single-phase Trip
&
&
SIG
CBx.79.Ready
1-pole AR Initiation
SIG
CBx.79.Sel_1PAR
SIG
CBx.79.Sel_1P/3PAR
>=1
Figure 3.28-4 Single-phase tripping initiating AR
When selecting 3-pole AR or 1/3-pole AR, three-phase tripping will trigger 3-pole AR. When AR is
ready to reclosing (“CBx.79.Ready”=1) and the three-phase tripping command is received, this
three-phase tripping command will be kept in the device, and 3-pole AR will be initiated after the
three-phase tripping command drops off. The three-phase tripping command kept in the device will
be cleared after the completion of auto-reclosing sequence (Reset Command). Its logic is shown
in Figure 3.28-5.
SIG
Reset Command
&
>=1
SIG
Three-phase Trip
&
&
SIG
CBx.79.Ready
3-pole AR Initiation
SIG
CBx.79.Sel_3PAR
SIG
CBx.79.Sel_1P/3PAR
>=1
Figure 3.28-5 Three-phase tripping initiating AR
2.
AR initiated by CB state
A logic setting [CBx.79.En_CBInit] is available for selection that AR is initiated by CB state. Under
normal conditions, when AR is ready to reclosing (“CBx.79.Ready”=1), AR will be initiated if circuit
breaker is open and corresponding phase current is nil. AR initiated by CB state can be divided
into initiating 1-pole AR and 3-pole AR, their logics are shown in Figure 3.28-6 and Figure 3.28-7
respectively. Usually normally closed contact of circuit breaker is used to reflect CB state.
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SIG
Phase A open
SIG
Phase B open
>=1
&
&
SIG
Phase C open
EN
[CBx.79.En_CBInit]
SIG
CBx.79.Ready
SIG
CBx.79.Sel_1PAR
SIG
CBx.79.Sel_1P/3PAR
&
&
1-pole AR Initiation
>=1
Figure 3.28-6 1-pole AR initiation
SIG
Phase A open
SIG
Phase B open
SIG
Phase C open
EN
[CBx.79.En_CBInit]
&
&
&
3-pole AR Initiation
SIG
CBx.79.Ready
EN
[CBx.79.Sel_3PAR]
EN
[CBx.79.Sel_1P/3PAR]
>=1
Figure 3.28-7 3-pole AR initiation
3.28.5.3 AR Reclosing
After AR is initiated, the device will output the initiating contact of AR. For 1-pole AR, in order to
prevent pole discrepancy protection from maloperation under pole discrepancy conditions, the
contact of “1-pole AR initiation” can be used to block pole discrepancy protection.
When the dead time delay of AR expires after AR is initiated, as for 1-pole AR, when the setting
[CBx.25.En_3PLvChk] is set as “0”, the result of synchronism check will not be judged, and
reclosing command will be output directly. When the setting [CBx.25.En_3PLvChk] is set as “1”,
the reclosing is not permissible unless live three-phase check is met. As far as the 3-pole AR, if the
synchronism check is enabled, the release of reclosing command shall be subject to the result of
synchronism check. After the dead time delay of AR expires, if the synchronism check is still
unsuccessful within the time delay [CBx.79.t_wait_Chk], the signal of synchronism check failure
(CBx.79.Fail_Syn) will be output and the AR will be blocked. If 3-pole AR with no-check is enabled,
the condition of synchronism check success (CBx.25.Ok_Chk) will always be established. And the
signal of synchronism check success (CBx.25.Ok_Chk) from the synchronism check logic can be
applied by auto-reclosing function inside the device or external auto-reclosure device.
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CBx.79.Inprog_1P
SIG
1-pole AR Initiation
SIG
3-pole AR Initiation
>=1
CBx.79.Inprog
CBx.79.Inprog_3P
SIG
1-pole AR Initiation
[CBx.79.t_Dd_1PS1]
0ms
&
>=1
AR Pulse
&
SIG
CBx.79.Ok_3PLvChk
SIG
3-pole AR Initiation
[CBx.79.t_Dd_3PS1]
0ms
&
>=1
[CBx.79.t_Wait_Chk] 0ms
&
SIG
CBx.79.Fail_Chk
CBx.79.Ok_Chk
Figure 3.28-8 One-shot AR
In the process of channel abnormality, an internal fault occurs on the transmission line, backup
protection at both ends of line will operate to trip the circuit breaker of each end. The operation
time of backup protection at both ends of the line is possibly non-accordant, whilst the time delay
of AR needs to consider the arc-extinguishing and insulation recovery ability for transient fault, so
the time delay of AR shall be considered comprehensively according to the operation time of the
device at both ends. When the communication channel of main protection is abnormal (input
signal [CBx.79.PLC_Lost] is energized), and the logic setting [CBx.79.En_AddDly] is set as “1”,
then the dead time delay of AR shall be equal to the original dead time delay of AR plus the extra
time delay [CBx.79.t_AddDly], so as to ensure the recovery of insulation intensity of fault point
when reclosing after transient fault. This extra time delay [CBx.79.t_AddDly] is only valid for the
first shot AR.
>=1
SIG
Any tripping signal
SIG
CBx.79.PLC_Lost
SIG
CBx.79.Active
EN
[CBx.79.En_AddDly]
&
&
&
Extend AR time
Figure 3.28-9 Extra time delay of AR
Reclosing pulse length may be set through the setting [CBx.79.t_PW_AR]. For the circuit breaker
without anti-pump interlock, a logic setting [CBx.79.En_CutPulse] is available to control the
reclosing pulse. When this function is enabled, if the device operates to trip during reclosing, the
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reclosing pulse will drop off immediately, so as to prevent multi-shot reclosing onto fault. After the
reclosing command is issued, AR will drop off with time delay [CBx.79.t_Reclaim], and can carry
out next reclosing.
SIG
SIG
WaitMasterValid
&
0ms
50ms
0ms
[CBx.79.t_PW_AR]
AR Pulse
SIG
Single-phase Trip
SIG
Three-phase Trip
EN
[CBx.79.En_CutPulse]
>=1
CBx.79.AR_Out
&
>=1
&
>=1
&
SIG
[CBx.79.t_Reclaim]
CBx.79.AR_Out
0ms
Reset Command
Figure 3.28-10 Reclosing output logic
The reclaim timer defines a time from the issue of the reclosing command, after which the
reclosing function resets. Should a new trip occur during this time, it is treated as a continuation of
the first fault. The reclaim timer is started when the CB closing command is given.
SIG
1-pole AR Initiation
>=1
0ms
SIG
3-pole AR Initiation
SIG
CBx.79.Fail_Rcls
SET
[CBx.79.Opt_Priority]=High
[CBx.79.t_Fail]
>=1
&
CBx.79.WaitToSlave
Figure 3.28-11 Wait to slave signal
The output signal “CBx.79.WaitToSlave” is usually configured to the signal “CBx.79.WaitMaster” of
slave AR. Slave AR is permissible to reclosing only if master AR is reclosed successfully.
3.28.5.4 Reclosing Failure and Success
For transient fault, the fault will be cleared after the device operates to trip. After the reclosing
command is issued, AR will drop off after time delay [CBx.79.t_Reclaim], and can carry out next
reclosing. When the reclosing is unsuccessful or the reclosing condition is not met after AR
initiated, the reclosing will be considered as unsuccessful, including the following cases.
1.
If any protection element operates to trip when AR is enabled ([CBx.79.On]=1) and AR is not
ready ([CBx.79.Ready]=0), the device will output the signal (CBx.79.Fail_Rcls).
2.
For one-shot AR, if the tripping command is received again within reclaim time after the
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reclosing pulse is issued, the reclosing shall be considered as unsuccessful.
3.
For multi-shot AR, if the reclosing times are equal to the setting value of AR number and the
tripping command is received again after the last reclosing pulse is issued, the reclosing shall
be considered as unsuccessful.
4.
The logic setting [CBx.79.En_FailCheck] is available to judge whether the reclosing is
successful by CB state, when it is set as “1”. If CB is still in open position with a time delay
[CBx.79.t_Fail] after the reclosing pulse is issued, the reclosing shall be considered as
unsuccessful. For this case, the device will issue a signal (CBx.79.Fail_Rcls) to indicate that
the reclosing is unsuccessful, and this signal will drop off after (Reset Command). AR will be
blocked if the reclosing shall be considered as unsuccessful.
SET [CBx.79.Opt_Priority]=Low
&
WaitMaster Valid
SIG
CBx.79.WaitMaster
SIG
CBx.79.On
SIG
CBx.79.Ready
SIG
Any tripping command
SIG
Last shot is made
SIG
CBx.79.Inprog
SIG
CBx.79.AR_Blkd
SIG
WaitMasterValid
&
&
>=1
0ms
200ms
>=1
CBx.79.Fail_Rcls
&
&
[CBx.79.t_WaitMaster]
0ms
>=1
SIG
AR Pulse
SIG
WaitMasterValid
EN
[CBx.79.En_FailCheck]
SIG
3 CB closed
&
[CBx.79.t_Fail] 0ms
&
&
&
CBx.79.Succ_Rcls
0ms [CBx.79.t_Fail]
Figure 3.28-12 Reclosing failure and success
After unsuccessful AR is confirmed, AR will be blocked. AR will not enter into the ready state
unless the circuit breaker position drops off , and can only begin to enter into the ready state again
after the circuit breaker is closed.
3.28.5.5 Reclosing Numbers Control
The device may be set up into one-shot or multi-shot AR. Through the setting [CBx.79.N_Rcls],
the maximum number of reclosing attempts may be set up to 4 times. Generally, only one-shot AR
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is selected. Some corresponding settings may be hidden if one-shot AR is selected.
1.
1-pole AR
[CBx.79.N_Rcls]=1 means one-shot reclosing. For one-shot 1-pole AR mode, 1-pole AR will be
initiated only for single-phase fault and respective faulty phase selected, otherwise, AR will be
blocked. For single-phase transient fault on the line, line protection device will operate to trip and
1-pole AR is initiated. After the dead time delay for 1-pole AR is expired, the device will send
reclosing pulse, and then the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to
ready for the next reclosing. For permanent fault, the device will operate to trip again after the
reclosing is performed, and the device will output the signal of reclosing failure [CBx.79.Fail_Rcls].
[CBx.79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 1-pole AR mode, the
first reclosing is 1-pole AR, and the subsequent reclosing can only be 3-pole AR. For single-phase
transient fault on the line, line protection device will operate to trip and then 1-pole AR is initiated.
After the dead time delay of the first reclosing is expired, the device will send reclosing pulse, and
then the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to ready for the next
reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed,
and then 3-pole AR is initiated. At this time, the time delay applies the setting [CBx.79.t_Dd_3PS2].
After the time delay is expired, if the reclosing condition is met, the device will send reclosing pulse.
The sequence is repeated until the reclosing is successful or the maximum permit reclosing
number [CBx.79.N_Rcls] is reached. If the first fault is multi-phase fault, the device operates to trip
three-phase and initiate 3-pole AR. At this time, the time delay applies the setting
[CBx.79.t_Dd_3PS1]. For the possible reclosing times of 3-pole AR in 1-pole AR mode, please
refer to Table 3.28-2.
2.
3-pole AR
[CBx.79.N_Rcls]=1 means one-shot reclosing. For one-shot 3-pole AR mode, line protection
device will operate to trip when a transient fault occurs on the line and 3-pole AR will be initiated.
After the dead time delay for 3-pole AR is expired, the device will send reclosing pulse, and then
the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to ready for the next
reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed,
and the device will output the signal of reclosing failure [CBx.79.Fail_Rcls].
[CBx.79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 3-pole AR mode, line
protection device will operate to trip when a transient fault occurs on the line and 3-pole AR will be
initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing
pulse, and then the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to ready for
the next reclosing. For permanent fault, the device will operate to trip again after the reclosing is
performed, and then 3-pole AR is initiated after the tripping contact drops off. After the time delay
for AR is expired, the device will send reclosing pulse. The sequence is repeated until the
reclosing is successful or the maximum permit reclosing number [CBx.79.N_Rcls] is reached.
3.
1/3-pole AR
[CBx.79.N_Rcls]=1 means one-shot reclosing. For one-shot 1/3-pole AR mode, line protection
device will operate to trip when a transient fault occurs on the line and 1-pole AR will be initiated
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for single-phase fault and 3-pole AR will be initiated for multi-phase fault. After respective dead
time delay for AR is expired, the device will send reclosing pulse, and then the auto-reclosure will
drop off after the time delay [CBx.79.t_Reclaim] to ready for the next reclosing. For permanent
fault, the device will operate to trip again after the reclosing is performed, and the device will
output the signal of reclosing failure [CBx.79.Fail_Rcls].
[CBx.79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 1/3-pole AR mode, line
protection device will operate to trip when a transient fault occurs on the line and AR will be
initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing
pulse, and then the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to ready for
the next reclosing. For permanent fault, the device will operate to trip again after the reclosing is
performed, and then 3-pole AR is initiated after the tripping contact drops off. After the time delay
for AR is expired, the device will send reclosing pulse. The sequence is repeated until the
reclosing is successful or the maximum permit reclosing number [CBx.79.N_Rcls] is reached. For
the possible reclosing times of 3-pole AR in 1/3-pole AR mode, please refer to Table 3.28-2. The
table below shows the number of reclose attempts with respect to the settings and AR modes.
Table 3.28-2 Reclosing number
Setting Value
1-pole AR
3-pole AR
1/3-pole AR
N-1AR
N-3AR
N-1AR
N-3AR
N-1AR
N-3AR
1
1
0
0
1
1
1
2
1
1
0
2
1
2
3
1
2
0
3
1
3
4
1
3
0
4
1
4
N-1AR: the reclosing number of 1-pole AR
N-3AR: the reclosing number of 3-pole AR
4.
Coordination between dual auto-reclosures
Duplicated protection configurations are normally applied for UHV lines. If reclosing function is
integrated within line protections, the auto-reclosing function can be enabled in any or both of the
line protections without coordination.
If both sets of reclosing functions are enabled, when one of them first recloses onto a permanent
fault, the other will block the reclosing pulse according to the latest condition of the faulty phase.
For one-shot AR mode, if the current is detected in the faulty phase, AR will be blocked
immediately to prevent the circuit breaker from repetitive reclosing. For multi-shot AR mode, if the
current is detected in the faulty phase, the current reclosing pulse will be blocked and go into the
next reclosing pulse logic automatically. If the maximum permitted reclosing number
[CBx.79.N_Rcls] is reached, the auto-reclosure will drop off after the time delay
[CBx.79.t_Reclaim].
For one-shot or multi-shot AR, there is a corresponding reclosing counter at each stage. After
reclosing pulse is sent, the corresponding reclosing counter will plus 1 and the reclosing counter
may be cleared by the submenu “Clear Counter”. If the circuit breaker is reclosed by other
devices during AR initiation, the auto-reclosure will go into the next reclosing pulse logic.
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3.28.5.6 AR Time Sequence Diagram
The following two examples indicate typical time sequence of AR process for transient fault and
permanent fault respectively.
Signal
Fault
Trip
CB 52b
Open
[CBx.79.t_Reclaim]
CBx.79.t_Reclaim
CBx.79.Active
CBx.79.Inprog
[CBx.79.t_Dd_1PS1]
CBx.79.Inprog_1P
[CBx.79.t_Dd_1PS1]
CBx.79.Ok_Chk
AR Out
[CBx.79.t_PW_AR]
CBx.79.Perm_Trp3P
CBx.79.Fail_Rcls
Time
Figure 3.28-13 Single-phase transient fault
Signal
Fault
Trip
52b
Open
Open
[CBx.79.t_Reclaim]
CBx.79.t_Reclaim
CBx.79.Active
CBx.79.Inprog
CBx.79.Inprog_1P
CBx.79.Inprog_3PS2
[CBx.79.t_Dd_1PS1]
[CBx.79.t_Dd_3PS2]
CBx.79.Ok_Chk
AR Out
[CBx.79.t_PW_AR]
[CBx.79.t_PW_AR]
CBx.79.Perm_Trp3P
CBx.79.Fail_Rcls
200ms
Time
Figure 3.28-14 Single-phase permanent fault ([CBx.79.N_Rcls]=2)
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3.28.6 Settings
Table 3.28-3 Auto-reclosing settings
No.
Name
Range
Step
Unit
Remark
Maximum
1
CBx.79.N_Rcls
1~4
1
2
CBx.79.t_Dd_1PS1
0.000~600.000
0.001
s
3
CBx.79.t_Dd_3PS1
0.000~600.000
0.001
s
4
CBx.79.t_Dd_3PS2
0.000~600.000
0.001
s
5
CBx.79.t_Dd_3PS3
0.000~600.000
0.001
s
6
CBx.79.t_Dd_3PS4
0.000~600.000
0.001
s
7
CBx.79.t_CBClsd
0.000~600.000
0.001
s
number
of
reclosing
attempts
Dead time of first shot 1-pole
reclosing
Dead time of first shot 3-pole
reclosing
Dead time of second shot 3-pole
reclosing
Dead time of third shot 3-pole
reclosing
Dead time of fourth shot 3-pole
reclosing
Time delay of circuit breaker in
closed position before reclosing
Time delay to wait for CB healthy,
and begin to timing when the input
8
CBx.79.t_CBReady
0.000~600.000
0.001
s
signal
[79.CB_Healthy]
de-energized
and
if
it
is
is
not
energized within this time delay, AR
will be blocked.
9
CBx.79.t_Wait_Chk
0.000~600.000
0.001
s
Maximum wait time for synchronism
check
Time delay allow for CB status
10
CBx.79.t_Fail
0.000~600.000
0.001
s
change
to
conform
reclosing
successful
11
CBx.79.t_PW_AR
0.000~600.000
0.001
s
Pulse width of AR closing signal
12
CBx.79.t_Reclaim
0.000~600.000
0.001
s
Reclaim time of AR
13
CBx.79.t_PersistTrp
0.000~600.000
0.001
s
Time delay of excessive trip signal to
block auto-reclosing
Drop-off time delay of blocking AR,
14
CBx.79.t_DDO_BlkAR
0.000~600.000
0.001
s
when
blocking
signal
for
AR
disappears, AR blocking condition
drops off after this time delay
15
CBx.79.t_AddDly
0.000~600.000
0.001
s
16
CBx.79.t_WaitMaster
0.000~600.000
0.001
s
17
CBx.79.t_SecFault
0.000~600.000
0.001
s
Additional
time
delay
for
auto-reclosing
Maximum wait time for reclosing
permissive signal from master AR
Time delay of discriminating another
fault, and begin to times after 1-pole
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No.
Name
Range
Step
Unit
Remark
AR initiated, 3-pole AR will be
initiated if another fault happens
during this time delay. AR will be
blocked if another fault happens
after that.
Enabling/disabling
auto-reclosing
blocked when a fault occurs under
18
CBx.79.En_PDF_Blk
0 or 1
pole disagreement condition
0: disable
1: enable
Enabling/disabling
19
CBx.79.En_AddDly
auto-reclosing
with an additional dead time delay
0 or 1
0: disable
1: enable
Enabling/disabling adjust the length
20
CBx.79.En_CutPulse
of reclosing pulse
0 or 1
0: disable
1: enable
Enabling/disabling confirm whether
AR is successful by checking CB
21
CBx.79.En_FailCheck
0 or 1
state
0: disable
1: enable
Enabling/disabling auto-reclosing
22
CBx.79.En
0 or 1
0: disable
1: enable
Enabling/disabling AR by external
input signal besides logic setting
23
CBx.79.En_ExtCtrl
[79.En]
0 or 1
0: only logic setting
1: logic setting and external input
signal
Enabling/disabling AR be initiated by
24
CBx.79.En_CBInit
open state of circuit breaker
0 or 1
0: disable
1: enable
Option of AR priority
None: single-breaker arrangement
25
CBx.79.Opt_Priority
None, High or
High: master AR of multi-breaker
Low
arrangement
Low: slave AR of multi-breaker
arrangement
26
CBx.79.SetOpt
0 or 1
Control option of AR mode
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No.
Name
Range
Step
Unit
Remark
1: select AR mode by internal logic
settings
0: select AR mode by external input
signals
Enabling/disabling 1-pole AR mode
27
CBx.79.En_1PAR
0 or 1
0: disable
1: enable
Enabling/disabling 3-pole AR mode
28
CBx.79.En_3PAR
0 or 1
0: disable
1: enable
Enabling/disabling
29
CBx.79.En_1P/3PAR
1/3-pole
AR
mode
0 or 1
0: disable
1: enable
3.29 Transfer Trip
3.29.1 General Application
This function module provides a binary input [TT.Init] for receiving transfer trip from the remote end.
This feature ensures simultaneous tripping at both ends.
3.29.2 Function Description
Transfer trip can be controlled by local fault detector by logic settings [TT.En_FD_Ctrl]. In addition,
the binary input [TT.Init] is always supervised, and the device will issue an alarm [TT.Alm] and
block transfer trip once the binary input is energized for longer than [TT.t_Op]+5s and drop off after
resumed to normal with a time delay of 10s.
3.29.3 Function Block Diagram
TT
TT.Init
TT.Alm
TT.En
TT.Op
TT.Blk
TT.On
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3.29.4 I/O Signals
Table 3.29-1 I/O signals of transfer trip
No.
Input Signal
1
TT.Init
2
TT.En
3
TT.Blk
No.
Description
Input signal of initiating transfer trip after receiving transfer trip
Transfer trip enabling input, it is triggered from binary input or programmable logic
etc.
Transfer trip blocking input, it is triggered from binary input or programmable logic
etc.
Output Signal
Description
1
TT.Alm
Input signal of receiving transfer trip is abnormal
2
TT.Op
Transfer trip operates
3
TT.On
Transfer trip is enabled
3.29.5 Logic
SIG
TT.En
SIG
TT.Blk
SIG
TT.Alm
EN
[TT.En_FD_Ctrl]
SIG
FD.Pkp
BI
TT.Init
&
TT.On
&
[TT.t_Op]
>=1
0ms
&
[TT.t_Op]+5s
10s
TT.Op
TT.Alm
Figure 3.29-1 Logic diagram of transfer trip
3.29.6 Settings
Table 3.29-2 Settings of transfer trip
No.
1
Name
TT.t_Op
Range
Step
Unit
0.000~600.000
0.001
s
2
TT.En_FD_Ctrl
0 or 1
3
TT.En_BlkAR
0 or 1
Remark
Time delay of transfer trip
Transfer trip controlled by local fault detector
element
0: not controlled by local fault detector
element
1: controlled by local fault detector element
Enabling/disabling transfer trip operate to
block AR
0: disable
1: enable
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3.30 Trip Logic
3.30.1 General Application
For any enabled protection tripping elements, their operation signal will convert to appropriate
tripping signals through trip logics and then trigger output contacts by configuration.
NOTICE!
For double circuit breakers mode, the device will provide independent trip logic for CB1
and CB2 respectively. Both trip logics have the same logic. The difference is that the
prefix “CBx.” is added to all signals for circuit breaker No.x (x=1 or 2). For trip logic
settings, only the setting [En_Trp3P] will be added the prefix “CBx.” for circuit breaker
No.x, which means that both circuit breakers corresponding to the same line protection
can be set different trip mode.
3.30.2 Function Description
This module gathers signals from phase selection and protection tripping elements and then
converts the operation signal from protection tripping elements to appropriate tripping signals.
The device can implement phase-segregated tripping or three-phase tripping, and may output the
contact of blocking AR and the contact of initiating breaker failure protection.
3.30.3 Function Block Diagram
TRP
Line.Enable
Line.Trp3P_PSFail
Line.Block
CBx.TRP.On
CBx.TRP.En
CBx.TrpA
CBx.TRP.Blk
CBx.TrpB
Faulty phase selection
CBx.TrpC
CBx.PrepTrp3P
CBx.Trp
Line tripping element
CBx.Trp3P
Breaker tripping element
CBx.BFI_A
Initiating BFP element
CBx.BFI_B
CBx.BFI_C
CBx.BFI
CBx.TRP.BlkAR
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3.30.4 I/O Signals
Table 3.30-1 I/O signals of trip logic
No.
Input Signal
Description
1
Line.Enable
Input signal of enabling line trip logic
2
Line.Block
Input signal of blocking line trip logic
3
CBx.Enable
Input signal of enabling trip logic of circuit breaker No.x
4
CBx.Block
Input signal of blocking trip logic of circuit breaker No.x
Faulty phase selection (phase
The result of fault phase selection
A, phase B, phase C)
If multi-phase is selected, three-phase breakers will be tripped.
5
Input signal of permitting three-phase tripping
6
CBx.PrepTrp3P
When this signal is valid, three-phase tripping will be adopted for any
kind of faults.
7
Line tripping element
8
Breaker tripping element
9
Initiating BFP element
All operation signals of various line protection tripping elements, such
as distance protection, overcurrent protection, etc.
All protection tripping elements concerned with breaker, such as pole
discrepancy protection, etc.
Tripping element to initiate BFP, except undervoltage protection,
tripping elements of all protections initiate BFP
No.
Output Signal
Description
1
Line.Trp3P_PSFail
Initiating three-phase tripping due to failure in fault phase selection
2
CBx.TRP.On
Tripping logic is enabled.
3
CBx.TrpA
Tripping A-phase circuit breaker
4
CBx.TrpB
Tripping B-phase circuit breaker
5
CBx.TrpC
Tripping C-phase circuit breaker
6
CBx.Trp
Tripping any phase circuit breaker
7
CBx.Trp3P
Tripping three-phase circuit breaker
8
CBx.BFI_A
9
CBx.BFI_B
10
CBx.BFI_ C
11
CBx.BFI
12
CBx.TRP.BlkAR
Protection tripping signal of A-phase configured to initiate BFP, BFI
signal shall be reset immediately after tripping signal drops off.
Protection tripping signal of B-phase configured to initiate BFP, BFI
signal shall be reset immediately after tripping signal drops off.
Protection tripping signal of C-phase configured to initiate BFP, BFI
signal shall be reset immediately after tripping signal drops off.
Protection tripping signal configured to initiate BFP, BFI signal shall be
reset immediately after tripping signal drops off.
Blocking auto-reclosing
3.30.5 Logic
After tripping signal is issued, the tripping pulse will be kept as same as the setting [t_Dwell_Trp] at
least. When the time delay is expired, for phase-segregated tripping, the tripping signal will drop
off immediately if the faulty current of corresponding phase is less than 0.06In (In is secondary
rated current), otherwise the tripping signal will be always kept until the faulty current of
corresponding phase is less than 0.06In. For three-phase tripping, the tripping signal will drop off
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immediately if three-phase currents are all less than 0.06In, otherwise the tripping signal will be
always kept until three-phase currents are all less than 0.06In.
NOTICE!
The line trip command was sent to the circuit breaker, and the circuit breaker will be
tripped. And then the circuit breaker will be in open position and its current will be zero.
Hence, under this condition, there is on need to trip second time in the duration of the
device picking up.
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SIG Line tripping element without FPS
SIG
FPS (phase A)
>=1
&
&
Line trip command (phase A)
SIG Line tripping element with FPS
SIG Ia<0.06In
[t_Dwell_Trp]
&
0
SIG Line tripping element without FPS
SIG FPS (phase B)
>=1
&
&
Line trip command (phase B)
SIG Line tripping element with FPS
SIG Ib<0.06In
[t_Dwell_Trp]
&
0
SIG Line tripping element without FPS
SIG FPS (phase C)
>=1
&
&
Line trip command (phase C)
SIG Line tripping element with FPS
SIG Ic<0.06In
[t_Dwell_Trp]
&
0
SIG Line trip command (phase A)
&
SIG Line trip command (phase B)
SIG Line trip command (phase C)
SIG Line trip command (phase A)
&
SIG Line trip command (phase B)
>=1
>=1
Line trip 3P command
SIG Line trip command (phase C)
SIG Line trip command (phase A)
&
SIG Line trip command (phase B)
SIG Line trip command (phase C)
SIG Line trip command (phase A)
&
SIG Line trip command (phase B)
SIG Line trip command (phase C)
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SIG FPS (phase A)
>=1
SIG FPS (phase B)
&
200ms
0ms
Line.Trp3P_PSFail
SIG FPS (phase C)
SIG Line tripping element with FPS
SIG CBx.TRP.En
&
CBx.TRP.On
SIG CBx.TRP.Blk
>=1
SIG Breaker tripping element
SIG Ia<0.06In
&
&
SIG Ib<0.06In
&
SIG Ic<0.06In
[t_Dwell_Trp]
CB No.x Trip Command
&
0
SIG CBx.TRP.On
&
CBx.TrpA
SIG Line trip command (phase A)
&
CBx.TrpB
SIG Line trip command (phase B)
&
CBx.TrpC
SIG Line trip command (phase C)
>=1
&
SIG CBx.PrepTrp3P
EN
>=1
[CBX.En_3PTrp]
SIG Line.Trip 3P Command
&
>=1
CBx.Trp3P
>=1
SIG Line.Trp3P_PSFail
SIG CB No.x Trip Command
Figure 3.30-1 Tripping logic
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>=1
&
Except undervoltage protection,
tripping elements of all
protections all initiate BFP
CBx.BFI
SIG Initiating BFP element
&
CBx.BFI_A
SIG CBx.TrpA
&
CBx.BFI_B
SIG CBx.TrpB
&
CBx.BFI_C
SIG CBx.TrpC
Figure 3.30-2 Breaker failure initiation logic
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SIG
85-1.Op_DEF
SIG
85-2.Op_DEF
EN
[85.DEF.En_BlkAR]
SIG
78.Op
SIG
Yi.ZP.Op
>=1
&
&
>=1
>=1
>=1
EN
[Yi.ZP.En_BlkAR]
SIG
Yi.ZG.Op
EN
[Yi.ZG.En_BlkAR]
SIG
50/51Pm.Op
EN
[50/51Pm.En_BlkAR]
SIG
50/51Gm.Op
EN
[50/51Gm.En_BlkAR]
SIG
50/51Qm.Op
EN
[50/51Qm.En_BlkAR]
SIG
50PVT1(2).Op
SIG
50GVT1(2).Op
SIG
46BC.Op
SIG
81O.OFm.Op
SIG
81U.UFm.Op
SIG
TT.Op
EN
[TT.En_BlkAR]
SIG
CBx.50BF.Op_t1
SIG
CBx.50BF.Op_t2
SIG
CBx.50DZ.Op
SIG
49-1.Op
SIG
49-2.Op
SIG
87STB.Op
SIG
32R1.Op
SIG
32R2.Op
SIG
CBx.62PD.Op
SIG
59Pz.Op
SIG
59Gz.Op
SIG
59Q.Op
SIG
27Pz.Op
EN
En_MPF_Blk_AR
SIG
Multi-phase fault
EN
En_3PF_Blk_AR
SIG
Three-phase fault
EN
En_PhSF_Blk_AR
SIG
Phase selection failure
SIG
21SOTF.Op
SIG
50PSOTF.Op
SIG
50GSOTF.Op
SIG
Manual closing signal
&
&
&
>=1
&
>=1
>=1
>=1
&
>=1
>=1
>=1
>=1
>=1
CBx.BlkAR
>=1
>=1
>=1
&
&
>=1
&
>=1
>=1
&
Figure 3.30-3 Blocking AR logic
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Y can be 21M or 21Q
i can be 1, 2, 3, 4 or 5
m can be 1, 2, 3 or 4
z can be 1, 2 or 3
x can be 1 or 2
3.30.6 Settings
Table 3.30-2 Settings of trip logic
No.
Name
Range
Step
Unit
Remark
Enabling/disabling
1
En_MPF_Blk_AR
auto-reclosing
blocked
when multi-phase fault happens
0 or 1
0: disable
1: enable
Enabling/disabling
2
En_3PF_Blk_AR
auto-reclosing
blocked
when three-phase fault happens
0 or 1
0: disable
1: enable
Enabling/disabling
3
En_PhSF_Blk_AR
auto-reclosing
blocked
when faulty phase selection fails
0 or 1
0: disable
1: enable
The dwell time of tripping command, empirical
value is 0.04
4
t_Dwell_Trp
0.000~10.000
0.001
s
The tripping contact shall drop off under
conditions of no current or protection tripping
element drop-off.
Enabling/disabling three-phase tripping mode
5
CBx.En_Trp3P
0 or 1
for any fault conditions
0: disable
1: enable
3.31 VT Circuit Supervision
3.31.1 General Application
The purpose of VT circuit supervision is to detect whether VT circuit is normal. Because some
protection functions, such as distance protection, under-voltage protection and so on, will be
influenced by VT circuit failure, these protection functions should be disabled when VT circuit fails.
VT circuit failure can be caused by many reasons, such as fuse blown due to short-circuit fault,
poor contact of VT circuit, VT maintenance and so on. The device can detect them and issue an
alarm signal to block relevant protection functions. However, the alarm of VT circuit failure should
not be issued when the following cases happen.
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1.
Line VT is used as protection VT and the protected line is out of service.
2.
Only current protection functions are enabled and VT is not connected to the device.
3.31.2 Function Description
VT circuit supervision can detect failure of single-phase, two-phase and three-phase on protection
VT. Under normal condition, the device continuously supervises input voltage from VT, VT circuit
failure signal will be activated if residual voltage exceeds the threshold value or positive-sequence
voltage is lower than the threshold value. If the device is under pickup state due to system fault or
other abnormality, VT circuit supervision will be disabled.
Under normal conditions, the device detect residual voltage greater than the setting [VTS.3U0_Set]
to determine single-phase or two-phase VT circuit failure, and detect positive-sequence voltage
less than the setting [VTS.U1_Set] to determine three-phase VT circuit failure. Upon detecting
abnormality on VT circuit, an alarm will comes up with the time delay [VTS.t_DPU] and drop off
with the time delay [VTS.t_DDO] after VT circuit restored to normal.
VT (secondary circuit) MCB auxiliary contact as a binary input can be connected to the binary
input circuit of the device. If MCB is open (i.e. [VTS.MCB_VT] is energized), the device will
consider the VT circuit is not in a good condition and issues an alarm without a time delay.
When VT is not connected into the device, the alarm will be not issued if the logic setting
[VTS.En_Out_VT] is set as “1”. However, the alarm is still issued if the binary input [VTS.MCB_VT]
is energized, no matter that the logic setting [VTS.En_Out_VT] is set as “1” or “0”.
When VT neutral point fails, third harmonic of residual voltage is comparatively large. If third
harmonic amplitude of residual voltage is larger than the setting [VTNS.3U0_Hm3] and without
operation of fault detector element, VT neutral point failure alarm signal [VTNS.Alm] will be issued
with the time delay [VTS.t_DPU] and drop off with the time delay [VTS.t_DDO] after three phases
voltage restored to normal.
3.31.3 Function Block Diagram
VTS
VTS.En
VTNS
VTS.Alm
VTNS.En
VTS.Blk
VTNS.Alm
VTNS.Blk
VTS.MCB_VT
3.31.4 I/O Signals
Table 3.31-1 I/O signals of VT circuit supervision
No.
1
Input Signal
VTS.En
Description
VT supervision enabling input, it is triggered from binary input or programmable
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logic etc.
VT supervision blocking input, it is triggered from binary input or programmable
2
VTS.Blk
3
VTNS.En
4
VTNS.Blk
5
VTS.MCB_VT
No.
logic etc.
VT neutral point supervision enabling input, it is triggered from binary input or
programmable logic etc.
VT neutral point supervision blocking input, it is triggered from binary input or
programmable logic etc.
Binary input for VT MCB auxiliary contact
Output Signal
Description
1
VTS.Alm
Alarm signal to indicate VT circuit fails
2
VTNS.Alm
Alarm signal to indicate VT neutral point fails
3.31.5 Logic
SIG
FD.Pkp
SIG
79.Inprog
SIG
3U0>[VTS.3U0_Set]
SIG
U1<[VTS.U1_Set]
EN
[VTS.En_LineVT]
SIG
52b_PhA
SIG
52b_PhB
SIG
52b_PhC
EN
[VTS.En_Out_VT]
BI
>=1
&
>=1
&
If the signal [FD.Pkp] or [CBx.79.Inprog] operates,
the circuit of time delay will be interrupted.
>=1
&
&
[VTS.t_DPU] [VTS.t_DDO ]
&
>=1
>=1
&
VTS.Alm
[VTS.MCB_VT]
EN
[VTS.En]
SIG
[VTS.En]
SIG
[VTS.Blk]
&
Figure 3.31-1 Logic of VT circuit supervision
&
SIG FD.Pkp
>=1
SIG 79.Inprog
If the signal [FD.Pkp] or [CBx.79.Inprog] operates,
the circuit of time delay will be interrupted.
SIG U03>[VTNS.3U0_Hm3_Set]
&
>=1
[VTS.t_DPU]
EN
[VTS.En_Out_VT]
EN
[VTS.En]
SIG
[VTS.t_DDO]
&
VTNS.Alm
&
[VTNS.En]
SIG [VTNS.Blk]
Figure 3.31-2 Logic of VT neutral point supervision
U03 is third harmonic amplitude of neutral point residual voltage
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If there is already a VTS alarm before FD operated, VTS will continue to block distance protection,
that is VTS will be latched when FD operates.
3.31.6 Settings
Table 3.31-2 VTS settings
No.
Name
Range
Step
Unit
1
VTS.3U0_Set
0.000~220.000
0.001
V
2
VTS.U1_Set
22.000~110.000
0.001
V
3
VTNS.3U0_Hm3_Set
0.000~220.000
0.001
V
4
VTS.t_DPU
0.200~100.000
0.001
s
5
VTS.t_DDO
0.200~100.000
0.001
s
Remark
Zero-sequence voltage setting of VT
circuit supervison
Positive-sequence voltage setting of VT
circuit supervison
Third harmonic setting of zero-sequence
voltage of VT circuit supervision
Pickup
time
delay
of
VT
circuit
delay
of
VT
circuit
used
for
supervision
Dropoff
time
supervision
No
voltage
protection
calculation
1: enable
6
VTS.En_Out_VT
0 or 1
0: disable
In general, when VT is not connected to
the device, this logic setting should be
set as “1”
Voltage
7
VTS.En_LineVT
selection
for
protection
calculation from busbar VT or line VT
0 or 1
1: line VT
0: busbar VT
Enabling/disabling alarm function of VT
8
VTS.En
circuit supervision
0 or 1
1: enable
0: disable
3.32 CT Circuit Supervision
3.32.1 General Application
The purpose of the CT circuit supervision is to detect any abnormality on CT secondary circuit.
NOTICE!
For double circuit breakers mode, the device will provide independent CT circuit
supervision function for CB1 and CB2 respectively. Both CT circuit supervision
functions have the same logic. The difference is that the prefix “CBx.” is added to all
signals for circuit breaker No.x (x=1 or 2).
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3.32.2 Function Description
Under normal conditions, CT secondary signal is continuously supervised by detecting the
residual current and voltage. If residual current is larger than 10%In whereas residual voltage is
less than 3V, an error in CT circuit is considered, the concerned protection functions are blocked
and an alarm is issued with a time delay of 10s and drop off with a time delay of 10s after CT
circuit is restored to normal condition.
3.32.3 Function Block Diagram
CTS
CBx.CTS.En
CBx.CTS.Alm
CBx.CTS.Blk
3.32.4 I/O Signals
Table 3.32-1 I/O signals of CT circuit supervision
No.
Input Signal
1
CBx.CTS.En
2
CBx.CTS.Blk
No.
1
Description
CT circuit supervision enabling input, it is triggered from binary input or
programmable logic etc.
CT circuit supervision blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
CBx.CTS.Alm
Description
Alarm signal to indicate CT circuit fails
3.32.5 Logic
SIG
CBx.CTS.En
SIG
CBx.CTS.Blk
SIG
3I0>0.1In
SIG
3U0<3V
SIG
IA<0.06In
SIG
IB<0.06In
SIG
IC<0.06In
&
&
10s
10s
CBx.CTS.Alm
&
>=1
Figure 3.32-1 Logic diagram of CT circuit failure
3.33 Control and Synchrocheck for Manual Closing
3.33.1 General Application
The purpose of control is to open or close primary equipment, including circuit breaker (CB),
disconnector (DS) and earth switch (ES), or to issue outputs for signaling purpose. Synchronism
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check and dead check are also provided for the control processes as below:
1. Local manual closing CB
2. Local closing CB by access the menu “Local Cmd→Control”
3. Remote closing CB from SCADA (i.e., local HMI system) or control center (CC)
Programmable interlocking logics within a bay and amongst different bays are provided by using
PCS-Explorer.
NOTICE!
For double circuit breakers mode, the device will provide independent control and
synchrocheck function of manual closing for CB1 and CB2 respectively. Both control
and synchrocheck for manual closing functions have the same logic. The difference is
that the prefix “CBx.” is added to all signals and settings for circuit breaker No.x (x=1 or
2).
3.33.2 Function Description
1. Control
High reliability is ensured by adopting the principle of selection before operation (abbreviated
SBO). When the binary input [BI_Maintenance] is energized as “1”, remote control from
SCADA/CC will be disabled, but local control will not be influenced.
The integrated control process is as follow:
1) The control source (SCADA/CC, or local LCD control operation, or manual control operation)
sends control selection command to this device
2) This device sends back the control selection result (success or failure) to the control source
after logic judgment
3) The control source sends control operation command to this device if the control selection
result is “success”. The control source will send control cancellation command to this device if
the control selection result is “failure”.
4) This device sends back the control operation result (success or failure) to the control source
after logic judgment.
Logic calculation result of interlocking is input to the remote control module as a criterion of remote
operation. When the enabling parameter of remote open/close interlock is “1”, remote control
module determines whether it can be output according to the calculation result of interlocking. If
the current breaker position or programmable part can meet the interlocking condition, remote
control can be output normally, otherwise remote operation is blocked. When the enabling
parameter of remote open/close interlock is “0”, interlocking function is disabled and remote
control will be output directly without the judgment of interlocking.
Holding time of each binary output contact can be set by configuring corresponding settings and is
often configured as 250ms. However, for the control circuits without latched relays, the holding
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time must be longer to ensure successful control operation.
EN
1
[MCBrd.CBx.25.En_SynChk]
MCBrd.CBx.25.On_SynChk
SIG
MCBrd.CBx.25.Sel_SynChk
EN
[MCBrd.CBx.25.SetOpt]
EN
[MCBrd.CBx.25.En_NoChk]
SIG
MCBrd.CBx.25.Sel_NoChk
EN
[MCBrd.CBx.25.SetOpt]
0
1
MCBrd.CBx.25.On_NoChk
0
Figure 3.33-1 Synchrocheck mode selection for manual closing
SIG CSWI01.CILO.Disable
>=1
SIG BIinput.CILO.Disable
>=1
EN
[CSWI01.En_Cls_Blk]
SIG CSWI01.CILO.EnCls
SIG CSWI01.RmtCtrl
>=1
&
SIG BIinput.RmtCtrl
>=1
&
[CSWI01.t_PW_Cls]
SIG CSWI01.Cmd_RmtCtrl
SIG CSWI01.LocCtrl
CSWI01.Op_Cls
>=1
&
SIG BIinput.LocCtrl
SIG CSWI01.ManSynCls
0ms
>=1
SIG CSWI01.Cmd_LocCtrl
SIG MCBrd.CB1.25.On_SynChk
>=1
SIG MCBrd.CB1.25.Ok_Chk
SIG MCBrd.CB1.Alm_VTS
&
&
&
EN
[MCBrd.CB1.En_Alm_VTS]
EN
[MCBrd.CB1.25.En_VTS_Blk_SynChk]
EN
[MCBrd.CB1.En_Alm_VTS]
&
&
SIG MCBrd.CB1.Alm_VTS
EN
[MCBrd.CB1.25.En_VTS_Blk_DdChk]
EN
[MCBrd.CB1.25.En_LvL_DdB]
EN
[MCBrd.CB1.25.En_DdL_LvB]
EN
[MCBrd.CB1.25.En_DdL_DdB]
>=1
&
>=1
>=1
SIG MCBrd.CB1.25.Ok_Chk
SIG MCBrd.CB1.25.On_NoChk
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Figure 3.33-2 Logic diagram of closing circuit breaker 1
SIG CSWI02.CILO.Disable
>=1
SIG BIinput.CILO.Disable
>=1
EN
[CSWI02.En_Cls_Blk]
SIG CSWI02.CILO.EnCls
SIG CSWI02.RmtCtrl
>=1
&
SIG BIinput.RmtCtrl
>=1
&
[CSWI02.t_PW_Cls]
SIG CSWI02.Cmd_RmtCtrl
SIG CSWI02.LocCtrl
0ms
CSWI02.Op_Cls
>=1
&
SIG BIinput.LocCtrl
SIG CSWI02.ManSynCls
>=1
SIG CSWI02.Cmd_LocCtrl
SIG MCBrd.CB2.25.On_SynChk
>=1
SIG MCBrd.CB2.25.Ok_Chk
SIG MCBrd.CB2.Alm_VTS
&
&
&
EN
[MCBrd.CB2.En_Alm_VTS]
EN
[MCBrd.CB2.25.En_VTS_Blk_SynChk]
EN
[MCBrd.CB2.En_Alm_VTS]
&
&
SIG MCBrd.CB2.Alm_VTS
EN
[MCBrd.CB2.25.En_VTS_Blk_DdChk]
EN
[MCBrd.CB2.25.En_LvL_DdB]
EN
[MCBrd.CB2.25.En_DdL_LvB]
EN
[MCBrd.CB2.25.En_DdL_DdB]
>=1
&
>=1
>=1
SIG MCBrd.CB2.25.Ok_Chk
SIG MCBrd.CB2.25.On_NoChk
Figure 3.33-3 Logic diagram of closing circuit breaker 2
As shown in Figure 3.33-3, for double circuit breakers application, both the first closing command
“CSWI01.Op_Cls” and the second closing command “CSWI02.Op_Cls”, which are controlled by
synchrocheck logic, can be used for CB closing, otherwise, the logic of the second closing
command “CSWI02.Op_Cls” should comply with Figure 3.33-4.
After receiving a closing command, this device will continuously check whether the 2 voltages
(Incoming voltage and reference voltage) involved in synchronism check (or dead check) can meet
the criteria. Within the duration of [MCBrd.CBx.25.t_Wait_Chk], if the synchronism check (or dead
check) criteria are not met, the signal “MCBrd.CBx.25.Ok_Chk” will be set as “0”; if the
synchronism check (or dead check) criteria are met, the signal “MCBrd.CBx.25.Ok_Chk” will be
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set as “1”.
When any of the following criteria is fulfilled, an alarm signal [MCBrd.CBx.Alm_VTS] will be issued
with a time delay of 1.25s, and drop off with a time delay of 10s after three phases voltage restored
to normal. The alarm signal will block the closing command for circuit breaker.
1.
The negative-sequence voltage is greater than 8V.
2.
The positive-sequence voltage is smaller than 30V, and any phase current is greater than
0.04In.
SIG
CSWIxx.CILO.Disable
SIG
BIinput.CILO.Disable
EN
[CSWIxx.En_Cls_Blk]
SIG
CSWIxx.CILO.EnCls
SIG
CSWIxx.RmtCtrl
SIG
BIinput.RmtCtrl
SIG
CSWIxx.Cmd_RmtCtrl
SIG
CSWIxx.LocCtrl
SIG
BIinput.LocCtrl
SIG
CSWIxx.Cmd_LocCtrl
>=1
>=1
&
[CSWIxx.t_PW_Cls]
0ms
[CSWIxx.Op_Cls]
>=1
&
>=1
>=1
&
Figure 3.33-4 Logic diagram of closing switch (xx=02~15)
Access the menu “Local Cmd→Control” to issue control command locally, and this signal
“CSWIxx.Cmd_LocCtrl” will be set as “1”. Remote control commands from SCADA/CC can be
transmitted via IEC 60870-5-103 protocol or IEC 61850 protocol, and this signal
“CSWIxx.Cmd_RmtCtrl” will be set as “1”.
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SIG CSWI01.CILO.Disable
>=1
SIG BIinput.CILO.Disable
>=1
EN
[CSWI01.En_Opn_Blk]
&
[CSWI01.t_PW_Opn]
0ms
CSWI01.Op_Opn
[CSWI02.t_PW_Opn]
0ms
CSWI02.Op_Opn
SIG CSWI01.CILO.EnOpn
SIG CSWI01.RmtCtrl
>=1
&
SIG BIinput.RmtCtrl
>=1
SIG CSWI01.Cmd_RmtCtrl
SIG CSWI01.LocCtrl
>=1
&
SIG BIinput.LocCtrl
SIG CSWI01.ManOpn
>=1
SIG CSWI01.Cmd_LocCtrl
SIG CSWI02.CILO.Disable
>=1
SIG BIinput.CILO.Disable
>=1
EN
[CSWI02.En_Opn_Blk]
&
SIG CSWI02.CILO.EnOpn
SIG CSWI02.RmtCtrl
>=1
&
SIG BIinput.RmtCtrl
>=1
SIG CSWI02.Cmd_RmtCtrl
SIG CSWI02.LocCtrl
>=1
&
SIG BIinput.LocCtrl
SIG CSWI02.ManOpn
>=1
SIG CSWI02.Cmd_LocCtrl
Figure 3.33-5 Logic diagram of open circuit breaker
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SIG CSWIxx.CILO.Disable
>=1
SIG BIinput.CILO.Disable
>=1
EN
[CSWIxx.En_Opn_Blk]
&
[CSWIxx.t_PW_Opn]
SIG CSWIxx.CILO.EnOpn
SIG CSWIxx.RmtCtrl
0ms
CSWIxx.Op_Opn
>=1
&
SIG BIinput.RmtCtrl
>=1
SIG CSWIxx.Cmd_RmtCtrl
SIG CSWIxx.LocCtrl
>=1
&
SIG BIinput.LocCtrl
SIG CSWIxx.Cmd_LocCtrl
Figure 3.33-6 Logic diagram of open switch (xx=02~15)
The control output fulfills signal output circuit, and opens or closes circuit breaker, disconnector
and earth switch according to the control command. Object manipulation strictly performs three
steps: selection, check and execute, and perform output relay check, to ensure that the remote
control can be executed safely and reliably.
When logic interlock is enabled, the device can receive the programmable interlock logic. The
device can automatically initiate the interlock logic to determine whether to allow control
operations. The device provides corresponding settings ([CSWIxx.En_Opn_Blk] and
[CSWIxx.En_Cls_Blk]) for each control object. When they are set as “1”, the interlock function of
the corresponding control object is enabled. The interlock logic can be configured by using
PCS-Explorer, and downloaded to the device via the Ethernet port. If the interlock function is
enabled, but it is not configured the interlock logic, the result of the logic output is 0.
The control record is a file which is used to store remote control command records of this device
circularly. If the record number is to 256, the storage area of the control record will be full. If this
device has received a new remote command, this device will delete the oldest remote control
record, and then store the latest remote control record.
There are 15 configuration pages corresponding to 15 control outputs in total respectively. Each
configuration page can finish some signals configuration, including remote control, local control,
disable interlock blocking, and so on.
In order to conveniently configure control output, the same output signals, including
“BIinput.RmtCtrl”, “BIinput.LocCtrl” and “BIinput.CILO.Disable”, are available after processing
binary signals internally, as shown in figure below.
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Figure 3.33-7 Configuration page of control output 01 (default configuration)
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Figure 3.33-8 Configuration page of control output 02 (default configuration)
Control output 03~15 is as same as control output 02.
The configuration rule about remote control and local control to binary outputs is as bellow:
X means that it is not configured.
Remote
Local
CSWIxx.
BIinput.
CSWIxx.
BIinput.
RmtCtrl
RmtCtrl
LocCtrl
LocCtrl
X
X
X
X
0
X
X
X
X
0
X
X
1
X
X
X
X
1
X
X
X
X
0
X
X
X
X
0
X
X
1
X
X
X
X
1
0
X
0
X
0
X
X
0
X
0
0
X
X
0
X
0
0
X
1
X
X
0
1
X
0
X
X
1
Control Mode
Neither Local control nor remote control are permissible.
Only local control is permissible.
Only remote control is permissible.
Only remote control is permissible.
Only local control is permissible.
Neither Local control nor remote control are permissible.
Only local control is permissible.
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X
0
X
1
1
X
0
X
1
X
X
0
X
1
0
X
X
1
X
0
1
X
1
X
1
X
X
1
X
1
1
X
X
1
X
1
Only remote control is permissible.
Both Local control and remote control are permissible.
For remote control or local control, they can be configured by either of “CSWIxx.RmtCtrl” and
“BIinput.RmtCtrl”, or either of “CSWIxx.LocCtrl” and “BIinput.LocCtrl”.
2. Synchrocheck
Three synchrocheck modes are designed for CB closing: no check mode, dead check mode and
synchronism check mode, if any one of the condition of three synchrocheck modes satisfied, then
synchrocheck signal “MCBrd.CBx.25.Ok_Chk” will be asserted.
The synchronism check function measures the conditions across the circuit breaker and compares
them with the corresponding settings. The output is only given if all measured quantities are
simultaneously within their set limits. Compared to the synchronism check for auto-reclosing, an
additional criterion is applied to check the rate of frequency change (df/dt) between both sides of
the CB.
When the following four conditions are all met, the synchronism check is successful.
1) Phase angle difference between incoming voltage and reference voltage is less than the
setting [MCBrd.CBx.25.phi_Diff]
2) Frequency difference between incoming voltage and reference voltage is less than
[MCBrd.CBx.25.f_Diff]
3) Voltage difference between incoming voltage and reference voltage is less than
[MCBrd.CBx.25.U_Diff]
4) Rate of frequency change between incoming voltage and reference voltage is less than
[MCBrd.CBx.25.df/dt]
The dead check function measures the amplitude of line voltage and bus voltage at both sides of
the circuit breaker, and then compare them with the live check setting [MCBrd.CBx.25.U_Lv] and
the dead check setting [MCBrd.CBx.25.U_Dd]. The dead check is successful when the measured
quantities comply with the criteria.
When this device is set to work in no check mode and receives a closing command, CB will be
closed without synchronism check and dead check.
Synchrocheck for manual closing also supports voltage switching. In general, voltage switching is
fulfilled by external circuit ([CBx.CBConfigMode]=NoVoltSel). If using this module to fulfill voltage
switching, the busbar arrangement should be determined by the setting [CBx.CBConfigMode],
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including:

Double busbars arrangement ([CBx.CBConfigMode]=DblBusOneCB)

1½ breakers arrangement ([CBx.CBConfigMode]=3/2BusCB or 3/2TieCB)
Analog input defines four voltage inputs, UL1, UB1, UL2, UB2, and their usage are as follow:
UL1: it connects with three-phase protection voltages (from line or busbar), which mainly are used
by distance protection, voltage protection and so on. According to the voltage switching result,
synchrocheck logic choose one voltage to be used for synchrocheck function, synchrocheck
function requires to judgment the phase identification information of the voltage, which is
determined by the setting [MCBrd.CBx.25.Opt_Source_UL1]. If voltage switching function is not
used, the reference voltage will be selected from UL1 fixedly.
UB1: according to the voltage switching result, synchrocheck logic determined whether the voltage
is used for synchrocheck function. Synchrocheck function requires to judgment the phase
identification information of the voltage, which is determined by the setting
[MCBrd.CBx.25.Opt_Source_UB1]. If voltage switching function is not used, UB1 will be taken as
the synchronism voltage.
UL2: according to the voltage switching result, synchrocheck logic determined whether the voltage
is used for synchrocheck function. Synchrocheck function requires to judgment the phase
identification information of the voltage, which is determined by the setting
[MCBrd.CBx.25.Opt_Source_UL2]. When voltage switching is available, it is only available for 1½
breakers arrangement, it is fixedly connected to the voltage of the other line of the same diameter
in 1½ breakers arrangement.
UB2: according to the voltage switching result, synchrocheck logic determined whether the voltage
is used for synchrocheck function. Synchrocheck function requires to judgment the phase
identification information of the voltage, which is determined by the setting
[MCBrd.CBx.25.Opt_Source_UB2]. When voltage switching is available, it is connected to
synchronism voltage for double busbars arrangement or 1½ breakers arrangement.
Synchrocheck for manual closing supports voltage switching function, and the switching logic is as
same as that of synchrocheck for protection closing. The setting [CBx.CBConfigMode] should be
set according to the actual primary busbar arrangement, otherwise, the voltage switching of
synchrocheck for manual closing will fail, so as to block manual closing with synchrocheck.
During dead charge check, when only single-phase voltage is connected to UL1, live voltage is
valid if the setting [VTS.En] should be set as “0” and the connected single-phase voltage is higher
than the setting [MCBrd.CBx.25.U_Lv], otherwise, live voltage is regarded as live only when three
phases voltages are all higher than [MCBrd.CBx.25.U_Lv].
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3.33.3 Function Block Diagram
CSWI01
CSWI01.CILO.EnOpn
CSWI01.Op_Opn
CSWI01.CILO.EnCls
CSWI01.Op_Cls
CSWI01.RmtCtrl
CSWI01.LocCtrl
CSWI01.CILO.Disable
CSWI02
CSWI02.CILO.EnOpn
CSWI02.Op_Opn
CSWI02.CILO.EnCls
CSWI02.Op_Cls
CSWI02.RmtCtrl
CSWI02.LocCtrl
CSWI02.CILO.Disable
CSWIxx
CSWIxx.CILO.EnOpn
CSWIxx.Op_Opn
CSWIxx.CILO.EnCls
CSWIxx.Op_Cls
CSWIxx.RmtCtrl
CSWIxx.LocCtrl
CSWIxx.CILO.Disable
BIinput
BIinput.RmtCtrl
BIinput.RmtCtrl
BIinput.LocCtrl
BIinput.LocCtrl
BIinput.CILO.Disable
BIinput.CILO.Disable
CSWI01.ManSynCls
CSWI01.ManOpn
CSWI02.ManSynCls
CSWI02.ManOpn
xx can be from 02 or 03 to 15
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3.33.4 I/O Signals
Table 3.33-1 I/O signals of control
No.
Input Signal
Description
From receiving a closing command, this device will continuously check
whether the 2 voltages (Incoming voltage and reference voltage)
involved in synchronism check (or dead check) can meet the criteria.
1
MCBrd.CBx.25.Ok_Chk
Within the duration of [MCBrd.CBx.25.t_Wait_Chk], if the synchronism
check (or dead check) criteria are not met, [MCBrd.CBx.25.Ok_Chk] will
be set as “0”; if the synchronism check (or dead check) criteria are met,
[MCBrd.CBx.25.Ok_Chk] will be set as “1”.
2
CSWIxx.CILO.EnOpn
3
CSWIxx.CILO.EnCls
It is used to indicate the interlock status of open output for binary output
No.xx. (xx=01~15)
It is used to indicate the interlock status of closing output for binary
output No.xx. (xx=01~15)
It is used to select the local control to binary output No.xx. When the
4
CSWIxx.LocCtrl
local control is active, binary output No.xx can only be locally controlled.
(xx=01~15)
It is used to select the remote control to binary output No.xx. When the
5
CSWIxx.RmtCtrl
remote control is active, binary output No.xx can only be remotely
controlled from SCADA or control centers. (xx=01~15)
It is used to disable the interlock blocking function for control output. If
6
CSWIxx.CILO.Disable
the signal “CSWIxx.CILO.Disable” is “1”, binary output No.xx will not be
blocked by interlock conditions. (xx=01~15)
7
BIinput.LocCtrl
It is used to select the local control to all binary outputs. When the local
control is active, all binary outputs can only be locally controlled.
It is used to select the remote control to all binary outputs. When the
8
BIinput.RmtCtrl
remote control is active, all binary outputs can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
9
BIinput.CILO.Disable
the signal “BIinput.CILO.Disable” is “1”, all binary outputs will not be
blocked by interlock conditions.
When the condition of local control is met and the signal
10
CSWI01.ManSynCls
“CSWI01.ManSynCls” is “1”, the output contact [BO_CtrlCls01] is closed
to execute manually closing the circuit breaker with synchrocheck.
When the condition of local control is met and the signal
11
CSWI01.ManOpn
“CSWI01.ManOpn” is “1”, the output contact [BO_CtrlOpn01] is closed
to execute manually open the circuit breaker.
When the condition of local control is met and the signal
12
CSWI02.ManSynCls
“CSWI02.ManSynCls” is “1”, the output contact [BO_CtrlCls02] is closed
to execute manually closing the circuit breaker with synchrocheck. (for
double circuit breakers application)
13
CSWI02.ManOpn
When the condition of local control is met and the signal
“CSWI02.ManOpn” is “1”, the output contact [BO_CtrlOpn02] is closed
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to execute manually open the circuit breaker. (for double circuit breakers
application)
14
MCBrd.CBx.25.Sel_SynChk
Synchronism check for manual closing is selected.
15
MCBrd.CBx.25.Sel_NoChk
No check for manual closing is selected.
No.
Output Signal
Description
1
CSWIxx.Op_Opn
Open output of binary output No.xx. (xx=01~15)
2
CSWIxx.Op_Cls
Closing output of binary output No.xx. (xx=01~15)
3
BIinput.LocCtrl
In order to be convenient to user configure control output, three same
4
BIinput.RmtCtrl
output signals with input signals are available. The relationship with 15
binary output have been configured inside the device. The user only
assigns a specific binary input to input signal, the relevant function can
5
BIinput.CILO.Disable
be gained. If some binary output need not be controlled by three signals,
please cancel the configuration by PCS-Explorer, and configure it
independently.
6
MCBrd.CBx.Alm_VTS
VT circuit of circuit breaker No.x is abnormal.
3.33.5 Settings
Table 3.33-2 Function settings
No.
Name
Range
Step
Unit
Remark
Enabling/disabling alarm function
1
MCBrd.CBx.En_Alm_VTS
when VT circuit is abnormal
0 or 1
0: disable
1: enable
Table 3.33-3 Synchrocheck settings
No.
Name
Range
Step
Unit
Remark
Voltage selecting mode of
1
MCBrd.CBx.25.Opt_Source_UL1
Ua
line 1
Ub
Ua: A-phase voltage
Uc
Ub: B-phase voltage
Uab
Uc: C-phase voltage
Ubc
Uab: AB-phase voltage
Uca
Ubc: BC-phase voltage
Uca: CA-phase voltage
Voltage selecting mode of
2
MCBrd.CBx.25.Opt_Source_UB1
Ua
bus 1
Ub
Ua: A-phase voltage
Uc
Ub: B-phase voltage
Uab
Uc: C-phase voltage
Ubc
Uab: AB-phase voltage
Uca
Ubc: BC-phase voltage
Uca: CA-phase voltage
3
MCBrd.CBx.25.Opt_Source_UL2
Ua
Voltage selecting mode for
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No.
Name
Range
Step
Unit
Remark
Ub
line 2
Uc
Ua: A-phase voltage
Uab
Ub: B-phase voltage
Ubc
Uc: C-phase voltage
Uca
Uab: AB-phase voltage
Ubc: BC-phase voltage
Uca: CA-phase voltage
Voltage selecting mode for
4
MCBrd.CBx.25.Opt_Source_UB2
Ua
bus 2
Ub
Ua: A-phase voltage
Uc
Ub: B-phase voltage
Uab
Uc: C-phase voltage
Ubc
Uab: AB-phase voltage
Uca
Ubc: BC-phase voltage
Uca: CA-phase voltage
5
MCBrd.CBx.25.U_Dd
0.05Un~0.8Un
0.001
V
6
MCBrd.CBx.25.U_Lv
0.5Un~Un
0.001
V
Voltage threshold of dead
check for manual closing
Voltage threshold
of
live
check for manual closing
Compensation coefficient of
7
MCBrd.CBx.25.K_Usyn
0.20-5.00
synchronism
voltage
for
manual closing
Phase difference limit
8
MCBrd.CBx.25.phi_Diff
0~ 89
1
deg
synchronism
check
of
for
manual closing
Compensation
9
MCBrd.CBx.25.phi_Comp
0~359
difference
1
of
phase
between
synchronous
two
voltages
for
manual closing
Frequency difference limit of
10
MCBrd.CBx.25.f_Diff
0.02~1.00
0.01
Hz
synchronism
check
for
manual closing
Voltage difference limit of
11
MCBrd.CBx.25.U_Diff
0.02Un~0.8Un
0.01
V
synchronism
check
for
manual closing
Synchrocheck
mode
selection for manual closing
12
MCBrd.CBx.25.SetOpt
0, 1
1
0: determined by external
signal
1: determined by the setting
Enabling/disabling
13
MCBrd.CBx.25.En_SynChk
0 or 1
synchronism
check
for
manual closing
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No.
Name
Range
Step
Unit
Remark
0: disable
1: enable
Enabling/disabling dead line
and dead bus (DLDB) check
14
MCBrd.CBx.25.En_DdL_DdB
0 or 1
for manual closing
0: disable
1: enable
Enabling/disabling dead line
and live bus (DLLB) check
15
MCBrd.CBx.25.En_DdL_LvB
0 or 1
for manual closing
0: disable
1: enable
Enabling/disabling live line
and dead bus (LLDB) check
16
MCBrd.CBx.25.En_LvL_DdB
0 or 1
for manual closing
0: disable
1: enable
Enabling/disabling
17
MCBrd.CBx.25.En_NoChk
manual
closing without any check
0 or 1
0: disable
1: enable
Threshold
of
rate
of
frequency change between
18
MCBrd.CBx.25.df/dt
0.00~3.00
0.01
Hz/s
both
sides
synchronism
of
CB
for
check
of
manual closing
Enabling/disabling frequency
19
MCBrd.CBx.25.En_df/dtChk
slip check for manual closing
0 or 1
0: disable
1: enable
Circuit breaker closing time
for manual closing
20
MCBrd.CBx.25.t_Close_CB
20~1000
1
ms
It is the time from receiving
closing command pulse till
the CB is completely closed.
From receiving a closing
command, this device will
continuously check whether
21
MCBrd.CBx.25.t_Wait_Chk
5~30
0.001
s
between incoming voltage
and
reference
involved
in
voltage
synchronism
check (or dead check) can
meet
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No.
Name
Range
Step
Unit
Remark
synchronism check (or dead
check) criteria are not met
within the duration of this
time delay, the failure of
synchronism-check (or dead
check) will be confirmed.
Enabling/disabling
synchronism
22
MCBrd.CBx.25.En_VTS_Blk_SynChk
block
check
for
manual closing when VT
0 or 1
circuit is abnormal
0: disable
1: enable
Enabling/disabling
dead
23
MCBrd.CBx.25.En_VTS_Blk_DdChk
check
for
block
manual
closing when VT circuit is
0 or 1
abnormal
0: disable
1: enable
Table 3.33-4 Dual point binary input settings
No.
Name
Range
Step
Unit
Remark
It is applied to configure the debouncing time
1
CSWIxx.t_DPU_DPS
0~60000
1
ms
for dual-point binary input No.xx. (xx=01,
02….15)
Table 3.33-5 Control settings
No.
Name
Range
Step
Unit
Remark
It is applied to configure the holding time to
1
CSWIxx.t_PW_Opn
0~60000
1
ms
open CB or disconnector for binary output
No.xx. (xx=01, 02….15)
It is applied to configure the holding time to
2
CSWIxx.t_PW_Cls
0~60000
1
ms
close CB or disconnector for binary output
No.xx. (xx=01, 02….15)
Table 3.33-6 Interlock settings
No.
Name
Range
Step
Unit
Remark
Enabling/disabling open output of binary
output No.xx controlled by the interlocking
1
CSWIxx.En_Opn_Blk
0 or 1
logic (xx=01, 02….15)
0: disable
1: enable
2
CSWIxx.En_Cls_Blk
Enabling/disabling closing output of binary
0 or 1
output No.xx controlled by the interlocking
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No.
Name
Range
Step
Unit
Remark
logic (xx=01, 02….15)
0: disable
1: enable
3.34 Faulty Phase Selection
3.34.1 General Application
Faulty phase selection is used to discriminate faulty phase for all kinds of fault type. If protection
element operates, faulty phase selection is succeeded and the device output tripping command.
Faulty phase selection is adaptive to both earthed system and unearthed system. For unearthed
system, earthed protection elements should be disabled, such as phase-to-ground distance
protection, earth fault protection, and only phase-to-phase protection elements are enabled, such
as phase-to-phase distance protection, phase overcurrent protection.
1.
Detecting the variation of operating voltage
2.
Detecting the phase difference between I0 and I2A
3.
When phase overcurrent element operates, pickup phase due to overcurrent is judged as
faulty phase.
4.
When phase overvoltage element operates, pickup phase due to overvoltage is judged as
faulty phase.
5.
When phase undervoltage element operates, pickup phase due to undervoltage is judged as
faulty phase.
3.34.2 Function Description
3.34.2.1 Variation of Operating Voltage (Faulty Phase Selection Element 1)
1.
Variation of phase operating voltage
1)
Phase A: ΔUOPA
2)
Phase B: ΔUOPB
3)
Phase C: ΔUOPC
2.
Variation of phase-to-phase operating voltage
1)
Phase AB: ΔUOPAB
2)
Phase BC: ΔUOPBC
3)
Phase CA: ΔUOPCA
ΔUOΦMAX=Max(ΔUOPA, ΔUOPB, ΔUOPC)
ΔUOΦΦMAX=Max(ΔUOPAB, ΔUOPBC, ΔUOPCA)
If ΔUOΦMAX is several times higher than the variation of operating voltages of other two phases, the
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single-phase fault is ensured, otherwise, the multi-phase fault is ensured.
Table 3.34-1 Relation between ΔUOΦMAX and faulty phase
ΔUOΦMAX or ΔUOΦΦMAX
Fault phase
ΔUOPA
Phase A
ΔUOPB
Phase B
ΔUOPC
Phase C
ΔUOPAB
Phase AB
ΔUOPBC
Phase BC
ΔUOPCA
Phase CA
3.34.2.2 I0 and I2A (Faulty Phase Selection Element 2)
The phase selection algorithm uses the angle relation between I 0 and I2A of the device. As shown
in Figure 3.34-1, there are three faulty phase selection regions.
Region A
60°
-60°
Region B
Region C
180°
Figure 3.34-1 The region of faulty phase selection
Depended on the phase relation between I0 and I2A, the faulty phase can be determined.
1.
-60º<Arg(I0/I2A)<60º, region A is selected, possible faulty phase is phase A or phase BC.
2.
60º<Arg(I0/I2A)<180º, region B is selected, possible faulty phase is phase B or phase CA.
3.
180º<Arg(I0/I2A)<300º, region C is selected, possible faulty phase is phase C or phase AB.
For single-phase earth fault, I0 and I2 of faulty phase are in-phase and its distance element
operates.
For phase-to-phase earth fault, I0 and I2 of non-faulty phase are in-phase but its distance element
does not operate.
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3.34.2.3 Phase Current or Phase Voltage (Faulty Phase Selection Element 3)
When phase overcurrent element or phase voltage element, the corresponding phase which is
overcurrent, overvoltage or undervoltage will be judged as faulty phase.
SIG
50/51Pi.Op
SIG
50/51Pi.StA
SIG
87STB.Op
SIG
87STB.StA
SIG
50PVT.Op
SIG
50PVT.StA
SIG
27Pz.Op
SIG
27Pz.St1
SIG
59Pz.Op
SIG
59Pz.St1
SIG
50/51Pi.Op
SIG
50/51Pi.StB
SIG
87STB.Op
SIG
87STB.StB
SIG
50PVT.Op
SIG
50PVT.StB
SIG
27Pz.Op
SIG
27Pz.St2
SIG
59Pz.Op
SIG
59Pz.St2
&
&
>=1
>=1
Phase A
&
&
>=1
&
&
&
>=1
>=1
Phase B
&
&
>=1
&
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3 Operation Theory
SIG
50/51Pi.Op
SIG
50/51Pi.StC
SIG
87STB.Op
SIG
87STB.StC
SIG
50PVT.Op
SIG
50PVT.StC
SIG
27Pz.Op
SIG
27Pz.St3
SIG
59Pz.Op
SIG
59Pz.St3
&
&
>=1
>=1
Phase C
&
&
>=1
&
Figure 3.34-2 The logic of faulty phase selection
i= 1, 2, 3, 4
z=1, 2, 3
3.34.3 Function Block Diagram
PhSel
PhSA
PhSB
PhSC
GndFlt
3.34.4 I/O Signals
Table 3.34-2 I/O signals of faulty phase selection
No.
Output Signal
Description
1
PhSA
Phase-A is selected as faulty phase
2
PhSB
Phase-B is selected as faulty phase
3
PhSC
Phase-C is selected as faulty phase
4
GndFlt
Earth fault
NOTICE!
For single phase earth fault, for example phase-A earth fault, PhsA” and “GndFlt”
operate. For phase-to-phase fault, for example phase-BC short-circuit fault, “PhsB”
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3 Operation Theory
and “PhsC” operate. For two phase earth fault, for example phase-BC earth fault,
“PhsB”, “PhsC” and “GndFlt” operate. For three phases fault, “PhsA”, “PhsB” and
“PhsC” operate.
3.35 Fault Location
3.35.1 Application
The main objective of line protection is fast, selective and reliable operation for faults on a
protected line section. Besides this, information on distance to fault is very important for those
involved in operation and maintenance. Reliable information on the fault location greatly
decreases the outage of the protected lines and increases the total availability of a power system.
This fault location function cannot be used for the transmission line with series compensation.
3.35.2 Function Description
3.35.2.1 Fundamental Principle
The fault location is an essential function to various line protection devices, after selecting faulty
phase, it measures and indicates the distance to the fault with high accuracy. Thus, the fault can
be quickly located for repairs. The calculation algorithm considers the effect of load currents,
double-end infeed and additional fault resistance. Both double-end fault location and single-end
fault location are available in line differential relay, but only single-end fault location is provided in
other relays. The calculation equation is:
Where:
Dist: The distance of fault location according to the Zcalc (km)
Zcalc: The impedance value calculated from the location of protection device to fault point
Zl: The impedance value of the whole line + mutual impedance
Length: The input length of transmission line (km)
3.35.2.2 Mutual Compensation
When an earth fault occurred on a line of parallel lines arrangement, a distance relay at one end of
the faulty line will tend to underreach whilst the distance relay at the other end will tend to
overreach. Usually the degree of underreach or overreach is acceptable, however, for cases
where precise fault location is required for long lines with high mutual coupling, mutual
compensation is then required to improve the distance measurement. Practically, the mutual effect
between the parallel lines is insignificant to positive and negative sequence and thus the mutual
compensation is only for zero sequence
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3 Operation Theory
A
Ia
B
ZM
k
C
Ic
ZS
D
(1-k)ZL
kZL
ZL
The principle in the application of mutual compensation is shown as follows with the aid of
following sequence network diagram figure. The diagram indicates a parallel lines arrangement
with an earth fault at location k on line CD.
The equivalent sequence network for an earth fault on a parallel lines arrangement with single
source is shown as below.
Ia1
ZL1
ZS1
kZL1
(1-k)ZL1
Ic1
Ia2
ZL2
ZS2
kZL2
(1-k)ZL2
Ic2
Ia0
ZL0
ZS0
Z0M
kZL0
(1-k)ZL0
Ic0
Figure 3.35-1 Equivalent sequence network
The device at location C without mutual compensation will have voltage URC and current IRC
measured as shown in the expression
URC is the voltage of the device at location C.
If the line is fully transposed, ZL1=ZL2, Then
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3 Operation Theory
The impedance presented to the device is:
For an earth fault,
,
With the mutual compensation enabled,
(Actual distance of the fault)
The residual current from the parallel line should be added to the device. It should be connected to
terminal 08 and star point of the parallel line CT connected to terminal 07 as shown in the following
figure. Please note the connection diagram and the terminal numbers are for reference only. The
final connection terminals are subject to the device configuration at site.
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3 Operation Theory
A
B
C
P2
S2
P2
S2
P1
S1
P1
S1
02
01
02
01
04
03
04
03
06
05
06
05
08
07
08
07
NOTICE!
The mutual compensation only is to improve the accuracy of fault location for parallel
lines arrangement, and it is not used by settings calculation of earth fault protections.
3.35.3 Function Block Diagram
FL
FPS_Fault
FD.Pkp
Fault_Location
Fault_Phase
Fault_Phase_Curr
Fault_Resid_Curr
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3.35.4 I/O Signals
Table 3.35-1 I/O signals of fault location
No.
Input Signal
Description
1
FPS_Fault
Faulty phase selection
2
FD.Pkp
The device picks up
No.
Output Signal
Description
1
Fault_Location
The result of fault location
2
Faulty_Phase
The selected faulty phase
3
Fault_Phase_Curr
Maximum faulty current
4
Fault_Resid_Curr
Maximum residual current
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4 Supervision
4 Supervision
Table of Contents
4 Supervision ........................................................................................ 4-a
4.1 Overview .......................................................................................................... 4-1
4.2 Supervision Alarms ......................................................................................... 4-1
4.3 Relay Self-supervision.................................................................................... 4-8
4.3.1 Relay Hardware Monitoring ................................................................................................. 4-8
4.3.2 Fault Detector Monitoring .................................................................................................... 4-8
4.3.3 Check Setting ...................................................................................................................... 4-8
4.4 AC Input Monitoring ........................................................................................ 4-9
4.4.1 Voltage/current Drift Monitoring and Auto-adjustment......................................................... 4-9
4.4.2 Sampling Monitoring ............................................................................................................ 4-9
4.5 Secondary Circuit Monitoring ........................................................................ 4-9
4.5.1 Opto-coupler Power Supervision ......................................................................................... 4-9
4.5.2 Circuit Breaker Supervision ................................................................................................. 4-9
List of Tables
Table 4.2-1 Alarm description..................................................................................................... 4-1
Table 4.2-2 Troubleshooting ....................................................................................................... 4-6
PCS-902 Line Distance Relay
4-a
Date: 2019-03-01
4 Supervision
4-b
PCS-902 Line Distance Relay
Date: 2019-03-01
4 Supervision
4.1 Overview
Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults occurred on power system. When the device is in energizing process before the
LED “HEALTHY” is on, the device need to be checked to ensure no abnormality. Therefore, the
automatic supervision function, which checks the health of the protection system when startup and
during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.
When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed If required.
4.2 Supervision Alarms
Hardware circuit and operation status of the device are self-supervised continuously. If any
abnormal condition is detected, information or report will be displayed and a corresponding alarm
will be issued.
A minor abnormality may block a certain number of protections functions while the other functions
can still work. However, if severe hardware failure or abnormality, such as PWR module failure,
DC converter failure and so on, are detected, all protection functions will be blocked and the LED
“HEALTHY” will be extinguished and blocking output contacts BO_FAIL will be given. The
protective device then can not work normally and maintenance is required to eliminate the failure.
All the alarm signals and the corresponding handling suggestions are listed below.
NOTICE!
If the device is blocked or alarm signal is sent during operation, please do find out its
reason with the help of self-diagnostic record. If the reason can not be found at site,
please notify the factory NR. Please do not simply press button “TARGET RESET” on
the protection panel or re-energize on the device.
Table 4.2-1 Alarm description
No.
Item
Description
Blocking Device
Fail Signals
The device fails.
1
Fail_Device
This signal will be pick up if any fail signal picks up and it
Blocked
will drop off when all fail signals drop off.
2
Fail_Setting_OvRange
Set value of any setting is out of scope.
This signal will pick up instantaneously and will be
PCS-902 Line Distance Relay
Blocked
4-1
Date: 2019-03-01
4 Supervision
No.
Item
Description
Blocking Device
latched unless the recommended handling suggestion is
adopted.
3
Fail_BoardConfig
Mismatch between the configuration of plug-in modules
and the designing drawing of an applied-specific project.
Blocked
After configuration file is updated, settings of the file and
settings saved on the device are not matched.
4
Fail_SettingItem_Chgd
This signal will pick up instantaneously and will be
Blocked
latched unless the recommended handling suggestion is
adopted.
Error is found during checking memory data.
5
Fail_Memory
This signal will pick up instantaneously and will be
latched unless the recommended handling suggestion is
Blocked
adopted.
Error is found during checking settings.
6
Fail_Settings
This signal will pick up instantaneously and will be
latched unless the recommended handling suggestion is
Blocked
adopted.
DSP chip is damaged.
7
Fail_DSP
This signal will pick up instantaneously and will be
latched unless the recommended handling suggestion is
Blocked
adopted.
Communication between two DSP chips is abnormal
8
Fail_DSP_Comm
This signal will pick up instantaneously and will drop off
Blocked
instantaneously.
Software configuration is incorrect.
9
Fail_Config
This signal will pick up instantaneously and will be
latched unless the recommended handling suggestion is
Blocked
adopted.
AC current and voltage samplings are abnormal.
10
Fail_Sample
This signal will pick up with a time delay of 200ms and
will be latched unless the recommended handling
Blocked
suggestion is adopted.
11
MCBrd.Fail_Sample
12
MCBrd.Fail_Settings
For DSP plug-in module for measurement and control in
slot 06, AC current and voltage samplings are abnormal
Error is found during checking the settings of DSP
plug-in module for measurement and control in slot 06.
Blocked
Blocked
Alarm Signals
The device is abnormal.
13
Alm_Device
This signal will be pick up if any alarm signal picks up
Unblocked
and it will drop off when all alarm signals drop off.
14
Alm_Insuf_Memory
15
Alm_CommTest
The memory of MON plug-in module is insufficient.
The device is in the communication test mode.
This signal will pick up instantaneously and will drop off
4-2
Unblocked
Unblocked
PCS-902 Line Distance Relay
Date: 2019-03-01
4 Supervision
No.
Item
Description
Blocking Device
instantaneously.
The error is found during MON module checking
16
Alm_Settings_MON
settings of device.
This signal will pick up with a time delay of 10s and will
Unblocked
be latched unless re-powering or rebooting the device.
The error is found during checking the version of
17
Alm_Version
software downloaded to the device.
This signal will pick up instantaneously and will drop off
Unblocked
instantaneously.
The active group set by settings in device and that set
18
Alm_BI_SettingGrp
by binary input are not matched.
This signal will pick up instantaneously and will drop off
Unblocked
instantaneously.
Data frame is abnormal between two DSP modules.
19
Alm_DSP_Frame
This signal will pick up instantaneously and will drop off
Unblocked
instantaneously.
The power supply of BI plug-in module in slot xx is
20
Bxx.Alm_OptoDC
abnormal.
This signal will pick up with a time delay of 10s and will
Unblocked
drop off with a time delay of 10s.
Fault detector element operates for longer than 50s.
21
Alm_Pkp_FD
This signal will pick up with a time delay of 50s and will
Unblocked
drop off with a time delay of 10s.
Neutral current fault detector element operates for
22
Alm_Pkp_I0
longer than 10s.
This signal will pick up with a time delay of 10s and will
Unblocked
drop off with a time delay of 10s.
Protection VT circuit fails.
23
VTS.Alm
This signal will pick up with a time delay [VTS.t_DPU]
Unblocked
and will drop off with a time delay [VTS.t_DDO].
Protection VT circuit of neutral point fails.
24
VTNS.Alm
This signal will pick up with a time delay [VTS.t_DPU]
Unblocked
and will drop off with a time delay [VTS.t_DDO].
VT circuit of circuit breaker No.x is abnormal.
25
MCBrd.CBx.Alm_VTS
This signal will pick up with a time delay of 1.25s and will
Unblocked
drop off with a time delay of 10s.
CT circuit of corresponding circuit breaker No.x fails.
26
CBx.CTS.Alm
This signal will pick up with a time delay of 10s and will
Unblocked
drop off with a time delay of 10s.
The
27
CBx.Alm_52b
auxiliary
normally
closed
contact
(52b)
of
corresponding circuit breaker No.x is abnormal.
This signal will pick up with a time delay of 10s and will
Unblocked
drop off with a time delay of 10s.
PCS-902 Line Distance Relay
4-3
Date: 2019-03-01
4 Supervision
No.
Item
Description
Blocking Device
The device is in maintenance state.
28
BI_Maintenance
This signal will pick up with a time delay of 150ms and
Unblocked
will drop off with a time delay of 150ms.
29
Alm_TimeSyn
Unblocked
Time synchronization abnormality alarm.
It is an overall alarm signal and will be issued if any of
the following abnormalities is generated:
1. A network storm exists in the GOOSE network A or
GOOSE network B.
30
Alm_StatGOOSE
2. The GOOSE configuration file is incorrect.
3. The connection of GOOSE network A or GOOSE
Unblocked
network B is disconnected.
4. Between GOOSE control blocks received on network
and GOOSE control blocks defined in GOOSE
configuration file are unmatched.
Frequency of the system is higher than 65Hz or lower
31
Alm_Freq
than 45Hz.
This signal will pick up with a time delay of 100ms and
Unblocked
will drop off with a time delay of 10s.
32
Alm_Sparexx
(xx=01~08)
Spare alarm signals
The time delay of pickup and dropoff for these alarm
Unblocked
signals can be set by PCS-Explorer.
Protection Element Alarm Signals
Channel x is abnormal
33
FOx.Alm
This signal will pick up with a time delay of 100ms and
Unblocked
will drop off with a time delay of 1s.
Received ID from the remote end is not as same as the
34
FOx.Alm_ID
setting [FOx.RmtID] of the device in local end
This signal will pick up with a time delay of 100ms and
Unblocked
will drop off with a time delay of 1s.
No valid frame of channel x is received.
35
FOx.Alm_NoValFram
This signal will pick up with a time delay of 100ms and
Unblocked
will drop off with a time delay of 1s.
Rate of error code of channel x is larger than 40 error
36
FOx.Alm_CRC
codes per second.
This signal will pick up instantaneously and will drop off
Unblocked
with a time delay of 10s.
Channel x is out of service due to receive error codes
37
FOx.Alm_Off
after device picking up.
This signal will pick up instantaneously and will drop off
Unblocked
instantaneously.
38
FOx.Alm_Connect
Optical fibre of channel x is connected wrongly.
This signal will pick up with a time delay of 100ms and
4-4
Unblocked
PCS-902 Line Distance Relay
Date: 2019-03-01
4 Supervision
No.
Item
Description
Blocking Device
will drop off with a time delay of 1s.
Stage 3 of negative-sequence overcurrent protection
39
50/51Q3.Alm
40
59P1.Alm
Stage 1 of overvoltage protection alarms.
Unblocked
41
59P2.Alm
Stage 2 of overvoltage protection alarms.
Unblocked
42
59P3.Alm
Stage 3 of overvoltage protection alarms.
Unblocked
43
59G3.Alm
44
27P1.Alm
Stage 1 of undervoltage protection alarms.
Unblocked
45
27P2.Alm
Stage 2 of undervoltage protection alarms.
Unblocked
46
27P3.Alm
Stage 3 of undervoltage protection alarms.
Unblocked
47
49-1.Alm
48
49-2.Alm
operates to alarm.
Stage 3 of residual overvoltage protection operates to
alarm.
Stage 1 of thermal overload protection operates to
alarm.
Stage 2 of thermal overload protection operates to
alarm.
Unblocked
Unblocked
Unblocked
Unblocked
Differential current is abnormal.
49
87STB.Alm_Diff
This signal will pick up with a time delay of 1s and will
Unblocked
drop off with a time delay of 10s.
disconnector position is abnormal.
50
87STB.Alm_89b_DS
This signal will pick up with a time delay of 1s and will
Unblocked
drop off with a time delay of 10s.
51
46BC.Alm
52
CBx.Alm_Invalid_Sel
Broken-conductor protection operates to alarm.
Voltage selection corresponding to circuit breaker No.x
is invalid.
Unblocked
Unblocked
Synchronism voltage circuit corresponding to circuit
53
CBx.25.Alm_VTS_Usyn
breaker No.x is abnormal.
This signal will pick up with a time delay of 1.25s and will
Unblocked
drop off with a time delay of 10s.
Reference voltage circuit corresponding to circuit
54
CBx.25.Alm_VTS_Uref
breaker No.x is abnormal.
This signal will pick up with a time delay of 1.25s and will
Unblocked
drop off with a time delay of 10s.
55
CBx.79.Fail_Rcls
56
CBx.79.Fail_Chk
Auto-reclosing corresponding to circuit breaker No.x
fails.
Synchrocheck for AR corresponding to circuit breaker
No.x fails.
Unblocked
Unblocked
Input signal of receiving transfer trip is energized for
57
TT.Alm
longer than [TT.t_Op]+5s and it will drop off with a time
Unblocked
delay of 10s.
PCS-902 Line Distance Relay
4-5
Date: 2019-03-01
4 Supervision
Table 4.2-2 Troubleshooting
No.
Item
Handling suggestion
Fail Signals
1
Fail_Device
The signal is issued with other specific fail signals, and please refer to the
handling suggestion other specific alarm signals.
Please reset setting values according to the range described in the instruction
2
Fail_Setting_OvRange
manual, then re-power or reboot the device and the device will restore to
normal operation state.
5. Go to the menu “Information→Borad Info”, check the abnormality
information.
3
Fail_BoardConfig
6. For the abnormality board, if the board is not used, then remove, and if the
board is used, then check whether the board is installed properly and work
normally.
Please check the settings mentioned in the prompt message on the LCD, and
4
Fail_SettingItem_Chgd
go to the menu “Settings” and select “Confirm_Settings” item to confirm
settings. Then, the device will restore to normal operation stage.
5
Fail_Memory
Please inform the manufacture or the agent for repair.
6
Fail_Settings
Please inform the manufacture or the agent for repair.
7
Fail_DSP
8
Fail_DSP_Comm
9
Fail_Config
Chips are damaged and please inform the manufacture or the agent replacing
the module.
Please inform the manufacture or the agent for repair.
Please inform configuration engineers to check and confirm visualization
functions of the device
1. Please make the device out of service.
10
Fail_Sample
2. Then check if the analog input modules and wiring connectors connected to
those modules are installed at the position.
3. Re-power the device and the device will restore to normal operation state.
1. Please make the device out of service.
11
MCBrd.Fail_Sample
2. Then check if analog input modules and wiring connectors connected to
those modules are installed at the position.
3. Re-power the device and the device will restore to normal operation state.
12
MCBrd.Fail_Settings
Please inform the manufacturer or the agent for repair.
Alarm Signals
13
Alm_Device
14
Alm_Insuf_Memory
15
Alm_CommTest
16
Alm_Settings_MON
The signal is issued with other specific alarm signals, and please refer to the
handling suggestion other specific alarm signals.
Please replace MON plug-in module.
No special treatment is needed, and disable the communication test function
after the completion of the test.
Please inform the manufacture or the agent for repair.
Users may pay no attention to the alarm signal in the project commissioning
17
Alm_Version
stage, but it is needed to download the latest package file (including correct
version checksum file) provided by R&D engineer to make the alarm signal
disappear. Then users get the correct software version. It is not allowed that
4-6
PCS-902 Line Distance Relay
Date: 2019-03-01
4 Supervision
No.
Item
Handling suggestion
the alarm signal is issued on the device already has been put into service. the
devices having being put into service so that the alarm signal disappears.
Please check the value of setting [Active_Grp] and binary input of indicating
18
Alm_BI_SettingGrp
active group, and make them matched. Then the “ALARM” LED will be
extinguished and the corresponding alarm message will disappear and the
device will restore to normal operation state.
19
Alm_DSP_Frame
Please inform the manufacture or the agent for repair.
1. check whether the binary input module is connected to the power supply.
2. check whether the voltage of power supply is in the required range.
20
Bxx.Alm_OptoDC
3. After the voltage for binary input module restores to normal range, the
“ALARM” LED will be extinguished and the corresponding alarm message will
disappear and the device will restore to normal operation state.
Please check secondary values and protection settings. If settings are not set
21
Alm_Pkp_FD
reasonable to make fault detectors pick up, please reset settings, and then
the alarm message will disappear and the device will restore to normal
operation state.
Please check secondary values and protection settings. If settings are not set
22
Alm_Pkp_I0
reasonable to make fault detectors pick up, please reset settings, and then
the alarm message will disappear and the device will restore to normal
operation state.
23
VTS.Alm
24
VTNS.Alm
25
MCBrd.CBx.Alm_VTS
26
CBx.CTS.Alm
27
CBx.Alm_52b
Please check the corresponding VT secondary circuit. After the abnormality is
eliminated, the device returns to normal operation state.
Please check the corresponding VT secondary circuit of neutral point. After
the abnormality is eliminated, the device returns to normal operation state.
Please check the corresponding VT secondary circuit. After the abnormality is
eliminated, the device returns to normal operation state.
Please check the corresponding CT secondary circuit. After the abnormality is
eliminated, the device returns to normal operation state.
Please check the auxiliary contact of CB. After the abnormality is eliminated,
the device returns to normal operation state.
After maintenance is finished, please de-energized the binary input
28
BI_Maintenance
[BI_Maintenance] and then the alarm will disappear and the device restore to
normal operation state.
1. check whether the selected clock synchronization mode matches the clock
synchronization source;
2. check whether the wiring connection between the device and the clock
29
Alm_TimeSyn
synchronization source is correct
3. check whether the setting for selecting clock synchronization (i.e.
[Opt_TimeSyn]) is set correctly. If there is no clock synchronization, please
set the setting [Opt_TimeSyn] as ”No TimeSyn”.
4. After the abnormality is removed, the “ALARM” LED will be extinguished
PCS-902 Line Distance Relay
4-7
Date: 2019-03-01
4 Supervision
No.
Item
Handling suggestion
and the corresponding alarm message will disappear and the device will
restore to normal operation state.
Please check Ethernet switch of GOOSE network, GOOSE configuration file
30
Alm_StatGOOSE
31
Alm_Freq
Adjust the system operating mode
Alm_Sparexx
Find the reason according to specific problem. (These signals are
(xx=01~08)
user-defined.)
32
and GOOSE network.
Operation Alarm Signals
33
FOx.Alm
Please check the connection of optical fibre channel.
34
FOx.Alm_ID
Please check the connection of optical fibre channel.
35
FOx.Alm_NoValFram
Please check the connection of optical fibre channel.
36
FOx.Alm_CRC
Please check the connection of optical fibre channel.
37
FOx.Alm_Off
Please check the connection of optical fibre channel.
38
FOx.Alm_Connect
Please check the connection of optical fibre channel. (For example, receiving
and sending are inconsistent, or channel 1 and channel 2 are inconsistent)
Please check the corresponding current circuit. After the abnormality is
39
87STB.Alm_Diff
eliminated, “ALARM” LED will go off automatically and device returns to
normal operation state with a time delay of 10s.
Please check the corresponding binary input secondary circuit. After the
40
87STB.Alm_89b_DS
abnormality is eliminated, “ALARM” LED will go off automatically and device
returns to normal operation state with a time delay of 10s.
Please check the corresponding binary input secondary circuit. After the
41
TT.Alm
abnormality is eliminated, “ALARM” LED will go off automatically and device
returns to normal operation state with a time delay of 10s.
4.3 Relay Self-supervision
4.3.1 Relay Hardware Monitoring
All chips on DSP module are monitored to ensure whether they are damaged or having errors. If
any one of them is detected damaged or having error, the alarm signal [Fail_DSP] is issued with
the device being blocked.
4.3.2 Fault Detector Monitoring
When neutral current fault detector picks up and lasts for longer than 20 seconds, an alarm
[Alm_Pkp_I0] will be issued without the device blocked. When any fault detector picks up for
longer than 50s, an alarm will be issued [Alm_Pkp_FD] without the device blocked.
4.3.3 Check Setting
This relay has 10 setting groups, only one Setting group could be activated (is active) at a time.
The settings of active setting group are checked to ensure they are reasonable. If settings are
checked to be unreasonable or out of setting scopes, a corresponding alarm signal will be issued,
and the device is also blocked.
4-8
PCS-902 Line Distance Relay
Date: 2019-03-01
4 Supervision
4.4 AC Input Monitoring
4.4.1 Voltage/current Drift Monitoring and Auto-adjustment
Zero point of voltage and current may drift due to variation of temperature or other environment
factors. The device continually traces the drift and adjust it to normal value automatically.
4.4.2 Sampling Monitoring
AC current and voltage samplings of protection DSP and fault detector DSP are monitored and if
the samples of protection DSP and fault detector DSP are detected to be wrong or inconsistent
between them, the alarm signal [Fail_Sample] will be issued and the device will be blocked.
4.5 Secondary Circuit Monitoring
4.5.1 Opto-coupler Power Supervision
Positive power supply of opto-coupler is continually monitored. If an error or damage has occurred,
an alarm [Bxx.Alm_OptoDC] will be issued.
4.5.2 Circuit Breaker Supervision
If 52b of three phases are energized ,which indicates circuit breaker is open and there is no
current detected in the line, the line will be considered to be out of service. SOTF protection will be
enabled after 50ms.
If 52b of three phases are energized that indicates circuit breaker is open but there is still current
detected in the line (the measured current is greater than a settable threshold value) or
three-phase circuit breaker is in pole disagreement, an alarm signal [Alm_52b] will be issued after
10 seconds.
PCS-902 Line Distance Relay
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Date: 2019-03-01
4 Supervision
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PCS-902 Line Distance Relay
Date: 2019-03-01
5 Management
5 Management
Table of Contents
5 Management ...................................................................................... 5-a
5.1 Measurement ................................................................................................... 5-1
5.1.1 Measurement Values ........................................................................................................... 5-1
5.1.2 Metering Value ..................................................................................................................... 5-6
5.2 Recording ........................................................................................................ 5-6
5.2.1 Overview .............................................................................................................................. 5-6
5.2.2 Event Recording .................................................................................................................. 5-7
5.2.3 Disturbance Recording ........................................................................................................ 5-7
5.2.4 Present Recording ............................................................................................................... 5-9
PCS-902 Line Distance Relay
5-a
Date: 2019-03-01
5 Management
5-b
PCS-902 Line Distance Relay
Date: 2019-03-01
5 Management
5.1 Measurement
PCS-902 performs continuous measurement of the analogue input quantities. The current full
scale of relay is 40 times of rated current, and there is no effect to the performance of IED due to
overflowing of current full scale. The device samples 24 points per cycle and calculates the RMS
value in each interval and updated the LCD display in every 0.5 second. The measurement data
can be displayed on the LCD of the relay front panel or on the local/remote PC via software tool.
Navigate the menu to view the sampling value through LCD screen.
NOTICE!
This device can be configured to support single circuit breaker application or double
circuit breakers application by PCS-Explorer. For double circuit breakers mode, the
prefix “CBx.” is added to related measurement quantities for circuit breaker No.x (x=1 or
2).
5.1.1 Measurement Values
Access path: MainMenu  “Measurements”  “Measurements1”
“Measurements1” is used to display measured values from protection calculation DSP. The
measurement values can be displayed in primary value or secondary value by the setting
[Opt_Display_Status].
No.
Symbol
Definition
Resolution
Unit
1
CBx.Ia
Phase-A current corresponding to circuit breaker No.x
0.000
A
2
CBx.Ib
Phase-B current corresponding to circuit breaker No.x
0.000
A
3
CBx.Ic
Phase-C current corresponding to circuit breaker No.x
0.000
A
4
CBx.3I0
Residual current corresponding to circuit breaker No.x
0.000
A
5
Ia
0.000
A
6
Ib
0.000
A
7
Ic
0.000
A
8
I1
The positive-sequence current
0.000
A
9
I2
The negative-sequence current
0.000
A
10
3I0
0.000
A
11
3I0Adj
Residual current from parallel line
0.000
A
12
Ua
Phase-A protection voltage
0.000
V
13
Ub
Phase-B protection voltage
0.000
V
14
Uc
Phase-C protection voltage
0.000
V
15
Uab
Phase-AB protection voltage
0.000
V
Phase-A current (summation current for double circuit
breakers mode)
Phase-B current (summation current for double circuit
breakers mode)
Phase-C current (summation current for double circuit
breakers mode)
Residual current (summation current for double circuit
breakers mode)
PCS-902 Line Distance Relay
5-1
Date: 2019-03-01
5 Management
No.
Symbol
Definition
Resolution
Unit
16
Ubc
Phase-BC protection voltage
0.000
V
17
Uca
Phase-CA protection voltage
0.000
V
18
UB1
The voltage of busbar No.1
0.000
V
19
UL2
The voltage of line No.2
0.000
V
20
UB2
The voltage of busbar No.2
0.000
V
21
U1
The positive-sequence voltage
0.000
V
22
U2
The negative-sequence voltage
0.000
V
23
3U0
The calculated residual voltage
0.000
V
24
Ang (Ua-Ub)
0
deg
25
Ang (Ub-Uc)
0
deg
26
Ang (Uc-Ua)
0
deg
27
Ang (Ua-Ia)
0
deg
28
Ang (Ub-Ib)
0
deg
29
Ang (Uc-Ic)
0
deg
30
CBx.Ang (Ia-Ib)
0
deg
31
CBx.Ang (Ib-Ic)
0
deg
0
deg
0
deg
0
deg
0
deg
0
deg
0
deg
Phase angle between phase-A voltage and phase-B
voltage
Phase angle between phase-B voltage and phase-C
voltage
Phase angle between phase-C voltage and phase-A
voltage
Phase angle between phase-A voltage and phase-A
current
Phase angle between phase-B voltage and phase-B
current
Phase angle between phase-C voltage and phase-C
current
Phase angle between phase-A current and phase-B
current corresponding to circuit breaker No.x
Phase angle between phase-B current and phase-C
current corresponding to circuit breaker No.x
Phase angle of reference vector, which can be set as
32
AngRef
positive-sequence voltage, positive-sequence current of
circuit breaker No.1 or positve-sequence current of
circuit breaker No.2
33
CBx.Ang (Ia)
34
CBx.Ang (Ib)
35
CBx.Ang (Ic)
Phase angle between reference vector and phase-A
current corresponding to circuit breaker No.x
Phase angle between reference vector and phase-B
current corresponding to circuit breaker No.x
Phase angle between reference vector and phase-C
current corresponding to circuit breaker No.x
Phase angle between reference vector and phase-A
36
Ang (Ia)
current (summation current for double circuit breakers
mode)
37
Ang (Ib)
Phase angle between reference vector and phase-B
5-2
PCS-902 Line Distance Relay
Date: 2019-03-01
5 Management
No.
Symbol
Definition
Resolution
Unit
0
deg
0
deg
0
deg
0
deg
0
deg
0
deg
0
deg
0
deg
current (summation current for double circuit breakers
mode)
Phase angle between reference vector and phase-C
38
Ang (Ic)
current (summation current for double circuit breakers
mode)
Phase angle between reference vector and residual
39
Ang (3I0Adj)
40
Ang (Ua)
41
Ang (Ub)
42
Ang (Uc)
43
Ang (UB1)
44
Ang (UL2)
45
Ang (UB2)
46
f
Frequency of protection voltage
0.000
Hz
47
P1
The positive-sequence active power
0.000
W
48
CBx.25.f_Ref
0.000
Hz
49
CBx.25.f_Syn
0.000
Hz
0.000
Hz
0
V
0.000
V
current from parallel line
Phase angle between reference vector and phase-A
voltage
Phase angle between reference vector and phase-B
voltage
Phase angle between reference vector and phase-C
voltage
Phase angle between reference vector and the voltage
of busbar No.1
Phase angle between reference vector and the voltage
of line No.2
Phase angle between reference vector and the voltage
of busbar No.2
Frequency of reference voltage corresponding to circuit
breaker No.x
Frequency of synchronism voltage corresponding to
circuit breaker No.x
Frequency difference between protection voltage and
50
CBx.25.f_Diff
synchronism voltages corresponding to circuit breaker
No.x
Phase angle difference between protection voltage and
51
CBx.25.phi_Diff
synchronism voltages corresponding to circuit breaker
No.x
Voltage difference between protection voltage and
52
CBx.25.U_Diff
synchronism voltages corresponding to circuit breaker
No.x
Access path: MainMenu  “Measurements”  “Measurements2”
“Measurements2” is used to display measured values from fault detector DSP. The measurement
values can be displayed in primary value or secondary value by the setting [Opt_Display_Status].
PCS-902 Line Distance Relay
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Date: 2019-03-01
5 Management
No.
Symbol
Definition
Resolution
Unit
1
CBx.Ia
Phase-A current corresponding to circuit breaker No.x
0.000
A
2
CBx.Ib
Phase-B current corresponding to circuit breaker No.x
0.000
A
3
CBx.Ic
Phase-C current corresponding to circuit breaker No.x
0.000
A
4
Ia
0.000
A
5
Ib
0.000
A
6
Ic
0.000
A
7
49-1.Accu_A
0.000
%
8
49-1.Accu_B
0.000
%
9
49-1.Accu_C
0.000
%
10
49-2.Accu_A
0.000
%
11
49-2.Accu_B
0.000
%
12
49-2.Accu_C
0.000
%
Phase-A current (summation current for double circuit
breakers mode)
Phase-B current (summation current for double circuit
breakers mode)
Phase-C current (summation current for double circuit
breakers mode)
Phase-A thermal accumulation of stage 1 of thermal
overload protection
Phase-B thermal accumulation of stage 1 of thermal
overload protection
Phase-C thermal accumulation of stage 1 of thermal
overload protection
Phase-A thermal accumulation of stage 2 of thermal
overload protection
Phase-B thermal accumulation of stage 2 of thermal
overload protection
Phase-C thermal accumulation of stage 2 of thermal
overload protection
Access path: MainMenu  “Measurements”  “Measurements3”
“Measurements3” is used to display measured values of other calculated quantities related to the
measurement and control. The measurement values are always displayed in primary value.
No.
Symbol
1
CBx.Ia
2
CBx.Ib
3
CBx.Ic
4
CBx.I1
5
CBx.I2
6
CBx.3I0
Definition
The primary value of phase-A current corresponding to
circuit breaker No.x
The primary value of phase-B current corresponding to
circuit breaker No.x
The primary value of phase-C current corresponding to
circuit breaker No.x
The
primary
value
of
positive-sequence
current
corresponding to circuit breaker No.x
The
primary
value
of
negative-sequence
current
corresponding to circuit breaker No.x
The primary value
of
calculated
corresponding to circuit breaker No.x
5-4
residual
current
Resolution
Unit
0.000
A
0.000
A
0.000
A
0.000
A
0.000
A
0.000
A
PCS-902 Line Distance Relay
Date: 2019-03-01
5 Management
No.
Symbol
Definition
The primary value of phase-A current (summation current
Resolution
Unit
0.000
A
0.000
A
0.000
A
7
Ia
8
Ib
9
Ic
10
Ua
The primary value of phase-A voltage
0.000
kV
11
Ub
The primary value of phase-B voltage
0.000
kV
12
Uc
The primary value of phase-C voltage
0.000
kV
13
Uab
The primary value of phase-AB voltage
0.000
kV
14
Ubc
The primary value of phase-BC voltage
0.000
kV
15
Uca
The primary value of phase-CA voltage
0.000
kV
16
U1
The primary value of positive-sequence voltage
0.000
kV
17
U2
The primary value of negative-sequence voltage
0.000
kV
18
3U0
The primary value of calculated residual voltage
0.000
kV
19
UB1
The primary value of voltage of busbar No.1
0.000
kV
20
UL2
The primary value of voltage of line No.2
0.000
kV
21
UB2
The primary value of voltage of busbar No.2
0.000
kV
22
f
Frequency of protection voltage
0.000
Hz
23
UB1.f
Frequency of busbar 1 voltage
0.000
Hz
24
UL2.f
Frequency of line 2 voltage
0.000
Hz
25
UB2.f
Frequency of busbar 2 voltage
0.000
Hz
26
CBx.P
0.000
MW
27
CBx.Q
0.000
MVAr
28
CBx.S
0.000
MVA
29
CBx.Cos
0.000
-
30
CBx.Pa
0.000
MW
31
CBx.Pb
0.000
MW
32
CBx.Pc
0.000
MW
33
CBx.Qa
0.000
MVAr
for double circuit breakers mode)
The primary value of phase-B current (summation current
for double circuit breakers mode)
The primary value of phase-C current (summation current
for double circuit breakers mode)
The primary value of active power corresponding to circuit
breaker No.x
The primary value of reactive power corresponding to
circuit breaker No.x
The primary value of apparent power corresponding to
circuit breaker No.x
The value of power factor corresponding to circuit breaker
No.x
The primary value of phase-A active power corresponding
to circuit breaker No.x
The primary value of phase-B active power corresponding
to circuit breaker No.x
The
primary
value
of
phase-C
active
power
reactive
power
corresponding to circuit breaker No.x
The
primary
value
of
phase-A
PCS-902 Line Distance Relay
5-5
Date: 2019-03-01
5 Management
No.
Symbol
Definition
Resolution
Unit
0.000
MVAr
0.000
MVAr
0.000
-
0.000
-
0.000
-
0.000
Hz
0.000
Hz/s
0.00
deg
0.000
kV
corresponding to circuit breaker No.x
34
CBx.Qb
35
CBx.Qc
36
CBx.Cosa
37
CBx.Cosb
38
CBx.Cosc
The
primary
value
of
phase-B
reactive
power
reactive
power
corresponding to circuit breaker No.x
The
primary
value
of
phase-C
corresponding to circuit breaker No.x
The value of phase-A power factor corresponding to
circuit breaker No.x
The value of phase-B power factor corresponding to
circuit breaker No.x
The value of phase-C power factor corresponding to
circuit breaker No.x
The frequency difference between reference side and
39
CBx.f_Diff
incoming
side
for
manual
closing
synchrocheck
corresponding to circuit breaker No.x
The rate of frequency change between reference side and
40
CBx.df/dt
incoming
side
for
manual
closing
synchrocheck
corresponding to circuit breaker No.x
Phase angle difference between reference side and
41
CBx.phi_Diff
incoming
side
for
manual
closing
synchrocheck
corresponding to circuit breaker No.x
The primary value of voltage difference between
42
CBx.U_Diff
reference side and incoming side for manual closing
synchrocheck corresponding to circuit breaker No.x
5.1.2 Metering Value
Access path: MainMenu  “Measurements”  “Metering”
“Metering” is used to display metering values of active and reactive energy. The metering values
are always displayed in primary value.
No.
Symbol
Definition
Resolution
Unit
1
PHr+_Pri
The primary positive active energy
0.000
MWh
2
PHr-_Pri
The primary negative active energy
0.000
MWh
3
QHr+_Pri
The primary positive reactive energy
0.000
MVAh
4
QHr-_Pri
The primary negative reactive energy
0.000
MVAh
5.2 Recording
5.2.1 Overview
PCS-902 provides the following recording functions:
5-6
PCS-902 Line Distance Relay
Date: 2019-03-01
5 Management
1.
Event recording
2.
Disturbance recording
3.
Present recording
All the recording information except waveform can be viewed on local LCD or by printing.
Waveform could only be printed or extracted with PCS-Explorer software tool and a waveform
analysis software.
5.2.2 Event Recording
5.2.2.1 Overview
The device can store the latest 1024 disturbance records, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs. All the records are stored in non-volatile memory,
and when the available space is exhausted, the oldest record is automatically overwritten by the
latest one.
5.2.2.2 Disturbance Records
When any protection element operates or drops off, such as fault detector, distance protection etc.,
they will be logged in event records.
5.2.2.3 Supervision Events
The device is under automatic supervision all the time. If there are any failure or abnormal
condition detected, such as, chip damaged, VT circuit failure and so on, it will be logged in event
records.
5.2.2.4 Binary Events
When there is a binary input is energized or de-energized, i.e., its state has changed from “0” to “1”
or from “1” to “0”, it will be logged in event records.
5.2.2.5 Control Logs
When the total number of control command records reaches 256, “Control_Logs” memory area
will be full. If the device receives a new control command now, the oldest control command record
will be deleted, and then the latest control command record will be stored and displayed.
5.2.2.6 Device Logs
If an operator implements some operations on the device, such as reboot protective device,
modify setting, etc., they will be logged in event records.
5.2.3 Disturbance Recording
5.2.3.1 Application
Disturbance records can be used to have a better understanding of the behavior of the power
network and related primary and secondary equipment during and after a disturbance. Analysis of
the recorded data provides valuable information that can be used to improve existing equipment.
This information can also be used when planning for and designing new installations.
PCS-902 Line Distance Relay
5-7
Date: 2019-03-01
5 Management
5.2.3.2 Design
A disturbance record consists of fault record and fault waveform. The disturbance record can be
initiated by fault detector element, tripping element, reclosing element or configurable signal
[BI_TrigDFR].
5.2.3.3 Capacity and Information of Disturbance Records
The device can store up to 32 disturbance records with waveform in non-volatile memory. It is
based on first in first out queue that the oldest disturbance record will be overwritten by the latest
one.
For each disturbance record, the following items are included:
1.
Sequence number
Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.
2.
Date and time of fault occurrence
The time resolution is 1ms using the relay internal clock synchronized via clock synchronized
device if connected. The date and time is recorded when a system fault is detected.
3.
Relative operating time
An operating time (not including the operating time of output relays) is recorded in the record.
4.
Faulty phase
5.
Fault location
To get accurate result of fault location, the following settings shall be set correctly:
1)
Positive-sequence line reactance [X1L]
2)
Positive-sequence line resistance [R1L]
3)
Zero-sequence line reactance [X0L]
4)
Zero-sequence line resistance [R0L]
5)
Zero-sequence line mutual reactance [X0M]
6)
Zero-sequence line mutual resistance [R0M]
7)
Line positive-sequence sensitive angle [21-x.phi1_Reach] or [21.Pilot.phi1_Reach]
8)
Line zero-sequence sensitive angle [21-x.Real_K0] and [21-x.Imag_K0]
9)
Line length in km [LineLength]
6.
Protection elements
5.2.3.4 Capacity and Information of Fault Waveform
MON module can store 32 pieces of fault waveform oscillogram in non-volatile memory. If a new
5-8
PCS-902 Line Distance Relay
Date: 2019-03-01
5 Management
fault occurs when 32 fault waveform have been stored, the oldest will be overwritten by the latest
one.
Each fault record consists of all analog and digital quantities related to protection, such as original
current and voltage, alarm elements, and binary inputs and etc.
Each time recording includes pre-disturbance waveform and post-disturbance waveform, the
pre-disturbance waveform recorded duration is configured via the communication setting
[RecDur_PreTrigDFR], the waveform recorded duration after the fault disappears is configured via
the communication setting [RecDur_PostFault], the maximum post-disturbance waveform
recorded duration is configured via the communication setting [MaxRecDur_PostTrigDFR].
Trig point
1
Limit time
2
3
1.
Pre-fault recording time. Use the setting [RecDur_PreTrigDFR] to set this time.
2.
Fault time of the recording. The fault time cannot be set. It continues as long as any valid
trigger condition, binary or analog, persists (unless limited by the limit time, which is
determined by the setting [MaxRecDur_PostTrigDFR]).
3.
Post fault recording time. The time the disturbance recording continues afterall activated
triggers are reset. Use the setting [RecDur_PostFault] to set this time.
5.2.4 Present Recording
Present recording is a waveform triggered manually on on the device′s LCD or remotely through
PCS-Explorer software. Recording content of present recording is same to that of disturbance
recording.
Each time recording includes several-cycle waveform before triggering and several-cycle
waveform after triggering, the waveform recorded duration before triggering is configured via the
communication setting [RecDur_PreTrigDFR], the waveform recorded duration after triggering is
150ms+[RecDur_PostFault], but the waveform recorded duration after triggering must be less than
[MaxRecDur_PostTrigDFR].
PCS-902 Line Distance Relay
5-9
Date: 2019-03-01
5 Management
5-10
PCS-902 Line Distance Relay
Date: 2019-03-01
6 Hardware
6 Hardware
Table of Contents
6 Hardware ............................................................................................ 6-a
6.1 Overview .......................................................................................................... 6-1
6.2 Typical Wiring .................................................................................................. 6-4
6.2.1 Conventional CT/VT (For reference only) ........................................................................... 6-4
6.2.2 ECT/EVT (For reference only) ............................................................................................. 6-6
6.2.3 CT Requirement .................................................................................................................. 6-8
6.3 Plug-in Module Description ............................................................................ 6-9
6.3.1 PWR Plug-in Module (Power Supply) ................................................................................. 6-9
6.3.2 MON Plug-in Module (Monitor) ...........................................................................................6-11
6.3.3 AI Plug-in Module (Analog Input) ....................................................................................... 6-15
6.3.4 DSP Plug-in Module (Logic Process) ................................................................................ 6-28
6.3.5 NET-DSP Plug-in Module (GOOSE and SV) .................................................................... 6-28
6.3.6 CH Plug-in Module (Fibre Optical Channel Interface) ....................................................... 6-33
6.3.7 BI Plug-in Module (Binary Input)........................................................................................ 6-35
6.3.8 BO Plug-in Module (Binary Output) ................................................................................... 6-44
6.3.9 HMI Module........................................................................................................................ 6-48
List of Figures
Figure 6.1-1 Rear view of fixed module position ..................................................................... 6-1
Figure 6.1-2 Hardware diagram .................................................................................................. 6-2
Figure 6.1-3 Front view of PCS-902 ........................................................................................... 6-3
Figure 6.1-4 Typical rear view of PCS-902 ................................................................................ 6-4
Figure 6.2-1 Typical wiring of PCS-902 (conventional CT/VT) ................................................ 6-5
Figure 6.2-2 Typical wiring of PCS-902 (ECT/EVT) .................................................................. 6-7
Figure 6.3-1 View of PWR plug-in module .............................................................................. 6-10
Figure 6.3-2 Output contacts of PWR plug-in module........................................................... 6-10
PCS-902 Line Distance Relay
6-a
Date: 2018-02-13

6 Hardware
Figure 6.3-3 View of MON plug-in module .............................................................................. 6-12
Figure 6.3-4 Connection of communication terminal ............................................................ 6-14
Figure 6.3-5 Jumpers of clock synchronization port ............................................................ 6-14
Figure 6.3-6 Schematic diagram of CT circuit automatically closed ....................................... 6-15
Figure 6.3-7 Current connection of AI plug-in module (NR1401) ......................................... 6-16
Figure 6.3-8 Voltage connection 1 of AI plug-in module (NR1401) ...................................... 6-17
Figure 6.3-9 Voltage connection 2 of AI plug-in module (NR1401) ...................................... 6-17
Figure 6.3-10 View of AI plug-in module for one CT group input (NR1401) ........................ 6-18
Figure 6.3-11 Current connection of AI plug-in module (NR1408) ....................................... 6-20
Figure 6.3-12 Voltage connection 1 of AI plug-in module (NR1408) .................................... 6-20
Figure 6.3-13 Voltage connection 2 of AI plug-in module (NR1408) .................................... 6-21
Figure 6.3-14 View of AI plug-in module for one CT group input (NR1408) ........................ 6-21
Figure 6.3-15 Current connection of AI plug-in module (NR1401) ....................................... 6-23
Figure 6.3-16 Voltage connection of AI plug-in module (NR1401) ....................................... 6-23
Figure 6.3-17 View of AI plug-in module for two CT group input (NR1401) ........................ 6-24
Figure 6.3-18 Current connection of AI plug-in module (NR1401) ....................................... 6-25
Figure 6.3-19 Voltage connection of AI plug-in module (NR1401) ....................................... 6-26
Figure 6.3-20 View of AI plug-in module for two CT group input (NR1401) ........................ 6-26
Figure 6.3-21 View of DSP plug-in module ............................................................................. 6-28
Figure 6.3-22 View of NET-DSP plug-in module ..................................................................... 6-29
Figure 6.3-23 View of CH plug-in module ............................................................................... 6-33
Figure 6.3-24 Voltage dependence for binary inputs ............................................................. 6-35
Figure 6.3-25 Debounce technique.......................................................................................... 6-36
Figure 6.3-26 View of BI plug-in module (NR1503) ................................................................ 6-38
Figure 6.3-27 View of BI plug-in module (NR1504) ................................................................ 6-40
Figure 6.3-28 View of BI plug-in module (NR1508A).............................................................. 6-41
Figure 6.3-29 View of BO plug-in module (NR1521A) ............................................................ 6-45
Figure 6.3-30 View of BO plug-in module (NR1521C) ............................................................ 6-45
Figure 6.3-31 View of BO plug-in module (NR1521F) ............................................................ 6-46
Figure 6.3-32 View of BO plug-in module (NR1521G) ........................................................... 6-47
6-b
PCS-902 Line Distance Relay
Date: 2018-02-13

6 Hardware
Figure 6.3-33 View of BO plug-in module (NR1580A) ............................................................ 6-47
List of Tables
Table 6.3-1 Terminal definition and description of PWR plug-in module ............................ 6-10
Table 6.3-2 Terminal definition of AI module (NR1401) ......................................................... 6-18
Table 6.3-3 Terminal definition of AI module (NR1408) ......................................................... 6-21
Table 6.3-4 Terminal definition of AI module (NR1401) ......................................................... 6-24
Table 6.3-5 Terminal definition of AI module (NR1401) ......................................................... 6-27
Table 6.3-6 Encoding of IEC 61850-7-3 quality .......................................................................... 6-30
PCS-902 Line Distance Relay
6-c
Date: 2018-02-13

6 Hardware
6-d
PCS-902 Line Distance Relay
Date: 2018-02-13

6 Hardware
6.1 Overview
PCS-902 adopts 32-bit microchip processor CPU produced by FREESCALE as control core for
management and monitoring function, meanwhile, adopts high-speed digital signal processor DSP
for all the protection calculation. 24 points are sampled in every cycle and parallel processing of
sampled data can be realized in each sampling interval to ensure ultrahigh reliability and safety of
the device.
12
13
PWR module
11
BO module
09
BO module
08
BO module
06
BO module
DSP module
05
BI module
CH Module
04
BI module
DSP module
AI module
MON module
PCS-902 is comprised of intelligent plug-in modules, except that few particular plug-in modules’
position cannot be changed in the whole device (gray plug-in modules as shown in Figure 6.1-1),
other plug-in modules like AI (analog input) and IO (binary input and binary output) can be flexibly
configured in the remaining slot positions.
15
P1
Slot No.
01
02
03
07
10
14
Figure 6.1-1 Rear view of fixed module position
PCS-902 has 16 slots, PWR plug-in module, MON plug-in module, DSP plug-in module and CH
plug-in module are assigned at fixed slots.
Besides 5 fixed modules are shown in above figure, there are 12 slots can be flexibly configured.
AI plug-in module, BI plug-in module and BO plug-in module can be configured at position
between slot 02, 03 and 06~15. It should be pay attention that AI plug-in module will occupy two
slots.
This device is developed on the basis of our latest software and hardware platform, and the new
platform major characteristics are of high reliability, networking and great capability in
anti-interference. See Figure 6.1-2 for hardware diagram.
PCS-902 Line Distance Relay
6-1
Date: 2018-02-13

A/D
Protection
Calculation
DSP
A/D
Fault
Detector
DSP
Output Relay
Conventional CT/VT
External
Binary Input
6 Hardware
ECVT
Pickup
Relay
ECVT
ETHERNET
LCD
Power
Supply
Uaux
+E
Clock SYN
LED
CPU
RJ45
Keypad
PRINT
Figure 6.1-2 Hardware diagram
The working process of the device is as shown in above figure: current and voltage from
conventional CT/VT are converted into small voltage signal and sent to DSP module after filtered
and A/D conversion for protection calculation and fault detector respectively (ECVT signal is sent
to the device without small signal and A/D conversion). When DSP module completes all the
protection calculation, the result will be recorded in 32-bit CPU on MON module. DSP module
carries out fault detector, protection logic calculation, tripping output, and MON module performs
SOE (sequence of event) record, waveform recording, printing, communication between the
device and SAS and communication between HMI and CPU. When fault detector detects a fault
and picks up, positive power supply for output relay is provided.
The items can be flexibly configured depending on the situations like sampling method of the
device (conventional CT/VT or ECT/EVT), and the mode of binary output (conventional binary
output or GOOSE binary output). The configurations for PCS-900 series based on microcomputer
are classified into standard and optional modules.
Table 6.1-1 PCS-902 module configuration
Module ID
Module description
Remark
NR1101/NR1102
Management and monitor module (MON module)
standard
NR1401/NR1408
Analog input module (AI module)
standard
NR1161
Protection calculation and fault detector module (DSP module)
standard
NR1213/NR1214
Protection communication channel module (CH module)
option
NR1503/NR1504/NR1508
Binary input module (BI module)
standard
NR1521/NR1580
Binary output module (BO module)
standard
NR1301
Power supply module (PWR module)
standard
6-2
PCS-902 Line Distance Relay
Date: 2018-02-13

6 Hardware
Module ID
Module description
Remark
GOOSE and SV from merging unit by IEC61850-9-2 (NET-DSP
NR1136
module)
Human machine interface module (HMI module)
option
standard

MON module provides functions like communication with SAS, event record, setting
management etc.

AI module converts AC current and voltage from current transformers and voltage
transformers respectively to small voltage signal.

DSP module performs filtering, sampling, protection calculation and fault detector calculation.

CH module performs information exchange with the remote device through a dedicated
optical fibre channel, multiplex optical fibre channel or PLC channel.

BI module provides binary inputs via opto-couplers with rating voltage among
24V/110V/125V/220V/250V (configurable).

BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.

PWR module converts DC 250/220/125/110V into various DC voltage levels for modules of
the device.

NET-DSP module receives and sends GOOSE messages, sampled values (SV) from
merging unit by IEC61850-9-2 protocol.

HMI module is comprised of LCD, keypad, LED indicators and multiplex RJ45 ports for user
as human-machine interface.
PCS-902 is made of a 4U height 19” chassis for flush mounting. Components mounted on its front
include a 320×240 dot matrix LCD, a 9 button keypad, 20 LED indicators and a multiplex RJ45
port. A monolithic micro controller is installed in the equipment for these functions.
Following figures show front and rear views of PCS-902 respectively.
ALARM
11
PCS-902
12
13
4
14
5
15
6
16
7
17
8
18
9
19
10
20
GRP
3
HEALTHY
ESC
1
2
ENT
Figure 6.1-3 Front view of PCS-902
PCS-902 Line Distance Relay
6-3
Date: 2018-02-13

6 Hardware
20 LED indicators are, from top to bottom, operation (HEALTHY), self-supervision (ALARM),
others are configurable.
For the 9-button keypad, “ENT” is “enter”, “GRP” is “group number” and “ESC” is “escape”.
NR1102
NR1401
NR1161
NR1161
NR1213
NR1504
NR1504
NR1521
NR1521
NR1521
NR1521
NR1301
5V OK
ALM
TX
BO_ALM BO_FAIL
RX
ON
TX
OFF
RX
DANGER
1 BO_COM1
2
BO_FAIL
3
BO_ALM
4
BO_COM2
5
BO_FAIL
6
BO_ALM
7
OPTO+
8
OPTO-
9
10
PWR+
11
PWR-
12
GND
Figure 6.1-4 Typical rear view of PCS-902
6.2 Typical Wiring
6.2.1 Conventional CT/VT (For reference only)
12
13
PWR module
11
NR1521F NR1301
BO module
BO module
06
BO module
05
NR1521A NR1521C NR1521C
BO module
04
NR1504
BI module
NR1161
DSP module
NR1213
CH Module
AI module
NR1161
DSP module
NR1401
MON module
NR1102
15
P1
Slot No.
01
02
03
07
08
09
10
14
The following typical wiring is given based on above hardware configuration
6-4
PCS-902 Line Distance Relay
Date: 2018-02-13

6 Hardware
Power supply supervision
0801
CH-TX
CH-RX
BI_01
or
CH-TX
CH-RX
Fibre Optic
FC/PC Type (Rear)
0201
Ia
0203
Ib
0204
0205
To parallel line
Ic
0206
0207
From parallel line
IM0
0208
0215
Ub
0216
0217
0221
UL2
0222
0223
Power supply for
opto-coupler (24V)
P110
PWR-
P111
OPTO+
P107
OPTO-
P108
BO_ALM
P101
COM
P105
BO_FAIL
P106
BO_ALM
P104
COM
Not used
0815
+
0816
+
0821
0822
1101
BO_01
1102
1103
BO_02
1104
BO_11
1121
1122
1201
BO_01
1202
1203
BO_02
1204
BO_11
1221
1222
1301
BO_01
1302
1303
BO_02
1304
…
BO_FAIL
P103
0814
-
Power
Supply
P102
+
BI_13
Signal Binary Output
(option)
PWR+
0809
…
External DC power
supply
+
BI_12
Signal Binary Output
UB2
0224
0808
…
UB1
0220
Not used
BI_18
Synchronism Voltage
0219
0807
BI_07
Controlled by fault
detector element
Uc
0218
+
BI_06
…
Ua
0214
Protection Voltage
0213
0802
…
0202
+
…
*BI plug-in module can be independent common terminal
Dedicated Channel
Or
Telecom Equipment
BO_11
1321
1322
1501
B
0102
SGND
0103
BO_CtrlOpn1
0104
0101
SYN-
0102
SGND
0103
0104
Clock SYN
SYN+
1502
1503
BO_CtrlCls1
1504
…
Signal Binary Output (option)
0101
COM
To the screen of other coaxial
cable with single point earthing
A
1517
BO_CtrlOpn5
1518
1519
BO_CtrlCls5
1520
1521
0105
TXD
0106
SGND
0107
PRINT
PRINTER
RTS
BO_Ctrl
Multiplex
RJ45 (Front)
1522
P112
0225
Grounding
Bus
Figure 6.2-1 Typical wiring of PCS-902 (conventional CT/VT)
PCS-902 Line Distance Relay
6-5
Date: 2018-02-13

6 Hardware
PCS-902 (conventional CT/VT and conventional binary input and binary output)
Slot No.
01
04
05
08
09
11
12
13
15
P1
Module ID
NR1102
02
NR1401
03
NR1161
NR1213
06
07
NR1504
NR1504
10
NR1521
NR1521
NR1521
14
NR1521
NR1301
MON
AI
DSP
CH
BI
BI
BO
BO
BO
BO
PWR
08
09
11
12
13
PCS-902 (conventional CT/VT and GOOSE binary input and binary output)
Slot No.
01
04
05
06
Module ID
NR1102
02
NR1401
03
NR1161
NR1213
NR1136
07
NR1504
10
14
15
NR1301
P1
MON
AI
DSP
CH
NETDSP
BI
PWR
6.2.2 ECT/EVT (For reference only)
06
07
08
11
12
NR1301
PWR module
05
BO module
04
NR1521A NR1521C
BO module
BI module
NR1503
NET-DSP Module
NR1136
DSP module
NR1161
CH Module
NR1213
DSP module
NR1161
MON module
NR1102
Slot No.
01
02
03
09
10
13
14
15
P1
The following typical wiring is given based on above hardware configuration
6-6
PCS-902 Line Distance Relay
Date: 2018-02-13

6 Hardware
CH-RX
Dedicated Channel
Or
Telecom Equipment
or
CH-TX
CH-RX
Fibre Optic
MU
Phase B
RX
TX
…
P111
OPTO+
P107
OPTO-
P108
Power
Supply
BO_FAIL
P103
BO_ALM
P101
COM
P105
BO_FAIL
P106
BO_ALM
P104
COM
B
0102
SGND
0103
0104
0101
SYN-
0102
SGND
0103
0104
0105
TXD
0106
SGND
0107
0804
+
0805
-
0806
+
0821
-
0822
1101
1102
1103
BO_02
1104
BO_11
1121
1122
1201
BO_01
1202
1203
BO_02
1204
BO_11
1221
1222
1502
1503
BO_CtrlCls1
1504
1517
BO_CtrlOpn5
1518
1519
BO_CtrlCls5
1520
1521
BO_Ctrl
1522
IRIG-B
PRINT
PRINTER
RTS
-
BO_01
Clock SYN
SYN+
0803
…
0101
+
1501
COM
To the screen of other coaxial
cable with single point earthing
A
0802
BO_CtrlOpn1
Signal Binary Output (option)
P102
-
…
PWR-
0801
…
Power supply for
opto-coupler (24V)
P110
BI_11
Signal Binary Output
External DC power
supply
PWR+
BI_03
Controlled by fault
detector element
Phase C
BI_02
+
…
Phase A
FC/PC Type (Rear)
FO interface for SV channel
Up to 8
(LC Type)
SV from
ECT/EVT
BI_01
*BI plug-in module can be common negative
terminal
CH-TX
P112
Multiplex
RJ45 (Front)
0225
Grounding
Bus
Figure 6.2-2 Typical wiring of PCS-902 (ECT/EVT)
PCS-902 ECT/EVT, GOOSE binary input and binary output
Slot No.
01
04
05
06
Module ID
NR1102
02
03
NR1161
NR1213
NR1136
07
NR1504
08
09
10
11
12
13
14
15
NR1301
P1
MON
DSP
CH
NETDSP
BI
PWR
PCS-902 ECT/EVT, conventional binary input and binary output
Slot No.
01
Module ID
02
03
04
05
06
NR1102
NR1161
NR1213
MON
DSP
CH
07
08
09
NR1136
NR1504
NETDSP
BI
11
12
13
NR1504
NR1521
NR1521
BI
BO
BO
PCS-902 Line Distance Relay
10
14
15
P1
NR1521
NR1521
NR1301
BO
BO
PWR
6-7
Date: 2018-02-13

6 Hardware
In the protection system adopting electronic current and voltage transformer (ECT/EVT), the
merging unit will merge the sample data from ECT/EVT, and then send it to the device through
multi-mode optical fibre. DSP module receives the data from merging unit through the optical-fibre
interface to complete the protection calculation and fault detector.
The difference between the hardware platform based on ECT/EVT and the hardware platform
based on conventional CT/VT lies in the receiving module of sampled values only, and the device
receives the sampled value from merging unit through multi-mode optical fibre.
6.2.3 CT Requirement
-Rated primary current Ipn:
According to the rated current or maximum load current of primary apparatus.
-Rated continuous thermal current Icth:
According to the maximum load current.
-Rated short-time thermal current Ith and rated dynamic current Idyn:
According to the maximum fault current.
-Rated secondary current Isn
-Accuracy limit factor Kalf:
Ipn
Rated primary current (amps)
Icth
Rated continuous thermal current (amps)
Ith
Rated short-time thermal current (amps)
Idyn
Rated dynamic current (amps)
Isn
Rated secondary current (amps)
Kalf
Accuracy limit factor Kalf=Ipal/Ipn
IPal
Rated accuracy limit primary current (amps)
Performance verification
Esl > Esl′
Esl
Rated secondary limiting e.m.f (volts)
Esl = kalf×Isn×(Rct+Rbn)
Kalf
Accuracy limit factor (Kalf=Ipal/Ipn)
IPal
Rated accuracy limit primary current (amps)
Ipn
Rated primary current (amps)
Isn
Rated secondary current (amps)
Rct
Current transformer secondary winding resistance. (ohms)
Rbn
Rated resistance burden (ohms)
2
Rbn=Sbn/Isn
Sbn
Rated burden (VAs)
Esl′
Required secondary limiting e.m.f (volts)
6-8
PCS-902 Line Distance Relay
Date: 2018-02-13

6 Hardware
Esl′ = k×Ipcf ×Isn×(Rct+Rb)/Ipn
k
Ipcf
stability factor = 2
Protective checking factor current (amps)
Same as the maximum prospective fault current
Isn
Rated secondary current (amps)
Rct
Current transformer secondary winding resistance. (ohms)
Rb
Real resistance burden (ohms)
Rb=Rr+2×RL+Rc
Rc
Contact resistance, 0.05-0.1 ohm (ohms)
RL
Resistance of a single lead from relay to current transformer (ohms)
Rr
Impedance of relay phase current input (ohms)
Ipn
Rated primary current (amps)
For example:
1.
Kalf=30, Isn=5A, Rct=1ohm, Sbn=60VA
Esl = kalf×Isn×(Rct+Rbn) = kalf×Isn×(Rct+ Sbn/ Isn2)
= 30×5×(1+60/25)=510V
2.
Ipcf=40000A, RL=0.5ohm, Rr=0.1ohm, Rc=0.1ohm, Ipn=2000A
Esl′ = 2×Ipcf×Isn×(Rct+Rb)/Ipn
= 2×Ipcf ×Isn×(Rct+(Rr+2×RL+Rc))/Ipn
= 2×40000×5×(1+(0.1+2×0.5+0.1))/2000=440V
Thus, Esl > Esl′
6.3 Plug-in Module Description
The device consists of PWR plug-in module, MON plug-in module, DSP plug-in module, AI plug-in
module, BI plug-in module, BO plug-in module, CH plug-in module and NET-DSP plug-in module.
Terminal definitions and application of each plug-in module are introduced as follows.
6.3.1 PWR Plug-in Module (Power Supply)
PWR module is a DC/DC converter with electrical insulation between input and output. It has an
input voltage range as described in Chapter 2 “Technical Data”. The standardized output voltages
are +5V and +24V DC. The tolerances of the output voltages are continuously monitored.
The +5V DC output provides power supply for all the electrical elements that need +5V DC power
supply in this device.
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device is
in cold reserve.
A 12-pin connector is fixed on PWR module. The terminal definition of the connector is described
PCS-902 Line Distance Relay
6-9
Date: 2018-02-13

6 Hardware
as below.
NR1301
5V OK
ALM
BO_ALM BO_FAIL
ON
OFF
1
BO_COM1
2
BO_FAIL
3
BO_ALM
4
BO_COM2
5
BO_FAIL
6
BO_ALM
7
OPTO+
8
OPTO-
9
10 PWR+
11 PWR12 GND
Figure 6.3-1 View of PWR plug-in module
The power switch in the dotted box of above figure maybe is not existed.
01
BO_FAIL
02
BO_ALM
03
04
BO_FAIL
05
BO_ALM
06
Figure 6.3-2 Output contacts of PWR plug-in module
Terminal definition and description is shown as follows:
Table 6.3-1 Terminal definition and description of PWR plug-in module
Terminal No.
Symbol
Description
01
BO_COM1
Common terminal 1
02
BO_FAIL
Device failure output 1 (01-02, NC)
03
BO_ALM
Device abnormality alarm output 1 (01-03, NO)
04
BO_COM2
Common terminal 2
05
BO_FAIL
Device failure output 2 (04-05, NC)
6-10
PCS-902 Line Distance Relay
Date: 2018-02-13

6 Hardware
Terminal No.
Symbol
Description
06
BO_ALM
Device abnormality alarm output 2 (04-06, NO)
07
OPTO+
Positive power supply for BI module (24V)
08
OPTO-
Negative power supply for BI module (24V)
09
Blank
Not used
10
PWR+
Positive input of power supply for the device (250V/220V/125V/110V)
11
PWR-
Negative input of power supply for the device (250V/220V/125V/110V)
12
GND
Grounded connection of the power supply
NOTICE!
The standard rated voltage of PWR module is self-adaptive to 88~300 Vdc. If input
voltage is out of range, an alarm signal (Fail_Device) will be issued. For non-standard
rated voltage power supply module please specify when place order, and check if the
rated voltage of power supply module is the same as the voltage of power source
before the device being put into service.
PWR module provides terminal 12 and grounding screw for device grounding. Terminal
12 shall be connected to grounding screw and then connected to the earth copper bar
of panel via dedicated grounding wire.
Effective grounding is the most important measure for a device to prevent EMI, so
effective grounding must be ensured before the device is put into service.
PCS-902, like almost all electronic relays, contains electrolytic capacitors. These
capacitors are well known to be subject to deterioration over time if voltage is not
applied periodically. Deterioration can be avoided by powering the relays up once a
year.
6.3.2 MON Plug-in Module (Monitor)
MON module consists of high-performance built-in processor, FLASH, SRAM, SDRAM, Ethernet
controller and other peripherals. Its functions include management of the complete device, human
machine interface, communication and waveform recording etc.
MON module uses the internal bus to receive the data from other modules of the device. It
communicates with the LCD module by RS-485 bus. This module comprises 100BaseT Ethernet
interfaces, RS-485 communication interfaces that exchange information with above system by
using IEC 61850, PPS/IRIG-B differential time synchronization interface and RS-232 printing
interface.
Modules with various combinations of memory and interface are available as shown in the table
below.
PCS-902 Line Distance Relay
6-11
Date: 2018-02-13

6 Hardware
CAUTION!
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.
NR1102D
NR1102I
NR1101E
NR1102N
TX
TX
RX
RX
TX
TX
NR1101F
ETHERNET
ETHERNET
ETHERNET
RX
ETHERNET
RX
ETHERNET
Figure 6.3-3 View of MON plug-in module
Module ID
Memory
Interface
Terminal No.
4 RJ45 Ethernet
RS-485
NR1102D
128M DDR
128M DDR
Physical Layer
To SCADA
01
SYN+
02
SYN-
To
03
SGND
synchronization
clock
Twisted pair wire
04
RS-232
NR1102I
Usage
05
RTS
06
TXD
07
SGND
To printer
Cable
2 RJ45 Ethernet
To SCADA
Twisted pair wire
2 FO Ethernet
To SCADA
Optical fibre ST
RS-485
01
SYN+
02
SYN-
To
03
SGND
synchronization
RTS
To printer
clock
Twisted pair wire
04
RS-232
05
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independent
256M DDR
TXD
07
SGND
2 RJ45 Ethernet
To SCADA
Twisted pair wire
2 FO Ethernet
To SCADA
Optical fiber ST
NR1102N
(Support
06
RS-485/TTL
01
SYN+
02
SYN-
To
SGND
synchronization
03
clock
Twisted pair wire
04
MAC)
RS-232
05
RTS
06
TXD
07
SGND
2 RJ45 Ethernet
RS-485
To printer
Cable
To SCADA
01
A
02
B
03
SGND
To SCADA
04
RS-485
NR1101E
128M DDR
05
A
06
B
07
SGND
Twisted pair wire
To SCADA
08
RS-485
09
SYN+
10
SYN-
To
11
SGND
synchronization
clock
12
RS-232
13
RTS
14
TXD
15
SGND
To printer
Cable
16
3 RJ45 Ethernet
RS-485
To SCADA
01
A
02
B
03
SGND
To SCADA
04
NR1101F
(Support
independent
256M DDR
RS-485
05
A
06
B
07
SGND
Twisted pair wire
To SCADA
08
MAC)
RS-485/TTL
09
SYN+
10
SYN-
To
11
SGND
synchronization
clock
12
RS-232
13
RTS
14
TXD
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15
SGND
16
The correct connection is shown in Figure 6.3-4. Generally, the shielded cable with two pairs of
twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to connect
the “+” and “–” terminals of difference signal. The other pair of twisted pairs are used to connect
the signal ground of the communication interface. The module reserves a free terminal for all the
communication ports. The free terminal has no connection with any signal of the device, and it is
used to connect the external shields of the cable when connecting multiple devices in series. The
external shield of the cable shall be grounded at one of the ends only.
Twisted pair wire
01
B
02
SGND
03
COM
A
Twisted pair wire
SYN+
01
SYN-
02
SGND
03
Clock SYN
To the screen of other coaxial
cable with single point earthing
04
04
Cable
05
TXD
06
SGND
07
PRINT
RTS
Figure 6.3-4 Connection of communication terminal
Pin1
Pin2
Pin3
Figure 6.3-5 Jumpers of clock synchronization port
NOTICE!
As shown in Figure 6.3-5, the external receiving mode of IRIG-B differential time
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synchronization interface can be set by the jumper J8&J9.
Jumper
RS-485
TTL
J8
Pin-1 and Pin-2 are connected. (RS-485+)
Pin-2 and Pin-3 are connected. (TTL+)
J9
Pin-1 and Pin-2 are connected. (RS-485-)
Pin-2 and Pin-3 are connected. (TTL-)
6.3.3 AI Plug-in Module (Analog Input)
AI module is applicable for power plant or substation with conventional VT and CT. It is assigned to
slot numbers 02 and 03. However, the module is not required if the device is used with ECT/EVT.
For AI module, if the plug is not put in the socket, external CT circuit is closed itself. Just shown as
below.
Plug
Socket
In
Out
plug is not put in the socket
In
Out
Put the plug in the socket
Figure 6.3-6 Schematic diagram of CT circuit automatically closed
There are three types of AI module with rating 1A (NR1401), 5A (NR1401) or 1A/5A (NR1408).
Please declare which kind of AI module is needed before ordering. Maximum linear range of the
current converter is 40In.
1.
One CT group input without synchronism voltage switchover (optional NR1401 or NR1408)

NR1401
For one CT group input, three phase currents (Ia, Ib and Ic) and residual current from parallel line
(for mutual compensation) are input to AI module separately. Terminal 01, 03, 05 and 07 are
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polarity marks. It is assumed that polarity mark of CT installed on line is at line side.
Three phase voltages (Ua, Ub, and Uc) for protection calculation and one synchronism voltage are
input to AI module. The synchronism voltage could be any phase-to-ground voltage or
phase-to-phase voltage.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.
In order to accurately locate the fault for parallel lines arrangement, residual current from parallel
line is required to be connected to the device to eliminate the mutual effect between the parallel
lines. Otherwise, residual current from parallel line is not necessary.
Relevant description about parallel line to refer to section “Fault Location”.
A
B
C
P2
S2
P2
S2
P1
S1
P1
S1
02
01
02
01
04
03
04
03
06
05
06
05
08
07
08
07
Figure 6.3-7 Current connection of AI plug-in module (NR1401)
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A
B
C
13
14
15
16
17
18
19
20
Figure 6.3-8 Voltage connection 1 of AI plug-in module (NR1401)
A
B
C
13
14
15
16
17
18
19
20
Figure 6.3-9 Voltage connection 2 of AI plug-in module (NR1401)
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Ia
01
Ian
02
Ib
03
Ibn
04
Ic
05
Icn
06
IM0
07
IM0n
08
NR1401
09
10
11
12
Ua
13
Uan
14
Ub
15
Ubn
16
Uc
17
Ucn
18
Us
19
Usn
20
21
22
23
24
Figure 6.3-10 View of AI plug-in module for one CT group input (NR1401)
Table 6.3-2 lists the terminal number and definition of AI module.
Table 6.3-2 Terminal definition of AI module (NR1401)
Terminal No.
Definition
Definition
01
Ia
The current of A-phase (Polarity mark)
02
Ian
The current of A-phase
03
Ib
The current of B-phase (Polarity mark)
04
Ibn
The current of B-phase
05
Ic
The current of C-phase (Polarity mark)
06
Icn
The current of C-phase
07
IM0
Residual current of parallel line (Polarity mark)
08
IM0n
Residual current of parallel line
09
Reserve
10
Reserve
11
Reserve
12
Reserve
13
Ua
The voltage of A-phase (Polarity mark)
14
Uan
The voltage of A-phase
15
Ub
The voltage of B-phase (Polarity mark)
16
Ubn
The voltage of B-phase
17
Uc
The voltage of C-phase (Polarity mark)
18
Ucn
The voltage of C-phase
19
Us
Synchronism voltage (Polarity mark)
20
Usn
Synchronism voltage
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Terminal No.

Definition
21
Reserve
22
Reserve
23
Reserve
24
Reserve
25
GND
Definition
Ground
NR1408
For one CT group input, three phase currents (Ia, Ib and Ic) and residual current from parallel line
(for mutual compensation) are input to AI module separately. Terminal 01 (or 03), 05 (or 07), 09 (or
11) and 13 (or 15) are polarity marks. It is assumed that polarity mark of CT installed on line is at
line side.
Three phase voltages (Ua, Ub, and Uc) for protection calculation and one synchronism voltage are
input to AI module. The synchronism voltage could be any phase-to-ground voltage or
phase-to-phase voltage.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.
In order to accurately locate the fault for parallel lines arrangement, residual current from parallel
line is required to be connected to the device to eliminate the mutual effect between the parallel
lines. Otherwise, residual current from parallel line is not necessary.
Relevant description about parallel line to refer to section “Fault Location”.
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A
B
C
P2
S2
P2
S2
P1
S1
P1
S1
02/04
01/03
02/04
01/03
06/08
05/07
06/08
05/07
10/12
09/11
10/12
09/11
14/16
13/15
14/16
13/15
Figure 6.3-11 Current connection of AI plug-in module (NR1408)
A
B
C
17
18
19
20
21
22
23
24
Figure 6.3-12 Voltage connection 1 of AI plug-in module (NR1408)
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A
B
C
17
18
19
20
21
22
23
24
Figure 6.3-13 Voltage connection 2 of AI plug-in module (NR1408)
Ia-1A
01
Ian-1A
02
Ia-5A
03
Ian-5A
04
Ib-1A
05
Ibn-1A
06
Ib-5A
07
Ibn-5A
08
Ic-1A
09
Icn-1A
10
Ic-5A
11
Icn-5A
12
IM0-1A
13
IM0n-1A
14
IM0-5A
15
IM0n-5A
16
Ua
17
Uan
18
Ub
19
Ubn
20
Uc
21
Ucn
22
Us
23
Usn
24
NR1408
Figure 6.3-14 View of AI plug-in module for one CT group input (NR1408)
Table 6.3-3 lists the terminal number and definition of AI module.
Table 6.3-3 Terminal definition of AI module (NR1408)
Terminal No.
01
Definition
Ia-1A
Definition
The current of A-phase (Polarity mark)
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Terminal No.
2.
Definition
Definition
02
Ian-1A
The current of A-phase
03
Ia-5A
The current of A-phase (Polarity mark)
04
Ian-5A
The current of A-phase
05
Ib-1A
The current of B-phase (Polarity mark)
06
Ibn-1A
The current of B-phase
07
Ib-5A
The current of B-phase (Polarity mark)
08
Ibn-5A
The current of B-phase
09
Ic-1A
The current of C-phase (Polarity mark)
10
Icn-1A
The current of C-phase
11
Ic-5A
The current of C-phase (Polarity mark)
12
Icn-5A
The current of C-phase
13
IM0-1A
Residual current of parallel line (Polarity mark)
14
IM0n-1A
Residual current of parallel line
15
IM0-5A
Residual current of parallel line (Polarity mark)
16
IM0n-5A
Residual current of parallel line
17
Ua
The voltage of A-phase (Polarity mark)
18
Uan
The voltage of A-phase
19
Ub
The voltage of B-phase (Polarity mark)
20
Ubn
The voltage of B-phase
21
Uc
The voltage of C-phase (Polarity mark)
22
Ucn
The voltage of C-phase
23
Us
Synchronism voltage (Polarity mark)
24
Usn
Synchronism voltage
25
GND
Ground
Two CT groups input with synchronism voltage switchover (only NR1401)
For two circuit breakers configuration with two CT groups input, three phase currents
corresponding to CB1 and CB2 respectively (Ia1, Ib1, Ic1 and Ia2, Ib2, Ic2) are input to AI module.
Terminal 01, 03, 05, 07, 09 and 11 are polarity marks. It is assumed that polarity mark of CT
installed on line is at line side.
Three phase voltages (Ua, Ub, and Uc) are input to AI module. UB1, UB2 and UL2 are the
synchronism voltage from bus VT and line VT used for synchrocheck, it could be any
phase-to-ground voltage or phase-to-phase voltage. The device can automatically switch
synchronism voltage according to auxiliary contact of CB position or DS position.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.
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P2
P1
P1
P2
S1
S2
A
B
S2
S1
02
01
04
03
06
05
08
07
10
09
12
11
C
Figure 6.3-15 Current connection of AI plug-in module (NR1401)
A
B
C
A
13
14
15
16
17
18
19
20
21
22
23
24
B
C
Figure 6.3-16 Voltage connection of AI plug-in module (NR1401)
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Ia1
01
Ia1n
02
Ib1
03
Ib1n
04
Ic1
05
Ic1n
06
Ia2
07
Ia2n
08
Ib2
09
Ib2n
10
Ic2
11
Ic2n
12
Ua
13
Uan
14
Ub
15
Ubn
16
Uc
17
Ucn
18
UB1
19
UB1n
20
UL2
21
UL2n
22
UB2
23
UB2n
24
NR1401
Figure 6.3-17 View of AI plug-in module for two CT group input (NR1401)
Table 6.3-4 lists the terminal number and definition of AI module.
Table 6.3-4 Terminal definition of AI module (NR1401)
Terminal No.
Definition
Definition
01
Ia1
The current of A-phase (Polarity mark)
02
Ia1n
The current of A-phase
03
Ib1
The current of B-phase (Polarity mark)
04
Ib1n
The current of B-phase
05
Ic1
The current of C-phase (Polarity mark)
06
Ic1n
The current of C-phase
07
Ia2
The current of A-phase (Polarity mark)
08
Ia2n
The current of A-phase
09
Ib2
The current of B-phase (Polarity mark)
10
Ib2n
The current of B-phase
11
Ic2
The current of C-phase (Polarity mark)
12
Ic2n
The current of C-phase
13
Ua
The voltage of A-phase (Polarity mark)
14
Uan
The voltage of A-phase
15
Ub
The voltage of B-phase (Polarity mark)
16
Ubn
The voltage of B-phase
17
Uc
The voltage of C-phase (Polarity mark)
18
Ucn
The voltage of C-phase
19
UB1
The voltage of bus 1 (Polarity mark)
20
UB1n
The voltage of bus 1
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Terminal No.
3.
Definition
Definition
21
UL2
The voltage of line 2 (Polarity mark)
22
UL2n
The voltage of line 2
23
UB2
The voltage of bus 2 (Polarity mark)
24
UB2n
The voltage of bus 2
25
GND
Ground
Two CT groups input without synchronism voltage switchover (only NR1401)
For two circuit breakers configuration with two CT groups input, three phase currents
corresponding to CB1 and CB2 respectively (Ia1, Ib1, Ic1 and Ia2, Ib2, Ic2), and residual current
from parallel line (for mutual compensation) are input to AI module. Terminal 01, 03, 05, 07, 09, 11
and 13 are polarity marks. It is assumed that polarity mark of CT installed on line is at line side.
Three phase voltages (Ua, Ub, and Uc) for protection calculation and one synchronism voltage are
input to AI module. The synchronism voltage could be any phase-to-ground voltage or
phase-to-phase voltage.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.
P2
P1
P1
P2
A
B
S2
S1
S1
02
01
04
03
06
05
08
07
10
09
12
11
14
13
S2
C
To parallel line
From parallel line
Figure 6.3-18 Current connection of AI plug-in module (NR1401)
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A
B
C
A
15
16
17
18
19
20
21
22
23
24
B
C
Figure 6.3-19 Voltage connection of AI plug-in module (NR1401)
Ia1
01
Ia1n
02
Ib1
03
Ib1n
04
Ic1
05
Ic1n
06
Ia2
07
Ia2n
08
Ib2
09
Ib2n
10
Ic2
11
Ic2n
12
IM0
13
IM0n
14
Ua
15
Uan
16
Ub
17
Ubn
18
Uc
19
Ucn
20
Us
21
Usn
22
NR1401
23
24
Figure 6.3-20 View of AI plug-in module for two CT group input (NR1401)
Table 6.3-5 lists the terminal number and definition of AI module.
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Table 6.3-5 Terminal definition of AI module (NR1401)
Terminal No.
Definition
Definition
01
Ia1
The current of A-phase (Polarity mark)
02
Ia1n
The current of A-phase
03
Ib1
The current of B-phase (Polarity mark)
04
Ib1n
The current of B-phase
05
Ic1
The current of C-phase (Polarity mark)
06
Ic1n
The current of C-phase
07
Ia2
The current of A-phase (Polarity mark)
08
Ia2n
The current of A-phase
09
Ib2
The current of B-phase (Polarity mark)
10
Ib2n
The current of B-phase
11
Ic2
The current of C-phase (Polarity mark)
12
Ic2n
The current of C-phase
13
IM0
Residual current of parallel line (Polarity mark)
14
IM0n
Residual current of parallel line
15
Ua
The voltage of A-phase (Polarity mark)
16
Uan
The voltage of A-phase
17
Ub
The voltage of B-phase (Polarity mark)
18
Ubn
The voltage of B-phase
19
Uc
The voltage of C-phase (Polarity mark)
20
Ucn
The voltage of C-phase
21
Us
Synchronism voltage (Polarity mark)
22
Usn
Synchronism voltage
23
Reserve
24
Reserve
25
GND
Ground
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6.3.4 DSP Plug-in Module (Logic Process)
NR1161
Figure 6.3-21 View of DSP plug-in module
This device can be equipped with 2 DSP plug-in modules at most and 1 DSP plug-in module at
least. The default DSP plug-in module is necessary, which mainly is responsible for protection
function including fault detector and protection calculation.
The default module consists of high-performance double DSP (digital signal processor),16-digit
high-accuracy ADC that can perform synchronous sampling and manage other peripherals. One
of double DSP is responsible for protection calculation, and can fulfill analog data acquisition,
protection logic calculation and tripping output. The other is responsible for fault detector, and can
fulfill analog data acquisition, fault detector and providing power supply to output relay.
When the module is connected with conventional CT/VT, it can perform the synchronous data
acquisition through AI plug-in module. When the module is connected with ECT/EVT, it can
receive the real-time synchronous sampled value from merging unit through NET-DSP plug-in
module.
The other module is optional and it is not required unless control and manual closing with
synchronism check are equipped with this device. The default DSP plug-in module is fixed at slot
04 and the option DSP plug-in module is fixed at slot 06.
6.3.5 NET-DSP Plug-in Module (GOOSE and SV)
NOTICE!
NET-DSP plug-in module is only applied in process level of digital substation.
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NR1136A
NR1136C
RX
Figure 6.3-22 View of NET-DSP plug-in module
This module consists of high-performance DSP (digital signal processor), 2~8 100Mbit/s
optical-fibre interface (LC type) and selectable IRIG-B interface (ST type). It supports GOOSE and
SV by IEC 61850-9-2 protocols. It can receive and send GOOSE messages to intelligent control
device, and receive SV from MU (merging unit).
This module supports IEEE1588 network time protocol, E2E and P2P defined in IEEE1588
protocol can be selected. This module supports Ethernet IEEE802.3 time adjustment message
format, UDP time adjustment message format and GMRP.
CAUTION!
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.
The device can output q data by GOOSE, and an output signal is provided “Output_q”. This signal
is used to indicate the quality of all output signals. According to the standard definition about the
quality by IEC 61850, the value of this signal is “0” under normal conditions, and it will be “2048”
(Bit1 is “1”, and other bits is “0”) when the device is under maintenance condition.
The definition of each bit about quality signal by IEC 61850 is as below.
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Table 6.3-6 Encoding of IEC 61850-7-3 quality
Bit (s)
IEC 61850-7-3
Bit
0-1
Attribute name
Validity
Bit-String
Attribute value
Value
Good
00
Invalid
01
Reserved
10
Questionable
11
Default
00
2
Overflow
TRUE
FALSE
3
OutofRange
TRUE
FALSE
4
BadReference
TRUE
FALSE
5
Oscillatory
TRUE
FALSE
6
Failure
TRUE
FALSE
7
OldData
TRUE
FALSE
8
Inconsistent
TRUE
FALSE
9
Inaccurate
TRUE
FALSE
10
Source
Process
0
0
Subsituted
1
11
Test
TRUE
FALSE
12
OperatorBlocked
TRUE
FALSE
The method of adding q data is as bellow steps.
1.
Step1: Open the DEV file and find “MMS_GOOSE_Out” page.
2.
Step2: Taking “PTRC_out” module as an example, which can be found in “Symbol Library”
and instanced as bellow.
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3.
Step3: Double click the instanced module, the parameter list is displayed as bellow. Tr1~Tr8
are used for sending signals, q1~q8 are used for q data, the relationship between them is one
to one. Only one total q data can be added to all 8 sending signals by “batch_q”.
4.
Step4: The output q data, named “Output_q” in variable library, is used for all sending signals.
The path is shown as bellow which is marked in red color.
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5.
Step5: Put the mouse on the “Output_q” signal, hold the left button of the mouse and drag it to
the corresponding position, and then release. The detail is as bellow.
After the above steps, save the modifications and compress driver file. Check the latest GOOSE
and CID file.
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6.3.6 CH Plug-in Module (Fibre Optical Channel Interface)
NR1213
NR1213
NR1213
NR1213
TX
TX
TX
TX
RX
RX
RX
RX
TX
TX
RX
RX
NR1213A
NR1213
NR1213A-100
NR1213B
NR1213
NR1214
TX
TX
RX
RX
NR1213B-100
NR1214
TX1
TX1
RX1
RX1
TX1
TX1
TX1
RX1
RX1
RX1
NR1213F
NR1213F-100
NR1214A
NR1214B
Figure 6.3-23 View of CH plug-in module
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Type
Wavelength
Application
NR1213A
1310nm
Single-mode, single channel, transmission distance <60 km
NR1213A-100
1550nm
Single-mode, single channel, transmission distance <110 km
NR1213B
1310nm
Single-mode, dual channels, transmission distance <60 km
NR1213B-100
1550nm
Single-mode, dual channels, transmission distance <110 km
1310nm
Single-mode, single channel, transmission distance <60 km
850nm
Multi-mode, single channel, transmission distance <2 km
1550nm
Single-mode, single channel, transmission distance <110 km
850nm
Multi-mode, single channel, transmission distance <2 km
NR1214A
850nm
Multi-mode, single channel, transmission distance <2 km
NR1214B
850nm
Multi-mode, dual channels, transmission distance <2 km
NR1213F
NR1213F-100
PCS-902 series can exchange information with the device at the remote end through a dedicated
optical fibre channel or multiplex channel. The module transmits and receives optical signal using
FC/PC or ST optical connector.
The parameters are shown as follows:
Item
Type1
Type2
Type3
Fiber Optic
Single mode, Rec.G652
Single mode, Rec.G652
Multi mode, Rec.G652
Wavelength
1310nm
1550nm
850nm
Transmission power
-13.0±3.0 dBm
-5.0 dBm±3.0 dBm
-12dBm~-20 dBm
Receiving sensitivity
Min.-37 dBm
Min.-36 dBm
Min.-30 dBm
Transmission distance
Max.60 km
Max.110 km
Max.2 km
Optical overload point
Min.-3 dBm
Min.-3 dBm
Min.-8 dBm
NOTICE!
When using dedicated optical fibre channel, if the transmission distance is longer than
50km, the transmitted power may be enhanced to ensure received power larger than
receiving sensitivity. Please notify supplier before ordering and it will be considered as
special project using 1550nm laser diode.
When using multiplex channel, the sending power of the device is fixed.
When using channel multiplexing equipment, the parameters are shown as follows:
1.
Channel type: digital optical fibre or digital microwave.
2.
Interface standard: 2048kbit/s E1
The device′s requirements on the channel are shown as follows:
1.
The routine of both direction shall be same to each other, so the time delays of both direction
are the same.
2.
The maximum one-way channel propagation delay shall be less than 15 ms.
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CAUTION!
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.
6.3.7 BI Plug-in Module (Binary Input)
There are five kinds of BI modules available, NR1503A, NR1503AR, NR1504A, NR1504AR and
NR1508A. Up to 3 BI modules can be equipped with one device.
Voltage
264
176
154
140
110
87.5
77
62.5
55
Operation
Operation uncertain
No operation
0
110V
125V
220V
220V
Figure 6.3-24 Voltage dependence for binary inputs
The well-designed debounce technique is adopted in this device, and the state change of binary
input within “Debounce time” will be ignored. As shown in Figure 6.3-25.
All binary inputs should setup necessary debounce time to prevent the device from undesired
operation due to transient interference or mixed connection of AC system and DC system. When
the duration of binary input is less than the debounce time, the state of the binary input will be
ignored. When the duration of binary input is greater than the debounce time, the state of the
binary input will be validated and wrote into SOE.
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Binary input state
Validate binary input state change & write it
into SOE record
1
0
Debounce time of
delayed pickup
Debounce time of
delayed dropout
Time
Figure 6.3-25 Debounce technique
In order to meet flexible configurable requirement for different project feild, all binary inputs
provided by the device are configurable. The device provide two parameters to setup debounce
time of delayed pickup and debounce time of delayed dropout based on specific binary signal.
The configurable binary signals can be classified as follows:
1.
Type 1
This type of binary inputs include enable/disable of protection functions, AR mode selection,
"BI_Print", "BI_RstTarg", "BI_Maintenance", disconnector position, settings group switch, open
and close command of circuit breaker and disconnector, enable/disable of auxiliary functions (for
example, manually trigger recording). They is on the premise of reliability, and the debounce time
of delayed pickup and delayed dropout is recommended to set as 100ms at least.
2.
Type 2
This type of binary inputs include "85-x.Recv1", "85-x.RecvB", "85-x.RecvC", "85-x.Recv2" and
"BI_TimeSyn", the debounce time of delayed pickup and delayed dropout is usually set as 0ms.
3.
Type 3
This type of binary inputs include "BI_BFI_1", "BI_BFI_2", "TT.Init", "CSWIxx.Cmd_LocCtrl",
"CSWIxx.Cmd_RmtCtrl".
Debounce time
BI
Input Signal.X1
t1
t2
&
Time delay
Output
SIG Operation condition

Time delay is equal to 0
The debounce time of delayed pickup and delayed dropout is recommended to set as 15ms, in
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order to prevent binary signals from misoperation due to mixed connection of AC system and DC
system.

Time delay is not equal to 0
The debounce time of delayed pickup and delayed dropout is recommended to set as (-t1+
t2+Time delay)≥15ms, in order to prevent binary signals from misoperation due to mixed
connection of AC system and DC system.
ti is the debounce time of delayed pickup.
t2 is the debounce time of delayed dropout.
4.
Type 4
This type of binary inputs are usually used as auxiliary input condition, and include the following
signals.
No.
Binary input
1
CBx.52b_PhA
2
CBx.52b_PhB
3
CBx.52b_PhC
4
CBx.52b
5
CBx.52a
6
CBx.TCCS.Input
7
85-x.Abnor_Ch1
8
85-x.Abnor_Ch2
9
85-x.ExTrp
10
85-x.Unblocking1
11
85-x.Unblocking2
12
CBx.50DZ.Init
13
PrepTrp3P
14
CBx.50BF.ExTrp3P_L
15
CBx.50BF.ExTrp3P_GT
16
CBx.50BF.ExTrpA
17
CBx.50BF.ExTrpB
18
CBx.50BF.ExTrpC
19
CBx.50BF.ExTrp_WOI
20
CBx.25.MCB_VT_UL1
21
CBx.25.MCB_VT_UL2
22
CBx.25.MCB_VT_UB1
23
CBx.25.MCB_VT_UB2
24
79.Trp
25
79.Trp3P
26
79.TrpA
27
79.TrpB
28
79.TrpC
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29
79.WaitMaster
30
79.CB_Healthy
31
79.Clr_Counter
32
79.Ok_Chk
33
79.Lockout
34
79.PLC_Lost
35
VTS.MCB_VT
The debounce time of delayed pickup and delayed dropout is recommended to set as 5ms.
1.
NR1503
Each BI module is with a 22-pin connector for 11 binary inputs, and its rated voltage can be
selected to be 110Vdc, 125Vdc, 220Vdc. Each binary input of NR1503A and NR1503AR has
independent negative power input of opto-coupler and can be configurable. NR1503A′s pickup
voltage and dropoff voltage are fixed value, and the range is from 55%Un to 70%Un. NR1503AR′s
pickup voltage and dropoff voltage are settable by the setting [xx.U_Pickup_BI] and
[xx.U_Dropoff_BI] from 55%Un to 80%Un.
NR1503
BI_01
01
Opto01-
02
BI_02
03
Opto02-
04
BI_03
05
Opto03-
06
BI_04
07
Opto04-
08
BI_05
09
Opto05-
10
BI_06
11
Opto06-
12
BI_07
13
Opto07-
14
BI_08
15
Opto08-
16
BI_09
17
Opto09-
18
BI_10
19
Opto10-
20
BI_11
21
Opto11-
22
Figure 6.3-26 View of BI plug-in module (NR1503)
[BI_n] can be configured as a specified binary input by PCS-Explorer software (n=01, 02, ……).
Terminal description for NR1503 is shown as follows.
Terminal No.
Symbol
Description
01
BI_01
Configurable binary input 1
02
Opto01-
Negative supply of configurable binary input 1
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Terminal No.
Symbol
Description
03
BI_02
Configurable binary input 2
04
Opto02-
Negative supply of configurable binary input 2
05
BI_03
Configurable binary input 3
06
Opto03-
Negative supply of configurable binary input 3
07
BI_04
Configurable binary input 4
08
Opto04-
Negative supply of configurable binary input 4
09
BI_05
Configurable binary input 5
10
Opto05-
Negative supply of configurable binary input 5
11
BI_06
Configurable binary input 6
12
Opto06-
Negative supply of configurable binary input 6
13
BI_07
Configurable binary input 7
14
Opto07-
Negative supply of configurable binary input 7
15
BI_08
Configurable binary input 8
16
Opto08-
Negative supply of configurable binary input 8
17
BI_09
Configurable binary input 9
18
Opto09-
Negative supply of configurable binary input 9
19
BI_10
Configurable binary input 10
20
Opto10-
Negative supply of configurable binary input 10
21
BI_11
Configurable binary input 11
22
Opto11-
Negative supply of configurable binary input 11
2.
NR1504
Each BI module is with a 22-pin connector for 18 binary inputs, and its rated voltage can be
selected to be 110Vdc, 125Vdc, 220Vdc. All binary inputs of NR1504A and NR1504AR share one
common negative power input and can be configurable. NR1504A′s pickup voltage and dropoff
voltage are fixed value, and the range is from 55%Un to 70%Un. NR1504AR′s pickup voltage and
dropoff voltage are settable by the setting [xx.U_Pickup_BI] and [xx.U_Dropoff_BI] from 55%Un to
80%Un.
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NR1504
Opto+
01
BI_01
02
BI_02
03
BI_03
04
BI_04
05
BI_05
06
BI_06
07
08
BI_07
09
BI_08
10
BI_09
11
BI_10
12
BI_11
13
BI_12
14
15
BI_13
16
BI_14
17
BI_15
18
BI_16
19
BI_17
20
BI_18
21
COM-
22
Figure 6.3-27 View of BI plug-in module (NR1504)
[BI_n] can be configured as a specified binary input by PCS-Explorer software (n=01, 02, ……).
Terminal description for NR1504 is shown as follows.
Terminal No.
Symbol
Description
01
Opto+
Positive supply of power supply of the module
02
BI_01
Configurable binary input 1
03
BI_02
Configurable binary input 2
04
BI_03
Configurable binary input 3
05
BI_04
Configurable binary input 4
06
BI_05
Configurable binary input 5
07
BI_06
Configurable binary input 6
08
Blank
Not used
09
BI_07
Configurable binary input 7
10
BI_08
Configurable binary input 8
11
BI_09
Configurable binary input 9
12
BI_10
Configurable binary input 10
13
BI_11
Configurable binary input 11
14
BI_12
Configurable binary input 12
15
Blank
Not used
16
BI_13
Configurable binary input 13
17
BI_14
Configurable binary input 14
18
BI_15
Configurable binary input 15
19
BI_16
Configurable binary input 16
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Terminal No.
Symbol
Description
20
BI_17
Configurable binary input 17
21
BI_18
Configurable binary input 18
22
COM-
Common terminal of negative supply of binary inputs
3.
NR1508
NR1508A is with a 22-pin connector for 11 binary inputs, and its rated voltage is 220Vdc. Each
binary input of NR1508A has independent negative power input of opto-coupler and can be
configurable. NR1508A′s pickup voltage and dropoff voltage are fixed value, and the range is from
75%Un to 80%Un.
NR1508A
BI_01
01
Opto01-
02
BI_02
03
Opto02-
04
BI_03
05
Opto03-
06
BI_04
07
Opto04-
08
BI_05
09
Opto05-
10
BI_06
11
Opto06-
12
BI_07
13
Opto07-
14
BI_08
15
Opto08-
16
BI_09
17
Opto09-
18
BI_10
19
Opto10-
20
BI_11
21
Opto11-
22
Figure 6.3-28 View of BI plug-in module (NR1508A)
[BI_n] can be configured as a specified binary input by PCS-Explorer software (n=01, 02, ……).
Terminal description for NR 1508A is shown as follows.
Terminal No.
Symbol
Description
01
BI_01
Configurable binary input 1
02
Opto01-
Negative supply of configurable binary input 1
03
BI_02
Configurable binary input 2
04
Opto02-
Negative supply of configurable binary input 2
05
BI_03
Configurable binary input 3
06
Opto03-
Negative supply of configurable binary input 3
07
BI_04
Configurable binary input 4
08
Opto04-
Negative supply of configurable binary input 4
09
BI_05
Configurable binary input 5
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Terminal No.
Symbol
Description
10
Opto05-
Negative supply of configurable binary input 5
11
BI_06
Configurable binary input 6
12
Opto06-
Negative supply of configurable binary input 6
13
BI_07
Configurable binary input 7
14
Opto07-
Negative supply of configurable binary input 7
15
BI_08
Configurable binary input 8
16
Opto08-
Negative supply of configurable binary input 8
17
BI_09
Configurable binary input 9
18
Opto09-
Negative supply of configurable binary input 9
19
BI_10
Configurable binary input 10
20
Opto10-
Negative supply of configurable binary input 10
21
BI_11
Configurable binary input 11
22
Opto11-
Negative supply of configurable binary input 11
NOTICE!
A default configuration is given for first four binary signals (BI_01, BI_02, BI_03, BI_04)
in BI plug-in module at slot 12, and they are [BI_TimeSyn], [BI_Print], [BI_Maintenance]
and [BI_RstTarg] respectively. Only BI_02 and BI_04 can be configured as other
signals.
1.
Binary input: [BI_TimeSyn]
It is used to receive clock synchronization signal from clock synchronization device, the binary
input [BI_TimeSyn] will change from “0” to “1” once pulse signal is received. When the device
adopts “Conventional” mode as clock synchronization mode (refer to section “Communication
Settings”), the device can receives PPM (pulse per minute) and PPS (pulse per second). If the
setting [Opt_TimeSyn] is set as other values, this binary input is invalid.
2.
Binary input: [BI_Print]
It is used to manually trigger printing latest report when the equipment is configured as manual
printing mode by logic setting [En_AutoPrint]=0. The printer button is located on the panel usually.
If the equipment is configured as automatic printing mode ([En_AutoPrint]=1), report will be printed
automatically as soon as it is formed.
3.
Binary input: [BI_Maintenance]
It is used to block communication export when this binary input is energized. During device
maintenance or testing, this binary input is then energized not to send reports via communication
port, local display and printing still work as usual. This binary input should be de-energized when
the device is restored back to normal.
The application of the binary input [BI_Maintenance] for digital substation communication adopting
IEC61850 protocol is given as follows.
1)
Processing mechanism for MMS (Manufacturing Message Specification) message
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a)
The protection device should send the state of this binary input to client.
b) When this binary input is energized, the bit “Test” of quality (Q) in the sent message changes
to “1”.
c) When this binary input is energized, the client cannot control the isolator link and circuit
breaker, modify settings and switch setting group remotely.
d) According to the value of the bit “Test” of quality (Q) in the message sent, the client
discriminate whether this message is maintenance message, and then deal with it correspondingly.
If the message is the maintenance message, the content of the message will not be displayed on
real-time message window, audio alarm not issued, but the picture is refreshed so as to ensure
that the state of the picture is in step with the actual state. The maintenance message will be
stored, and can be inquired, in independent window.
2)
Processing mechanism for GOOSE message
a) When this binary input is energized, the bit “Test” in the GOOSE message sent by the
protection device changes to “1”.
b) For the receiving end of GOOSE message, it will compare the value of the bit “Test” in the
GOOSE message received by it with the state of its own binary input (i.e., [BI_Maintenance]), the
message will be thought as invalid unless they are conformable.
3)
Processing mechanism for SV (Sampling Value) message
a) When this binary input of merging unit is energized, the bit “Test” of quality (Q) of sampling
data in the SV message sent change “1”.
b) For the receiving end of SV message, if the value of bit “Test” of quality (Q) of sampling data
in the SV message received is “1”, the relevant protection functions will be disabled, but under
maintenance state, the protection device should calculate and display the magnitude of sampling
data.
c) For duplicated protection function configurations, all merging units of control module
configured to receive sampling should be also duplicated. Both dual protection devices and dual
merging units should be fully independent each other, and one of them is in maintenance state will
not affect the normal operation of the other.
4.
Binary input: [BI_RstTarg]
It is used to reset latching signal relay and LCD displaying. The reset is done by pressing a button
on the panel.
NOTICE!
The rated voltage of binary input is optional: 110V, 125V, 220V or 250V, which must be
specified when placed order. It is necessary to check whether the rated voltage of BI
module complies with site DC supply rating before put the relay in service.
There three binary signals are fixed for measurement functions, they are [BI_Rmt/Loc],
[BI_ManSynCls] and [BI_ManOpen] respectively.
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5.
Binary input: [BI_Rmt/Loc]
It is used to select the remote control or the local control.
“1”: the remote control, all the binary outputs can only be remotely controlled by SCADA or control
centers.
“0” the local control, each binary output can only be applied to open/close CB/DS/ES locally. Each
binary output can also be applied issue a signal locally.
6.
Binary input: [BI_ManSynCls]
When the device is under local control condition (i.e. [BI_Rmt/Loc] is de-energized), the manual
synchronism check for closing circuit breaker will be initiated if it is energized.
7.
Binary input: [BI_ManOpen]
When the device is under local control condition (i.e. [BI_Rmt/Loc] is de-energized), the manual
control for open circuit breaker will be initiated if it is energized.
6.3.8 BO Plug-in Module (Binary Output)
Three standard binary output modules, NR1521A, NR1521C and NR1521G, and two optional
binary output module, NR1521F and NR1580A, can be selected. The contacts provided by
NR1521A, NR1521C, NR1521G, NR1521F and NR1580A are all normally open (NO) contacts.
Output contact can be configured as a specified tripping output contact and a signal output contact
respectively by PCS-Explorer software according to user requirement.
The following signals can be configured to output contacts controlled by fault detector or output
contacts without controlled by fault detector.

Pickup signals of fault detector elements (FD)

Operation signals of protection elements (Op)

Start signals of protection elements (St)

Tripping signals, reclosing signal, AR failure signal, breaker failure signal
However, the signals which will be control the circuit breaker directly or initiate breaker failure
protection must be configured to output contacts controlled by fault detector.
The following signals must be configured to output contacts without controlled by fault detector.

Enable signals of protection elements (On)

Alarm signals of protection elements (Alm)

Blocking signals of protection elements (Fail)

Related signals with voltage switchover and synchrocheck and related signals with AR except
reclosing signal and AR failure signal.
NR1521A can provide 11 output contacts controlled by fault detector.
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BO_01
NR1521A
BO_02
BO_03
BO_04
BO_05
BO_06
BO_07
BO_08
BO_09
BO_10
BO_11
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 6.3-29 View of BO plug-in module (NR1521A)
NR1521C can provide 11 output contacts without controlled by fault detector.
BO_01
NR1521C
BO_02
BO_03
BO_04
BO_05
BO_06
BO_07
BO_08
BO_09
BO_10
BO_11
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 6.3-30 View of BO plug-in module (NR1521C)
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BO plug-in module (NR1521F) is dedicatedly for remote/manual open or closing to circuit breaker,
disconnector and earth switch. 5 pairs of binary outputs (one for open and the other for closing)
can be provided by this BO plug-in module configured in slot 15 if measurement and control
function is equipped with the device. More binary outputs can be provided by another BO plug-in
modules that can be configured in slot 11, 12, 13, 14 if open or closing contacts is not enough.
First pair of binary outputs are used to remote/manual open or close circuit breaker, and second
pair of binary outputs are also used to remote/manual open or close circuit breaker for double
circuit breakers application.
A normally open contact is presented via terminal 21-22 designated as ROS (i.e. remote operation
signal). Whenever any of binary output contacts for open or closing is closed, ROS contact will
close to issue a signal indicating that this device is undergoing a remote operation.
BO plug-in module (NR1521F) is displayed as shown in the following figure.
BO_CtrlOpn01
NR1521F
BO_CtrlCls01
BO_CtrlOpn02
BO_CtrlCls02
BO_CtrlOpn03
BO_CtrlCls03
BO_CtrlOpn04
BO_CtrlCls04
BO_CtrlOpn05
BO_CtrlCls05
BO_Ctrl
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 6.3-31 View of BO plug-in module (NR1521F)
NR1521G can provide 11 output contacts without controlled by fault detector. The first four output
contacts are in parallel with instantaneous operating contacts which are recommended to be
configured as fast signaling contacts to send PLC signal.
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BO_01
NR1521G
BO_02
BO_03
BO_04
BO_05
BO_06
BO_07
BO_08
BO_09
BO_10
BO_11
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
Figure 6.3-32 View of BO plug-in module (NR1521G)
NR1580A can provide 6 output contacts with controlled by fault detector. It is a heavy-capacity
binary output plug-in module, which can be used to control the circuit breaker directly.
+
01
BO_01
NR1580A
-
02
03
04
+
05
BO_02
-
06
07
08
+
09
BO_03
-
10
11
12
+
13
BO_04
-
14
15
16
+
17
BO_05
-
18
19
20
+
BO_06
-
21
22
Figure 6.3-33 View of BO plug-in module (NR1580A)
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6.3.9 HMI Module
The display panel consists of liquid crystal display module, keyboard, LED and ARM processor.
The functions of ARM processor include display control of the liquid crystal display module,
keyboard processing, and exchanging data with the CPU through LAN port etc. The liquid crystal
display module is a high-performance grand liquid crystal panel with soft back lighting, which has a
user-friendly interface and an extensive display range.
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7 Settings
Table of Contents
7 Settings .............................................................................................. 7-a
7.1 System Settings .............................................................................................. 7-1
7.1.1 Setting Description............................................................................................................... 7-1
7.1.2 Access Path ......................................................................................................................... 7-2
7.2 Device Setup.................................................................................................... 7-2
7.2.1 Setting Description............................................................................................................... 7-2
7.2.2 Access Path ...................................................................................................................... 7-13
7.3 Protection Settings ....................................................................................... 7-14
7.3.1 Setting Description............................................................................................................. 7-14
7.3.2 Access Path ....................................................................................................................... 7-56
7.4 Logic Link Settings ....................................................................................... 7-57
7.4.1 Setting Description............................................................................................................. 7-57
7.4.2 Access Path ....................................................................................................................... 7-57
7.5 Control and Synchrocheck for Manual Closing Settings .......................... 7-57
7.5.1 Setting Description............................................................................................................. 7-57
7.5.2 Access Path ....................................................................................................................... 7-63
List of Tables
Table 7.1-1 System settings ....................................................................................................... 7-1
Table 7.2-1 Device settings......................................................................................................... 7-2
Table 7.2-2 Communication settings ........................................................................................... 7-4
PCS-902 Line Distance Relay
7-a
Date: 2019-03-01
-09-07
7 Settings
7-b
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
The device has some setting groups for protection to coordinate with the mode of power system
operation, one of which is assigned to be active. However, communication settings, system
settings, device settings, logic link settings and measurement and control settings are common for
all protection setting groups.
NOTICE!
All current settings in this chapter are secondary current converted from primary current
by CT ratio. Zero-sequence current or voltage setting is configured according to 3I0 or
3U0 and negative sequence current setting according to I2 or U2.
7.1 System Settings
7.1.1 Setting Description
Table 7.1-1 System settings
No.
Item
Range
Unit
1
Active_Grp
1~20
2
Opt_SysFreq
50 or 60
3
PrimaryEquip_Name
Maximum 12 character
4
U1n
10.00~65500.00
kV
5
U2n
80.00~220.00
V
6
CBx.I1n
100~30000
A
7
I1n_Base
100~30000
A
8
I2n_Base
1 or 5
A
9
f_High_FreqAlm
50~65
Hz
10
f_Low_FreqAlm
45~60
Hz
11
Measmt.CBx.I1n
100~30000
A
12
Measmt.I1n_Base
100~30000
A
13
Measmt.I2n_Base
1 or 5
A
1.
Hz
Active_Grp
The number of active setting group, 20 setting groups can be configured for protection settings,
and only one is active at a time
2.
PrimaryEquip_Name
It is recognized by the device automatically. Such setting is used for printing messages
3.
Opt_SysFreq
It is option of system frequency, and can be set as 50Hz or 60Hz
4.
Un1
Primary rated voltage of VT
PCS-902 Line Distance Relay
7-1
Date: 2019-03-01
-09-07
7 Settings
5.
Un2
Secondary rated voltage of VT
6.
CBx.I1n
Primary rated value of CT corresponding to circuit breaker No.x
7.
I1n_Base
Primary calculation base rated current of CT
8.
I2n_Base
Secondary calculation base rated current of CT
9.
f_High_FreqAlm
It is frequency upper limit setting. The device will issue an alarm [Alm_Freq], when system
frequency is higher than the setting.
10. f_Low_FreqAlm
It is frequency lower limit setting. The device will issue an alarm [Alm_Freq], when system
frequency is lower than the setting.
11. Measmt.CBx.I1n
Primary rated value of measurement CT corresponding to circuit breaker No.x (available only in
digital substation application)
12. Measmt.I1n_Base
Primary calculation base rated current of measurement CT (available only in digital substation
application)
13. Measmt.I2n_Base
Secondary calculation base rated current of measurement CT (available only in digital substation
application)
7.1.2 Access Path
MainMenu“Settings”“System Settings”
7.2 Device Setup
7.2.1 Setting Description
7.2.1.1 Device Settings
Table 7.2-1 Device settings
No.
1
Item
Opt_Caption_103
Range
Current_language, Fixed_Chinese, Fixed_English
7-2
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
1.
No.
Item
Range
2
En_Send_MMS_Qual_Chg
Disable or Enable
3
Opt_DualNetMode_MMS
0, 1 or 2
4
Bxx.Un_BinaryInput
24V, 30V, 48V, 110V, 125V, 220V
5
Bxx.U_Pickup_BI
55%Un~80%Un
6
Bxx.U_Dropoff_BI
55%Un~80%Un
7
CBx.En_RevCT
Disable or Enable
8
3I0Adj.En_RevCT
Disable or Enable
9
Ctrl_Password
0~999
10
En_NoCtrlPwd
Disable or Enable
11
En_PopupRecord_Blkd
Disable or Enable
Opt_Caption_103
Select the caption language sent to SAS via IEC103 protocol
Default value of [Opt_Caption_103] is “Current_language”, and please set it to “Fixed_Chinese” if
the SAS is supplied by China Manufacturer.
2.
En_Send_MMS_Qual_Chg
It is used to enable or disable that IEC 61850 communication program uploads the variation of
data quality.
3.
Opt_DualNetMode_MM
It is used to select network mode of MMS network for the communication with SCADA
0: Single network
1: Hot standby mode (always two ports in service)
2: Cold standby mode (only one port in service)
4.
Bxx.Un_BinaryInput
This setting is used to set voltage level of binary input module. If low-voltage BI module is
equipped, 24V, 30V or 48V can be set according to the actual requirement, and if high-voltage BI
module is equipped, 110V, 125V or 220V can be set according to the actual requirement.
Bxx: this plug-in module is inserted in slot xx.
5.
Bxx.U_Pickup_BI
This setting is used to set pickup voltage of binary input module. Bxx: this plug-in module is
inserted in slot xx. Only NR1503AR or NR1504AR is equipped, the setting is valid.
6.
Bxx.U_Dropoff_BI
This setting is used to set dropoff voltage of binary input module. Bxx: this plug-in module is
inserted in slot xx. Only NR1503AR or NR1504AR is equipped, the setting is valid.
PCS-902 Line Distance Relay
7-3
Date: 2019-03-01
-09-07
7 Settings
7.
CBx.En_RevCT
It is used to adjust the current polarity corresponding to circuit breaker No.x.
Disable: keep connected current polarity unchanged
Enable: make connected current polarity reversed
8.
3I0Adj.En_RevCT
It is used to adjust residual current polarity from parallel line.
Disable: keep connected current polarity unchanged
Enable: make connected current polarity reversed
9.
Ctrl_Password
It is used to set local control password.
10. En_NoCtrlPwd
It is used to enable or disable the bypass function of local control password.
11. En_PopupRecord_Blkd
This setting is used to enable or disable the auto-popup function of event report in the device LCD.
7.2.1.2 Communication Settings
Table 7.2-2 Communication settings
No.
Item
Range
1
IEDNAME
2
IP_LAN1
000.000.000.000~255.255.255.255
3
Mask_LAN1
000.000.000.000~255.255.255.255
4
IP_LAN2
000.000.000.000~255.255.255.255
5
Mask_LAN2
000.000.000.000~255.255.255.255
6
En_LAN2
Disable or enable
7
IP_LAN3
000.000.000.000~255.255.255.255
8
Mask_LAN3
000.000.000.000~255.255.255.255
9
En_LAN3
Disable or enable
10
IP_LAN4
000.000.000.000~255.255.255.255
11
Mask_LAN4
000.000.000.000~255.255.255.255
12
En_LAN4
Disable or enable
13
Gateway
000.000.000.000~255.255.255.255
14
En_Broadcast
Disable or enable
15
Cfg_NetPorts_Bond
0~12
16
Addr_RS485A
0~255
17
Baud_RS485A
4800,9600,19200,38400,57600,115200 (bps)
7-4
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
No.
Item
Range
18
Protocol_RS485A
IEC103, Modbus, Resv1
19
Addr_RS485B
0~255
20
Baud_RS485B
4800,9600,19200,38400,57600,115200 (bps)
21
Protocol_RS485B
IEC103, Modbus, Resv1
22
En_BICheckBO
Disable or enable
23
En_BICheckLinkCtrl
Disable or enable
24
Threshold_Measmt_Net
0~100%
25
Period_Measmt_Net
0~65535s
26
Format_Measmt
0, 1
27
Baud_Printer
4800,9600,19200,38400,57600,115200 (bps)
28
En_AutoPrint
Disable or enable
29
Opt_TimeSyn
Conventional, SAS, Advanced or NoTImeSyn
30
IP_Server_SNTP
000.000.000.000~255.255.255.255
31
IP_StandbyServer_SNTP
000.000.000.000~255.255.255.255
32
OffsetHour_UTC
-12~+12 (hrs)
33
OffsetMinute_UTC
0~60 (min)
34
Opt_Display_Status
PriValue, SecValue
35
RecDur_PreTrigDFR
0~1s
36
RecDur_PostFault
0~10s
37
MaxRecDur_PostTrigDFR
0~10s
38
B01.En_DualNet_GOOSE
Disable or enable
39
En_TCPx_DNP
Disable or enable
40
Addr_Slave_TCPx_DNP
0~65519
41
Addr_Master_TCPx_DNP
0~65519
42
IP_Master_TCPx_DNP
000.000.000.000~255.255.255.255
43
Opt_Map_TCPx_DNP
0~4
44
Obj01DefltVar_TCPx_DNP
BISingleBit
BIWithStatus
BIChWoutT
45
Obj02DefltVar_TCPx_DNP
BIChWithAbsTime
BIChWithRelTime
AI32Int
AI16Int
46
Obj30DefltVar_TCPx_DNP
AI32IntWoutF
AI16IntWoutF
AI32Flt
AI32IntEvWoutT
47
Obj32DefltVar_TCPx_DNP
AI16IntEvWoutT
AI32FltEvWoutT
48
Obj40DefltVar_TCPx_DNP
AO32Int
PCS-902 Line Distance Relay
7-5
Date: 2019-03-01
-09-07
7 Settings
No.
Item
Range
AO16Int
AO32Flt
49
t_AppLayer_TCPx_DNP
0~5 (s)
50
t_KeepAlive_TCPx_DNP
0~7200 (s)
51
En_UR_TCPx_DNP
Disable or enable
52
Num_URRetry_TCPx_DNP
2~10
53
t_UROfflRetry_TCPx_DNP
1~5000 (s)
54
Class_BI_TCPx_DNP
0~3
55
Class_AI_TCPx_DNP
0~3
56
t_Select_TCPx_DNP
0~240 (s)
57
t_TimeSynIntvl_TCPx_DNP
0~3600 (s)
1.
IEDNAME
IED name of this device. If this setting is modified, the IED name in ".cid" file will be changed
simultaneously and vice versa.
2.
IP_LAN1, IP_LAN2, IP_LAN3, IP_LAN4
IP address of Ethernet port 1, Ethernet port 2, Ethernet port 3 and Ethernet port 4
3.
Mask_LAN1, Mask_LAN2, Mask_LAN3, Mask_LAN4
Subnet mask of Ethernet port 1, Ethernet port 2, Ethernet port 3 and Ethernet port 4
4.
En_LAN2, En_LAN3, En_LAN4
Put Ethernet port 2, Ethernet port 3 and Ethernet port 4 in service
They are used for Ethernet communication based on the IEC 60870-5-103 protocol. When the IEC
61850 protocol is applied, the IP address of Ethernet A will be GOOSE source MAC address.
Ethernet port 1 is always in service by default.
5.
Gateway
IP address of Gateway (router)
6.
En_Broadcast
This setting is only used only for IEC 60870-5-103 protocol. If NR network IEC 60870-5-103
protocol is used, the setting must be set as “Enable”.
Disable: the device does not send UDP messages through network
Enable: the device sends UDP messages through network
7.
Cfg_NetPorts_Bond
The setting is used to configure dual-networks switching, and it means that no dual-networks
switching is created when the setting is set as “0”. The device support a bond between any two
7-6
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
Ethernet ports, and the bond among three or above Ethernet ports is impermissible.
The devices communicate with SAS by station level network. In order to ensure reliable
communication, dual networks (i.e., network 1 and network 2) are adopted. Another special
communication mode based on dual networks is that Ethernet port 1 and Ethernet port 2 of the
device own the same IP address and MAC address, and network 1 and network 2 are used as hot
standby each other. When both network 1 and network 2 are normal, any of them is used to
communicate between the device and SAS. The device will automatically switch to the other
healthy network when one network is abnormal, which will not affect normal communication.
Taking NR1102D (with four Ethernet ports) as an example, each bit is corresponding with an
Ethernet port, i.e., Bit0, Bit1, Bit2 and Bit3 are corresponding with Ethernet port 1, Ethernet port 2,
Ethernet port 3 and Ethernet port 4 respectively. If a bond between Ethernet port 1 and Ethernet 2
is created, the setting [Cfg_NetPorts_Bond] is set as “3”. The specific setting is as below.
Bonding
Ethernet port 1
Bonding
Ethernet port 2
Ethernet port 1
Bonding
Ethernet port 3
Ethernet port 1
Ethernet port 4
Bit3
Bit2
Bit1
Bit0
Setting
Value
Bit3
Bit2
Bit1
Bit0
Setting
Value
Bit3
Bit2
Bit1
Bit0
Setting
Value
0
0
1
1
3
0
1
0
1
5
1
0
0
1
9
Bonding
Ethernet port 2
Bonding
Ethernet port 3
Ethernet port 2
Bonding
Ethernet port 4
Ethernet port 3
Ethernet port 4
Bit3
Bit2
Bit1
Bit0
Setting
Value
Bit3
Bit2
Bit1
Bit0
Setting
Value
Bit3
Bit2
Bit1
Bit0
Setting
Value
0
1
1
0
6
1
0
1
0
10
1
1
0
0
12
Ethernet port 1: Bit0, Ethernet port 2: Bit1, Ethernet port 3: Bit2, Ethernet port 4: Bit3
The switching logic is as below.

After the device is powered on, network 1 is selected when the link status of both network 1
and network 2 are normal.

When the link status of network 1 is abnormal, network 2 is selected if network 2 is normal.

When the link status of network 1 is abnormal, network 1 is kept to work if network 2 is also
abnormal.

When network 2 is working, network 2 is kept to work even if network 1 has been restored to
normal. The device will be switched to network 1 only if network 2 is abnormal.
PCS-902 Line Distance Relay
7-7
Date: 2019-03-01
-09-07
7 Settings
8.
Addr_RS485A, Addr_RS485B
They are the device′s communication address used to communicate with the SCADA or RTU via
serial ports (port A and port B).
9.
Baud_RS485A, Baud_RS485B
Baud rate of rear RS-485 serial port A or B
10. Protocol_RS485A, Protocol_RS485B
Communication protocol of rear RS-485 serial port A or B
IEC103: IEC 60870-5-103 protocol
Modbus: Modbus Protocol
Resv1: Reserved 1
NOTICE!
Above table listed all the communication settings, the device delivered to the user
maybe only show some settings of them according to the communication interface
configuration. If only the Ethernet ports are applied, the settings about the serial ports
(port A and port B) are not listed in this submenu. And the settings about the Ethernet
ports only listed in this submenu according to the actual number of Ethernet ports.
The standard arrangement of the Ethernet port is two, at most four (predetermined
when ordering). Set the IP address according to actual arrangement of Ethernet
numbers and the un-useful port/ports need not be configured. If PCS-Explorer
configuration tool auxiliary software is connected with this device through the Ethernet,
the IP address of PCS-Explorer must be set as one of the available IP address of this
device.
11. En_BICheckBO
This setting is used to set the relationship between the positon signal of the circuit breaker and the
operation of the control. Only remote control to close can be implemented if the circuit breaker is in
open position, and only remote control to open can be implemented if the circuit breaker is in
closed position. The remote control is not controlled by the circuit breaker position.
12. En_BICheckLinkCtrl
This setting is used to set the relationship between the positon signal of the circuit breaker and the
operation of the control via link. Only remote control to close can be implemented if the circuit
breaker is in open position, and only remote control to open can be implemented if the circuit
breaker is in closed position. Otherwise, the remote control is not controlled by the circuit breaker
position.
13. Threshold_Measmt_Net
Threshold value of sending measurement values to SCADA through IEC 60870-5-103 or
IEC61850 protocol via Ethernet port.
7-8
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
Default value: “1%”
14. Period_Measmt_Net
The time period for equipment sends measurement data to SCADA through IEC 60870-5-103
protocol via Ethernet port.
Default value: “60”
15. Format_Measmt
The setting is used to select the format of measurement data sent to SCADA through IEC
60870-5-103 protocol.
0: GDD data type through IEC103 protocol is 12
1: GDD data type through IEC103 protocol is 7, i.e. 754 short real number of IEEE standard
16. Baud_Printer
Baud rate of printer port
17. En_AutoPrint
If automatic print is required for fault report after protection operating, it is set as “Enable”.
Otherwise, it should be set to “Disable”.
18. Opt_TimeSyn
There are four selections for clock synchronization of device shown as follow.

Conventional
PPS (RS-485): Pulse per second (PPS) via RS-485 differential level
IRIG-B (RS-485): IRIG-B via RS-485 differential level
PPM (DIN): Pulse per minute (PPM) via the binary input [BI_TimeSyn]
PPS (DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn]

SAS
SNTP (PTP): Unicast (point-to-point) SNTP mode via Ethernet network
SNTP (BC): Broadcast SNTP mode via Ethernet network
Message (IEC103): Clock messages through IEC103 protocol

Advanced
IEEE1588: Clock message via IEEE1588
IRIG-B (Fiber): IRIG-B via optical-fibre interface
PPS (Fiber) PPS: Pulse per second (PPS) via optical-fibre interface

NoTimeSync
PCS-902 Line Distance Relay
7-9
Date: 2019-03-01
-09-07
7 Settings
When no time synchronization signal is connected to the device, please select this option and the
alarm message [Alm_TimeSyn] will not be issued anymore.
“Conventional” mode and “SAS” mode are always be supported by the device, but “Advanced”
mode is only supported when NET-DSP module is equipped. The alarm signal [Alm_TimeSyn]
may be issued to remind user loss of time synchronization signals.
1)
When “SAS” is selected, if there is no conventional clock synchronization signal, the device
will not send the alarm signal [Alm_TimeSyn]. When “Conventional” mode is selected, if there
is no conventional clock synchronization signal, “SAS” mode will be enabled automatically
with the alarm signal [Alm_TimeSyn] issued simultaneously.
2)
When “Advanced” mode is selected, if there is no conventional clock synchronization signal
connected to NET-DSP module, “SAS” mode is enabled automatically with the alarm signal
[Alm_TimeSyn] issued simultaneously.
3)
When “NoTimeSyn” mode is selected, the device will not send alarm signals without time
synchronization signal. But the device can be still synchronized if receiving time
synchronization signal.
NOTICE!
The clock message via IEC 60870-5-103 protocol is invalid when the device receives
the IRIG-B signal through RCS-485 port.
19. IP_Server_SNTP
It is the address of the SNTP time synchronization server which sends SNTP timing messages to
the relay or BCU.
20. IP_StandbyServer_SNTP
Both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are ineffective unless SNTP clock
synchronization is valid.
When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as "000.000.000.000", the
device receives broadcast SNTP synchronization message.
When either [IP_Server_SNTP] or [IP_StandbyServer_SNTP] is set as "000.000.000.000", the
device adopts the setting whose value is not equal to "000.000.000.000" as SNTP server address
and receives unicast SNTP synchronization message.
If neither [IP_Server_SNTP] nor [IP_StandbyServer_SNTP] is set as "000.000.000.000", the
device adopts the setting [IP_Server_SNTP] as SNTP server address to receive unicast SNTP
synchronization message. If the device does not receive any server response after 30s, it adopts
the setting [IP_StandbyServer_SNTP] as SNTP server address to receive unicast SNTP
synchronization message.
The device will switch between [IP_Server_SNTP] and [IP_StandbyServer_SNTP] repeatedly if it
does not receive any server response in 30s.
7-10
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
21. OffsetHour_UTC, OffsetMinute_UTC
If the IEC61850 protocol is adopted in substations, the time tags of communication messages are
required according to UTC (Universal Time Coordinated) time.
The setting [OffsetHour_UTC] is used to set the hour offset of the current time zone to the GMT
(Greenwich Mean Time) zone; for example, if a relay is applied in China, the time zone of China is
east 8th time zone, so this setting is set as “8”. The setting [OffsetMinute_UTC] is used to set the
minute offset of the current time zone to the GMT zone.
Time zone
East 1
0
1
Setting
Time zone
th
Setting
Time zone
East 7
6
7
th
West 1
12/-12
-1
East 8
West 2
East 9
rd
West 3
-3
th
th
East 4
4
th
9
nd
-2
th
rd
East 3
3
th
8
st
East/West 12
th
nd
East 2
2
th
East 6
Setting
Time zone
st
GMT zone
5
th
East 10
East 11th
10
11
th
West 4
-4
th
th
East 5
th
West 5
-5
th
th
West 6
West 7
West 8
West 9
West 10
West 11
-6
-7
-8
-9
-10
-11
Setting
22. Opt_Display_Status
This setting is used to set display mode of current and voltage in fault records, primary value or
secondary value. The sampled values of current and voltage are displayed as secondary value by
default. When it is set as primary value, both secondary voltage and secondary current are
converted into primary voltage and primary current according to rated secondary and primary
value of VT and CT respectively.
23. RecDur_PreTrigDFR
The setting is used to set waveform recorded duration before the trigger element operating.
24. RecDur_PostFault
The setting is used to set waveform recorded duration after the fault happens.
25. MaxRecDur_PostTrigDFR
The setting is used to set the maximum waveform recorded duration after the trigger element
operating.
26. B01.En_DualNet_GOOSE
This setting is used to enable/disable dual GOOSE networks (including GOOSE network A and
GOOSE network B).
27. En_TCPx_DNP
The logic setting is used to enable or disable network No.x DNP client. (x=1, 2, 3, 4)
When network No.x DNP client is not configured to be in service by PCS-Explorer, DNP client
settings corresponding to network No.x will be hidden.
PCS-902 Line Distance Relay
7-11
Date: 2019-03-01
-09-07
7 Settings
28. Addr_Slave_TCPx_DNP
It is the slave address of network No.x DNP client. (x=1, 2, 3, 4)
29. Addr_Master_TCPx_DNP
It is the master address of network No.x DNP client. (x=1, 2, 3, 4)
30. IP_Master_TCPx_DNP
It is the IP address of network No.x DNP client. (x=1, 2, 3, 4)
31. Opt_Map_TCPx_DNP
It is the communication map number of network No.x DNP client. (x=1, 2, 3, 4)
32. Obj01DefltVar_TCPx_DNP
It is the “OBJ1” default variation of network No.x DNP client. (x=1, 2, 3, 4)
BISingleBit: Binary Input format is packed with single bit
BIWithStatus: Binary Input with status flag
33. Obj02DefltVar_TCPx_DNP
It is the “OBJ2” default variation of network No.x DNP client. (x=1, 2, 3, 4)
BIChWoutT: Binary Input Event without time-of-occurrence
BIChWithAbsTime: Binary Input Event with absolute time-of-occurrence
BIChWithRelTime: Binary Input Event with relative time-of-occurrence
34. Obj30DefltVar_TCPx_DNP
It is the “OBJ30” default variation of network No.x DNP client. (x=1, 2, 3, 4)
AI32Int: Analog Input with a flag octet and a 32-bit, signed integer value
AI16Int: Analog Input with a flag octet and a 16-bit, signed integer value
AI32IntWoutF: Analog Input with a 32-bit (but without flags)
AI16IntWoutF: Analog Input with a 16-bit (but without flags)
AI32Flt: Analog Input with a flag octet and a single-precision, floating-point value
35. Obj32DefltVar_TCPx_DNP
It is the “OBJ32” default variation of network No.x DNP client. (x=1, 2, 3, 4)
AI32IntEvWoutT: Analog Input Event with a flag octet and a 32-bit, signed integer value (but
without time-of-occurrence)
AI16IntEvWoutT: Analog Input Event with a flag octet and a 16-bit, signed integer value (but
without time-of-occurrence)
7-12
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
AI32FltEvWoutT: Analog Input Event with single-precision, floating-point value (but without
time-of-occurrence)
36. Obj40DefltVar_TCPx_DNP
It is the “OBJ40” default variation of network No.x DNP client. (x=1, 2, 3, 4)
AO32Int: Analog Output with a flag octet and a 32-bit, signed integer value
AO16Int: Analog Output with a flag octet and a 16-bit, signed integer value
AO32Flt: Analog Output with a flag octet and a single-precision, floating-point value
37. t_AppLayer_TCPx_DNP
It is the timeout of application layer of network No.x DNP client. (x=1, 2, 3, 4)
38. t_KeepAlive_TCPx_DNP
It is the heartbeat time interval of network No.x DNP client. (x=1, 2, 3, 4)
39. En_UR_TCPx_DNP
The logic setting is used to enable or disable the unsolicited message function of network No.x
DNP client. (x=1, 2, 3, 4)
40. Num_URRetry_TCPx_DNP
It is the online retransmission number of the unsolicited message of network No.x DNP client. (x=1,
2, 3, 4)
41. t_UROfflRetry_TCPx_DNP
It is the offline timeout of the unsolicited message of network No.x DNP client. (x=1, 2, 3, 4)
42. Class_BI_TCPx_DNP
It is the class level of the “Binary Input” of network No.x DNP client. (x=1, 2, 3, 4)
43. Class_AI_TCPx_DNP
It is the class level of the “Analog Input” of network No.x DNP client. (x=1, 2, 3, 4)
44. t_Select_TCPx_DNP
It is the selection timeout of network No.x DNP client. (x=1, 2, 3, 4)
45. t_TimeSynIntvl_TCPx_DNP
It is the time interval of the time synchronization function of network No.x DNP client. (x=1, 2, 3, 4)
7.2.2 Access Path
MainMenu“Settings”“Device Setup”
PCS-902 Line Distance Relay
7-13
Date: 2019-03-01
-09-07
7 Settings
7.3 Protection Settings
All protection settings are based on secondary ratings of VT and CT.
Unn: rated secondary phase-to-phase voltage
Un: rated secondary phase-to-ground voltage
In: rated secondary current
7.3.1 Setting Description
7.3.1.1 Line Parameters Settings
No.
Item
Remark
Range
1
X1L
Positive sequence reactance of the line
(0.000~4Unn)/In (ohm)
2
R1L
Positive sequence resistance of the line
(0.000~4Unn)/In (ohm)
3
X0L
Zero-sequence reactance of the line
(0.000~4Unn)/In (ohm)
4
R0L
Zero-sequence resistance of the line
(0.000~4Unn)/In (ohm)
5
X0M
Line mutual zero-sequence reactance
(0.000~4Unn)/In (ohm)
6
R0M
Line mutual zero-sequence resistance
(0.000~4Unn)/In (ohm)
7
LineLength
Total length of the line
0.00~655.35 (km)
7.3.1.2 Fault Detector Settings (FD)
No.
Item
1
FD.DPFC.I_Set
2
FD.ROC.3I0_Set
3
FD.NOC.I2_Set
4
FD.NOC.En
Remark
Range
Current setting of DPFC current fault detector
element
Current setting of residual current fault detector
element
Current setting of negative-sequence current fault
detector element
Enable negative-sequence current fault detector
element
(0.050~30.000)×In (A)
(0.050~30.000)×In (A)
(0.050~30.000)×In (A)
0 or 1
7.3.1.3 Auxiliary Element Settings (AuxE)
No.
Item
1
AuxE.OCD.t_DDO
2
AuxE.OCD.En
3
AuxE.ROC1.3I0_Set
4
AuxE.ROC1.En
5
AuxE.ROC2.3I0_Set
6
AuxE.ROC2.En
Remark
Range
Drop-off time delay of current change auxiliary
element
Enable current change auxiliary element
0 or 1
Current setting of stage 1 residual current auxiliary
element
Enable stage 1 residual current auxiliary element
Current setting of stage 2 residual current
Enable stage 2 residual current auxiliary element
(0.050~30.000)×In (A)
0 or 1
auxiliary
element
7-14
0.000~10.000 (s)
(0.050~30.000)×In (A)
0 or 1
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
7
AuxE.ROC3.3I0_Set
8
AuxE.ROC3.En
9
AuxE.OC1.I_Set
Current setting of stage 3 residual current auxiliary
element
Enable stage 3 residual current auxiliary element
Current setting of stage 1 phase current auxiliary
element
Enable stage 1 phase current auxiliary element
(0.050~30.000)×In (A)
0 or 1
(0.050~30.000)×In (A)
10
AuxE.OC1.En
11
AuxE.OC2.I_Set
12
AuxE.OC2.En
13
AuxE.OC3.I_Set
14
AuxE.OC3.En
Enable stage 3 phase current auxiliary element
0 or 1
15
AuxE.UVD.U_Set
Voltage setting for voltage change auxiliary element
0~Un (V)
16
AuxE.UVD.t_DDO
17
AuxE.UVD.En
18
AuxE.UVG.U_Set
19
AuxE.UVG.En
20
AuxE.UVS.U_Set
21
AuxE.UVS.En
22
AuxE.ROV.3U0_Set
Voltage setting for residual voltage auxiliary element
0~Un (V)
23
AuxE.ROV.En
Enable residual voltage auxiliary element
0 or 1
Current setting of stage 2 phase current auxiliary
element
Enable stage 2 phase current auxiliary element
Current setting of stage 3 phase current auxiliary
element
Drop-off time delay of voltage change auxiliary
element
Enable voltage change auxiliary element
Voltage setting for phase-to-ground under voltage
auxiliary element
Enable phase-to-ground under voltage auxiliary
element
Voltage setting for phase-to-phase under voltage
auxiliary element
Enable phase-to-phase under voltage auxiliary
element
0 or 1
(0.050~30.000)×In (A)
0 or 1
(0.050~30.000)×In (A)
0.000~10.000 (s)
0 or 1
0~Un (V)
0 or 1
0~Unn (V)
0 or 1
7.3.1.4 DPFC Distance Protection Settings (21D)
No.
Item
Remark
Range
1
21D.Z_Set
Impedance setting of DPFC distance protection
(0.000~4Unn)/In (ohm)
2
21D.En
Enable DPFC distance protection
0 or 1
7.3.1.5 Load Encroachment Settings (LoadEnch)
No.
Item
Remark
Range
Angle setting of load trapezoid characteristic, it should
1
LoadEnch.phi
be set according to the maximum load area angle 0~45 (deg)
(φLoad_Max), φLoad_Max+5°is recommended.
Impedance setting of load trapezoid characteristic, it
2
LoadEnch.Z_Set
should be set according to the minimum load
resistance, 70%~90% minimum load resistance is
(0.05~200)/In (ohm)
recommended.
3
LoadEnch.En
Enable load trapezoid characteristic
PCS-902 Line Distance Relay
0 or 1
7-15
Date: 2019-03-01
-09-07
7 Settings
7.3.1.6 Distance Protection Settings with Mho Characteristic (21M)
No.
Item
1
21-1.Real_K0
2
21-1.Imag_K0
3
21-1.phi1_Reach
4
21M1.ZGQ.RCA
5
21M1.ZG.phi_Shift
6
21M1.ZP.phi_Shift
7
21M1.ZG.Z_Set
8
21M1.ZGQ.R_Set
9
21M1.ZG.t_Op
10
21M1.ZG.En
11
21M1.ZGQ.En
12
21M1.ZG.En_BlkAR
13
21M1.ZP.Z_Set
14
21M1.ZP.t_Op
15
21M1.ZP.En
16
21M1.ZP.En_BlkAR
17
21-2. DirMode
18
21-2.Real_K0
19
21-2.Imag_K0
20
21-2.phi1_Reach
21
21M2.ZGQ.RCA
Remark
Range
Real component of zero-sequence compensation
coefficient for zone 1
Imaginary
component
of
zero-sequence
compensation coefficient for zone 1
Phase angle of positive-sequence impedance for
zone 1
Downward offset angle of the reactance line for zone
1 of phase-to-ground distance protection
Phase shift of phase-to-ground distance protection for
zone 1
Phase shift of phase-to-phase distance protection for
zone 1
Impedance setting of zone 1 of phase-to-ground
distance protection
Resistance setting of zone 1 of phase-to-ground
distance protection
Time delay of zone 1 of phase-to-ground distance
protection
-4.000~4.000
-4.000~4.000
30~89 (deg)
0~45 (deg)
0, 15 or 30 (deg)
0, 15 or 30 (deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
Enable zone 1 of phase-to-ground distance protection 0 or 1
Enable zone 1 of quadrilateral phase-to-ground
distance protection
Enable phase-to-ground zone 1 of distance protection
operation to block AR
Impedance setting of zone 1 of phase-to-phase
distance protection
Time delay of zone 1 of phase-to-phase distance
protection
Enable zone 1 of phase-to-phase distance protection
Enable phase-to-phase zone 1 of distance protection
operation to block AR
Direction option for zone 2 of distance protection
coefficient for zone 2
component
of
zero-sequence
compensation coefficient for zone 2
Phase angle of positive-sequence impedance for
zone 2
Downward offset angle of the reactance line for zone
2 of phase-to-ground distance protection
7-16
0 or 1
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0 or 1
0 or 1
0 or 1
Real component of zero-sequence compensation
Imaginary
0 or 1
-4.000~4.000
-4.000~4.000
30~89 (deg)
0~45 (deg)
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
Phase shift of phase-to-ground distance protection for
22
21M2.ZG.phi_Shift
23
21M2.ZP.phi_Shift
24
21M2.ZG.Z_Set
25
21M2.ZGQ.R_Set
26
21M2.ZG.t_Op
27
21M2.ZG.t_ShortDly
28
21M2.ZG.En
29
21M2.ZGQ.En
30
21M2.ZG.En_BlkAR
31
21M2.ZP.Z_Set
32
21M2.ZP.t_Op
33
21M2.ZP.t_ShortDly
34
21M2.ZP.En
35
21M2.ZP.En_BlkAR
36
21M2.En_ShortDly
Enable fixed accelerate zone 2 of distance protection 0 or 1
37
21-3. DirMode
Direction option for zone 3 of distance protection
38
21-3.Real_K0
39
21-3.Imag_K0
40
21-3.phi1_Reach
41
21M3.ZGQ.RCA
42
21M3.ZG.phi_Shift
43
21M3.ZP.phi_Shift
44
21M3.ZG.Z_Set
zone 2
Phase shift of phase-to-phase distance protection for
zone 2
Impedance setting of zone 2 of phase-to-ground
distance protection
Resistance setting of zone 2 of phase-to-ground
distance protection
Time delay of zone 2 of phase-to-ground distance
protection
Short time delay of zone 2 of phase-to-ground
distance protection
0, 15 or 30 (deg)
0, 15 or 30 (deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
Enable zone 2 of phase-to-ground distance protection 0 or 1
Enable zone 2 of quadrilateral phase-to-ground
distance protection
Enable phase-to-ground zone 2 of distance protection
operation to block AR
Impedance setting of zone 2 of phase-to-phase
distance protection
Time delay of zone 2 of phase-to-phase distance
protection
Short time delay of zone 2 of phase-to-phase distance
protection
Enable zone 2 of phase-to-phase distance protection
Enable phase-to-phase zone 2 of distance protection
operation to block AR
Real component of zero-sequence compensation
coefficient for zone 3
Imaginary
component
of
zero-sequence
compensation coefficient for zone 3
Phase angle of positive-sequence impedance for
zone 3
Downward offset angle of the reactance line for zone
3 of phase-to-ground distance protection
Phase shift of phase-to-ground distance protection for
zone 3
Phase shift of phase-to-phase distance protection for
zone 3
Impedance setting of zone 3 of phase-to-ground
distance protection
PCS-902 Line Distance Relay
0 or 1
0 or 1
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0 or 1
0 or 1
-4.000~4.000
-4.000~4.000
30~89 (deg)
0~45 (deg)
0, 15 or 30 (deg)
0, 15 or 30 (deg)
(0.000~4Unn)/In (ohm)
7-17
Date: 2019-03-01
-09-07
7 Settings
Resistance setting of zone 3 of phase-to-ground
45
21M3.ZGQ.R_Set
46
21M3.ZG.t_Op
47
21M3.ZG.t_ShortDly
48
21M3.ZG.En
49
21M3.ZGQ.En
50
21M3.ZG.En_BlkAR
51
21M3.ZP.Z_Set
52
21M3.ZP.t_Op
53
21M3.ZP.t_ShortDly
54
21M3.ZP.En
55
21M3.ZP.En_BlkAR
56
21M3.En_ShortDly
Enable fixed accelerate zone 3 of distance protection 0 or 1
57
21-4. DirMode
Direction option for zone 4 of distance protection
58
21-4.Real_K0
59
21-4.Imag_K0
60
21-4.phi1_Reach
61
21M4.ZGQ.RCA
62
21M4.ZG.phi_Shift
63
21M4.ZP.phi_Shift
64
21M4.ZG.Z_Set
65
21M4.ZGQ.R_Set
66
21M4.ZG.t_Op
67
21M4.ZG.t_ShortDly
distance protection
Time delay of zone 3 of phase-to-ground distance
protection
Short time delay of zone 3 of phase-to-ground
distance protection
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
Enable zone 3 of phase-to-ground distance protection 0 or 1
Enable zone 3 of quadrilateral phase-to-ground
distance protection
Enable phase-to-ground zone 3 of distance protection
operation to block AR
Impedance setting of zone 3 of phase-to-phase
distance protection
Time delay of zone 3 of phase-to-phase distance
protection
Short time delay of zone 3 of phase-to-phase distance
protection
Enable zone 3 of phase-to-phase distance protection
Enable phase-to-phase zone 3 of distance protection
operation to block AR
coefficient for zone 4
component
of
zero-sequence
compensation coefficient for zone 4
Phase angle of positive-sequence impedance for
zone 4
Downward offset angle of the reactance line for zone
4 of phase-to-ground distance protection
Phase shift of phase-to-ground distance protection for
zone 4
Phase shift of phase-to-phase distance protection for
zone 4
Impedance setting of zone 4 of phase-to-ground
distance protection
Resistance setting of zone 4 of phase-to-ground
distance protection
Time delay of zone 4 of phase-to-ground distance
protection
Short time delay of zone 4 of phase-to-ground
distance protection
7-18
0 or 1
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0 or 1
0 or 1
Real component of zero-sequence compensation
Imaginary
0 or 1
-4.000~4.000
-4.000~4.000
30~89 (deg)
0~45 (deg)
0, 15 or 30 (deg)
0, 15 or 30 (deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
68
21M4.ZG.En
Enable zone 4 of phase-to-ground distance protection 0 or 1
69
21M4.ZGQ.En
70
21M4.ZG.En_BlkAR
71
21M4.ZP.Z_Set
72
21M4.ZP.t_Op
73
21M4.ZP.t_ShortDly
74
21M4.ZP.En
75
21M4.ZP.En_BlkAR
76
21M4.En_ShortDly
Enable fixed accelerate zone 4 of distance protection 0 or 1
77
21-5. DirMode
Direction option for zone 5 of distance protection
78
21-5.Real_K0
79
21-5.Imag_K0
80
21-5.phi1_Reach
81
21M5.ZGQ.RCA
82
21M5.ZG.phi_Shift
83
21M5.ZP.phi_Shift
84
21M5.ZG.Z_Set
85
21M5.ZGQ.R_Set
86
21M5.ZG.t_Op
87
21M5.ZG.t_ShortDly
88
21M5.ZG.En
89
21M5.ZGQ.En
90
21M5.ZG.En_BlkAR
Enable zone 4 of quadrilateral phase-to-ground
distance protection
Enable phase-to-ground zone 4 of distance protection
operation to block AR
Impedance setting of zone 4 of phase-to-phase
distance protection
Time delay of zone 4 of phase-to-phase distance
protection
Short time delay of zone 4 of phase-to-phase distance
protection
Enable zone 4 of phase-to-phase distance protection
Enable phase-to-phase zone 4 of distance protection
operation to block AR
Real component of zero-sequence compensation
coefficient for zone 5
Imaginary
component
of
zero-sequence
compensation coefficient for zone 5
Phase angle of positive-sequence impedance for
zone 5
Downward offset angle of the reactance line for zone
5 of phase-to-ground distance protection
Phase shift of phase-to-ground distance protection for
zone 5
Phase shift of phase-to-phase distance protection for
zone 5
Impedance setting of zone 5 of phase-to-ground
distance protection
Resistance setting of zone 5 of phase-to-ground
distance protection
Time delay of zone 5 of phase-to-ground distance
protection
Short time delay of zone 5 of phase-to-ground
distance protection
0 or 1
0 or 1
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0 or 1
0 or 1
-4.000~4.000
-4.000~4.000
30~89 (deg)
0~45 (deg)
0, 15 or 30 (deg)
0, 15 or 30 (deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
Enable zone 5 of phase-to-ground distance protection 0 or 1
Enable zone 5 of quadrilateral phase-to-ground
distance protection
Enable phase-to-ground zone 5 of distance protection
operation to block AR
PCS-902 Line Distance Relay
0 or 1
0 or 1
7-19
Date: 2019-03-01
-09-07
7 Settings
91
21M5.ZP.Z_Set
92
21M5.ZP.t_Op
93
21M5.ZP.t_ShortDly
94
21M5.ZP.En
95
21M5.ZP.En_BlkAR
96
21M5.En_ShortDly
Impedance setting of zone 5 of phase-to-phase
distance protection
Time delay of zone 5 of phase-to-phase distance
protection
Short time delay of zone 5 of phase-to-phase distance
protection
Enable zone 5 of phase-to-phase distance protection
Enable phase-to-phase zone 5 of distance protection
operation to block AR
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0 or 1
Enable fixed accelerate zone 5 of distance protection 0 or 1
7.3.1.7 Distance Protection Settings with Quad Characteristic (21Q)
No.
Item
1
21Q.Ang_Alpha
2
21-1.Real_K0
3
21-1.Imag_K0
4
21-1.phi1_Reach
5
21Q1.ZG.RCA
6
21Q1.ZG.Z_Set
7
21Q1.ZG.R_Set
8
21Q1.ZG.t_Op
9
21Q1.ZG.En
10
21Q1.ZG.En_BlkAR
11
21Q1.ZP.RCA
12
21Q1.ZP.Z_Set
13
21Q1.ZP.R_Set
14
21Q1.ZP.t_Op
15
21Q1.ZP.En
16
21Q1.ZP.En_BlkAR
17
21-2. DirMode
Remark
Range
The angle of directional line
5~30 (deg)
Real component of zero-sequence compensation
coefficient for zone 1
Imaginary
component
of
zero-sequence
compensation coefficient for zone 1
Phase angle of positive-sequence impedance for
zone 1
Downward offset angle of the reactance line for zone
1 of phase-to-ground distance protection
Impedance setting of zone 1 of phase-to-ground
distance protection
Resistance setting of zone 1 of phase-to-ground
distance protection
Time delay of zone 1 of phase-to-ground distance
protection
-4.000~4.000
-4.000~4.000
30~89 (deg)
0~45 (deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
Enable zone 1 of phase-to-ground distance protection 0 or 1
Enable phase-to-ground zone 1 of distance protection
operation to block AR
Downward offset angle of the reactance line for zone
1 of phase-to-phase distance protection
Impedance setting of zone 1 of phase-to-phase
distance protection
Resistance setting of zone 1 of phase-to-phase
distance protection
Time delay of zone 1 of phase-to-phase distance
protection
Enable zone 1 of phase-to-phase distance protection
Enable phase-to-phase zone 1 of distance protection
operation to block AR
Direction option for zone 2 of distance protection
7-20
0 or 1
0~45
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0 or 1
0 or 1
0 or 1
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
Real component of zero-sequence compensation
18
21-2.Real_K0
19
21-2.Imag_K0
20
21-2.phi1_Reach
21
21Q2.ZG.RCA
22
21Q2.ZG.Z_Set
23
21Q2.ZG.R_Set
24
21Q2.ZG.t_Op
25
21Q2.ZG.t_ShortDly
26
21Q2.ZG.En
27
21Q2.ZG.En_BlkAR
28
21Q2.ZP.RCA
29
21Q2.ZP.Z_Set
30
21Q2.ZP.R_Set
31
21Q2.ZP.t_Op
32
21Q2.ZP.t_ShortDly
33
21Q2.ZP.En
34
21Q2.ZP.En_BlkAR
35
21Q2.En_ShortDly
Enable fixed accelerate zone 2 of distance protection
0 or 1
36
21-3. DirMode
Direction option for zone 3 of distance protection
0 or 1
37
21-3.Real_K0
38
21-3.Imag_K0
39
21-3.phi1_Reach
40
21Q3.ZG.RCA
coefficient for zone 2
Imaginary
component
of
zero-sequence
compensation coefficient for zone 2
Phase angle of positive-sequence impedance for
zone 2
Downward offset angle of the reactance line for zone
2 of phase-to-ground distance protection
Impedance setting of zone 2 of phase-to-ground
distance protection
Resistance setting of zone 2 of phase-to-ground
distance protection
Time delay of zone 2 of phase-to-ground distance
protection
Short time delay of zone 2 of phase-to-ground
distance protection
-4.000~4.000
-4.000~4.000
30~89 (deg)
0~45 (deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
Enable zone 2 of phase-to-ground distance protection 0 or 1
Enable phase-to-ground zone 2 of distance protection
operation to block AR
Downward offset angle of the reactance line for zone
2 of phase-to-phase distance protection
Impedance setting of zone 2 of phase-to-phase
distance protection
Resistance setting of zone 2 of phase-to-phase
distance protection
Time delay of zone 2 of phase-to-phase distance
protection
Short time delay of zone 2 of phase-to-ground
distance protection
Enable zone 2 of phase-to-phase distance protection
Enable phase-to-phase zone 2 of distance protection
operation to block AR
Real component of zero-sequence compensation
coefficient for zone 3
Imaginary
component
of
zero-sequence
compensation coefficient for zone 3
Phase angle of positive-sequence impedance for
zone 3
Downward offset angle of the reactance line for zone
3 of phase-to-ground distance protection
PCS-902 Line Distance Relay
0 or 1
0~45
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0 or 1
-4.000~4.000
-4.000~4.000
30~89 (deg)
0~45 (deg)
7-21
Date: 2019-03-01
-09-07
7 Settings
Impedance setting of zone 3 of phase-to-ground
41
21Q3.ZG.Z_Set
42
21Q3.ZG.R_Set
43
21Q3.ZG.t_Op
44
21Q3.ZG.t_ShortDly
45
21Q3.ZG.En
46
21Q3.ZG.En_BlkAR
47
21Q3.ZP.RCA
48
21Q3.ZP.Z_Set
49
21Q3.ZP.R_Set
50
21Q3.ZP.t_Op
51
21Q3.ZP.t_ShortDly
52
21Q3.ZP.En
53
21Q3.ZP.En_BlkAR
54
21Q3.En_ShortDly
Enable fixed accelerate zone 3 of distance protection
0 or 1
55
21-4. DirMode
Direction option for zone 4 of distance protection
0 or 1
56
21-4.Real_K0
57
21-4.Imag_K0
58
21-4.phi1_Reach
59
21Q4.ZG.RCA
60
21Q4.ZG.Z_Set
61
21Q4.ZG.R_Set
62
21Q4.ZG.t_Op
63
21Q4.ZG.t_ShortDly
distance protection
Resistance setting of zone 3 of phase-to-ground
distance protection
Time delay of zone 3 of phase-to-ground distance
protection
Short time delay of zone 3 of phase-to-ground
distance protection
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
Enable zone 3 of phase-to-ground distance protection 0 or 1
Enable phase-to-ground zone 3 of distance protection
operation to block AR
Downward offset angle of the reactance line for zone
3 of phase-to-phase distance protection
Impedance setting of zone 3 of phase-to-phase
distance protection
Resistance setting of zone 3 of phase-to-phase
distance protection
Time delay of zone 3 of phase-to-phase distance
protection
Short time delay of zone 3 of phase-to-ground
distance protection
Enable zone 3 of phase-to-phase distance protection
Enable phase-to-phase zone 3 of distance protection
operation to block AR
Real component of zero-sequence compensation
coefficient for zone 4
Imaginary
component
of
zero-sequence
compensation coefficient for zone 4
Phase angle of positive-sequence impedance for
zone 4
Downward offset angle of the reactance line for zone
4 of phase-to-ground distance protection
Impedance setting of zone 4 of phase-to-ground
distance protection
Resistance setting of zone 4 of phase-to-ground
distance protection
Time delay of zone 4 of phase-to-ground distance
protection
Short time delay of zone 4 of phase-to-ground
distance protection
7-22
0 or 1
0~45
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0 or 1
-4.000~4.000
-4.000~4.000
30~89 (deg)
0~45 (deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
64
21Q4.ZG.En
Enable zone 4 of phase-to-ground distance protection 0 or 1
65
21Q4.ZG.En_BlkAR
66
21Q4.ZP.RCA
67
21Q4.ZP.Z_Set
68
21Q4.ZP.R_Set
69
21Q4.ZP.t_Op
70
21Q4.ZP.t_ShortDly
71
21Q4.ZP.En
72
21Q4.ZP.En_BlkAR
73
21Q4.En_ShortDly
Enable fixed accelerate zone 4 of distance protection
0 or 1
74
21-5. DirMode
Direction option for zone 5 of distance protection
0 or 1
75
21-5.Real_K0
76
21-5.Imag_K0
77
21-5.phi1_Reach
78
21Q5.ZG.RCA
79
21Q5.ZG.Z_Set
80
21Q5.ZG.R_Set
81
21Q5.ZG.t_Op
82
21Q5.ZG.t_ShortDly
83
21Q5.ZG.En
84
21Q5.ZG.En_BlkAR
85
21Q5.ZP.RCA
86
21Q5.ZP.Z_Set
Enable phase-to-ground zone 4 of distance protection
operation to block AR
Downward offset angle of the reactance line for zone
4 of phase-to-phase distance protection
Impedance setting of zone 4 of phase-to-phase
distance protection
Resistance setting of zone 4 of phase-to-phase
distance protection
Time delay of zone 4 of phase-to-phase distance
protection
Short time delay of zone 4 of phase-to-ground
distance protection
Enable zone 4 of phase-to-phase distance protection
Enable phase-to-phase zone 4 of distance protection
operation to block AR
Real component of zero-sequence compensation
coefficient for zone 5
Imaginary
component
of
zero-sequence
compensation coefficient for zone 5
Phase angle of positive-sequence impedance for
zone 5
Downward offset angle of the reactance line for zone
5 of phase-to-ground distance protection
Impedance setting of zone 5 of phase-to-ground
distance protection
Resistance setting of zone 5 of phase-to-ground
distance protection
Time delay of zone 5 of phase-to-ground distance
protection
Short time delay of zone 5 of phase-to-ground
distance protection
0 or 1
0~45
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0 or 1
-4.000~4.000
-4.000~4.000
30~89 (deg)
0~45 (deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
Enable zone 5 of phase-to-ground distance protection 0 or 1
Enable phase-to-ground zone 5 of distance protection
operation to block AR
Downward offset angle of the reactance line for zone
5 of phase-to-phase distance protection
Impedance setting of zone 5 of phase-to-phase
distance protection
PCS-902 Line Distance Relay
0 or 1
0~45
(0.000~4Unn)/In (ohm)
7-23
Date: 2019-03-01
-09-07
7 Settings
87
21Q5.ZP.R_Set
88
21Q5.ZP.t_Op
89
21Q5.ZP.t_ShortDly
90
21Q5.ZP.En
91
21Q5.ZP.En_BlkAR
92
21Q5.En_ShortDly
Resistance setting of zone 5 of phase-to-phase
distance protection
Time delay of zone 5 of phase-to-phase distance
protection
Short time delay of zone 5 of phase-to-ground
distance protection
Enable zone x of phase-to-phase distance protection
Enable phase-to-phase zone 5 of distance protection
operation to block AR
Enable fixed accelerate zone 5 of distance protection
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0 or 1
0 or 1
7.3.1.8 Pilot Distance Zone Settings
No.
Item
1
21.Pilot.Real_K0
2
21.Pilot.Imag_K0
3
21.Pilot.phi1_Reach
4
21M.Pilot.Z_Set
5
21M.Pilot.R_Set_Quad
6
21Q.Pilot.Z_Set
7
21M.Pilot.Z_Rev
8
21M.Pilot.En_Z_Quad
9
21Q.Pilot.Z_Rev
10
21Q.Pilot.R_Set
11
21Q.Pilot.R_Rev
Remark
Range
Real component of zero-sequence compensation
coefficient for pilot distance protection
Imaginary
component
of
zero-sequence
compensation coefficient for pilot distance protection
Phase angle of positive-sequence impedance for pilot
distance protection
Impedance setting of pilot distance protection (Mho
characteristic)
Resistance setting of pilot distance protection (Mho
characteristic)
Impedance setting of pilot distance protection (Quad
characteristic)
Impedance setting of pilot distance protection in
reverse direction (Mho characteristic)
Enable quadrilateral characteristic of phase-to-ground
distance protection
Impedance setting of pilot distance protection in
reverse direction (Quad characteristic)
Resistance setting of pilot distance protection (Quad
characteristic)
Resistance setting of pilot distance protection in
reverse direction (Quad characteristic)
30.00~89.00 (deg)
-4.000~4.000
-4.000~4.000
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0 or 1
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
7.3.1.9 Out-of-step Protection Settings (78)
No.
Item
Remark
Range
1
78.En
Enable out-of-step protection
0 or 1
2
78.En_Trp
Enable out-of-step protection operate to trip
0 or 1
3
78.Z_Fwd
The forward impedance setting of zone detector
element
7-24
(0.000~4Unn)/In (ohm)
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
4
78.Z_Rev
5
78.phi1_Reach
6
78.phi_Start
The reversal impedance setting of zone detector
element
The system impedance angle
The minimum start angle, which generally should be
greater than maximum load angle.
(0.000~4Unn)/In (ohm)
30.00~89.00 (deg)
0~180 (deg)
It is the maximum tripping angle after out-of-step
protection operating, which is used to prevent the
7
78.phi_Trp
circuit breaker from incorrect operation due to too 0~180.00 (deg)
large current during tripping. It is generally set based
on the breaking capacity of circuit breaker.
8
78.N_Limit
The number setting of out-of-step cycle, and it is set
as 2~3 generally
1~20
7.3.1.10 Power Swing Blocking Releasing Settings (PSBR)
No.
Item
1
21M1.En_PSBR
2
21Q1.En_PSBR
3
21M2.En_PSBR
4
21Q2.En_PSBR
5
21M3.En_PSBR
6
21Q3.En_PSBR
7
21M4.En_PSBR
8
21Q4.En_PSBR
9
21M5.En_PSBR
10
21Q5.En_PSBR
11
21M.Pilot.En_PSBR
12
21Q.Pilot.En_PSBR
13
21M.I_PSBR
14
21Q.I_PSBR
Remark
Enable zone 1 of distance protection controlled by
PSBR (Mho characteristic)
Enable zone 1 of distance protection controlled by
PSBR (Quad characteristic)
Enable zone 2 of distance protection controlled by
PSBR (Mho characteristic)
Enable zone 2 of distance protection controlled by
PSBR (Quad characteristic)
Enable zone 3 of distance protection controlled by
PSBR (Mho characteristic)
Enable zone 3 of distance protection controlled by
PSBR (Quad characteristic)
Enable zone 4 of distance protection controlled by
PSBR (Mho characteristic)
Enable zone 4 of distance protection controlled by
PSBR (Quad characteristic)
Enable zone 5 of distance protection controlled by
PSBR (Mho characteristic)
Enable zone 5 of distance protection controlled by
PSBR (Quad characteristic)
Enable pilot distance zone controlled by PSBR (Mho
characteristic)
Enable pilot distance zone controlled by PSBR (Quad
characteristic)
Current setting for power swing blocking (Mho
characteristic)
Current setting for power swing blocking (Quad
characteristic)
PCS-902 Line Distance Relay
Range
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
(0.050~30.000)×In (ohm)
(0.050~30.000)×In (ohm)
7-25
Date: 2019-03-01
-09-07
7 Settings
7.3.1.11 Distance SOTF Protection Settings (21SOTF)
No.
Item
Remark
Range
Time delay of enabling SOTF protection (shared
1
SOTF.t_En
by distance SOTF protection, phase current SOTF 0.000~10.000 (s)
protection and residual current SOTF protection)
2
21SOTF.En
Enable distance SOTF protection
0 or 1
3
21SOTF.Z2.En_ManCls
4
21SOTF.Z3.En_ManCls
5
21SOTF.Z4.En_ManCls
6
21SOTF.t_ManCls
7
21SOTF.Z2.En_3PAR
8
21SOTF.Z3.En_3PAR
9
21SOTF.Z4.En_3PAR
10
21SOTF.Z2.En_PSBR
11
21SOTF.Z3.En_PSBR
12
21SOTF.Z4.En_PSBR
13
21SOTF.t_3PAR
14
21SOTF.En_1PAR
15
21SOTF.t_1PAR
16
21SOTF.En_PDF
17
21SOTF.t_PDF
18
SOTF.U_Ddl
Undervoltage setting of deadline detection
0~Unn (V)
19
SOTF.t_Ddl
Time delay of deadline detection
0.000~600.000 (s)
Enable zone 2 of distance SOTF protection for
manual closing
Enabling/disabling zone 3 of distance SOTF
protection for manual closing
Enable zone 4 of distance SOTF protection for
manual closing
Time delay of distance protection accelerating to
trip when manual closing
Enable zone 2 of distance SOTF protection for
3-pole reclosing
Enable zone 3 of distance SOTF protection for
3-pole reclosing
Enable zone 4 of distance SOTF protection for
3-pole reclosing
Enable zone 2 controlled by PSB of distance
SOTF protection for 3-pole reclosing
Enable zone 3 controlled by PSB of distance
SOTF protection for 3-pole reclosing
Enable zone 4 controlled by PSB of distance
SOTF protection for 3-pole reclosing
Time delay of distance protection accelerating to
trip when 3-pole reclosing
Enable distance SOTF protection for 1-pole
reclosing
Time delay of distance protection accelerating to
trip when 1-pole reclosing
Enable distance SOTF protection under pole
discrepancy conditions
Time delay of distance protection operating under
pole discrepancy conditions
7-26
0 or 1
0 or 1
0 or 1
0.000~10.000 (s)
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0.000~10.000 (s)
0 or 1
0.000~10.000 (s)
0 or 1
0.000~10.000 (s)
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
ManClsBI
CBPos
20
SOTF.Opt_Mode_ManCls Option of manual SOTF mode
ManClsBI/ CBPos
AutoInit
All
7.3.1.12 Optical Pilot Channel Settings
No.
Item
Remark
Range
1
FO.LocID
Identity code of the device at local end
0-65535
2
FO.RmtID
Identity code of the device at remote end
0-65535
3
FO.BaudRate
Baud rate of optical pilot channel
64 or 2048
4
FO.Protocol
It is used to select protocol type, G.703 or C37.94
G.703 or C37.94
5
FOx.Nx64k_C37.94
6
FOx.En_IntClock
Option of internal clock or external clock
0 or 1
7
FOx.En
Enable channel x
0 or 1
The setting for the times of 64kbits/s, which is an
N*64kbits/s standard defined by IEEE C37.94 standard
1-12
7.3.1.13 Pilot Distance Protection Settings (85)
No.
Item
Remark
Range
POTT
1
85.Opt_PilotMode
Option of pilot scheme
PUTT
Blocking
Option of phase-segregated signal scheme or single
2
85.Opt_Ch_PhSeg
3
85.En_WI
4
85.En_WI_Pkp
5
85.U_UV_WI
Undervoltage setting of weak infeed logic
0~Unn (V)
6
85.Z.En
Enable pilot distance protection
0 or 1
7
85.En_Unblocking1
Enable unblocking scheme
0 or 1
8
85.t_DPU_Blocking1
9
85.t_DPU_CR1
Time delay pickup for current reversal logic
0.000~1.000 (s)
10
85.t_DDO_CR1
Time delay dropoff for current reversal logic
0.000~1.000 (s)
11
85.ZX.En
Enable zone extension protection
0 or 1
12
85.t_DPU_ZX
signal scheme
Enable weak infeed scheme
For weak infeed end, If the device does not pick up for
internal fault, it is used to enable the device pick up.
Time delay for blocking scheme of pilot distance
protection operation
Pickup time delay for zone extension protection
operation
0 or 1
0 or 1
0 or 1
0.000~1.000 (s)
0.000~10.000 (s)
7.3.1.14 Pilot Directional Earth-fault Protection Settings (85)
No.
1
Item
85.DEF.En
Remark
Enable pilot directional earth-fault protection
PCS-902 Line Distance Relay
Range
0 or 1
7-27
Date: 2019-03-01
-09-07
7 Settings
2
85.DEF.En_BlkAR
3
85.DEF.En_IndepCh
4
85.En_Unblocking2
5
85.DEF.3I0_Set
6
85.DEF.t_DPU
Enable pilot directional earth-fault protection operate
to block AR
Enable independent pilot channel for pilot directional
earth-fault protection
Enable unblocking scheme for pilot DEF via pilot
channel 2
Current
setting
of
pilot
directional
earth-fault
protection
Time delay of pilot directional earth-fault protection
0 or 1
0 or 1
0 or 1
(0.050~30.000)×In (A)
0.001~10.000 (s)
Time delay pickup for current reversal logic when pilot
7
85.t_DPU_CR2
directional earth-fault protection adopts independent 0.000~1.000 (s)
pilot channel 2
Time delay dropoff for current reversal logic when
8
85.t_DDO_CR2
pilot
directional
earth-fault
protection
adopts 0.000~1.000 (s)
independent pilot channel 2
7.3.1.15 Current Direction Settings
No.
Item
Remark
The
characteristic
angle
Range
of
directional
phase
1
RCA_OC
2
RCA_ROC
3
RCA_NegOC
4
Z0_Comp
Zero-sequence compensation impedance setting
(0.000~4Unn)/In (ohm)
5
Z2_Comp
Negative-sequence compensation impedance setting
(0.000~4Unn)/In (ohm)
overcurrent element
The characteristic angle of directional earth fault
element
The
characteristic
angle
of
directional
negative-sequence overcurrent element
30.00~89.00 (deg)
30.00~89.00 (deg)
30.00~89.00 (deg)
7.3.1.16 Phase Overcurrent Protection Settings (50/51P)
No.
Item
1
50/51P.K_Hm2
2
50/51P1.I_Set
3
50/51P1.t_Op
4
50/51P1.En
5
50/51P1.En_BlkAR
6
50/51P1.En_VTS_Blk
7
50/51P1.Opt_Dir
Remark
Range
Setting of second harmonic component for blocking
phase overcurrent elements
Current setting for stage 1 of phase overcurrent
protection
Time delay for stage 1 of phase overcurrent
protection
Enable stage 1 of phase overcurrent protection
(0.050~30.000)×In (A)
0.000~20.000 (s)
0 or 1
Enable auto-reclosing blocked when stage 1 of
phase overcurrent protection operates
Enable stage 1 of phase overcurrent protection is
blocked by VT circuit failure
Direction option for stage 1 of phase overcurrent
protection
0.000~1.000
0 or 1
0 or 1
Non_Directional
Forward
Reverse
7-28
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
8
50/51P1.En_Hm2_Blk
Enable second harmonic blocking for stage 1 of
phase overcurrent protection
0 or 1
DefTime
IECN
IECV
IECE
IECST
IECLT
9
50/51P1.Opt_Curve
Option of characteristic curve for stage 1 of phase ANSIE
overcurrent protection
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
10
50/51P1.TMS
11
50/51P1.tmin
12
50/51P1.Alpha
13
50/51P1.C
14
50/51P1.K
15
50/51P2.I_Set
16
50/51P2.t_Op
17
50/51P2.En
18
50/51P2.En_BlkAR
19
50/51P2.En_VTS_Blk
20
21
50/51P2.Opt_Dir
50/51P2.En_Hm2_Blk
Time multiplier setting for stage 1 of inverse-time
phase overcurrent protection
Minimum operating time for stage 1 of inverse-time
phase overcurrent protection
Constant “α” for stage 1 of customized inverse-time
characteristic phase overcurrent protection
Constant “C” for stage 1 of customized inverse-time
characteristic phase overcurrent protection
Constant “K” for stage 1 of customized inverse-time
characteristic phase overcurrent protection
Current setting for stage 2 of phase overcurrent
protection
Time delay for stage 2 of phase overcurrent
protection
Enable stage 2 of phase overcurrent protection
Enable auto-reclosing blocked when stage 2 of
phase overcurrent protection operates
Enable stage 2 of phase overcurrent protection is
blocked by VT circuit failure
Direction option for stage 2 of phase overcurrent
protection
0.010~200.000
0.000~20.000 (s)
0.010~5.000
0.000~20.000
0.050~20.000
(0.050~30.000)×In (A)
0.000~20.000 (s)
0 or 1
0 or 1
0 or 1
Non_Directional
Forward
Reverse
Enable second harmonic blocking for stage 2 of
phase overcurrent protection
PCS-902 Line Distance Relay
0 or 1
7-29
Date: 2019-03-01
-09-07
7 Settings
DefTime
IECN
IECV
IECE
IECST
22
50/51P2.Opt_Curve
Option of characteristic curve for stage 2 of phase
overcurrent protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
23
50/51P2.TMS
24
50/51P2.tmin
25
50/51P3.I_Set
26
50/51P3.t_Op
27
50/51P3.En
28
50/51P3.En_BlkAR
29
50/51P3.En_VTS_Blk
30
31
50/51P3.Opt_Dir
50/51P3.En_Hm2_Blk
Time multiplier setting for stage 2 of inverse-time
phase overcurrent protection.
Minimum operating time for stage 2 of inverse-time
phase overcurrent protection
Current setting for stage 3 of phase overcurrent
protection
Time delay for stage 3 of phase overcurrent
protection
Enable stage 3 of phase overcurrent protection
0.010~200.000
0.000~20.000 (s)
(0.050~30.000)×In (A)
0.000~20.000 (s)
0 or 1
Enable auto-reclosing blocked when stage 3 of
phase overcurrent protection operates
Enable stage 3 of phase overcurrent protection is
blocked by VT circuit failure
Direction option for stage 3 of phase overcurrent
protection
0 or 1
0 or 1
Non_Directional
Forward
Reverse
Enable second harmonic blocking for stage 3 of
phase overcurrent protection
0 or 1
DefTime
IECN
IECV
IECE
IECST
32
50/51P3.Opt_Curve
Option of characteristic curve for stage 3 of phase
overcurrent protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
7-30
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
33
50/51P3.TMS
34
50/51P3.tmin
35
50/51P4.I_Set
36
50/51P4.t_Op
37
50/51P4.En
38
50/51P4.En_BlkAR
39
50/51P4.En_VTS_Blk
40
41
50/51P4.Opt_Dir
50/51P4.En_Hm2_Blk
Time multiplier setting for stage 3 of inverse-time
phase overcurrent protection.
Minimum operating time for stage 3 of inverse-time
phase overcurrent protection
Current setting for stage 4 of phase overcurrent
protection
Time delay for stage 4 of phase overcurrent
protection
Enable stage 4 of phase overcurrent protection
Enable auto-reclosing blocked when stage 4 of
phase overcurrent protection operates
Enable stage 4 of phase overcurrent protection is
blocked by VT circuit failure
Direction option for stage 4 of phase overcurrent
protection
0.010~200.000
0.000~20.000 (s)
(0.050~30.000)×In (A)
0.000~20.000 (s)
0 or 1
0 or 1
0 or 1
Non_Directional
Forward
Reverse
Enable second harmonic blocking for stage 4 of
phase overcurrent protection
0 or 1
DefTime
IECN
IECV
IECE
IECST
42
50/51P4.Opt_Curve
Option of characteristic curve for stage 4 of phase
overcurrent protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
43
50/51P4.TMS
44
50/51P4.tmin
Time multiplier setting for stage 4 of inverse-time
phase overcurrent protection.
Minimum operating time for stage 4 of inverse-time
phase overcurrent protection
0.010~200.000
0.010~20.000 (s)
7.3.1.17 Earth Fault Protection Settings (50/51G)
No.
Item
Remark
Setting of second harmonic component for blocking
Range
1
50/51G.K_Hm2
2
50/51G1.3I0_Set
Current setting for stage 1 of earth fault protection
(0.050~30.000)×In (A)
3
50/51G1.t_Op
Time delay for stage 1 of earth fault protection
0.000~20.000 (s)
4
50/51G1.En
Enable stage 1 of earth fault protection
0 or 1
earth fault elements
PCS-902 Line Distance Relay
0.000~1.000
7-31
Date: 2019-03-01
-09-07
7 Settings
5
50/51G1.En_BlkAR
Enable auto-reclosing blocked when stage 1 of
earth fault protection operates
0 or 1
Non_Directional
6
50/51G1.Opt_Dir
Direction option for stage 1 of earth fault protection
Forward
Reverse
7
50/51G1.En_Hm2_Blk
8
50/51G1.En_Abnor_Blk
9
50/51G1.En_VTS_Blk
10
50/51G1.En_CTS_Blk
Enable second harmonic blocking for stage 1 of
earth fault protection
Enable blocking for stage 1 of earth fault protection
under abnormal conditions
Enable blocking for stage 1 of earth fault protection
under VT failure conditions
Enable blocking for stage 1 of earth fault protection
under CT failure conditions
0 or 1
0 or 1
0 or 1
0 or 1
DefTime
IECN
IECV
IECE
IECST
IECLT
11
50/51G1.Opt_Curve
Option of characteristic curve for stage 1 of earth ANSIE
fault protection
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Time multiplier setting for stage 1 of inverse-time
12
50/51G1.TMS
13
50/51G1.tmin
14
50/51G1.Alpha
15
50/51G1.C
16
50/51G1.K
17
50/51G2.3I0_Set
Current setting for stage 2 of earth fault protection
(0.050~30.000)×In (A)
18
50/51G2.t_Op
Time delay for stage 2 of earth fault protection
0.000~20.000 (s)
19
50/51G2.t_ShortDly
Short time delay for stage 2 of earth fault protection 0.000~20.000 (s)
20
50/51G2.En
Enable stage 2 of earth fault protection
21
50/51G2.En_ShortDly
earth fault protection
Minimum operating time for stage 1 of inverse-time
earth fault protection
Constant “α” for stage 1 of customized inverse-time
characteristic earth fault protection
Constant “C” for stage 1 of customized inverse-time
characteristic earth fault protection
Constant “K” for stage 1 of customized inverse-time
characteristic earth fault protection
7-32
0.050~20.000 (t)
0.010~5.000
0.000~20.000
0.050~20.000
0 or 1
Enable short time delay for stage 2 of earth fault
protection
0.010~200.000
0 or 1
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
22
50/51G2.En_BlkAR
Enable auto-reclosing blocked when stage 2 of
earth fault protection operates
0 or 1
Non_Directional
23
50/51G2.Opt_Dir
Direction option for stage 2 of earth fault protection
Forward
Reverse
24
50/51G2.En_Hm2_Blk
25
50/51G2.En_Abnor_Blk
26
50/51G2.En_VTS_Blk
27
50/51G2.En_CTS_Blk
Enable second harmonic blocking for stage 2 of
earth fault protection
Enable blocking for stage 2 of earth fault protection
under abnormal conditions
Enable blocking for stage 2 of earth fault protection
under VT failure conditions
Enable blocking for stage 2 of earth fault protection
under CT failure conditions
0 or 1
0 or 1
0 or 1
0 or 1
DefTime
IECN
IECV
IECE
IECST
28
50/51G2.Opt_Curve
Option of characteristic curve for stage 2 of earth
fault protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 2 of inverse-time
29
50/51G2.TMS
30
50/51G2.tmin
31
50/51G3.3I0_Set
Current setting for stage 3 of earth fault protection
(0.050~30.000)×In (A)
32
50/51G3.t_Op
Time delay for stage 3 of earth fault protection
0.000~20.000 (s)
33
50/51G3.t_ShortDly
Short time delay for stage 3 of earth fault protection 0.000~20.000 (s)
34
50/51G3.En
Enable stage 3 of earth fault protection
35
50/51G3.En_ShortDly
36
50/51G3.En_BlkAR
earth fault protection
Minimum operating time for stage 2 of inverse-time
earth fault protection
Enable short time delay for stage 3 of earth fault
protection
Enable auto-reclosing blocked when stage 3 of
earth fault protection operates
0.010~200.000
0.050~20.000 (s)
0 or 1
0 or 1
0 or 1
Non_Directional
37
50/51G3.Opt_Dir
Direction option for stage 3 of earth fault protection
Forward
Reverse
38
50/51G3.En_Hm2_Blk
Enable second harmonic blocking for stage 3 of
earth fault protection
PCS-902 Line Distance Relay
0 or 1
7-33
Date: 2019-03-01
-09-07
7 Settings
39
50/51G3.En_Abnor_Blk
40
50/51G3.En_VTS_Blk
41
50/51G3.En_CTS_Blk
Enable blocking for stage 3 of earth fault protection
under abnormal conditions
Enable blocking for stage 3 of earth fault protection
under VT failure conditions
Enable blocking for stage 3 of earth fault protection
under CT failure conditions
0 or 1
0 or 1
0 or 1
DefTime
IECN
IECV
IECE
IECST
42
50/51G3.Opt_Curve
Option of characteristic curve for stage 3 of earth
fault protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 3 of inverse-time
43
50/51G3.TMS
44
50/51G3.tmin
45
50/51G4.3I0_Set
Current setting for stage 4 of earth fault protection
(0.050~30.000)×In (A)
46
50/51G4.t_Op
Time delay for stage 4 of earth fault protection
0.000~20.000 (s)
47
50/51G4.t_ShortDly
Short time delay for stage 4 of earth fault protection 0.000~20.000 (s)
48
50/51G4.En
Enable stage 4 of earth fault protection
49
50/51G4.En_ShortDly
50
50/51G4.En_BlkAR
earth fault protection
Minimum operating time for stage 3 of inverse-time
earth fault protection
0.010~200.000
0.050~20.000 (s)
0 or 1
Enable short time delay for stage 4 of earth fault
protection
Enable auto-reclosing blocked when stage 4 of
earth fault protection operates
0 or 1
0 or 1
Non_Directional
51
50/51G4.Opt_Dir
Direction option for stage 4 of earth fault protection
Forward
Reverse
52
50/51G4.En_Hm2_Blk
53
50/51G4.En_Abnor_Blk
54
50/51G4.En_VTS_Blk
55
50/51G4.En_CTS_Blk
Enable second harmonic blocking for stage 4 of
earth fault protection
Enable blocking for stage 4 of earth fault protection
under abnormal conditions
Enable blocking for stage 4 of earth fault protection
under VT failure conditions
Enable blocking for stage 4 of earth fault protection
under CT failure conditions
7-34
0 or 1
0 or 1
0 or 1
0 or 1
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
DefTime
IECN
IECV
IECE
IECST
56
50/51G4.Opt_Curve
Option of characteristic curve for stage 4 of earth
fault protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
57
50/51G4.TMS
58
50/51G4.tmin
Time multiplier setting for stage 4 of inverse-time
earth fault protection
Minimum operating time for stage 4 of inverse-time
earth fault protection
0.010~200.000
0.050~20.000 (s)
7.3.1.18 Negative-sequence Overcurrent Protection Settings (50/51Q)
No.
Item
1
50/51Q1.I2_Set
2
50/51Q1.I2/I1_Set
3
50/51Q1.t_Op
4
50/51Q1.En
5
50/51Q1.En_BlkAR
6
50/51Q1.Opt_Dir
7
50/51Q1.En_Abnor_Blk
8
50/51Q1.En_VTS_Blk
9
50/51Q1.En_CTS_Blk
Remark
Range
Current setting for stage 1 of negative-sequence
overcurrent protection
Ratio
coefficient
(I2/I1)
for
stage
1
of
negative-sequence overcurrent protection
Time delay for stage 1 of negative-sequence
overcurrent protection
Enable stage 1 of negative-sequence overcurrent
protection
Enable auto-reclosing blocked when stage 1 of
negative-sequence overcurrent protection operates
Direction option for stage 1 of negative-sequence
overcurrent protection
Enable blocking for stage 1 of negative-sequence
overcurrent protection under abnormal conditions
Enable blocking for stage 1 of negative-sequence
overcurrent protection under VT failure conditions
Enable blocking for stage 1 of negative-sequence
overcurrent protection under CT failure conditions
PCS-902 Line Distance Relay
(0.050~30.000)×In (A)
0.00~1.00
0.000~20.000 (s)
0 or 1
0 or 1
Non_Directional
Forward
Reverse
0 or 1
0 or 1
0 or 1
7-35
Date: 2019-03-01
-09-07
7 Settings
DefTime
IECN
IECV
IECE
IECST
IECLT
10
50/51Q1.Opt_Curve
Option of characteristic curve for stage 1 of ANSIE
negative-sequence overcurrent protection
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
11
50/51Q1.TMS
12
50/51Q1.tmin
Time multiplier setting for stage 1 of inverse-time
negative-sequence overcurrent protection
Minimum operating time for stage 1 of inverse-time
negative-sequence overcurrent protection
0.010~200.000
0.050~20.000 (s)
Constant “α” for stage 1 of customized inverse-time
13
50/51Q1.Alpha
characteristic
negative-sequence
overcurrent 0.010~5.000
protection
Constant “C” for stage 1 of customized inverse-time
14
50/51Q1.C
characteristic
negative-sequence
overcurrent 0.000~20.000
protection
Constant “K” for stage 1 of customized inverse-time
15
50/51Q1.K
characteristic
negative-sequence
overcurrent 0.050~20.000
protection
16
50/51Q2.I2_Set
17
50/51Q2.I2/I1_Set
18
50/51Q2.t_Op
19
50/51Q2.En
20
50/51Q2.En_BlkAR
21
22
50/51Q2.Opt_Dir
50/51Q2.En_Abnor_Blk
Current setting for stage 2 of negative-sequence
overcurrent protection
Ratio
coefficient
(I2/I1)
for
stage
2
of
negative-sequence overcurrent protection
Time delay for stage 2 of negative-sequence
overcurrent protection
Enable stage 2 of negative-sequence overcurrent
protection
Enable auto-reclosing blocked when stage 2 of
negative-sequence overcurrent protection operates
Direction option for stage 2 of negative-sequence
overcurrent protection
0.00~1.00
0.000~20.000 (s)
0 or 1
0 or 1
Non_Directional
Forward
Reverse
Enable blocking for stage 2 of negative-sequence
overcurrent protection under abnormal conditions
7-36
(0.050~30.000)×In (A)
0 or 1
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
23
50/51Q2.En_VTS_Blk
24
50/51Q2.En_CTS_Blk
Enable blocking for stage 2 of negative-sequence
overcurrent protection under VT failure conditions
Enable blocking for stage 2 of negative-sequence
overcurrent protection under CT failure conditions
0 or 1
0 or 1
DefTime
IECN
IECV
IECE
IECST
25
50/51Q2.Opt_Curve
Option of characteristic curve for stage 2 of
negative-sequence overcurrent protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
26
50/51Q2.TMS
27
50/51Q2.tmin
28
50/51Q3.I2_Set
29
50/51Q3.I2/I1_Set
30
50/51Q3.t_Op
31
50/51Q3.En
32
50/51Q3.En_BlkAR
33
50/51Q3.Opt_Dir
34
50/51Q3.En_Abnor_Blk
35
50/51Q3.En_VTS_Blk
36
50/51Q3.En_CTS_Blk
Time multiplier setting for stage 2 of inverse-time
negative-sequence overcurrent protection
Minimum operating time for stage 2 of inverse-time
negative-sequence overcurrent protection
Current setting for stage 3 of negative-sequence
overcurrent protection
Ratio
coefficient
(I2/I1)
for
stage
3
of
negative-sequence overcurrent protection
Time delay for stage 3 of negative-sequence
overcurrent protection
Enable stage 3 of negative-sequence overcurrent
protection
Enable auto-reclosing blocked when stage 3 of
negative-sequence overcurrent protection operates
Direction option for stage 3 of negative-sequence
overcurrent protection
Enable blocking for stage 3 of negative-sequence
overcurrent protection under abnormal conditions
Enable blocking for stage 3 of negative-sequence
overcurrent protection under VT failure conditions
Enable blocking for stage 3 of negative-sequence
overcurrent protection under CT failure conditions
PCS-902 Line Distance Relay
0.010~200.000
0.050~20.000 (s)
(0.050~30.000)×In (A)
0.00~1.00
0.000~20.000 (s)
0 or 1
0 or 1
Non_Directional
Forward
Reverse
0 or 1
0 or 1
0 or 1
7-37
Date: 2019-03-01
-09-07
7 Settings
DefTime
IECN
IECV
IECE
IECST
37
50/51Q3.Opt_Curve
Option of characteristic curve for stage 3 of
negative-sequence overcurrent protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
38
50/51Q3.TMS
39
50/51Q3.tmin
40
50/51Q4.I2_Set
41
50/51Q4.I2/I1_Set
42
50/51Q4.t_Op
43
50/51Q4.En
44
50/51Q4.En_Trp
45
50/51Q4.En_BlkAR
46
50/51Q4.Opt_Dir
47
50/51Q4.En_Abnor_Blk
48
50/51Q4.En_VTS_Blk
49
50/51Q4.En_CTS_Blk
Time multiplier setting for stage 3 of inverse-time
negative-sequence overcurrent protection
Minimum operating time for stage 3 of inverse-time
negative-sequence overcurrent protection
Current setting for stage 4 of negative-sequence
overcurrent protection
Ratio
coefficient
(I2/I1)
for
stage
4
of
negative-sequence overcurrent protection
Time delay for stage 4 of negative-sequence
overcurrent protection
Enable stage 4 of negative-sequence overcurrent
protection
Enable stage 4 of negative-sequence overcurrent
protection operate to trip or alarm.
Enable auto-reclosing blocked when stage 4 of
negative-sequence overcurrent protection operates
Direction option for stage 4 of negative-sequence
overcurrent protection
0.050~20.000 (s)
(0.050~30.000)×In (A)
0.00~1.00
0.000~20.000 (s)
0 or 1
0 or 1
0 or 1
Non_Directional
Forward
Reverse
Enable blocking for stage 4 of negative-sequence
overcurrent protection under abnormal conditions
Enable blocking for stage 4 of negative-sequence
overcurrent protection under VT failure conditions
Enable blocking for stage 4 of negative-sequence
overcurrent protection under CT failure conditions
7-38
0.010~200.000
0 or 1
0 or 1
0 or 1
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
DefTime
IECN
IECV
IECE
IECST
50
50/51Q4.Opt_Curve
Option of characteristic curve for stage 4 of
negative-sequence overcurrent protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
51
50/51Q4.TMS
52
50/51Q4.tmin
Time multiplier setting for stage 4 of inverse-time
negative-sequence overcurrent protection
Minimum operating time for stage 4 of inverse-time
negative-sequence overcurrent protection
0.010~200.000
0.050~20.000 (s)
7.3.1.19 Overcurrent Protection Settings for VT Circuit Failure (50PVT/50GVT)
No.
Item
1
50PVT1.I_Set
2
50PVT1.t_Op
3
50PVT1.En
4
50PVT2.I_Set
5
50PVT2.t_Op
6
50PVT2.En
Remark
Current setting for stage 1 of phase overcurrent
protection when VT circuit failure
Time delay for stage 1 of phase overcurrent
protection when VT circuit failure
Enable stage 1 of phase overcurrent protection
when VT circuit failure
Current setting for stage 2 of phase overcurrent
protection when VT circuit failure
Time delay for stage 2 of phase overcurrent
protection when VT circuit failure
Enable stage 2 of phase overcurrent protection
when VT circuit failure
Range
(0.050~30.000)×In (A)
0.000~10.000 (s)
0 or 1
(0.050~30.000)×In (A)
0.000~10.000 (s)
0 or 1
DefTime
IECN
IECV
IECE
Option of inverse-time characteristic curve for
7
50PVT2.Opt_Curve
stage 2 of phase overcurrent protection when VT
circuit failure
IECST
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
PCS-902 Line Distance Relay
7-39
Date: 2019-03-01
-09-07
7 Settings
ANSILT
8
50PVT2.TMS
9
50PVT2.tmin
Time multiplier setting for
overcurrent protection when VT circuit failure
Minimum operating time for stage 2
50PVT2.Alpha
of phase
overcurrent protection when VT circuit failure
Constant
10
stage 2 of phase
“α”
inverse-time
for
stage
characteristic
2
of
customized
phase
overcurrent
0.010~200.000
0.000~20.000 (s)
0.010~5.000
protection when VT circuit failure
Constant
11
50PVT2.C
“C”
inverse-time
for
stage
characteristic
2
of
customized
phase
overcurrent
0.000~20.000
protection when VT circuit failure
Constant
12
50PVT2.K
“K”
inverse-time
for
stage
characteristic
2
of
customized
phase
overcurrent
0.050~20.000
protection when VT circuit failure
13
50GVT1.3I0_Set
14
50GVT1.t_Op
15
50GVT1.En
16
50GVT2.3I0_Set
17
50GVT2.t_Op
18
50GVT2.En
Current setting for stage 1 of ground overcurrent
protection when VT circuit failure
Time delay for stage 1 of ground overcurrent
protection when VT circuit failure
Enable stage 1 of ground overcurrent protection
when VT circuit failure
Current setting for stage 2 of ground overcurrent
protection when VT circuit failure
Time delay for stage 2 of ground overcurrent
protection when VT circuit failure
Enable stage 2 of ground overcurrent protection
when VT circuit failure
(0.050~30.000)×In (A)
0.000~10.000 (s)
0 or 1
(0.050~30.000)×In (A)
0.000~10.000 (s)
0 or 1
DefTime
IECN
IECV
IECE
IECST
19
50GVT2.Opt_Curve
Option of inverse-time characteristic curve for
IECLT
stage 2 of ground overcurrent protection when VT
ANSIE
circuit failure
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
20
50GVT2.TMS
21
50GVT2.tmin
22
50GVT2.Alpha
Time multiplier setting for stage 2 of ground
overcurrent protection when VT circuit failure
Minimum operating time for stage 2 of ground
overcurrent protection when VT circuit failure
Constant
“α”
for
stage
2
7-40
of
customized
0.010~200.000
0.000~20.000 (s)
0.010~5.000
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
inverse-time characteristic ground overcurrent
protection when VT circuit failure
Constant
23
50GVT2.C
“C”
for
stage
2
of
customized
inverse-time characteristic ground overcurrent
0.000~20.000
protection when VT circuit failure
Constant
24
50GVT2.K
“K”
for
stage
2
of
customized
inverse-time characteristic ground overcurrent
0.050~20.000
protection when VT circuit failure
7.3.1.20 Phase Current SOTF Protection Settings (50PSOTF)
No.
Item
Remark
Range
1
50PSOTF.I_Set
Current setting of phase current SOTF protection
(0.050~30.000)×In (A)
2
50PSOTF.t_Op
Time delay for phase current SOTF protection
0.000~10.000 (s)
3
50PSOTF.En
Enable phase current SOTF protection
0 or 1
4
50PSOTF.En_Hm2_Blk
5
50PSOTF.Up_Set
6
50PSOTF.Upp_Set
7
50PSOTF.U2_Set
8
50PSOTF.3U0_Set
9
50PSOTF.En_Up_UV
10
50PSOTF.En_Upp_UV
11
50PSOTF.En_U2_OV
12
50PSOTF.En_3U0_OV
Enable second harmonic
blocking for phase
overcurrent SOTF protection
Voltage setting for phase undervoltage supervision
logic
Voltage setting for phase-phase undervoltage
supervision logic
Voltage setting for negative-sequence overvoltage
supervision logic
Voltage setting for zero-sequence overvoltage
supervision logic
Enable phase undervoltage supervision logic for
phase current SOTF protection
Enable phase-phase undervoltage supervision logic
for phase current SOTF protection
Enable negative-sequence overvoltage supervision
logic for phase current SOTF protection
Enable zero-sequence overvoltage supervision
logic for phase current SOTF protection
0 or 1
(0~1) ×Un (V)
(0~1) ×Un (V)
(0~1) ×Un (V)
(0~1) ×Un (V)
0 or 1
0 or 1
0 or 1
0 or 1
7.3.1.21 Residual Current SOTF Protection Settings (50GSOTF)
No.
Item
1
50GSOTF.3I0_Set
2
50GSOTF.t_Op_3P
3
50GSOTF.t_Op_1P
4
50GSOTF.En
5
50GSOTF.En_Hm2_Blk
Remark
Current setting of residual current SOTF protection
Time delay for residual current SOTF protection
when 3 pole closed
Time delay for residual current SOTF protection
when 1 pole closed
Enable residual current SOTF protection
Enable residual current SOTF protection blocked by
harmonic
PCS-902 Line Distance Relay
Range
(0.050~30.000)×In (A)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0 or 1
7-41
Date: 2019-03-01
-09-07
7 Settings
7.3.1.22 Overvoltage Protection Settings (59P)
No.
Item
Remark
Range
1
59P1.U_Set
Voltage setting for stage 1 of overvoltage protection
Un~2Unn (V)
2
59P1.t_Op
Time delay for stage 1 of overvoltage protection
0.000~30.000 (s)
3
59P1.En
Enable stage 1 of overvoltage protection
0 or 1
4
59P1.Opt_1P/3P
5
59P1.Opt_Up/Upp
6
59P1.En_Alm
7
59P1.En_52b_TT
8
59P1.En_TT
Option of 1-out-of-3 mode or 3-out-of-3 mode for stage
1 of overvoltage protection
Option of phase-to-phase voltage or phase voltage for
stage 1 of overvoltage protection
Enable stage 1 of overvoltage protection for alarm
purpose
Enable transfer trip controlled by CB open position for
stage 1 of overvoltage protection
Enable stage 1 of overvoltage protection operate to
initiate transfer trip
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
DefTime
IECN
IECV
IECE
IECST
9
59P1.Opt_Curve
Option of characteristic curve for stage 1 of overvoltage
protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 1 of inverse-time
10
59P1.TMS
11
59P1.tmin
12
59P2.U_Set
Voltage setting for stage 2 of overvoltage protection
Un~2Unn (V)
13
59P2.t_Op
Time delay for stage 2 of overvoltage protection
0.000~30.000 (s)
14
59P2.En
Enable stage x of overvoltage protection
0 or 1
15
59P2.Opt_1P/3P
16
59P2.Opt_Up/Upp
17
59P2.En_Alm
overvoltage protection
Minimum delay for stage 1 of inverse-time overvoltage
protection
Option of 1-out-of-3 mode or 3-out-of-3 mode for stage
2 of overvoltage protection
Option of phase-to-phase voltage or phase voltage for
stage 2 of overvoltage protection
Enable stage 2 of overvoltage protection for alarm
purpose
7-42
0.010~200.000
0.050~20.000 (s)
0 or 1
0 or 1
0 or 1
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
18
59P2.En_52b_TT
19
59P2.En_TT
Enable transfer trip controlled by CB open position for
stage 2 of overvoltage protection
Enable stage 2 of overvoltage protection operate to
initiate transfer trip
0 or 1
0 or 1
DefTime
IECN
IECV
IECE
IECST
20
59P2.Opt_Curve
Option of characteristic curve for stage 2 of overvoltage
protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 2 of inverse-time
21
59P2.TMS
22
59P2.tmin
23
59P3.U_Set
Voltage setting for stage 3 of overvoltage protection
Un~2Unn (V)
24
59P3.t_Op
Time delay for stage 3 of overvoltage protection
0.000~30.000 (s)
25
59P3.En
Enable stage 3 of overvoltage protection
0 or 1
26
59P3.Opt_1P/3P
27
59P3.Opt_Up/Upp
28
59Px.En_Alm
29
59P3.En_52b_TT
30
59P3.En_TT
overvoltage protection
Minimum delay for stage 2 of inverse-time overvoltage
protection
Option of 1-out-of-3 mode or 3-out-of-3 mode for stage
3 of overvoltage protection
Option of phase-to-phase voltage or phase voltage for
stage 3 of overvoltage protection
Enable stage 3 of overvoltage protection for alarm
purpose
Enable transfer trip controlled by CB open position for
stage 3 of overvoltage protection
Enable stage 3 of overvoltage protection operate to
initiate transfer trip
PCS-902 Line Distance Relay
0.010~200.000
0.050~20.000 (s)
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
7-43
Date: 2019-03-01
-09-07
7 Settings
DefTime
IECN
IECV
IECE
IECST
31
59P3.Opt_Curve
Option of characteristic curve for stage 3 of overvoltage
protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
32
59P3.TMS
33
59P3.tmin
Time multiplier setting for stage 3 of inverse-time
overvoltage protection
Minimum delay for stage 3 of inverse-time overvoltage
protection
0.010~200.000
0.050~20.000 (s)
7.3.1.23 Negative-sequence Overvoltage Protection Settings (59Q)
No.
Item
1
59Q.U_Set
2
59Q.t_Op
3
59Q.En
Remark
Range
Voltage setting for negative-sequence overvoltage
protection
Time
delay
for
negative-sequence
overvoltage
protection
Enable negative-sequence overvoltage protection
0~Un (V)
0.000~30.000 (s)
0 or 1
7.3.1.24 Residual Overvoltage Protection Settings (59G)
No.
Item
1
59G1.3U0_Set
2
59G1.t_Op
3
59G1.En
4
59G2.3U0_Set
5
59G2.t_Op
6
59G2.En
Remark
Range
Voltage setting of stage 1 of residual overvoltage
protection.
Time delay of stage 1 of residual overvoltage
protection.
Enable stage 1 of residual overvoltage protection.
Voltage setting of stage 2 of residual overvoltage
protection.
Time delay of stage 2 of residual overvoltage
protection.
Enable stage 2 of residual overvoltage protection.
7-44
0~2Unn (V)
0.000~3600.000 (s)
0 or 1
0~2Unn (V)
0.000~3600.000 (s)
0 or 1
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
DefTime
IECN
IECV
IECE
IECST
IECLT
7
59G2.Opt_Curve
Option of characteristic curve for stage 2 of residual ANSIE
overvoltage protection
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
8
59G2.TMS
9
59G2.tmin
10
59G2.Alpha
11
59G2.C
12
59G2.K
13
59G3.3U0_Set
14
59G3.t_Op
15
59G3.En
16
59G3.En_Trp
Time multiplier setting for stage 2 of residual
overvoltage protection
Minimum operating time for stage 2 of residual
overvoltage protection
Constant “α” for stage 2 of customized inverse-time
characteristic residual overvoltage protection
Constant “C” for stage 2 of customized inverse-time
characteristic residual overvoltage protection
Constant “K” for stage 2 of customized inverse-time
characteristic residual overvoltage protection
Voltage setting of stage 3 of residual overvoltage
protection.
Time delay of stage 3 of residual overvoltage
protection.
Enable stage 3 of residual overvoltage protection.
Enable stage 3 of residual overvoltage protection for
trip purpose.
PCS-902 Line Distance Relay
0.050~3.200
0.000~20.000 (s)
0.020~5.000
0.000~20.000
0.000~120.000
0~2Unn (V)
0.000~3600.000 (s)
0 or 1
0 or 1
7-45
Date: 2019-03-01
-09-07
7 Settings
DefTime
IECN
IECV
IECE
IECST
IECLT
17
59G3.Opt_Curve
Option of characteristic curve for stage 3 of residual ANSIE
overvoltage protection
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
18
59G3.TMS
19
59G3.tmin
20
59G3.Alpha
21
59G3.C
22
59G3.K
Time multiplier setting for stage 3 of residual
overvoltage protection
Minimum operating time for stage 3 of residual
overvoltage protection
Constant “α” for stage 3 of customized inverse-time
characteristic residual overvoltage protection
Constant “C” for stage 3 of customized inverse-time
characteristic residual overvoltage protection
Constant “K” for stage 3 of customized inverse-time
characteristic residual overvoltage protection
0.050~3.200
0.000~20.000 (s)
0.020~5.000
0.000~20.000
0.000~120.000
7.3.1.25 Undervoltage Protection Settings (27P)
No.
Item
Remark
Range
1
27P1.U_Set
Voltage setting for stage 1 of undervoltage protection
0~Unn (V)
2
27P1.t_Op
Time delay for stage 1 of undervoltage protection
0.000~30.000 (s)
3
27P1.En
Enable stage 1 of undervoltage protection
0 or 1
4
27P1.En_FD_Ctrl
5
27P1.En_Curr_Ctrl
6
27P1.En_VTS_Blk
7
27P1.Opt_1P/3P
Enable stage 1 of undervoltage protection controlled by
FD element reflecting current
Enable stage 1 of undervoltage protection controlled by
current condition
Enable stage 1 of undervoltage protection controlled by
VT circuit failure
Option of 1-out-of-3 mode or 3-out-of-3 mode for stage
1 of undervoltage protection
0 or 1
0 or 1
0 or 1
0 or 1
Option of voltage criterion adopting phase-to-phase
8
27P1.Opt_Up/Upp
voltage or phase voltage for stage 1 of undervoltage 0 or 1
protection
9
27P1.En_Alm
Enable stage 1 of undervoltage protection operate to
alarm
7-46
0 or 1
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
DefTime
IECN
IECV
IECE
IECST
10
27P1.Opt_Curve
Option
of
characteristic
curve
for
stage
1
of
undervoltage protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 1 of inverse-time
11
27P1.TMS
12
27P1.tmin
13
27P2.U_Set
Voltage setting for stage 2 of undervoltage protection
0~Unn (V)
14
27P2.t_Op
Time delay for stage 2 of undervoltage protection
0.000~30.000 (s)
15
27P2.En
Enable stage 2 of undervoltage protection
0 or 1
16
27P2.En_FD_Ctrl
17
27P2.En_Curr_Ctrl
18
27P2.En_VTS_Blk
19
27P2.Opt_1P/3P
undervoltage protection
Minimum delay for stage 1 of inverse-time undervoltage
protection
Enable stage 2 of undervoltage protection controlled by
FD element reflecting current
Enable stage 2 of undervoltage protection controlled by
current condition
Enable stage 2 of undervoltage protection controlled by
VT circuit failure
Option of 1-out-of-3 mode or 3-out-of-3 mode for stage
2 of undervoltage protection
0.010~200.000
0.050~20.000 (s)
0 or 1
0 or 1
0 or 1
0 or 1
Option of voltage criterion adopting phase-to-phase
20
27P2.Opt_Up/Upp
voltage or phase voltage for stage 2 of undervoltage 0 or 1
protection
21
27P2.En_Alm
Enable stage 2 of undervoltage protection operate to
alarm
PCS-902 Line Distance Relay
0 or 1
7-47
Date: 2019-03-01
-09-07
7 Settings
DefTime
IECN
IECV
IECE
IECST
22
27P2.Opt_Curve
Option
of
characteristic
curve
for
stage
2
of
undervoltage protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 2 of inverse-time
23
27P2.TMS
24
27P2.tmin
25
27P3.U_Set
Voltage setting for stage 3 of undervoltage protection
0~Unn (V)
26
27P3.t_Op
Time delay for stage 3 of undervoltage protection
0.000~30.000 (s)
27
27P3.En
Enable stage 3 of undervoltage protection
0 or 1
28
27P3.En_FD_Ctrl
29
27P3.En_Curr_Ctrl
30
27P3.En_VTS_Blk
31
27P3.Opt_1P/3P
undervoltage protection
Minimum delay for stage 2 of inverse-time undervoltage
protection
Enable stage 3 of undervoltage protection controlled by
FD element reflecting current
Enable stage 3 of undervoltage protection controlled by
current condition
Enable stage 3 of undervoltage protection controlled by
VT circuit failure
Option of 1-out-of-3 mode or 3-out-of-3 mode for stage
3 of undervoltage protection
0.010~200.000
0.050~20.000 (s)
0 or 1
0 or 1
0 or 1
0 or 1
Option of voltage criterion adopting phase-to-phase
32
27P3.Opt_Up/Upp
voltage or phase voltage for stage 3 of undervoltage 0 or 1
protection
33
27P3.En_Alm
Enable stage 3 of undervoltage protection operate to
alarm
7-48
0 or 1
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
DefTime
IECN
IECV
IECE
IECST
34
27P3.Opt_Curve
Option
of
characteristic
curve
for
stage
3
of
undervoltage protection
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
35
27P3.TMS
36
27P3.tmin
Time multiplier setting for stage 3 of inverse-time
undervoltage protection
Minimum delay for stage 3 of inverse-time undervoltage
protection
0.010~200.000
0.050~20.000 (s)
7.3.1.26 Frequency Protection Settings (81O and 81U)
No.
Item
Remark
Range
1
81O.f_Pkp
Frequency pickup setting for overfrequency protection 50.000~65.000 (Hz)
2
81O.OF1.f_Set
3
81O.OF1.t_Op
Time delay for stage 1 of overfrequency protection
0.000~20.000 (s)
4
81O.OF1.En
Enable stage 1 of overfrequency protection
0 or 1
5
81O.OF2.f_Set
6
81O.OF2.t_Op
Time delay for stage 2 of overfrequency protection
0.000~20.000 (s)
7
81O.OF2.En
Enable stage 2 of overfrequency protection
0 or 1
8
81O.OF3.f_Set
9
81O.OF3.t_Op
Time delay for stage 3 of overfrequency protection
0.000~20.000 (s)
10
81O.OF3.En
Enable stage 3 of overfrequency protection
0 or 1
11
81O.OF4.f_Set
12
81O.OF4.t_Op
Time delay for stage 4 of overfrequency protection
0.000~20.000 (s)
13
81O.OF4.En
Enable stage 4 of overfrequency protection
0 or 1
14
81U.f_Pkp
15
81U.df/dt_Blk
16
81U.UF1.f_Set
Frequency setting for stage 1 of overfrequency
protection
Frequency setting for stage 2 of overfrequency
protection
Frequency setting for stage 3 of overfrequency
protection
Frequency setting for stage 4 of overfrequency
protection
Frequency
pickup
setting
for
underfrequency
protection
Rate
of
frequency
change
for
blocking
underfrequency protection
Frequency setting for stage 1 of underfrequency
protection
PCS-902 Line Distance Relay
50.000~65.000 (Hz)
50.000~65.000 (Hz)
50.000~65.000 (Hz)
50.000~65.000 (Hz)
45.000~60.000 (Hz)
0.200~20.000 (Hz/s)
45.000~60.000 (Hz)
7-49
Date: 2019-03-01
-09-07
7 Settings
17
81U.UF1.t_Op
Time delay for stage 1 of underfrequency protection
0.000~30.000 (s)
18
81U.UF1.En
Enable stage 1 of underfrequency protection
0 or 1
19
81U.UF1.En_df/dt_Blk
20
81U.UF2.f_Set
21
81U.UF2.t_Op
Time delay for stage 2 of underfrequency protection
0.000~30.000 (s)
22
81U.UF2.En
Enable stage 2 of underfrequency protection
0 or 1
23
81U.UF2.En_df/dt_Blk
24
81U.UF3.f_Set
25
81U.UF3.t_Op
Time delay for stage 3 of underfrequency protection
0.000~30.000 (s)
26
81U.UF3.En
Enable stage 3 of underfrequency protection
0 or 1
27
81U.UF3.En_df/dt_Blk
28
81U.UF4.f_Set
29
81U.UF4.t_Op
Time delay for stage 4 of underfrequency protection
0.000~30.000 (s)
30
81U.UF4.En
Enable stage 4 of underfrequency protection
0 or 1
31
81U.UF4.En_df/dt_Blk
Enable rate of frequency change to block stage 1 of
underfrequency protection
Frequency setting for stage 2 of underfrequency
protection
Enable rate of frequency change to block stage 2 of
underfrequency protection
Frequency setting for stage 3 of underfrequency
protection
Enable rate of frequency change to block stage 3 of
underfrequency protection
Frequency setting for stage 4 of underfrequency
protection
Enable rate of frequency change to block stage 4 of
underfrequency protection
0 or 1
45.000~60.000 (Hz)
0 or 1
45.000~60.000 (Hz)
0 or 1
45.000~60.000 (Hz)
0 or 1
7.3.1.27 Breaker Failure Protection Settings (50BF)
NOTICE!
PCS-902 can be configured to support single circuit breaker application or double
circuit breakers application by PCS-Explorer. The prefix “CBx.” is added to all settings
for circuit breaker No.x (x=1 or 2).
No.
Item
Remark
Range
1
CBx.50BF.I_Set
Current setting of phase current criterion for BFP
2
CBx.50BF.3I0_Set
Current setting of zero-sequence current criterion
(0.050~30.000 )×In (A)
for BFP
3
CBx.50BF.I2_Set
Current setting of negative-sequence current
(0.050~30.000 )×In (A)
criterion for BFP
4
CBx.50BF.t_ReTrp
Time delay of re-tripping for BFP
0.000~10.000 (s)
5
CBx.50BF.t1_Op
Time delay of stage 1 for BFP
0.000~10.000 (s)
6
CBx.50BF.t2_Op
Time delay of stage 2 for BFP
0.000~10.000 (s)
7
CBx.50BF.En
Enable breaker failure protection
0 or 1
8
CBx.50BF.En_ReTrp
Enable re-trip function for BFP
0 or 1
9
CBx.50BF.En_3I0_1P
Enable zero-sequence current criterion for BFP
0 or 1
initiated by single-phase tripping contact
7-50
(0.050~30.000 )×In (A)
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
10
CBx.50BF.En_3I0_3P
11
CBx.50BF.En_I2_3P
12
CBx.50BF.En_CB_Ctrl
Enable zero-sequence current criterion for BFP
0 or 1
initiated by three-phase tripping contact
Enable negative-sequence current criterion for BFP
0 or 1
initiated by three-phase tripping contact
Enable breaker failure protection can be initiated by
0 or 1
normally closed contact of circuit breaker
7.3.1.28 Thermal Overload Protection Settings (49)
No.
Item
Remark
Range
49-1.K
The factor setting for stage 1 of thermal overload
protection which is associated to the thermal state 1.000~3.000
formula
2
49-2.K
The factor setting for stage 2 of thermal overload
protection which is associated to the thermal state 1.000~3.000
formula
3
49.Ib_Set
4
49.Tau
5
49-1.En_Alm
6
49-1.En_Trp
7
49-2.En_Alm
8
49-2.En_Trp
1
The reference current setting of the thermal
(0.050~30.000 )×In (A)
overload protection
The time constant setting of the IDMT overload
0.100~100.000 (min)
protection
Enable stage 1 of thermal overload protection for
0 or 1
alarm purpose
Enable stage 1 of thermal overload protection for
0 or 1
trip purpose
Enable stage 2 of thermal overload protection for
0 or 1
alarm purpose
Enable stage 2 of thermal overload protection for
0 or 1
trip purpose
7.3.1.29 Stub Differential Protection Settings (87STB)
No.
Name
Remark
Range
1
87STB.I_Pkp
Pickup current setting of stub differential protection
(0.050~30.000)×In (A)
2
87STB.I_ Alm
Current setting of differential current alarm
(0.050~30.000)×In (A)
3
87STB.Slope
Slope of current differential protection
0.5~1
4
87STB.t_Op
Time delay of stub differential protection
0.000~10.000 (s)
5
87STB.En
Enable stub differential protection
0 or 1
6
87STB.En_Alm
Enable differential current alarm function
0 or 1
7
87STB.En_CTS_Blk
Enable stub differential protection controlled by CT
circuit failure
0 or 1
7.3.1.30 Dead Zone Protection Settings (50DZ)
NOTICE!
PCS-902 can be configured to support single circuit breaker application or double
circuit breakers application by PCS-Explorer. The prefix “CBx.” is added to all settings
for circuit breaker No.x (x=1 or 2).
No.
1
Name
CBx.50DZ.I_Set
Remark
Current setting of dead zone protection
PCS-902 Line Distance Relay
Range
(0.050~30.000)×In (A)
7-51
Date: 2019-03-01
-09-07
7 Settings
2
CBx.50DZ.t_Op
Time delay of dead zone protection
0.000~10.000 (s)
3
CBx.50DZ.En
Enable dead zone protection
0 or 1
7.3.1.31 Pole Discrepancy Protection Settings (62PD)
NOTICE!
PCS-902 can be configured to support single circuit breaker application or double
circuit breakers application by PCS-Explorer. The prefix “CBx.” is added to all settings
for circuit breaker No.x (x=1 or 2).
No.
Item
Remark
Range
1
CBx.62PD.3I0_Set
Current setting of residual current criterion for
(0.050~30.000 )×In (A)
pole discrepancy protection
2
CBx.62PD.I2_Set
Current setting of negative-sequence current
(0.050~30.000 )×In (A)
criterion for pole discrepancy protection
3
CBx.62PD.t_Op
Time delay of pole discrepancy protection
0.000~600.000 (s)
4
CBx.62PD.En
Enable pole discrepancy protection
0 or 1
5
CBx.62PD.En_3I0/I2_Ctrl
Enable residual
current criterion and
negative-sequence current criterion for pole 0 or 1
discrepancy protection
7.3.1.32 Broken Conductor Protection Settings (46BC)
No.
Item
Remark
Range
1
46BC.I2/I1_Set
Ratio setting (negative-sequence current to
positive-sequence current) of broken conductor 0.20~1.00
protection
2
46BC.t_Op
Time delay of broken conductor protection
3
46BC.I_Min
Minimum operation current of broken conductor
(0.050~30.000)×In (A)
protection
4
46BC.En_Trp
Enable broken conductor protection to operate to
0 or 1
trip
5
46BC.En_Alm
Enable broken conductor protection to operate to
0 or 1
alarm
0.000~600.000 (s)
7.3.1.33 Reverse Power Protection Settings (32R)
No.
Item
Remark
Range
Power setting of stage 1 of reverse power
1
32R1.P_Set
2
32R1.t_Trp
3
32R1.t_Alm
4
32R1.En_Trp
5
32R1.En_Alm
(0.100~50.000)×In (W)
protection
Time delay of stage 1 of reverse power protection
0.100~3000.000 (s)
for tripping purpose
Time delay of stage 1 of reverse power protection
0.100~3000.000 (s)
for alarm purpose
Enable stage 1 of reverse power protection to
0 or 1
operate to trip
Enable stage 1 of reverse power protection to
operate to alarm
7-52
0 or 1
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
Power setting of stage 2 of reverse power
6
32R2.P_Set
7
32R2.t_Trp
8
32R2.En_Trp
9
32R.Opt_Dir
(0.100~50.000)×In (W)
protection
Time delay of stage 2 of reverse power protection 0.100~3000.000 (s)
Enable stage 2 of reverse power protection to
0 or 1
operate to trip
The
directionality
option
of
protection
reverse
power Forward direction
Reverse direction
7.3.1.34 Synchrocheck Settings (25)
NOTICE!
PCS-902 can be configured to support single circuit breaker application or double
circuit breakers application by PCS-Explorer. The prefix “CBx.” is added to all settings
for circuit breaker No.x (x=1 or 2).
No.
Item
Remark
Range
Ua
Ub
1
CBx.25.Opt_Source_UL1
Voltage selecting mode of line 1.
Uc
Uab
Ubc
Uca
Ua
Ub
2
CBx.25.Opt_Source_UB1 Voltage selecting mode of bus 1.
Uc
Uab
Ubc
Uca
Ua
Ub
3
CBx.25.Opt_Source_UL2
Voltage selecting mode of line 2.
Uc
Uab
Ubc
Uca
Ua
Ub
4
CBx.25.Opt_Source_UB2 Voltage selecting mode of bus 2.
Uc
Uab
Ubc
Uca
PCS-902 Line Distance Relay
7-53
Date: 2019-03-01
-09-07
7 Settings
NoVoltSel
Option of circuit breaker configuration, and it
5
CBx.CBConfigMode
should be set as “NoVoltSel” if no voltage selection
DblBusOneCB
3/2BusCB
is adopted.
3/2TieCB
6
CBx.25.U_Dd
Voltage threshold of dead check
0.05Un~0.8Un (V)
7
CBx.25.U_Lv
Voltage threshold of live check
0.5Un~Un (V)
8
CBx.25.K_Usyn
Compensation coefficient for synchronism voltage 0.20-5.00
9
CBx.25.phi_Diff
Phase difference limit of synchronism check for
AR
Compensation for phase difference between two
0~ 89 (deg)
10
CBx.25.phi_Comp
11
CBx.25.f_Diff
12
CBx.25.U_Diff
13
CBx.25.t_DdChk
14
CBx.25.t_SynChk
15
CBx.25.En_fDiffChk
Enable frequency difference check
0 or 1
16
CBx.25.SetOpt
Synchrocheck mode selection
0, 1
17
CBx.25.En_SynChk
Enable synchronism check
0 or 1
18
CBx.25.En_DdL_DdB
Enable dead line and dead bus (DLDB) check
0 or 1
19
CBx.25.En_DdL_LvB
Enable dead line and live bus (DLLB) check
0 or 1
20
CBx.25.En_LvL_DdB
Enable live line and dead bus (LLDB) check
0 or 1
21
CBx.25.En_NoChk
Enable AR without any check
0 or 1
22
CBx.25.En_3PLvChk
Enable live three-phase check of line
0 or 1
synchronism voltages
Frequency difference limit of synchronism check
for AR
Voltage difference limit of synchronism check for
AR
Time delay to confirm dead check condition
Time
delay
to
confirm
synchronism
0~359 (deg)
0.02~1.00 (Hz)
0.02Un~0.8Un (V)
0.010~25.000 (s)
check
condition
0.010~25.000 (s)
7.3.1.35 Auto-reclosing Settings (79)
NOTICE!
PCS-902 can be configured to support single circuit breaker application or double
circuit breakers application by PCS-Explorer. The prefix “CBx.” is added to all settings
for circuit breaker No.x (x=1 or 2).
No.
Item
Remark
Range
1
CBx.79.N_Rcls
Maximum number of reclosing attempts
1~4
2
CBx.79.t_Dd_1PS1
Dead time of first shot 1-pole reclosing
0.000~600.000 (s)
3
CBx.79.t_Dd_3PS1
Dead time of first shot 3-pole reclosing
0.000~600.000 (s)
4
CBx.79.t_Dd_3PS2
Dead time of second shot 3-pole reclosing
0.000~600.000 (s)
5
CBx.79.t_Dd_3PS3
Dead time of third shot 3-pole reclosing
0.000~600.000 (s)
6
CBx.79.t_Dd_3PS4
Dead time of fourth shot 3-pole reclosing
0.000~600.000 (s)
7-54
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
7
CBx.79.t_CBClsd
Time delay of circuit breaker in closed position
before reclosing
0.000~600.000 (s)
Time delay to wait for CB healthy, and begin to
8
CBx.79.t_CBReady
timing when the input signal [79.CB_Healthy] is
de-energized and if it is not energized within this
0.000~600.000 (s)
time delay, AR will be blocked.
9
CBx.79.t_Wait_Chk
Maximum wait time for synchronism check
Time delay allow for CB status change to conform
0.000~600.000 (s)
10
CBx.79.t_Fail
11
CBx.79.t_PW_AR
Pulse width of AR closing signal
0.000~600.000 (s)
12
CBx.79.t_Reclaim
Reclaim time of AR
0.000~600.000 (s)
13
CBx.79.t_PersistTrp
reclosing successful
Time delay of excessive trip signal to block
auto-reclosing
0.000~600.000 (s)
0.000~600.000 (s)
Drop-off time delay of blocking AR, when blocking
14
CBx.79.t_DDO_BlkAR
signal for AR disappears, AR blocking condition 0.000~600.000 (s)
drops off after this time delay
15
CBx.79.t_AddDly
16
CBx.79.t_WaitMaster
Additional time delay for auto-reclosing
Maximum wait time for reclosing permissive signal
from master AR
0.000~600.000 (s)
0.000~600.000 (s)
Time delay of discriminating another fault, and begin
to times after 1-pole AR initiated, 3-pole AR will be
17
CBx.79.t_SecFault
initiated if another fault happens during this time 0.000~600.000 (s)
delay. AR will be blocked if another fault happens
after that.
Enable auto-reclosing blocked when a fault occurs
18
CBx.79.En_PDF_Blk
19
CBx.79.En_AddDly
20
CBx.79.En_CutPulse
21
CBx.79.En_FailCheck
22
CBx.79.En
23
CBx.79.En_ExtCtrl
24
CBx.79.En_CBInit
25
CBx.79.Opt_Priority
Option of AR priority
None, High or Low
26
CBx.79.SetOpt
Control option of AR mode
0 or 1
27
CBx.79.En_1PAR
Enable 1-pole AR mode
0 or 1
28
CBx.79.En_3PAR
Enable 3-pole AR mode
0 or 1
29
CBx.79.En_1P/3PAR
Enable 1/3-pole AR mode
0 or 1
under pole disagreement condition
Enable auto-reclosing with an additional dead time
delay
Enable adjust the length of reclosing pulse
Enable confirm whether AR is successful by
checking CB state
Enable auto-reclosing
Enable AR by external input signal besides logic
setting [79.En]
Enable AR be initiated by open state of circuit
breaker
PCS-902 Line Distance Relay
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
7-55
Date: 2019-03-01
-09-07
7 Settings
7.3.1.36 Transfer Trip Settings (TT)
No.
Item
Remark
Range
1
TT.t_Op
Time delay of transfer trip
0.000~600.000 (s)
2
TT.En_FD_Ctrl
Enable transfer trip controlled by local fault detector
0 or 1
3
TT.En_BlkAR
Enable transfer trip operate to block AR
0 or 1
7.3.1.37 Tripping Logic Settings
NOTICE!
PCS-902 can be configured to support single circuit breaker application or double
circuit breakers application by PCS-Explorer. The prefix “CBx.” is added to all settings
for circuit breaker No.x (x=1 or 2).
No.
Item
1
En_MPF_Blk_AR
2
En_3PF_Blk_AR
3
En_PhSF_Blk_AR
4
t_Dwell_Trp
5
CBx.En_Trp3P
Remark
Range
Enable auto-reclosing blocked when multi-phase fault
happens
Enable auto-reclosing blocked when three-phase fault
happens
Enable auto-reclosing blocked when selection of faulty
phase fails
The dwell time of tripping command, empirical value is
0.04
Enable three-phase tripping mode for any fault
conditions
0 or 1
0 or 1
0 or 1
0.000~10.000 (s)
0 or 1
7.3.1.38 VT Circuit Supervision Settings (VTS)
No.
Item
Remark
Range
1
VTS.3U0_Set
Zero-sequence voltage setting of VT circuit supervison
2
VTS.U1_Set
3
VTNS.3U0_Hm3_Set
4
VTS.t_DPU
Pickup time delay of VT circuit supervision
0.200~100.000 (s)
5
VTS.t_DDO
Dropoff time delay of VT circuit supervision
0.200~100.000 (S)
6
VTS.En_Out_VT
VT is not connected to the protection device
0 or 1
Positive-sequence
voltage
setting
of
VT
circuit
supervison
Third harmonic setting of zero-sequence voltage of VT
circuit supervision
0.000~220.000 (V)
22.000~110.000 (V)
0.000~220.000 (V)
If three-phase voltage used for protection measurement
7
VTS.En_LineVT
comes from line side (for example, 3/2 breaker), it
should be set as “1”. If three-phase voltage comes from
0 or 1
busbar side, it should be set as “0”.
8
VTS.En
Enable alarm function of VT circuit supervision
0 or 1
7.3.2 Access Path
MainMenu“Settings”“Prot Settings”
7-56
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
7.4 Logic Link Settings
The logic link settings are used to determine whether the relevant function of this device is
enabled or disabled. If this device supports the logic link function, it will have a corresponding
submenu in the submenu “Logic Links” for the logic link settings.
Each logic link settings is an “AND” condition of enabling the relevant function with the
corresponding binary input and logic setting. Through SAS or RTU, logic link settings can be set
as “1” or “0”; and it means that the relevant function can be in service or out of service through
remote command. It provides convenience for operation management.
7.4.1 Setting Description
7.4.1.1 Function Link Settings
The function link settings can be defined according to project specification through the
configuration tool, PCS-Explorer.
No.
Item
Remark
Range
1
Link_01
Function link setting 01
0 or 1
2
Link_02
Function link setting 02
0 or 1
3
Link_03
Function link setting 03
0 or 1
4
Link_04
Function link setting 04
0 or 1
5
Link_05
Function link setting 05
0 or 1
6
Link_06
Function link setting 06
0 or 1
7
Link_07
Function link setting 07
0 or 1
8
Link_08
Function link setting 08
0 or 1
7.4.2 Access Path
MainMenu“Settings”“Logic Links”
7.5 Control and Synchrocheck for Manual Closing Settings
NOTICE!
PCS-902 can be configured to support single circuit breaker application or double
circuit breakers application by PCS-Explorer. The prefix “CBx.” is added to all settings
for circuit breaker No.x (x=1 or 2).
7.5.1 Setting Description
7.5.1.1 Function Settings
No.
1
Item
MCBrd.CBx.En_Alm_VTS
Remark
Enable alarm function when VT circuit is
abnormal
PCS-902 Line Distance Relay
Range
0 or 1
7-57
Date: 2019-03-01
-09-07
7 Settings
7.5.1.2 Synchronism Settings
No.
Item
Remark
Range
Ua
Ub
1
MCBrd.CBx.25.Opt_Source_UL1
Uc
Voltage selecting mode for line 1
Uab
Ubc
Uca
Ua
Ub
2
MCBrd.CBx.25.Opt_Source_UB1
Uc
Voltage selecting mode for bus 1
Uab
Ubc
Uca
Ua
Ub
3
MCBrd.CBx.25.Opt_Source_UL2
Uc
Voltage selecting mode for line 2
Uab
Ubc
Uca
Ua
Ub
4
MCBrd.CBx.25.Opt_Source_UB2
Uc
Voltage selecting mode for bus 2
Uab
Ubc
Uca
5
MCBrd.CBx.25.U_Dd
Voltage threshold of dead check
1.000~100.000 (V)
6
MCBrd.CBx.25.U_Lv
Voltage threshold of live check
1.000~100.000 (V)
7
MCBrd.CBx.25.K_Usyn
8
MCBrd.CBx.25.phi_Diff
9
MCBrd.CBx.25.phi_Comp
10
MCBrd.CBx.25.f_Diff
11
MCBrd.CBx.25.U_Diff
12
MCBrd.CBx.25.SetOpt
13
MCBrd.CBx.25.En_SynChk
14
MCBrd.CBx.25.En_DdL_DdB
Compensation
coefficient
for
synchronism voltage
Phase difference limit of synchronism
check for manual closing
Compensation
for
phase
difference
between two synchronous voltages
Frequency
difference
limit
of
synchronism check for manual closing
Voltage difference limit of synchronism
check for manual closing
Synchrocheck mode selection for manual
closing
Enable synchronism check
7-58
0.10~ 180.00 (deg)
0~360 (deg)
0.00~3.00 (Hz)
1.000~100.000 (V)
0, 1
0 or 1
Enable dead line and dead bus (DLDB)
check
0.20-5.00
0 or 1
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
15
MCBrd.CBx.25.En_DdL_LvB
16
MCBrd.CBx.25.En_LvL_DdB
17
MCBrd.CBx.25.En_NoChk
Enable dead line and live bus (DLLB)
check
Enable live line and dead bus (LLDB)
check
0 or 1
0 or 1
Enable manual closing without any check 0 or 1
Threshold of rate of frequency change
18
MCBrd.CBx.25.df/dt
between
both
sides
of
CB
for 0.10~5.00 (Hz/s)
synchronism-check.
19
MCBrd.CBx.25.En_df/dtChk
Enable frequency slip check for manual
closing
0 or 1
Circuit breaker closing time. It is the time
20
MCBrd.CBx.25.t_Close_CB
from receiving closing command pulse till 0~1000 (ms)
the CB is completely closed.
From receiving a closing command, this
device will continuously check whether
between incoming voltage and reference
voltage involved in synchronism check
21
MCBrd.CBx.25.t_Wait_Chk
(or dead check) can meet the criteria. If
the synchronism check (or dead check)
5.000~30.000 (s)
criteria are not met within the duration of
this
time
delay,
the
failure
of
synchronism-check (or dead check) will
be confirmed.
Enable block synchronism check for
22
MCBrd.CBx.25.En_VTS_Blk_SynChk
manual closing when VT circuit is 0 or 1
abnormal
23
MCBrd.CBx.25.En_VTS_Blk_DdChk
Enable block dead check for manual
closing when VT circuit is abnormal
0 or 1
7.5.1.3 Dual Point Binary Input Settings
These settings are applied to configure the status change confirmation time for No.xx double point
binary inputs. Up to 15 virtual double point binary inputs are provided in this device.
If a double point binary input changes from normal status to invalid status, i.e.: double point error
occurs, [CSWIxx.t_DPU_DPS] will be applied as the debouncing time for No.xx double point
binary input. (xx=01, 02….15)
No.
Name
1
CSWI01.t_DPU_DPS
2
CSWI02.t_DPU_DPS
3
CSWI03.t_DPU_DPS
Remark
It is applied to configure the debouncing time for
dual-point binary input No.01.
It is applied to configure the debouncing time for
dual-point binary input No.02.
It is applied to configure the debouncing time for
dual-point binary input No.03.
PCS-902 Line Distance Relay
Range
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
7-59
Date: 2019-03-01
-09-07
7 Settings
No.
Name
4
CSWI04.t_DPU_DPS
5
CSWI05.t_DPU_DPS
6
CSWI06.t_DPU_DPS
7
CSWI07.t_DPU_DPS
8
CSWI08.t_DPU_DPS
9
CSWI09.t_DPU_DPS
10
CSWI10.t_DPU_DPS
11
CSWI11.t_DPU_DPS
12
CSWI12.t_DPU_DPS
13
CSWI13.t_DPU_DPS
14
CSWI14.t_DPU_DPS
15
CSWI15.t_DPU_DPS
Remark
Range
It is applied to configure the debouncing time for
dual-point binary input No.04.
It is applied to configure the debouncing time for
dual-point binary input No.05.
It is applied to configure the debouncing time for
dual-point binary input No.06.
It is applied to configure the debouncing time for
dual-point binary input No.07.
It is applied to configure the debouncing time for
dual-point binary input No.08.
It is applied to configure the debouncing time for
dual-point binary input No.09.
It is applied to configure the debouncing time for
dual-point binary input No.10.
It is applied to configure the debouncing time for
dual-point binary input No.11.
It is applied to configure the debouncing time for
dual-point binary input No.12.
It is applied to configure the debouncing time for
dual-point binary input No.13.
It is applied to configure the debouncing time for
dual-point binary input No.14.
It is applied to configure the debouncing time for
dual-point binary input No.15.
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
7.5.1.4 Control Settings
No.
Name
1
CSWI01.t_PW_Opn
2
CSWI01.t_PW_Cls
3
CSWI02.t_PW_Opn
4
CSWI02.t_PW_Cls
5
CSWI03.t_PW_Opn
6
CSWI03.t_PW_Cls
Remark
Range
It is applied to configure the holding time to open CB or
disconnector for binary output No.01.
It is applied to configure the holding time to close CB or
disconnector for binary output No.01.
It is applied to configure the holding time to open CB or
disconnector for binary output No.02.
It is applied to configure the holding time to close CB or
disconnector for binary output No.02.
It is applied to configure the holding time to open CB or
disconnector for binary output No.03.
It is applied to configure the holding time to close CB or
disconnector for binary output No.03.
7-60
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
No.
Name
7
CSWI04.t_PW_Opn
8
CSWI04.t_PW_Cls
9
CSWI05.t_PW_Opn
10
CSWI05.t_PW_Cls
11
CSWI06.t_PW_Opn
12
CSWI06.t_PW_Cls
13
CSWI07.t_PW_Opn
14
CSWI07.t_PW_Cls
15
CSWI08.t_PW_Opn
16
CSWI08.t_PW_Cls
17
CSWI09.t_PW_Opn
18
CSWI09.t_PW_Cls
19
CSWI10.t_PW_Opn
20
CSWI10.t_PW_Cls
21
CSWI11.t_PW_Opn
22
CSWI11.t_PW_Cls
23
CSWI12.t_PW_Opn
24
CSWI12.t_PW_Cls
25
CSWI13.t_PW_Opn
26
CSWI13.t_PW_Cls
Remark
It is applied to configure the holding time to open CB or
disconnector for binary output No.04.
It is applied to configure the holding time to close CB or
disconnector for binary output No.04.
It is applied to configure the holding time to open CB or
disconnector for binary output No.05.
It is applied to configure the holding time to close CB or
disconnector for binary output No.05.
It is applied to configure the holding time to open CB or
disconnector for binary output No.06.
It is applied to configure the holding time to close CB or
disconnector for binary output No.06.
It is applied to configure the holding time to open CB or
disconnector for binary output No.07.
It is applied to configure the holding time to close CB or
disconnector for binary output No.07.
It is applied to configure the holding time to open CB or
disconnector for binary output No.08.
It is applied to configure the holding time to close CB or
disconnector for binary output No.08.
It is applied to configure the holding time to open CB or
disconnector for binary output No.09.
It is applied to configure the holding time to close CB or
disconnector for binary output No.09.
It is applied to configure the holding time to open CB or
disconnector for binary output No.10.
It is applied to configure the holding time of close CB or
disconnector for binary output No.10.
It is applied to configure the holding time to open CB or
disconnector for binary output No.11.
It is applied to configure the holding time to close CB or
disconnector for binary output No.11.
It is applied to configure the holding time to open CB or
disconnector for binary output No.12.
It is applied to configure the holding time to close CB or
disconnector for binary output No.12.
It is applied to configure the holding time to open CB or
disconnector for binary output No.13.
It is applied to configure the holding time to close CB or
PCS-902 Line Distance Relay
Range
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
7-61
Date: 2019-03-01
-09-07
7 Settings
No.
Name
Remark
Range
disconnector for binary output No.13.
27
CSWI14.t_PW_Opn
28
CSWI14.t_PW_Cls
29
CSWI15.t_PW_Opn
30
CSWI15.t_PW_Cls
It is applied to configure the holding time to open CB or
disconnector for binary output No.14.
It is applied to configure the holding time to close CB or
disconnector for binary output No.14.
It is applied to configure the holding time to open CB or
disconnector for binary output No.15.
It is applied to configure the holding time to close CB or
disconnector for binary output No.15.
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
0~60000 (ms)
7.5.1.5 Interlock Settings
No.
Name
1
CSWI01.En_Opn_Blk
2
CSWI01.En_Cls_Blk
3
CSWI02.En_Opn_Blk
4
CSWI02.En_Cls_Blk
5
CSWI03.En_Opn_Blk
6
CSWI03.En_Cls_Blk
7
CSWI04.En_Opn_Blk
8
CSWI04.En_Cls_Blk
9
CSWI05.En_Opn_Blk
10
CSWI05.En_Cls_Blk
11
CSWI06.En_Opn_Blk
12
CSWI06.En_Cls_Blk
13
CSWI07.En_Opn_Blk
14
CSWI07.En_Cls_Blk
Remark
Range
Enable open output of binary output No.01 controlled by
the interlocking logic
Enable closing output of binary output No.01 controlled by
the interlocking logic
Enable open output of binary output No.02 controlled by
the interlocking logic
Enable closing output of binary output No.02 controlled by
the interlocking logic
Enable open output of binary output No.03 controlled by
the interlocking logic
Enable closing output of binary output No.03 controlled by
the interlocking logic
Enable open output of binary output No.04 controlled by
the interlocking logic
Enable closing output of binary output No.04 controlled by
the interlocking logic
Enable open output of binary output No.05 controlled by
the interlocking logic
Enable closing output of binary output No.05 controlled by
the interlocking logic
Enable open output of binary output No.06 controlled by
the interlocking logic
Enable closing output of binary output No.06 controlled by
the interlocking logic
Enable open output of binary output No.07 controlled by
the interlocking logic
Enable closing output of binary output No.07 controlled by
7-62
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
7 Settings
No.
Name
Remark
Range
the interlocking logic
15
CSWI08.En_Opn_Blk
16
CSWI08.En_Cls_Blk
17
CSWI09.En_Opn_Blk
18
CSWI09.En_Cls_Blk
19
CSWI10.En_Opn_Blk
20
CSWI10.En_Cls_Blk
21
CSWI11.En_Opn_Blk
22
CSWI11.En_Cls_Blk
23
CSWI12.En_Opn_Blk
24
CSWI12.En_Cls_Blk
25
CSWI13.En_Opn_Blk
26
CSWI13.En_Cls_Blk
27
CSWI14.En_Opn_Blk
28
CSWI14.En_Cls_Blk
29
CSWI15.En_Opn_Blk
30
CSWI15.En_Cls_Blk
Enable open output of binary output No.08 controlled by
the interlocking logic
Enable closing output of binary output No.08 controlled by
the interlocking logic
Enable open output of binary output No.09 controlled by
the interlocking logic
Enable closing output of binary output No.09 controlled by
the interlocking logic
Enable open output of binary output No.10 controlled by
the interlocking logic
Enable closing output of binary output No.10 controlled by
the interlocking logic
Enable open output of binary output No.11 controlled by
the interlocking logic
Enable closing output of binary output No.11 controlled by
the interlocking logic
Enable open output of binary output No.12 controlled by
the interlocking logic
Enable closing output of binary output No.12 controlled by
the interlocking logic
Enable open output of binary output No.13 controlled by
the interlocking logic
Enable closing output of binary output No.13 controlled by
the interlocking logic
Enable open output of binary output No.14 controlled by
the interlocking logic
Enable closing output of binary output No.14 controlled by
the interlocking logic
Enable open output of binary output No.15 controlled by
the interlocking logic
Enable closing output of binary output No.15 controlled by
the interlocking logic
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
7.5.2 Access Path
MainMenu“Settings”“BCU Settings”
PCS-902 Line Distance Relay
7-63
Date: 2019-03-01
-09-07
7 Settings
7-64
PCS-902 Line Distance Relay
Date: 2019-03-01
-11-23
8 Human Machine Interface
8 Human Machine Interface
Table of Contents
8 Human Machine Interface ................................................................ 8-a
8.1 Overview .......................................................................................................... 8-1
8.1.1 Keypad Operation ................................................................................................................ 8-2
8.1.2 LED Indications .................................................................................................................... 8-3
8.1.3 Front Communication Port ................................................................................................... 8-4
8.1.4 Ethernet Port Setup ............................................................................................................. 8-4
8.2 Menu Tree ........................................................................................................ 8-5
8.2.1 Overview .............................................................................................................................. 8-5
8.2.2 Main Menus ......................................................................................................................... 8-6
8.2.3 Sub Menus ........................................................................................................................... 8-7
8.3 Access Authority Management .................................................................... 8-27
8.3.1 Authority Classification ...................................................................................................... 8-28
8.3.2 Authority Identification........................................................................................................ 8-29
8.4 LCD Display ................................................................................................... 8-30
8.4.1 Overview ............................................................................................................................ 8-30
8.4.2 Function Shortcuts Key...................................................................................................... 8-31
8.4.3 Normal Display .................................................................................................................. 8-34
8.4.4 Display Disturbance Records ............................................................................................ 8-35
8.4.5 Display Supervision Event ................................................................................................. 8-37
8.4.6 Display IO Events .............................................................................................................. 8-38
8.4.7 Display Device Logs .......................................................................................................... 8-38
8.5 Keypad Operation ......................................................................................... 8-39
8.5.1 View Device Measurements .............................................................................................. 8-39
8.5.2 View Device Status ............................................................................................................ 8-40
8.5.3 View Device Records......................................................................................................... 8-40
PCS-902 Line Distance Relay
8-a
Date: 2019-03-01
8 Human Machine Interface
8.5.4 Print Device Records ......................................................................................................... 8-40
8.5.5 View Device Setting ........................................................................................................... 8-41
8.5.6 Modify Device Setting ........................................................................................................ 8-42
8.5.7 Copy Device Setting .......................................................................................................... 8-45
8.5.8 Switch Setting Group ......................................................................................................... 8-45
8.5.9 Delete Device Records ...................................................................................................... 8-46
8.5.10 Remote Control via Menu ................................................................................................ 8-47
8.5.11 Remote Control via SLD .................................................................................................. 8-50
8.5.12 Control with Open/Close Buttons (if Available) ............................................................... 8-53
8.5.13 Modify Device Clock ........................................................................................................ 8-55
8.5.14 View Module Information ................................................................................................. 8-56
8.5.15 Check Software Version .................................................................................................. 8-56
8.5.16 Communication Test ........................................................................................................ 8-57
8.5.17 Select Language .............................................................................................................. 8-57
List of Figures
Figure 8.1-1 Front panel .............................................................................................................. 8-1
Figure 8.1-2 Keypad buttons ...................................................................................................... 8-2
Figure 8.1-3 LED indications ...................................................................................................... 8-3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel .................................. 8-4
Figure 8.1-5 Rear view and terminal definition of NR1102D ................................................... 8-5
Figure 8.2-1 Menu tree ................................................................................................................ 8-7
List of Tables
Table 8.1-1 Definition of the 8-core cable ................................................................................. 8-4
Table 8.4-1 Tripping report messages ..................................................................................... 8-37
Table 8.4-2 User operating event list ....................................................................................... 8-39
Table 8.5-1 Primary equipment symbols in SLD .................................................................... 8-50
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8 Human Machine Interface
The operator can access the protective device from the front panel. Local communication with the
protective device is possible using a computer via a multiplex RJ45 port on the front panel.
Furthermore, remote communication is also possible using a PC with the substation automation
system via rear RS485 port or rear Ethernet port. The operator is able to check the protective
device status at any time.
This chapter describes human machine interface (HMI), and give operator an instruction about
how to display or print event report, setting and so on through HMI menu tree and display metering
value, including r.m.s. current, voltage and frequency etc. through LCD. Procedures to change
active setting group or a settable parameter value through keypad is also described in details.
NOTICE!
About the measurements and metering in menu “Measurements”, please refer to the
following description:
“Measurements1” is used to display measured values from protection calculation DSP.
The measurement values can be displayed in primary value or secondary value by the
setting [Opt_Display_Status].
“Measurements2” is used to display measured values from fault detector DSP. The
measurement values can be displayed in primary value or secondary value by the
setting [Opt_Display_Status].
“Measurements3” is used to display measured values of other calculated quantities
related to the measurement and control. The measurement values are always
displayed in primary value.
“Metering” is used to display metering values of active and reactive energy. The
metering values are always displayed in primary value.
8.1 Overview
The human-machine interface consists of a human-machine interface (HMI) module which allows
a communication to be as simple as possible for the user.
HEALTHY
11
13
4
14
5
15
6
16
7
17
8
18
9
19
10
20
GRP
3
PCS-902
5
12
ALARM
ESC
1
2
ENT
1
4
3
2
Figure 8.1-1 Front panel
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8 Human Machine Interface
The HMI module helps to draw your attention to something that has occurred which may activate a
LED or a report displayed on the LCD. Operator can locate the data of interest by navigating the
keypad. The function of HMI module:
No.
Item
Description
A 320×240 dot matrix backlight LCD display is visible in dim lighting
1
LCD
conditions. The corresponding messages are displayed when there is
operation implemented.
20 status indication LEDs, 2 LEDs are fixed as the signals of “HEALTHY”
2
LED
(green) and “ALARM” (yellow), 18 LEDs are configurable with selectable
color among green, yellow and red.
3
Keypad
Navigation keypad and command keys for full access to device
4
Communication port
a multiplex RJ45 port for local communication with a PC
5
Logo
Type and designation and manufacturer of device
GR
P
8.1.1 Keypad Operation
ENT
ESC
Figure 8.1-2 Keypad buttons
1.
2.
3.
“ESC”:

Cancel the operation

Quit the current menu
“ENT”:

Execute the operation

Confirm the interface
“GRP”

4.
5.
Activate the switching interface of setting group
leftward and rightward direction keys (“◄” and “►”):

Move the cursor horizontally

Enter the next menu or return to the previous menu
upward and downward direction keys (“▲” and “▼”)

Move the cursor vertically

Select command menu within the same level of menu
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8 Human Machine Interface
6.
plus and minus sign keys (“＋” and “－”)

Modify the value

Modify and display the message number

Page up/down
8.1.2 LED Indications
HEALTHY
ALARM
Figure 8.1-3 LED indications
A brief explanation has been made as bellow.
LED
Display
Off
HEALTHY
Steady Green
Off
Description
When the equipment is out of service or any hardware error is defected during
self-check.
Lit when the equipment is in service and ready for operation.
When equipment in normal operating condition.
ALARM
Steady Yellow
Lit when VT circuit failure, CT circuit failure or other abnormal alarm is issued.
NOTICE!
“HEALTHY” LED can only be turned on by energizing the device and no abnormality
detected.
“ALARM” LED is turned on when abnormalities of device occurs like above mentioned
and can be turned off after abnormalities are removed except alarm report [CTS.Alm]
which can only be reset only when the failure is removed and the device is rebooted or
re-energized.
Other LED indicators with no labels are configurable and user can configure them to be
lit by signals of operation element, alarm element and binary output contact according
to requirement through PCS-Explorer software, but as drawn in figure, 2 LEDs are fixed
as the signals of “HEALTHY” (green) and “ALARM” (yellow), 18 LEDs are configurable
with selectable color among green, yellow and red.
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8 Human Machine Interface
8.1.3 Front Communication Port
There is a multiplex RJ45 port on the front panel. This port can be used as an RS-232 serial port
as well as a twisted-pair ethernet port. As shown in the following figure, a customized cable is
applied for debugging via this multiplex RJ45 port.
P2
P1
P3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel
In the above figure and the following table:
P1: To connect the multiplex RJ45 port. An 8-core cable is applied here.
P2: To connect the twisted-pair ethernet port of the computer.
P3: To connect the RS-232 serial port of the computer.
The definition of the 8-core cable in the above figure is introduced in the following table.
Table 8.1-1 Definition of the 8-core cable
Terminal
No.
Core color
Function
Device side
Computer side
(Left)
(Right)
1
Orange & white
TX+ of the ethernet port
P1-1
P2-1
2
Orange
TX- of the ethernet port
P1-2
P2-2
3
Green & white
RX+ of the ethernet port
P1-3
P2-3
4
Blue
TXD of the RS-232 serial port
P1-4
P3-2
5
Brown & white
RXD of the RS-232 serial port
P1-5
P3-3
6
Green
RX- for the ethernet port
P1-6
P2-6
7
Blue & white
8
Brown
The ground connection of the RS-232 port.
P1-7
P1-8
P3-5
8.1.4 Ethernet Port Setup
MON plug-in module is equipped with two or four 100Base-TX Ethernet interface, take NR1102D
as an example, as shown in Figure 8.1-5. Its rear view and the definition of terminals.
The Ethernet port can be used to communication with PC via auxiliary software (PCS-Explorer)
after connecting the protection device with PC, so as to fulfill on-line function (please refer to the
instruction manual of PCS-Explorer). At first, the connection between the protection device and PC
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8 Human Machine Interface
must be established. Through setting the IP address and subnet mask of corresponding Ethernet
interface in the menu “Settings→Device Setup→Comm Settings”, it should be ensured that the
protection device and PC are in the same network segment. For example, setting the IP address
and subnet mask of network A. (using network A to connect with PC)
PC: IP address is set as “198.87.96.102”, subnet mask is set as “255.255.255.0”
The IP address and subnet mask of protection device should be [IP_LAN1]= 198.87.96.XXX,
[Mask_LAN1]=255.255.255.0, [En_LAN1]=1. (XXX can be any value from 0 to 255 except 102)
If the logic setting [En_LAN1] is non-available, it means that network A is always enabled.
NR1102D
ETHERNET
Network A
Network B
Network C
Network D
Figure 8.1-5 Rear view and terminal definition of NR1102D
NOTICE!
If using other Ethernet port, for example, Ethernet B, the logic setting [En_LAN2] must
be set as “1”.
8.2 Menu Tree
8.2.1 Overview
Press “▲” of any running interface and enter the main menu. Select different submenu by “▲” and
“▼”. Enter the selected submenu by pressing “ENT” or “►”. Press “◄” and return to the previous
menu. Press “ESC” back to main menu directly. For sake of entering the command menu again, a
command menu will be recorded in the quick menu after its execution. Five latest command
menus can be recorded in the quick menu. When five command menus are recorded, the latest
command menu will cover the earliest one, adopting the “first in first out” principle. It is arranged
from top to bottom and in accordance with the execution order of command menus.
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8 Human Machine Interface
Press “▲” to enter the main menu with the interface as shown in the following diagram:
MainMenu
Language
Clock
Quick Menu
For the first powered device, there is no record in quick menu. Press “▲” to enter the main menu
with the interface as shown in the following diagram:
Measurements
Status
Records
Settings
Print
Local Cmd
Information
Test
Clock
Language
The descriptions about menu are based on the maximized configuration, for a specific project, if
some function is not available, the corresponding submenu will hidden.
8.2.2 Main Menus
The menu of PCS-902 is organized into main menu and submenus, much like a PC directory
structure. The menu of PCS-902 is divided into 10 sections:
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8 Human Machine Interface
Main Menu
Measurements
Status
Records
Settings
Print
Local Cmd
Information
Test
Clock
Language
Figure 8.2-1 Menu tree
Under main interface, press “▲” to enter main menu, and select submenu by pressing “▲”, “▼”
and “ENT”. The command menu adopts a tree shaped content structure. The above diagram
provides the integral structure and all main menus (first-level menus) under menu tree of the
device.
8.2.3 Sub Menus
8.2.3.1 Measurements
Main Menu
Measurements
Measurements1
Measurements2
Measurements3
Metering
This menu is used to display real-time measured values, including AC voltage, AC current, phase
angle and calculated quantities. These data can help users to acquaint the device′s status. This
menu comprises following submenus. Please refer to section “Measurement” about the detailed
measured values.
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8 Human Machine Interface
No.
Item
Function description
1
Measurements1
Display measured values from protection calculation DSP
2
Measurements2
Display measured values from fault detector DSP
3
Measurements3
4
Metering
Display measured values of other calculated quantities related to the
measurement and control
Display metering values of active and reactive energy
8.2.3.2 Status
Main Menu
Status
Inputs
Outputs
Superv State
Running Status
This menu is used to display real time input signals, output signals, alarm signals and running
status of the device. These data can help users to acquaint the device′s status. This menu
comprises following submenus. Please respectively refer to section “Signal List” about the detailed
introduction of input signals and output signals, and section “Supervision Alarms” about the
detailed introduction of alarm signals.
No.
Item
Function description
1
Inputs
Display all input signal states
2
Outputs
Display all output signal states
3
Superv State
Display supervision alarm states
4
Running Status
Display running status
The submenu “Inputs” comprises the following command menus.
Main Menu
Status
Inputs
Contact Inputs
GOOSE Inputs
Prot Ch Inputs
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No.
Item
Function description
1
Contact Inputs
Display states of binary inputs derived from opto-isolated channels
2
GOOSE Inputs
Display states of GOOSE binary inputs.
3
Prot Ch Inputs
Display states of binary inputs received from protection channel.
The submenu “Outputs” comprises the following command menus.
Main Menu
Status
Outputs
Contact Outputs
GOOSE Outputs
Interlock Status
Prot Ch Outputs
No.
Item
Function description
1
Contact Outputs
Display states of contact binary outputs
2
GOOSE Outputs
Display states of GOOSE binary outputs
3
Interlock Status
Display states of interlock result of each remote control.
4
Prot Ch Outputs
Display states of channel outputs
The submenu “Superv State” comprises the following command menus.
Main Menu
Status
Superv State
Prot Superv
FD Superv
GOOSE Superv
SV Superv
BCU Superv
NetPort Superv
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No.
Item
Function description
1
Prot Superv
Display states of self-supervision signals from protection calculation DSP
2
FD Superv
Display states of self-supervision signals from fault detector DSP
3
GOOSE Superv
Display states of GOOSE self-supervision signals
4
SV Superv
Display states of SV self-supervision signals
5
BCU Superv
Display states of measurement and control self-supervision signals
6
NetPort Superv
Display working status (0: abnormal, 1: normal), link status (0:
disconnection, 1: connection) and bonding status of Ethernet ports
The submenu “Running Status” comprises the following command menus.
Main Menu
Status
Running Status
Net Port
No.
Item
Function description
Display working state (0: abnormal, 1: normal) and link state (0:
1
Net Port
disconnection, 1: connection) of Ethernet port 1, 2, 3, 4 and bonding
ports
8.2.3.3 Records
Main Menu
Records
Disturb Records
Superv Events
IO Events
Device Logs
Control Logs
Clear Records
This menu is used to display all kinds of records, including the disturbance records, supervision
events, binary events and device logs, so that the operator can load to view and use as the
reference of analyzing accidents and repairing the device. All records are stored in non-volatile
memory, it can still record them even if it loses its power.
This menu comprises the following submenus.
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8 Human Machine Interface
No.
Item
Function description
1
Disturb Records
Display disturbance records of the device
2
Superv Events
Display supervision events of the device
3
IO Events
Display binary events of the device
4
Device Logs
Display device logs of the device
5
Control Logs
Display control logs of the device
6
Clear Records
Clear all records.
8.2.3.4 Settings
Main Menu
Settings
System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup
This menu is used to check the device setup, system parameters, protection settings and logic
links settings, as well as modifying any of the above setting items. Moreover, it can also execute
the setting copy between different setting groups.
This menu comprises the following submenus.
No.
Item
Function description
1
System Settings
Check or modify the system parameters
2
Prot Settings
Check or modify the protection settings
3
BCU Settings
Check or modify the measurement and control settings
4
Logic Links
5
Device Setup
Check or modify the logic links settings, including function links, SV links,
GOOSE links and spare links
Check or modify the device setup
The submenu “Prot Settings” includes the following command menus.
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8 Human Machine Interface
Main Menu
Settings
Prot Settings
No.
Line Settings
BFP Settings
FD Settings
Deadzone Settings
AuxE Settings
OV Settings
Direction Settings
UV Settings
Pilot Scheme Settings
NegOV Settings
Rmt CommCh Settings
ThOvld Settings
DPFC Dist Settings
PD Settings
LoadEnch Settings
Stub Settings
Dist Settings
FreqProt Settings
ROC Settings
OOS Settings
NegOC Settings
MiscProt Settings
SOTF Settings
Superv Settings
OC Settings
Trip Logic Settings
VTF OC Settings
CB1 AR/Syn Settings
RevPower Settings
CB2 AR/Syn Settings
BRC Settings
Copy Settings
Item
Function description
1
Line Settings
Check or modify line parameters
2
FD Settings
Check or modify fault detector element settings
3
AuxE Settings
Check or modify auxiliary element settings
4
Direction Settings
Check or modify direction control element settings
5
Pilot Scheme Settings
6
Rmt CommCh Settings
Check or modify optical pilot channel settings
7
DPFC Dist Settings
Check or modify DPFC distance protection settings
8
LoadEnch Settings
Check or modify load encroachment settings
9
Dist Settings
Check or modify distance protection settings
10
ROC Settings
Check or modify directional earth-fault protection settings
11
NegOC Settings
Check or modify negative-sequence overcurrent protection settings
Check or modify pilot distance protection and pilot directional earth-fault
protection settings
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8 Human Machine Interface
12
SOTF Settings
Check or modify SOTF distance and overcurrent protection settings
13
OC Settings
Check or modify phase overcurrent protection settings
14
VTF OC Settings
Check or modify overcurrent protection settings for VT circuit failure
15
RevPower Settings
Check or modify reverse power protection settings
16
BRC Settings
Check or modify broken conductor protection settings
17
BFP Settings
Check or modify breaker failure protection settings
18
Deadzone Settings
Check or modify dead zone settings
19
OV Settings
Check or modify overvoltage protection settings
20
UV Settings
Check or modify undervoltage protection settings
21
NegOV Settings
Check or modify negative-sequence overvoltage protection settings
22
ThOvld Settings
Check or modify thermal overload protection settings
23
PD Settings
Check or modify pole discrepancy protection settings
24
Stub Settings
Check or modify stub overcurrent protection settings
25
FreqProt Settings
Check or modify frequency protection settings
26
OOS Settings
Check or modify out-of-step protection settings
27
MiscProt Settings
Check or modify miscellaneous settings
28
Superv Settings
Check or modify VT circuit supervision and CT circuit supervision settings
29
Trip Logic Settings
Check or modify trippling logic settings
30
CB1 AR/Syn Settings
31
CB2 AR/Syn Settings
32
Copy Settings
Check or modify synchronism check and auto-reclosing settings of circuit
breaker No.1
Check or modify synchronism check and auto-reclosing settings of circuit
breaker No.2
Copy setting between different setting groups
The submenu “BCU Settings” includes the following command menus.
Main Menu
Settings
BCU Settings
FUN Settings
CB1 Syn Settings
CB2 Syn Settings
BI Settings
Control Settings
Interlock Settings
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No.
Item
Function description
1
FUN Settings
Check or modify function settings
2
CB1 Syn Settings
Check or modify manual synchronism check settings for circuit breaker 1
3
CB2 Syn Settings
Check or modify manual synchronism check settings for circuit breaker 2
4
BI Settings
Check or modify binary input settings
5
Control Settings
Check or modify control settings
6
Interlock Settings
Check or modify interlock settings
The submenu “Logic Links” comprises the following command menus.
Main Menu
Settings
Logic Links
Function Links
GOOSE Send Links
GOOSE Recv Links
SV Links
No.
Item
Function description
1
Function Links
Check or modify function links settings
2
GOOSE Send Links
Check or modify GOOSE sending links settings
3
GOOSE Recv Links
Check or modify GOOSE receiving links settings
4
SV Links
Check or modify SV links settings
The submenu “Device Setup” comprises the following command menus.
Main Menu
Settings
Device Setup
Device Settings
Comm Settings
Label Settings
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No.
Item
Function description
1
Device Settings
Check or modify the device settings.
2
Comm Settings
Check or modify the communication settings.
3
Label Settings
Check or modify the label settings of each protection element.
8.2.3.5 Print
Main Menu
Print
Device Info
Settings
Disturb Records
Superv Events
IO Events
Prot Ch Superv
Prot Ch Statistics
Device Status
Waveforms
IEC103 Info
Cancel Print
This menu is used to print device description, settings, all kinds of records, waveforms, information
related with IEC60870-5-103 protocol, channel state and channel statistic.
This menu comprises the following submenus.
No.
1
Item
Device Info
Function description
Print the description information of the device, including software
version.
Print device setup, system parameters, protection settings and logic
2
Settings
links settings. It can print by different classifications as well as printing all
settings of the device. Besides, it can also print the latest modified
settings.
3
Disturb Records
Print the disturbance records
4
Superv Events
Print the supervision events
5
IO Events
Print the binary events
6
Prot Ch Superv
Print the self-check information of optical fibre channel, which is made of
some hexadecimal characters and used to developer analyze channel
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8 Human Machine Interface
state
7
Prot Ch Statistics
8
Device Status
9
Waveforms
Print the statistic report of optical fibre channel, which is formed A.M.
9:00 every day
Print the current state of the device, including the sampled value of
voltage and current, the state of binary inputs, setting and so on
Print the recorded waveforms
Print 103 Protocol information, including function type (FUN),
10
IEC103 Info
information serial number (INF), general classification service group
number, and channel number (ACC)
11
Cancel Print
Cancel the print command
The submenu “Settings” comprises the following submenus.
Main Menu
Print
Settings
System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup
All Settings
Latest Chgd Settings
No.
Item
Function description
1
System Settings
Print the system parameters
2
Prot Settings
Print the protection settings
3
BCU Settings
Print the measurement and control settings
4
Logic Links
Print the logic links settings
5
Device Setup
Print the settings related to device setup
6
All Settings
7
Latest Chgd Settings
Print all settings including device setup, system parameters, protection
settings and logic links settings
Print the setting latest modified
The submenu “Prot Settings” comprises the following command menus.
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8 Human Machine Interface
Main Menu
Print
Settings
Prot Settings
No.
Line Settings
BFP Settings
FD Settings
Deadzone Settings
AuxE Settings
OV Settings
Direction Settings
UV Settings
Pilot Scheme Settings
NegOV Settings
Rmt CommCh Settings
ThOvld Settings
DPFC Dist Settings
PD Settings
LoadEnch Settings
Stub Settings
Dist Settings
FreqProt Settings
ROC Settings
OOS Settings
NegOC Settings
MiscProt Settings
SOTF Settings
Superv Settings
OC Settings
Trip Logic Settings
VTF OC Settings
CB1 AR/Syn Settings
RevPower Settings
CB2 AR/Syn Settings
BRC Settings
All Settings
Item
Function description
1
Line Settings
Print line parameters
2
FD Settings
Print fault detector element settings
3
AuxE Settings
Print auxiliary element settings
4
Direction Settings
Print direction control element settings
5
Pilot Scheme Settings
6
Rmt CommCh Settings
Print optical pilot channel settings
7
DPFC Dist Settings
Print y DPFC distance protection settings
8
LoadEnch Settings
Print load encroachment settings
9
Dist Settings
Print distance protection settings
10
ROC Settings
Print directional earth-fault protection settings
11
NegOC Settings
Print negative-sequence overcurrent protection settings
12
SOTF Settings
Print SOTF distance and overcurrent protection settings
Print pilot distance protection and pilot directional earth-fault protection
settings
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13
OC Settings
Print phase overcurrent protection settings
14
VTF OC Settings
Print overcurrent protection settings for VT circuit failure
15
RevPower Settings
Print reverse power protection settings
16
BRC Settings
Print broken conductor protection settings
17
BFP Settings
Print breaker failure protection settings
18
Deadzone Settings
Print dead zone settings
19
OV Settings
Print overvoltage protection settings
20
UV Settings
Print undervoltage protection settings
21
NegOV Settings
Print negative-sequence overvoltage protection settings
22
ThOvld Settings
Print thermal overload protection settings
23
PD Settings
Print pole discrepancy protection settings
24
Stub Settings
Print stub overcurrent protection settings
25
FreqProt Settings
Print frequency protection settings
26
OOS Settings
Print out-of-step protection settings
27
MiscProt Settings
Print miscellaneous settings
28
Superv Settings
Print VT circuit supervision and CT circuit supervision settings
29
Trip Logic Settings
Print trippling logic settings
30
CB1 AR/Syn Settings
31
CB2 AR/Syn Settings
32
All Settings
Print synchronism check and auto-reclosing settings of circuit breaker
No.1
Print synchronism check and auto-reclosing settings of circuit breaker
No.2
Print all settings included in “Prot Settings” submenu
The submenu “BCU Settings” includes the following command menus.
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Main Menu
Print
Settings
BCU Settings
FUN Settings
CB1 Syn Settings
CB2 Syn Settings
BI Settings
Control Settings
Interlock Settings
All Settings
No.
Item
Function description
1
FUN Settings
Print function settings
2
CB1 Syn Settings
Print manual synchronism check settings for circuit breaker 1
3
CB2 Syn Settings
Print manual synchronism check settings for circuit breaker 2
4
BI Settings
Print binary input settings
5
Control Settings
Print control settings
6
Interlock Settings
Print interlock settings
7
All Settings
Print all settings included in “BCU Settings” submenu
The submenu “Logic Links” comprises the following command menus.
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Main Menu
Print
Settings
Logic Links
Function Links
GOOSE Send Links
GOOSE Recv Links
SV Links
All Settings
No.
Item
Function description
1
Function Links
Print function links settings
2
GOOSE Send Links
Print GOOSE sending links settings
3
GOOSE Recv Links
Print GOOSE receiving links settings
4
SV Links
Print SV links settings
5
All Settings
Print all settings included in “Logic Links” submenu
The submenu “Device Setup” comprises the following command menus.
Main Menu
Print
Settings
Device Setup
Device Settings
Comm Settings
Label Settings
All Settings
No.
Item
Function description
1
Device Settings
Print the device settings.
2
Comm Settings
Print the communication settings.
3
Label Settings
Print the label settings of each protection element.
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4
Print all settings included in “Device Setup” submenu
All Settings
The submenu “Prot Ch Superv” comprises the following command menus.
Main Menu
Print
Prot Ch Superv
Channel 1
Channel 2
No.
Item
1
Channel 1
2
Channel 2
Function description
Print the self-check information of optical fibre channel 1, which is made of some
hexadecimal characters and used to developer analyze channel state
Print the self-check information of optical fibre channel 2, which is made of some
hexadecimal characters and used to developer analyze channel state
The submenu “Prot Ch Statistics” includes the following command menus.
Main Menu
Print
Prot Ch Statistics
Channel 1
Channel 2
No.
Item
1
Channel 1
2
Channel 2
Function description
Print the statistic report of optical fibre channel 1, which is formed A.M. 9:00 every
day
Print the statistic report of optical fibre channel 2, which is formed A.M. 9:00 every
day
The submenu “Waveforms” includes the following command menus.
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Main Menu
Print
Waveforms
Wave
No.
1
Item
Function description
Wave
Print the recorded current and voltage waveforms
8.2.3.6 Local Cmd
Main Menu
Local Cmd
Reset Target
Trig Oscillograph
Control
Download
Clear Counter
Clear CB1 AR Counter
Clear CB2 AR Counter
Clear Energy Counter
This menu is used to reset the tripping relay with latch, indicator LED, LCD display, and as same
as the reset function of binary inputs. This menu provides a method of manually recording the
current waveform data of the device under normal condition for printing and uploading SAS.
Besides, it can send out the request of program download, clear statistic information about
GOOSE, SV, AR, FO channel and energy.
This menu comprises the following submenus.
No.
Item
Function description
1
Reset Target
Reset the local signal, indicator LED, LCD display and so on
2
Trig Oscillograph
Trigger waveform recording
3
Control
Manually operating to trip, close output or for signaling purpose
4
Download
Send out the request of downloading program
5
Clear Counter
Clear GOOSE, SV and FO channel statistic data
6
Clear CB1 AR Counter
Clear AR statistic data of circuit breaker No.1
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7
Clear CB2 AR Counter
8
Clear Energy Counter
Clear AR statistic data of circuit breaker No.2
Clear all energy metering values (i.e., PHr+_Pri, PHr-_Pri, Qr+_Pri,
QHr-_Pri)
8.2.3.7 Information
Main Menu
Information
Version Info
Board Info
MOT Info
In this menu, LCD can display software information of all kinds of intelligent plug-in modules,
which consists of version, creating time of software, CRC codes and management sequence
number. Besides, plug-in module information and MOT information can also be viewed.
This menu comprises the following command menus.
No.
Item
Function description
Display software information of DSP module, MON module and HMI module,
1
Version Info
which consists of version, creating time of software, CRC codes and
management sequence number.
2
Board Info
Monitor the current working state of each intelligent module.
3
MOT Info
Display ordering code
8.2.3.8 Test
Main Menu
Test
Prot Ch Counter
GOOSE Comm Counter
SV Comm Counter
Device Test
Internal Signal
AR Counter
HMI Setup
This menu is mainly used for developers to debug the program and for engineers to maintain the
device. It can be used to fulfill the communication test function. It is also used to generate all kinds
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of reports or events to transmit to the SAS without any external input, so as to debug the
communication on site. Besides, it can also display statistic information about GOOSE, SV, AR
and FO channel.
This menu comprises the following submenus.
No.
Item
Function description
1
Prot Ch Counter
Check communication statistics data of protection FO channel
2
GOOSE Comm Counter
Check communication statistics data of GOOSE
3
SV Comm Counter
Check communication statistics data of SV (Sampled Values)
Automatically generate all kinds of reports or events to transmit to SCADA,
4
including disturbance records, self-supervision events and binary events. It
Device Test
can realize the report uploading by different classification, as well as the
uploading of all kinds of reports
5
Internal Signal
This submenu is only reserved for the manufacturer
6
AR Counter
Check AR counters
7
HMI Setup
Configure LCD display and check LCD display and LED indicators
The submenu “Prot Ch Counter” comprises the following command menus.
Main Menu
Test
Prot Ch Counter
Ch1 Counter
Ch2 Counter
No.
Item
Function description
1
Ch1 Counter
Check communication statistic information of channel 1
2
Ch2 Counter
Check communication statistic information of channel 2
The submenu “Device Test” comprises the following submenus.
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Main Menu
Test
Device Test
Disturb Events
Superv Events
IO Events
No.
Item
1
Disturb Events
2
Superv Events
3
IO Events
Function description
View the relevant information about disturbance records (only used for
debugging persons)
View the relevant information about supervision events (only used for
debugging persons)
View the relevant information about binary events (only used for debugging
persons)
Users can respectively execute the test automatically or manually by selecting commands “All
Test” or “Select Test”.
The submenu “Disturb Events” comprises the following command menus.
Main Menu
Test
Device Test
Disturb Events
All Test
Select Test
No.
Item
Description
1
All Test
Ordinal test of all protection elements
2
Select Test
Selective test of corresponding classification
The submenu “Superv Events” comprises the following command menus.
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Main Menu
Test
Device Test
Superv Events
All Test
Select Test
No.
Item
Description
1
All Test
Ordinal test of all self-supervisions
2
Select Test
Selective test of corresponding classification
The submenu “IO Events” comprises the following command menus.
Main Menu
Test
Device Test
IO Events
All Test
Select Test
No.
Item
Description
1
All Test
Ordinal test of change of all binary inputs
2
Select Test
Selective test of corresponding classification
The submenu “AR Counter” comprises the following command menus.
Main Menu
Test
AR Counter
CB1 AR Counter
CB2 AR Counter
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No.
Item
Function description
1
CB1 AR Counter
Check AR counters of circuit breaker No.1
2
CB2 AR Counter
Check AR counters of circuit breaker No.2
The submenu “HMI Setup” comprises the following command menus.
Main Menu
Test
HMI Setup
Contrast
BacklitDur
LgtIntnsty
SupervLCD
SupervLED
No.
Item
Function description
1
Contrast
To adjust the contrast of LCD display
2
BacklitDur
To adjust the duration of LCD backlight
3
Lgtlntnsty
To adjust the brightness of LCD display
4
SupervLCD
To find out dead pixel of LCD display
5
SupervLED
To find out broken LED indicator 03~20
8.2.3.9 Clock
The current time of internal clock can be viewed here. The time is displayed in the form
YY-MM-DD and hh:mm:ss. All values are presented with digits and can be modified.
8.2.3.10 Language
This menu is mainly used to set LCD display language.
8.3 Access Authority Management
In order to conveniently manage access authority, the device support setup up to 40 users and
allow each user to own different password (user password can support 8 characters at most and
must include one lowercase letter, one capital letter and one number at least) and access authority
(such as modify settings, view records, remote control)
According to different access authority, the corresponding operations to the device by LCD panel
can be allowed to perform. For the operation that requires authorization, the corresponding user
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logs in and the correct password must be input after the operation can be performed.
8.3.1 Authority Classification
The device provide four kinds of authorities: View, Control, Setting, Project. The default
configuration of the device is no multi-users. Each item of different authority class can be enabled
or disabled independently, and the operation without access authority can be performed directly
no password provided. The valid time of the password can be set, and the password need not be
input again within the valid time ,which ensure both security and convenience.
Taking “User1” as an example, four kinds of authorities: View, Control, Setting, Project are shown
as below.
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8.3.2 Authority Identification
The operation is as follows:
1.
Press the “▲” to enter the main menu, the following interface will be shown when performing
an operation. (Multi-users have been configured in advance)
2.
Press the “◄” or “►” to select username, and press the “ESC” to exit this menu
Username
User1
Password
3.
Press the “ENT” or “▼” to move, and the following interface will be shown after the username
is confirmed.
Username
User1
Password
******
0 1 2 3 4 5 6 7 8 9
[OK]
4.
Press the “◄” or “►” to select number or letter, and press “ENT” to ensure selected character.
5.
Press the “▲” or “▼” to page up/down to select previous group or next group characters.
6.
Press the “GRP” to switch uppercase or lowercase to be chosen characters.
7.
When the password reaches to 8 bits, the device will verify whether the username and
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password are correctly. If the password is shorter than 8 bits, select and press “OK” to begin
to verify whether the username and password are correctly.
8.
Press the “ESC” to cancel entered character during entering password, and the password will
be cleared if the password check fails. When the password is cleared, press the “ESC” to
select the username again.
9.
The device provides the function of password memory, the following interface will be shown if
the valid time of the password is set and last entered password is no timeout.
Username
User1
Password
*******
10. Press the “ENT” to verify the password, press the “◄” or “►” to switch the username and the
password will be cleared, and press the “ESC” to exit the interface.
11. If the password is correct and the user owns the authority of the operation performed, the
operation will be performed.
If the password is incorrect, the device will issue an alarm signal “Password Error”. If the password
is correct but the user has no the authority of the operation performed, the device will issue an
alarm signal “Unauthorized”. If the password is incorrect or the user has no the authority of the
operation performed more than three times, the device will issue an alarm signal “PWD Error or
Unauthorized, Screen Locked” and the device will return to main interface after the screen is
locked for 1 minutes, which will be recorded in device log.
8.4 LCD Display
8.4.1 Overview
There are some kinds of LCD display, SLD (single line diagram) display, disturbance records,
supervision events, IO events, control logs and device logs. Disturbance records and supervision
events will not disappear until them are acknowledged by pressing the “RESET” button in the
protection panel (i.e. energizing the binary input [BI_RstTarg]). If any event is detected, the
corresponding event display will pop up automatically, and user can keep pressing “ENT” and then
press “ESC” to switch between normal display and event display. IO events will be displayed for 5s
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and then it will return to the previous display interface automatically. Device logs will not pop up
and can only be viewed by navigating the corresponding menu.
8.4.2 Function Shortcuts Key
The device provide some function shortcuts key, which can be configured by PCS-Explorer and be
fulfilled by combination key of devices' keypad, to execute some operation quickly.
8.4.2.1 Shortcuts Key Configuration
1.
Right-click the menu “LCD Graph”, and select the menu item “Edit Shortcut Key” to display
the configuration interface of function key shortcuts as shown below.
2.
In configuration interface, double-click the table item in the list of “Extend Command” to select
LCD extend command of dropdown list corresponding with keypads in front panel as shown
below. Select the first blank item in dropdown list to cancel the setup.
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3.
Double-click the table item in the list of “Attribute” to edit the attribute of keypad in front panel
as shown below. When the attribute is set as “1”, the corresponding operation can not execute
unless input correct password. When the attribute is set as “0” or blank, password is not
required. After finishing configuration, click the button “OK”.
4.
The name description of extend command can be modified in signal setup interface, the
operation “Refresh” in the interface of “Source” must be execute at first before configuring
function shortcuts key or generating drive file package.
5.
Right-click device node and execute the menu “Compress Driver File” to generate drive file
package of the device. The file “LCDConfig.txt” in drive file package of the device records
related contents about shortcuts key. If shortcuts keys are not required, set “Extend
Command” corresponding with function shortcuts key as blank, and generate drive file
package of the device again.
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8.4.2.2 Function Description
In general, the function of “GRP” is switch setting group, however, the original function of “GRP” is
blocked when configuring function shortcuts key. (the setting group can be switched by shortcuts
key, binary input or modifying the setting) Under main interface, press “GRP” to display the
interface of function shortcuts key and press “ESC” to return to main interface.
Shortcut keys
[
]
LCD.ExtCmd04
[
]
LCD.ExtCmd05
[
]
LCD.ExtCmd06
[
]
LCD.ExtCmd07
[ + ]
LCD.ExtCmd08
[
]
LCD.ExtCmd09
[ ENT ]
LCD.ExtCmd10
-
The device support 10 extended command, LCD.ExtCmd01~LCD.ExtCmd10, and the name can
be modified by PCS-Explorer. The first three extend command is fixed in program, so only
LCD.ExtCmd04~LCD.ExtCmd10 are configurable, and configured as any of seven function
shortcuts key (“▲”, “▼”, “◄”, “►”, “＋”, “－” and “ENT”).
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Password:
000
Under the interface of function shortcuts key, press a shortcuts key to execute corresponding
operation. If the attribute of the extend command is set as “1”, the corresponding operation can not
execute unless input correct password. The extend command executed by shortcuts key outputs a
pulse signal with 500ms, and for the operation requiring latching signal, the device provides
“T_FF” and “RS_FF” to fulfill the application, which can be configured by PCS-Explorer.
8.4.3 Normal Display
After the device is powered and entered into the initiating interface, it takes tens of seconds to
complete the initialization of the device. During the initialization of the device, the “HEALTHY”
indicator lamp of the device goes out.
The device can display single line diagram (SLD) and primary operation information, it can support
wiring configuration function. LCD configuration file can be downloaded via the network. Remote
control operation through single line diagram is also supported.
Under normal condition, LCD will display the following interface. LCD adopts white color as its
backlight that is activated if once there is any keyboard operation, moreover, the backlight will be
extinguished automatically if no keyboard operation is detected for a duration.
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S
2010-06-08 10:10:00
Ia
0.00A
Ib
0.00A
Ic
0.00A
3I0
0.00A
Ua
0.02V
Ub
0.00V
Uc
0.00V
3U0
0.02V
U_Syn
0.00V
f
50.00Hz
Addr 24343
Group 01
The content displayed on the screen contains: the current date and time of the device (with a
format of yyyy-mm-dd hh:mm:ss:), the active setting group number, three-phase current sampling
value, residual current sampling value, three-phase voltage sampling value, residual voltage
sampling value, the synchronism voltage sampling value, line frequency and the address relevant
to IP address of Ethernet A. If all the sampling values of the voltage and the current can’t be fully
displayed within one screen, they will be scrolling-displayed automatically from the top to the
bottom.
If IP address of Ethernet A is “xxx.xxx.a.b”, the displayed address equals to (a×256+b). For
example, If IP address of Ethernet A is “198.087.095.023”, the displayed address will be “95×
256+23=24343”.
If the device has detected any abnormal state, it′ll display the self-check alarm information.
“S” indicates that device clock is synchronized. If “S” disappears, it means that device clock is not
synchronized.
8.4.4 Display Disturbance Records
This device can store up to 32 groups of disturbance records with fault waveform. Each group
consists of disturbance records of operation elements and corresponding fault detector elements.
Up to 1024 disturbance records can be stored in this device. If there is protection element
operation, LCD will automatically display the latest group of disturbance records, and two kinds of
LCD display interfaces will be available depending on whether there are supervision events or not.
For the situation that the disturbance records and the supervision events coexist, the upper half
part is the disturbance record, and the lower half part is the supervision event. The following items
are listed in the upper half part: record No., record name, generation time of the disturbance
record. If there is protection element operation, faulty phase and relative operation time (with
reference to the corresponding fault detector element) will be displayed. If the disturbance records
can not be displayed in one page, they will be displayed in several pages alternately.
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If there is no supervision event, disturbance records will be displayed as shown in the following
figure.
2013-01-15 13:22:23:669
NO.001
0000ms
Disturb
FD.DPFC.Pkp
0024ms
AB
21Q.Z1.Op
If the device has the supervision event, the display interface will show the disturbance record and
the supervision event at the same time.
2013-01-15 13:22:23:669
NO.001
0000ms
Disturb
FD.DPFC.Pkp
0024ms
AB
21Q.Z1.Op
Superv Events
Alm_Device
NO.001
shows the SOE No. of the disturbance record.
2013-01-15 13:22:23:669
shows the time of the disturbance record, the format is
“yyyy-mm-dd hh:mm:ss:fff”.
Disturb
shows the title of the disturbance record.
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0000ms FD.DPFC.Pkp
shows fault detector element and its operation time (set as
“0000ms” fixedly).
0024ms AB
shows operation element and its relative operation time (with
21Q.Z1.Op
reference to the corresponding fault detector element).
All the protection elements have been listed in chapter “Operation Theory”, and please refer to
each protection element for details. The reports related to oscillography function are showed in the
following table.
Table 8.4-1 Tripping report messages
No.
Message
Description
1
TrigDFR_Man
Oscillography function is triggered manually.
2
TrigDFR_Rmt
Oscillography function is triggered remotely.
Oscillography function is triggered by binary input [BI_TrigDFR]. The
3
TrigDFR_BI
binary input [BI_TrigDFR] is configurable, and it can be designated to
internal signal or external input.
8.4.5 Display Supervision Event
This device can store 1024 pieces of supervision events. During the running of the device, the
supervision event of hardware self-check errors or system running abnormity will be displayed
immediately.
S
Superv Events
Alm_Device
Alm_Version
S
indicates that device clock is synchronized. If “S” disappears, it
means that device clock is not synchronized.
Superv Events
shows the title of the supervision events.
Alm_Device
shows the contents of supervision events.
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Alm_Version
8.4.6 Display IO Events
This device can store 1024 pieces of binary events. During the running of the device, the binary
input will be displayed once its state has changed, i.e. from “0” to “1” or from “1” to “0”.
NO.001
2013-01-15 13:31:23:669
IO Chg
BI_Maintenance
0
1
NO.001
shows the No. of the binary event.
2013-01-15 13:31:23:669
shows date and time when the report occurred, the format is
“yyyy-mm-dd hh:mm:ss:fff”.
IO Chg
shows the title of the binary event.
BI_Maintenance 0→1
shows the state change of binary input, including binary input
name, original state and final state.
8.4.7 Display Device Logs
This device can store 1024 pieces of device logs. Please refer to section “8.5.3” for LCD operation
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4. Device Logs NO.4
2008-11-28 10:18:47:569ms
Reboot
Device Logs NO. 4
shows the title and the number of the device log
2008-11-28 10:18:47:569
shows date and time when the report occurred, the format is
year–month-date and hour:minute:second:millisecond
Reboot
shows the manipulation content of the device log
User operating information listed below may be displayed.
Table 8.4-2 User operating event list
No.
Message
Description
1
Reboot
The device has been reboot.
2
Settings_Chgd
The device′s settings have been changed.
3
ActiveGrp_Chgd
Active setting group has been changed.
4
Report_Cleared
All reports have been deleted. (Device logs can not be deleted)
5
Waveform_Cleared
All waveforms have been deleted.
6
Process_Exit
A process has exited.
7
Counter_Cleared
Clear counter
It will be displayed on LCD before disturbance records and supervision events are confirmed. Only
pressing both “ENT” and “ESC” at the same time can switch among disturbance records,
supervision events and the normal running state of the device to display it. IO events will be
displayed for 5s and then it will return to the previous display interface automatically.
8.5 Keypad Operation
8.5.1 View Device Measurements
The operation is as follows:
1.
Press the “▲” to enter the main menu;
2.
Press the “▲” or “▼” to move the cursor to the “Measurements” menu, and then press
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the “ENT” or “►” to enter the menu;
3.
Press the “▲” or “▼” to move the cursor to any command menu, and then press the
“ENT” to enter the menu;
4.
Press the “▲” or “▼” to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most);
5.
Press the “◄” or “►” to select pervious or next command menu;
6.
Press the “ENT” or “ESC” to exit this menu (returning to the “Measurements” menu);
8.5.2 View Device Status
The operation is as follows:
1.
Press the key “▲” to enter the main menu.
2.
Press the key “▲” or “▼” to move the cursor to the “Status” menu, and then press the
“ENT” or “►” to enter the menu.
3.
Press the key “▲” or “▼” to move the cursor to any command menu item, and then press
the key “ENT” to enter the submenu.
4.
Press the “▲” or “▼” to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most).
5.
Press the key “◄” or “►” to select pervious or next command menu.
6.
Press the key “ENT” or “ESC” to exit this menu (returning to the “Status” menu).
8.5.3 View Device Records
The operation is as follows:
1.
Press the “▲” to enter the main menu;
2.
Press the “▲” or “▼” to move the cursor to the “Records” menu, and then press the
“ENT” or “►” to enter the menu;
3.
Press the “▲” or “▼” to move the cursor to any command menu, and then press the
“ENT” to enter the menu;
4.
Press the “▲” or “▼” to page up/down;
5.
Press the “＋” or “－” to select pervious or next record;
6.
Press the “◄” or “►” to select pervious or next command menu;
7.
Press the “ENT” or “ESC” to exit this menu (returning to the “Records” menu);
8.5.4 Print Device Records
The operation is as follows:
1.
Press the “▲” to enter the main menu;
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2.
Press the “▲” or “▼” to move the cursor to the “Print” menu, and then press the “ENT” or
“►” to enter the menu;
3.
Press the “▲” or “▼” to move the cursor to any command menu, and then press the
“ENT” to enter the menu;

Selecting the “Disturb Records”, and then press the “＋” or “－” to select pervious
or next record. After pressing the key “ENT”, the LCD will display “Start Printing... ”,
and then automatically exit this menu (returning to the menu “Print”). If the printer
doesn’t complete its current print task and re-start it for printing, and the LCD will
display “Printer Busy…”. Press the key “ESC” to exit this menu (returning to the
menu “Print”).

Selecting the command menu “Superv Events” or “IO Events”, and then press the
key “▲” or “▼” to move the cursor. Press the “＋” or “－” to select the starting and
ending numbers of printing message. After pressing the key “ENT”, the LCD will
display “Start Printing…”, and then automatically exit this menu (returning to the
menu “Print”). Press the key “ESC” to exit this menu (returning to the menu “Print”).
4.
If selecting the command menu “Device Info”, “Device Status“ or “IEC103 Info”, press
the key “ENT”, the LCD will display “Start printing..”, and then automatically exit this menu
(returning to the menu “Print”).
5.
If selecting the “Settings”, press the key “ENT” or “►” to enter the next level of menu.
6.
After entering the submenu “Settings”, press the key “▲” or “▼” to move the cursor, and
then press the key “ENT” to print the corresponding default value. If selecting any item to
printing:
Press the key “＋” or “－” to select the setting group to be printed. After pressing the key
“ENT”, the LCD will display “Start Printing…”, and then automatically exit this menu
(returning to the menu “Settings”). Press the key “ESC” to exit this menu (returning to the
menu “Settings”).
7.
After entering the submenu “Waveforms”, press the “＋” or “－” to select the waveform
item to be printed and press ”ENT” to enter. If there is no any waveform data, the LCD will
display “No Waveform Data!” (Before executing the command menu “Waveforms”, it is
necessary to execute the command menu “Trig Oscillograph” in the menu “Local Cmd”,
otherwise the LCD will display “No Waveform Data!”). With waveform data existing:
Press the key “＋” or “－” to select pervious or next record. After pressing the key “ENT”, the LCD
will display “Start Printing…”, and then automatically exit this menu (returning to the menu
“Waveforms”). If the printer does not complete its current print task and re-start it for printing, and
the LCD will display “Printer Busy…”. Press the key “ESC” to exit this menu (returning to the menu
“Waveforms”).
8.5.5 View Device Setting
The operation is as follows:
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1.
Press the “▲” to enter the main menu;
2.
Press the “▲” or “▼” to move the cursor to the “Settings” menu, and then press the
“ENT” or “►” to enter the menu;
3.
Press the “▲” or “▼” to move the cursor to any command menu, and then press the
“ENT” to enter the menu;
4.
Press the “▲” or “▼” to move the cursor;
5.
Press the “+” or “-” to page up/down;
6.
Press the “◄” or “►” to select pervious or next command menu;
7.
Press the “ESC” to exit this menu (returning to the menu “Settings”).
NOTICE!
If the displayed information exceeds 14 lines, the scroll bar will appear on the right side
of the LCD to indicate the quantity of all displayed information of the command menu
and the relative location of information where the current cursor points at.
8.5.6 Modify Device Setting
The operation is as follows:
1.
Press the “▲” to enter the main menu;
2.
Press the “▲” or “▼” to move the cursor to the “Settings” menu, and then press the
“ENT” or “►” to enter the menu;
3.
Press the “▲” or “▼” to move the cursor to any command menu, and then press the
“ENT” to enter the menu;
4.
Press the “▲” or “▼” to move the cursor;
5.
Press the “+” or “-” to page up/down;
6.
Press the “◄” or “►” to select pervious or next command menu;
7.
Press the “ESC” to exit this menu (returning to the menu “Settings” );
8.
If selecting the command menu “System Settings”, move the cursor to the setting item
to be modified, and then press the “ENT”;
Press the “＋” or “－” to modify the value (if the modified value is of multi-bit, press the “◄” or “►”
to move the cursor to the digit bit, and then press the “＋” or “－” to modify the value), press the
“ESC” to cancel the modification and return to the displayed interface of the command menu
“System Settings”. Press the “ENT” to automatically exit this menu (returning to the displayed
interface of the command menu “System Settings”).
Move the cursor to continue modifying other setting items. After all setting values are modified,
press the “◄”, “►” or “ESC”, and the LCD will display “Save or Not?”. Directly press the “ESC” or
press the “◄” or “►” to move the cursor. Select the “Cancel”, and then press the “ENT” to
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automatically exit this menu (returning to the displayed interface of the command menu “System
Settings”).
Press the “◄” or “►” to move the cursor. Select “No” and press the “ENT”, all modified setting item
will restore to its original value, exit this menu (returning to the menu “Settings”).
Press the “◄” or “►” to move the cursor to select “Yes”, and then press the “ENT”, the LCD will
display password input interface.
Password:
____
Input a 4-bit password (“＋”, “◄”, “▲” and “－”). If the password is incorrect, continue inputting it,
and then press the “ESC” to exit the password input interface and return to the displayed interface
of the command menu “System Settings”. If the password is correct, LCD will display “Save
Setting Now…”, and then exit this menu (returning to the displayed interface of the command
menu “System Settings”), with all modified setting items as modified values.
NOTICE!
For different setting items, their displayed interfaces are different but their modification
methods are the same. The following is ditto.
9.
If selecting the submenu “Prot Settings”, and press “ENT” to enter. After selecting
different command menu, the LCD will display the following interface: (take “FD
Settings” as an example)
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FD Settings
Please Select Group for Config
Active Group:
01
Selected Group:
02
Press the “＋” or “－” to modify the value, and then press the “ENT” to enter it. Move the cursor to
the setting item to be modified, press the “ENT” to enter.
Take the setting [FD.DPFC.I_Set] as an example is selected to modify, then press the “ENT” to
enter and the LCD will display the following interface. Press “＋” or “－” to modify the value and
then press the “ENT” to confirm.
FD.DPFC.I_Set
Current Value
0.200
Modified Value
0.202
Min Value
0.050
Max Value
30.000
NOTICE!
After modifying protection settings in current active setting group or system parameters
of the device, the “HEALTHY” LED indicator the device will be lit off, and the MON
module will check the new settings. If the abnormality is detected during the setting
check, corresponding alarm signals will be issued. Moreover, if the critical error is
detected, the device will be blocked.
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8.5.7 Copy Device Setting
The operation is as follows:
1.
Press the “▲” to enter the main menu;
2.
Press the “▲” or “▼” to move the cursor to the “Settings” menu, and then press the
“ENT” or “►” to enter the menu;
3.
Press the “▲” or “▼” to move the cursor to the command menu “Copy Settings”, and
then press the “ENT” to enter the menu.
Copy Settings
Active Group:
01
Copy To Group:
02
Press the “＋” or “－” to modify the value. Press the “ESC”, and return to the menu “Settings”.
Press the “ENT”, the LCD will display the interface for password input, if the password is incorrect,
continue inputting it, press the “ESC” to exit the password input interface and return to the menu
“Settings”. If the password is correct, the LCD will display “Settings Copied!”, and exit this menu
(returning to the menu “Settings”).
8.5.8 Switch Setting Group
The operation is as follows:
1.
Exit the main menu;
2.
Press the “GRP”
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Change Active Group
Active Group:
01
Change To Group:
02
Press the “＋” or “－” to modify the value, and then press the “ESC” to exit this menu (returning to
the main menu). After pressing the “ENT”, the LCD will display the password input interface. If the
password is incorrect, continue inputting it, and then press the “ESC” to exit the password input
interface and return to its original state. If the password is correct, the “HEALTHY” indicator lamp
of the protection device will go out, and the protection device will re-check the protection setting. If
the check doesn’t pass, the protection device will be blocked. If the check is successful, the LCD
will return to its original state.
8.5.9 Delete Device Records
The operation is as follows:
1.
Exit the main menu;
2.
Press the “＋”, “－”, “＋”, “－” and “ENT”; Press the “ESC” to exit this menu (returning to
the original state). Press the “ENT” to carry out the deletion.
Press <ENT> To Clear
Press <ESC> To Exit
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NOTICE!
The operation of deleting device message will delete all messages saved by the
protection device, including disturbance records, supervision events, binary events, but
not including device logs. Furthermore, the message is irrecoverable after deletion, so
the application of the function shall be cautious.
8.5.10 Remote Control via Menu
Control operation method is introduced as below:
1.
Press the key “▲” to enter the main menu.
2.
Press the key “▲” or “▼” to move the cursor to the command menu “Local Cmd”, and
then press the key “ENT” to enter submenus. Press the key “▲” or “▼” to move the
cursor to the command menu “Control”, and then press the key “ENT” to enter and the
following display will be shown on LCD.
Password:
000
Input a 3-bit password (“111”). If the password is incorrect, continue inputting it, and then press the
“ESC” to exit the password input interface and return to the displayed interface of the command
menu “Control”. If the password is correct, it will go to the following step.
3.
Press the key “▲” or “▼” to move the cursor to the control object and press the key
“ENT” to select control object.
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Control
4.
1.
Step1: select Control Object
CSWI01
2.
CSWI02
3.
CSWI03
4.
CSWI04
5.
CSWI05
6.
CSWI06
7.
CSWI07
8.
CSWI08
9.
CSWI09
10.
CSWI10
Press the key “◄” or “►” to select control command press the key “ENT” to the next step.
Three control commands are optional:
1) Open (Lower): Remote open
2) Close (Raise): Remote close
3) (Stop): Reserved
CSWI01
Step2: select Control Command
Open(Lower)
Close(Raise)
NoCheck
SynchroCheck
LoopCheck
EF Line Selection
InterlockChk
InterlockNotChk
Select
Execute
(Stop)
DeadCheck
Cancel
Result
5.
Press the key “◄” or “►” to select synchronism check mode and press the key “ENT” to
the next step.
Five synchronism check modes are optional:
1) NoCheck: Without any check
2) SynchroCheck: Synchronism-check mode
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3) DeadCheck: Dead check mode
4) LoopCheck: Reserved
5) EF Line Selection: Reserved
CSWI01
Step3: select Execution Condition
Open(Lower)
Close(Raise)
NoCheck
SynchroCheck
LoopCheck
EF Line Selection
InterlockChk
InterlockNotChk
Select
Execute
(Stop)
DeadCheck
Cancel
Result
6.
Press the key “◄” or “►” to select interlock mode and press the key “ENT” to next step.
Two interlock check modes are optional:
1) InterlockChk: Check interlocking criteria
2) InterlockNotChk: Not check interlocking criteria
CSWI01
Step4: select Interlock Condition
Open(Lower)
Close(Raise)
NoCheck
SynchroCheck
LoopCheck
EF Line Selection
InterlockChk
InterLockNotChk
Select
Execute
(Stop)
DeadCheck
Cancel
Result
7.
Press the key “◄” or “►” to select control type and press the key “ENT”.
As shown in the following figure, operation results will be shown after “Result” at the bottom of the
LCD.
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Three synchronism control types are optional:
1) Select: Select control object
2) Execute: Execute control operation
3) Cancel: Cancel control operation
CSWI01
Step5: select Control Type
Open(Lower)
Close(Raise)
NoCheck
SynchroCheck
LoopCheck
EF Line Selection
InterlockChk
InterLockNotChk
Select
Execute
(Stop)
DeadCheck
Cancel
Result
NOTICE!
“Execute” operation must be operated after “Select” operation.
8.5.11 Remote Control via SLD
The control operation (close or open) also can be executed on the single line diagram (SLD) of the
default display under normal operation condition. The signs of the circuit breaker (abbreviated as
CB) and switch (DS or ES) are listed in the following table.
Table 8.5-1 Primary equipment symbols in SLD
Sign
Explanation
Sign
Explanation
Position of CB: Open
Position of switch: Open
Position of CB: Closed
Position of switch: Closed
?
Position of CB: Intermediate state
?
Position of switch: Intermediate state
×
Position of CB: Bad state
×
Position of switch: Bad state
An example of normal display with SLD is shown in the following figure. The single line diagram of
the default display on the LCD is shown as below when the device is in normal situation, if this
device adopts the single line diagram as default display.
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S
Addr:150
2008-11-28 10:10:00
Group 01
Bus1
Bus2
M011
M0112
M0131
M01
M0151
M0171
Feeder M01
In SLD display, press "▲" or "▼" to select a switchgear to be opened/closed, and then press key
"ENT" to control selected CB/switch. After the selection of an open or close operation, the
confirmation window will be valid for a short duration after inputting the correct control password.
This password is configurable by the setting [Ctrl_Password] in the menu “Device Settings”. A
control operation result of success or fail will be returned at last.
1)
The selected object will be framed in a dotted line.
Step 1: Select the control object
2)
Note: From the last step, press “ENT” to popup this operation selection window.
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Step 1: Select the control object
CSWI**
Open
3)
Close
Consult or modify the password through [Ctrl_Password] in "Device Settings".
Step 3: Enter the control password
CSWI** open/close
Password: xxx
4)
Use "←", "→" and "ENT" to confirm or cancel the control operation.
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Step 4: Confirm/Cancel the control operation
CSWI** open/close
Open
5)
Close
Check the operation success or fail result from the control report.
Step 5: Check the control operation result
CSWI** open/close
Op success (or Op fail)
8.5.12 Control with Open/Close Buttons (if Available)
In SLD display, press "▲" or "▼" to select a switchgear to be opened/closed, and then press key
"ENT" to control selected CB/switch. Press the open or close button on the HMI panel and the
confirmation window will be valid for a short duration after inputting the correct control password.
This password is configurable by the setting [Ctrl_Password] in the menu “Device Settings”. A
control operation result of success or fail will be returned at last.
1)
The selected object will be framed in a dotted line.
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Step 1: Select the control object
2)
From the last step, press a control button to popup this window. Consult or modify the
password through [Ctrl_Password] in "Device Settings".
Step 3: Enter the control password
CSWI** open/close
Password: xxx
3)
Use "←", "→" and "ENT" to confirm or cancel the control operation.
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Step 4: Confirm/Cancel the control operation
CSWI** open/close
Open
4)
Close
Check the operation success or fail result from the control report.
Step 5: Check the control operation result
CSWI** open/close
Op success (or Op fail)
8.5.13 Modify Device Clock
The operation is as follows:
1.
Press the “▲” to enter the main menu;
2.
Press the “▲” or “▼” to move the cursor to the “Clock” menu, and then press the “ENT”
to enter clock display
3.
Press the “▲” or “▼” to move the cursor to the date or time to be modified;
4.
Press the “+” or “-” to modify value, and then press the “ENT” to save the modification
and return to the main menu;
5.
Press the “ESC” to cancel the modification and return to the main menu.
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NOTICE!
Move the cursor to select the item “Format” to setup time display format. Press the “+”
or “-” to modify from the following options.
1. YYYY-MM-DD (Default display format)
2. YYYY/MM/dd
3. DD-MM-YYYY
4. DD/MM/YYYY
5. MM-DD-YYYY
6. MM/DD/YYYY
Clock
Year:
2008
Month:
11
Day:
28
Hour:
20
Minute:
59
Format:
YYYY/MM/DD
8.5.14 View Module Information
The operation is as follows:
1.
Press the “▲” to enter the main menu;
2.
Press the “▲” or “▼” to move the cursor to the “Information” menu, and then press the
“ENT” or “►” to enter the menu;
3.
Press the “▲” or “▼” to move the cursor to the command menu “Board Info”, and then
press the “ENT” to enter the menu;
4.
Press the “▲” or “▼” to move the scroll bar;
5.
Press the “ENT” or “ESC” to exit this menu (returning to the “Information” menu).
8.5.15 Check Software Version
The operation is as follows:
1.
Press the “▲” to enter the main menu.
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2.
Press the “▲” or “▼” to move the cursor to the “Information” menu, and then press the
“ENT” to enter the submenu.
3.
Press the key “▲” or “▼” to move the cursor to the command menu “Version Info”, and
then press the key “ENT” to display the software version.
4.
Press the “ESC” to return to the main menu.
8.5.16 Communication Test
The operation is as follows:
1.
Press the key “▲” to enter the main menu.
2.
Press the key “▲” or “▼” to move the cursor to the “Test” menu, and then press the key
“ENT” or “►” to enter the menu.
3.
Press the key “▲” or “▼” to move the cursor to the submenu “Device Test”, and then
press the key “ENT” to enter the submenu, to select test item. If “Disturb Events”
“Superv Events” or “IO Events” is selected, two options “All Test” and “Select Test” are
provided.
4.
Press the key “▲” or “▼” to move the cursor to select the corresponding command menu
“All Test” or “Select Test”. If selecting the “All Test”, press the “ENT”, and the device will
successively carry out all operation element message test one by one.
5.
If “Select Test” is selected, press the key “ENT”. Press the “＋” or “－” to page up/down,
and then press the key “▲” or “▼” to move the scroll bar. Move the cursor to select the
corresponding protection element. Press the key “ENT” to execute the communication
test of this protection element, the substation automatic system (SAS) will receive the
corresponding message.
NOTICE!
If no input operation is carried out within 60s, exit the communication transmission and
return to the “Test” menu, at this moment, the LCD will display “Communication Test
Timeout and Exiting...”.
Press the key “ESC” to exit this menu (returning to the menu “Test”, at this moment, the LCD will
display “Communication Test Exiting…”.
8.5.17 Select Language
The operation is as follows:
1.
Press the key “▲” to enter the main menu.
2.
Press the key “▲” or “▼” to move the cursor to the command menu “Language”, and
then press the key “ENT” to enter the menu and the following display will be shown on
LCD.
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Please Select Language:
1
中文
2
English
3
XXXX
Third language selected by the user
3.
Press the key “▲” or “▼” to move the cursor to the language user preferred and press
the key “ENT” to execute language switching. After language switching is finished, LCD
will return to the menu “Language”, and the display language is changed. Otherwise,
press the key “ESC” to cancel language switching and return to the menu “Language”.
NOTICE!
LCD interface provided in this chapter is only a reference and available for explaining
specific definition of LCD. The displayed interface of the actual device may be some
different from it, so you shall be subject to the actual protection device.
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9 Configurable Function
Table of Contents
9 Configurable Function ...................................................................... 9-a
9.1 Overview .......................................................................................................... 9-1
9.2 Introduction on PCS-Explorer Software ........................................................ 9-1
9.3 Signal List ........................................................................................................ 9-2
9.3.1 Input Signal .......................................................................................................................... 9-2
9.3.2 Output Signal ..................................................................................................................... 9-22
List of Tables
Table 9.3-1 Input signals ............................................................................................................. 9-2
Table 9.3-2 Output signals ........................................................................................................ 9-22
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9 Configurable Function
9.1 Overview
By adoption of PCS-Explorer software, it is able to make device configuration, function
configuration, LCD configuration, binary input and binary output configuration, LED indicator
configuration and programming logic for PCS-902.
9.2 Introduction on PCS-Explorer Software
PCS-Explorer software is developed in order to meet customer’s demand on functions of UAPC
platform device such as device configuration and programmable design. It selects substation as
the core of data management and the device as fundamental unit, supporting one substation to
govern many devices. The software provides on-line and off-line functions: on-line mode: Ethernet
connected with the device supporting IEC60870-5-103 and capable of uploading and downloading
configuration files through Ethernet net; off-line mode: off-line setting configuration. In addition, it
also supports programmable logic to meet customer’s demand.
After function configuration is finished, disabled protection function will be hidden in the device and
in setting configuration list of PCS-Explorer Software. The user can select to show or hide some
setting by this way, and modify the setting value.
Please refer to the instruction manual “PCS-Explorer Auxiliary Software” for details.
Overall functions:

Programmable logic

Device configuration

Function configuration

LCD configuration

LED indicators configuration

Binary signals configuration

Setting configuration

Real-time display of analogue and digital quantity of device

Display of sequence of report (SOE)

Analysis of waveform

File downloading/uploading

LCD function shortcut keys configuration

DNP communication information map configuration

Export RIO file
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9 Configurable Function

Multi-user access authority management
9.3 Signal List
If an input signal or output signal is gray in PCS-Explorer, it means that the input signal or output
signal is not configurable. Otherwise, it is configurable signal.
NOTICE!
PCS-902 can be configured to support single circuit breaker application or double
circuit breakers application by PCS-Explorer. The prefix “CBx.” is added to all signals
for circuit breaker No.x (x=1 or 2). The related protection functions include circuit
breaker position supervision, breaker failure protection, dead zone protection, pole
discrepancy protection, synchrocheck, automatic reclosure, trip logic, CT circuit
supervision, control and synchrocheck for manual closing.
9.3.1 Input Signal
All input signals of this device are listed in the following table.
Table 9.3-1 Input signals
No.
Item
Description
Circuit breaker position supervision
1
CBx.52b_PhA
Normally closed contact of A-phase of circuit breaker No.x
2
CBx.52b_PhB
Normally closed contact of B-phase of circuit breaker No.x
3
CBx.52b_PhC
Normally closed contact of C-phase of circuit breaker No.x
Maintenance status binary input of circuit breaker No.x
If any circuit breaker is in maintenance and out of service, CBx.52b or
4
CBx.Test
CBx.Test should be set as “1” in fixed, and CB No.x will be not take effect
in corresponding protection logics. (CB position supervision is still kept.)
It is only available for double circuit breakers mode.
External manual closing binary input of circuit breaker No.x, it is only
5
CBx.ManCls
6
CBx.52b
Normally closed contact of three-phase of circuit breaker No.x
7
CBx.52a
Normally open contact of three-phase of circuit breaker No.x
applied to SOTF logic
Control circuit failure of circuit breaker No.x (normally closed contacts of
8
CBx.TCCS.Input
tripping position (52b) and closing position (52a) of three-phase circuit
breaker are all de-energized due to DC power loss of control circuit)
Auxiliary element
9
AuxE.OCD.En
10
AuxE.OCD.Blk
11
AuxE.ROC1.En
Current change auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Current change auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 1 of residual current auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
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9 Configurable Function
No.
Item
12
AuxE.ROC1.Blk
13
AuxE.ROC2.En
14
AuxE.ROC2.Blk
15
AuxE.ROC3.En
16
AuxE.ROC3.Blk
17
AuxE.OC1.En
18
AuxE.OC1.Blk
19
AuxE.OC2.En
20
AuxE.OC2.Blk
21
AuxE.OC3.En
22
AuxE.OC3.Blk
23
AuxE.UVD.En
24
AuxE.UVD.Blk
25
AuxE.UVG.En
26
AuxE.UVG.Blk
27
AuxE.UVS.En
28
AuxE.UVS.Blk
29
AuxE.ROV.En
30
AuxE.ROV.Blk
Description
Stage 1 of residual current auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Stage 2 of residual current auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Stage 2 of residual current auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Stage 3 of residual current auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Stage 3 of residual current auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Stage 1 of phase current auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Stage 1 of phase current auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Stage 2 of phase current auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Stage 2 of phase current auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Stage 3 of phase current auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Stage 3 of phase current auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Voltage change auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Voltage change auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Phase-to-ground under voltage auxiliary element enabling input, it is
triggered from binary input or programmable logic etc.
Phase-to-ground under voltage auxiliary element blocking input, it is
triggered from binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element enabling input, it is
triggered from binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element blocking input, it is
triggered from binary input or programmable logic etc.
Residual voltage auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Residual voltage auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Distance protection
31
21D.En
32
21D.Blk
DPFC distance protection enabling input, it is triggered from binary input
or programmable logic etc.
DPFC distance protection blocking input, it is triggered from binary input
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9 Configurable Function
No.
Item
Description
or programmable logic etc.
Load trapezoid characteristic enabling input, it is triggered from binary
33
LoadEnch.En
34
LoadEnch.Blk
35
21.En
36
21.Blk
37
21M1.ZG.En
38
21M1.ZG.Blk
39
21M1.ZP.En
40
21M1.ZP.Blk
41
21M1.En_Instant
42
21M2.ZG.En
43
21M2.ZG.Blk
44
21M2.ZP.En
45
21M2.ZP.Blk
46
21M2.En_ShortDly
Enable accelerating zone 2 of distance protection
47
21M2.Blk_ShortDly
Accelerating zone 2 of distance protection is disabled
48
21M3.ZG.En
49
21M3.ZG.Blk
50
21M3.ZP.En
51
21M3.ZP.Blk
52
21M3.En_ShortDly
Enable accelerating zone 3 of distance protection
53
21M3.Blk_ShortDly
Accelerating zone 3 of distance protection is disabled
54
21M4.ZG.En
55
21M4.ZG.Blk
input or programmable logic etc.
Load trapezoid characteristic blocking input, it is triggered from binary
input or programmable logic etc.
Distance protection enabling input, it is triggered from binary input or
programmable logic etc.
Distance protection blocking input, it is triggered from binary input or
programmable logic etc.
Zone 1 of phase-to-ground distance protection enabling input, default
value is “1”
Zone 1 of phase-to-ground distance protection blocking input, default
value is “0”
Zone 1 of phase-to-phase distance protection enabling input, default
value is “1”
Zone 1 of phase-to-phase distance protection blocking input, default
value is “0”
Enable zone 1 of distance protection operates without time delay
Zone 2 of phase-to-ground distance protection enabling input, default
value is “1”
Zone 2 of phase-to-ground distance protection blocking input, default
value is “0”
Zone 2 of phase-to-phase distance protection enabling input, default
value is “1”
Zone 2 of phase-to-phase distance protection blocking input, default
value is “0”
Zone 3 of phase-to-ground distance protection enabling input, default
value is “1”
Zone 3 of phase-to-ground distance protection blocking input, default
value is “0”
Zone 3 of phase-to-phase distance protection enabling input, default
value is “1”
Zone 3 of phase-to-phase distance protection blocking input, default
value is “0”
Zone 4 of phase-to-ground distance protection enabling input, default
value is “1”
Zone 4 of phase-to-ground distance protection blocking input, default
value is “0”
9-4
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Item
Description
Zone 4 of phase-to-phase distance protection enabling input, default
56
21M4.ZP.En
57
21M4.ZP.Blk
58
21M4.En_ShortDly
Enable accelerating zone 4 of distance protection
59
21M4.Blk_ShortDly
Accelerating zone 4 of distance protection is disabled
60
21M5.ZG.En
61
21M5.ZG.Blk
62
21M5.ZP.En
63
21M5.ZP.Blk
64
21M5.En_ShortDly
Enable accelerating zone 5 of distance protection
65
21M5.Blk_ShortDly
Accelerating zone 5 of distance protection is disabled
66
21Q1.ZG.En
67
21Q1.ZG.Blk
68
21Q1.ZP.En
69
21Q1.ZP.Blk
70
21Q1.En_Instant
71
21Q2.ZG.En
72
21Q2.ZG.Blk
73
21Q2.ZP.En
74
21Q2.ZP.Blk
75
21Q2.En_ShortDly
Enable accelerating zone 2 of distance protection
76
21Q2.Blk_ShortDly
Accelerating zone 2 of distance protection is disabled
77
21Q3.ZG.En
78
21Q3.ZG.Blk
79
21Q3.ZP.En
80
21Q3.ZP.Blk
value is “1”
Zone 4 of phase-to-phase distance protection blocking input, default
value is “0”
Zone 5 of phase-to-ground distance protection enabling input, default
value is “1”
Zone 5 of phase-to-ground distance protection blocking input, default
value is “0”
Zone 5 of phase-to-phase distance protection enabling input, default
value is “1”
Zone 5 of phase-to-phase distance protection blocking input, default
value is “0”
Zone 1 of phase-to-ground distance protection enabling input, default
value is “1”
Zone 1 of phase-to-ground distance protection blocking input, default
value is “0”
Zone 1 of phase-to-phase distance protection enabling input, default
value is “1”
Zone 1 of phase-to-phase distance protection blocking input, default
value is “0”
Enable zone 1 of distance protection operates without time delay
Zone 2 of phase-to-ground distance protection enabling input, default
value is “1”
Zone 2 of phase-to-ground distance protection blocking input, default
value is “0”
Zone 2 of phase-to-phase distance protection enabling input, default
value is “1”
Zone 2 of phase-to-phase distance protection blocking input, default
value is “0”
Zone 3 of phase-to-ground distance protection enabling input, default
value is “1” (x=1, 2, 3, 4, 5)
Zone 3 of phase-to-ground distance protection blocking input, default
value is “0” (x=1, 2, 3, 4, 5)
Zone 3 of phase-to-phase distance protection enabling input, default
value is “1” (x=1, 2, 3, 4, 5)
Zone 3 of phase-to-phase distance protection blocking input, default
PCS-902 Line Distance Relay
9-5
Date: 2019-03-01
9 Configurable Function
No.
Item
Description
value is “0” (x=1, 2, 3, 4, 5)
81
21Q3.En_ShortDly
Enable accelerating zone 3 of distance protection (x=2, 3, 4, 5)
82
21Q3.Blk_ShortDly
Accelerating zone 3 of distance protection is disabled (x=2, 3, 4, 5)
83
21Q4.ZG.En
84
21Q4.ZG.Blk
85
21Q4.ZP.En
86
21Q4.ZP.Blk
87
21Q4.En_ShortDly
Enable accelerating zone 4 of distance protection
88
21Q4.Blk_ShortDly
Accelerating zone 4 of distance protection is disabled
89
21Q5.ZG.En
90
21Q5.ZG.Blk
91
21Q5.ZP.En
92
21Q5.ZP.Blk
93
21Q5.En_ShortDly
Enable accelerating zone 5 of distance protection
94
21Q5.Blk_ShortDly
Accelerating zone 5 of distance protection is disabled
95
78.En
96
78.Blk
97
78.Clr_Counter
Clear the counter
98
21M1.En_PSBR
Enabling power swing blocking releasing of zone 1 (Mho characteristic)
99
21Q1.En_PSBR
Enabling power swing blocking releasing of zone 1 (Quad characteristic)
100
21M1.Blk_PSBR
Blocking power swing blocking releasing of zone 1 (Mho characteristic)
101
21Q1.Blk_PSBR
Blocking power swing blocking releasing of zone 1 (Quad characteristic)
102
21M2.En_PSBR
Enabling power swing blocking releasing of zone 2 (Mho characteristic)
103
21Q2.En_PSBR
Enabling power swing blocking releasing of zone 2 (Quad characteristic)
104
21M2.Blk_PSBR
Blocking power swing blocking releasing of zone 2 (Mho characteristic)
105
21Q2.Blk_PSBR
Blocking power swing blocking releasing of zone 2 (Quad characteristic)
106
21M3.En_PSBR
Enabling power swing blocking releasing of zone 3 (Mho characteristic)
107
21Q3.En_PSBR
Enabling power swing blocking releasing of zone 3 (Quad characteristic)
108
21M3.Blk_PSBR
Blocking power swing blocking releasing of zone 3 (Mho characteristic)
109
21Q3.Blk_PSBR
Blocking power swing blocking releasing of zone 3 (Quad characteristic)
110
21M4.En_PSBR
Enabling power swing blocking releasing of zone 4 (Mho characteristic)
111
21Q4.En_PSBR
Enabling power swing blocking releasing of zone 4 (Quad characteristic)
Zone 4 of phase-to-ground distance protection enabling input, default
value is “1”
Zone 4 of phase-to-ground distance protection blocking input, default
value is “0”
Zone 4 of phase-to-phase distance protection enabling input, default
value is “1”
Zone 4 of phase-to-phase distance protection blocking input, default
value is “0”
Zone 5 of phase-to-ground distance protection enabling input, default
value is “1”
Zone 5 of phase-to-ground distance protection blocking input, default
value is “0”
Zone 5 of phase-to-phase distance protection enabling input, default
value is “1”
Zone 5 of phase-to-phase distance protection blocking input, default
value is “0”
Out-of-step protection enabling input, it is triggered from binary input or
programmable logic etc.
Out-of-step protection blocking input, it is triggered from binary input or
programmable logic etc.
9-6
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Item
Description
112
21M4.Blk_PSBR
Blocking power swing blocking releasing of zone 4 (Mho characteristic)
113
21Q4.Blk_PSBR
Blocking power swing blocking releasing of zone 4 (Quad characteristic)
114
21M5.En_PSBR
Enabling power swing blocking releasing of zone 5 (Mho characteristic)
115
21Q5.En_PSBR
Enabling power swing blocking releasing of zone 5 (Quad characteristic)
116
21M5.Blk_PSBR
Blocking power swing blocking releasing of zone 5 (Mho characteristic)
117
21Q5.Blk_PSBR
Blocking power swing blocking releasing of zone 5 (Quad characteristic)
118
21M.Pilot.En_PSBR
119
21M.Pilot.Blk_PSBR
120
21Q.Pilot.En_PSBR
121
21Q.Pilot.Blk_PSBR
122
21SOTF.En
123
21SOTF.Blk
Enabling power swing blocking releasing of pilot distance zone (Mho
characteristic)
Blocking power swing blocking releasing of pilot distance zone (Mho
characteristic)
Enabling power swing blocking releasing of pilot distance zone (Quad
characteristic)
Blocking power swing blocking releasing of pilot distance zone (Quad
characteristic)
Distance SOTF protection enabling input, it is triggered from binary input
or programmable logic etc.
Distance SOTF protection blocking input, it is triggered from binary input
or programmable logic etc.
Optical pilot channel
124
FOx.En
Enabling channel x
125
FOx.Send1
Sending signal 1 of channel x
126
FOx.Send2
Sending signal 2 of channel x
127
FOx.Send3
Sending signal 3 of channel x
128
FOx.Send4
Sending signal 4 of channel x
129
FOx.Send5
Sending signal 5 of channel x
130
FOx.Send6
Sending signal 6 of channel x
131
FOx.Send7
Sending signal 7 of channel x
132
FOx.Send8
Sending signal 8 of channel x
Sending signal 9 of channel x (it is configured by fault as sending
133
FOx.Send9
permissive signal 1 or sending A-phase permissive signal (only for
phase-segregated command scheme))
Sending signal 10 of channel x (it is configured by fault as sending
134
FOx.Send10
B-phase permissive signal (only for phase-segregated command
scheme))
Sending signal 11 of channel x (it is configured by fault as sending
135
FOx.Send11
C-phase permissive signal (only for phase-segregated command
scheme))
Sending signal 12 of channel x (it is configured by fault as sending
136
FOx.Send12
permissive signal 2 only for pilot directional earth-fault protection
adopting independent pilot channel 2)
Pilot distance protection and pilot directional earth-fault protection
137
85-x.Z.En1
Pilot distance protection x enabling input 1, it is triggered from binary
PCS-902 Line Distance Relay
9-7
Date: 2019-03-01
9 Configurable Function
No.
Item
Description
input or programmable logic etc. (x=1 or 2)
138
85-x.Z.En2
139
85-x.Z.Blk
140
85-x.Abnor_Ch1
Pilot distance protection x enabling input 2, it is triggered from binary
input or programmable logic etc. (x=1 or 2)
Pilot distance protection x blocking input, it is triggered from binary input
or programmable logic etc. (x=1 or 2)
Input signal of indicating that pilot channel 1 is abnormal for pilot
distance protection x (x=1 or 2)
Input signal of receiving permissive signal via channel No.1 for pilot
141
85-x.Recv1
distance protection x, or input signal of receiving permissive signal of
A-phase via channel No.1 for pilot distance protection x (only for
phase-segregated command scheme, x=1 or 2)
Input signal of receiving permissive signal of B-phase via channel No.1
142
85-x.RecvB
for pilot distance protection x (only for phase-segregated command
scheme, x=1 or 2)
Input signal of receiving permissive signal of C-phase via channel No.1
143
85-x.RecvC
for pilot distance protection x (only for phase-segregated command
scheme, x=1 or 2)
144
85-x.ExTrp
145
85-x.Unblocking1
146
85-x.ZX.En1
147
85-x.ZX.En2
148
85-x.ZX.Blk1
149
85-x.ZX.Blk2
150
85-x.DEF.En1
151
85-x.DEF.En2
152
85-x.DEF.Blk
153
85-x.Abnor_Ch1
154
85-x.Abnor_Ch2
155
85-x.Recv1
156
85-x.Recv2
157
85-x.ExTrp
Input signal of initiating sending permissive signal from external tripping
signal for pilot distance protection x (x=1 or 2)
Unblocking signal 1 of pilot distance protection x (x=1 or 2)
Zone Extension enabling input 1 of pilot distance protection x, it is
triggered from binary input or programmable logic etc. (x=1 or 2)
Zone Extension enabling input 2 of pilot distance protection x, it is
triggered from binary input or programmable logic etc. (x=1 or 2)
Zone Extension blocking input 1 of pilot distance protection x, it is
triggered from binary input or programmable logic etc. (x=1 or 2)
Zone Extension blocking input 2 of pilot distance protection x, it is
triggered from binary input or programmable logic etc. (x=1 or 2)
Pilot directional earth-fault protection x enabling input 1, it is triggered
from binary input or programmable logic etc. (x=1 or 2)
Pilot directional earth-fault protection x enabling input 2, it is triggered
from binary input or programmable logic etc. (x=1 or 2)
Pilot directional earth-fault protection x blocking input, it is triggered from
binary input or programmable logic etc. (x=1 or 2)
Input signal of indicating that pilot channel 1 is abnormal for pilot
directional earth-fault protection x (x=1 or 2)
Input signal of indicating that pilot channel 2 is abnormal for pilot
directional earth-fault protection x (x=1 or 2)
Input signal of receiving permissive signal via channel 1 for pilot
directional earth-fault protection x (x=1 or 2)
Input signal of receiving permissive signal via channel 2 for pilot
directional earth-fault protection x (x=1 or 2)
Input signal of initiating sending permissive signal from external tripping
9-8
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Item
Description
signal (x=1 or 2)
158
85-x.Unblocking1
Unblocking signal 1 for pilot directional earth-fault protection x (x=1 or 2)
159
85-x.Unblocking2
Unblocking signal 2 for pilot directional earth-fault protection x (x=1 or 2)
Phase overcurrent protection
160
50/51P1.En1
161
50/51P1.En2
162
50/51P1.Blk
163
50/51P2.En1
164
50/51P2.En2
165
50/51P2.Blk
166
50/51P3.En1
167
50/51P3.En2
168
50/51P3.Blk
169
50/51P4.En1
170
50/51P4.En2
171
50/51P4.Blk
Stage 1 of phase overcurrent protection enabling input 1, it is triggered
from binary input or programmable logic etc.
Stage 1 of phase overcurrent protection enabling input 2, it is triggered
from binary input or programmable logic etc.
Stage 1 of phase overcurrent protection blocking input, it is triggered
from binary input or programmable logic etc.
Stage 2 of phase overcurrent protection enabling input 1, it is triggered
from binary input or programmable logic etc.
Stage 2 of phase overcurrent protection enabling input 2, it is triggered
from binary input or programmable logic etc.
Stage 2 of phase overcurrent protection blocking input, it is triggered
from binary input or programmable logic etc.
Stage 3 of phase overcurrent protection enabling input 1, it is triggered
from binary input or programmable logic etc.
Stage 3 of phase overcurrent protection enabling input 2, it is triggered
from binary input or programmable logic etc.
Stage 3 of phase overcurrent protection blocking input, it is triggered
from binary input or programmable logic etc.
Stage 4 of phase overcurrent protection enabling input 1, it is triggered
from binary input or programmable logic etc.
Stage 4 of phase overcurrent protection enabling input 2, it is triggered
from binary input or programmable logic etc.
Stage 4 of phase overcurrent protection blocking input, it is triggered
from binary input or programmable logic etc.
Earth fault protection
172
50/51G1.En1
173
50/51G1.En2
174
50/51G1.Blk
175
50/51G2.En1
176
50/51G2.En2
177
50/51G2.Blk
178
50/51G2.En_ShortDly
Stage 1 of earth fault protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Stage 1 of earth fault protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Stage 1 of earth fault protection blocking input, it is triggered from binary
input or programmable logic etc.
Stage 2 of earth fault protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Stage 2 of earth fault protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Stage 2 of earth fault protection blocking input, it is triggered from binary
input or programmable logic etc.
Short time delay for stage 2 of earth fault protection enabling input, it is
PCS-902 Line Distance Relay
9-9
Date: 2019-03-01
9 Configurable Function
No.
Item
Description
triggered from binary input or programmable logic etc.
179
50/51G2.Blk_ShortDly
180
50/51G3.En1
181
50/51G3.En2
182
50/51G3.Blk
183
50/51G3.En_ShortDly
184
50/51G3.Blk_ShortDly
185
50/51G4.En1
186
50/51G4.En2
187
50/51G4.Blk
188
50/51G4.En_ShortDly
189
50/51G4.Blk_ShortDly
Short time delay for stage 2 of earth fault protection blocking input, it is
triggered from binary input or programmable logic etc.
Stage 3 of earth fault protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Stage 3 of earth fault protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Stage 3 of earth fault protection blocking input, it is triggered from binary
input or programmable logic etc.
Short time delay for stage 3 of earth fault protection enabling input, it is
triggered from binary input or programmable logic etc.
Short time delay for stage 3 of earth fault protection blocking input, it is
triggered from binary input or programmable logic etc.
Stage 4 of earth fault protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Stage 4 of earth fault protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Stage 4 of earth fault protection blocking input, it is triggered from binary
input or programmable logic etc.
Short time delay for stage 4 of earth fault protection enabling input, it is
triggered from binary input or programmable logic etc.
Short time delay for stage 4 of earth fault protection blocking input, it is
triggered from binary input or programmable logic etc.
Negative-sequence overcurrent protection
190
50/51Q1.En1
191
50/51Q1.En2
192
50/51Q1.Blk
193
50/51Q2.En1
194
50/51Q2.En2
195
50/51Q2.Blk
196
50/51Q3.En1
197
50/51Q3.En2
198
50/51Q3.Blk
Stage 1 of negative-sequence overcurrent protection enabling input 1, it
is triggered from binary input or programmable logic etc.
Stage 1 of negative-sequence overcurrent protection enabling input 2, it
is triggered from binary input or programmable logic etc.
Stage 1 of negative-sequence overcurrent protection blocking input, it is
triggered from binary input or programmable logic etc.
Stage 2 of negative-sequence overcurrent protection enabling input 1, it
is triggered from binary input or programmable logic etc.
Stage 2 of negative-sequence overcurrent protection enabling input 2, it
is triggered from binary input or programmable logic etc.
Stage 2 of negative-sequence overcurrent protection blocking input, it is
triggered from binary input or programmable logic etc.
Stage 3 of negative-sequence overcurrent protection enabling input 1, it
is triggered from binary input or programmable logic etc.
Stage 3 of negative-sequence overcurrent protection enabling input 2, it
is triggered from binary input or programmable logic etc.
Stage 3 of negative-sequence overcurrent protection blocking input, it is
triggered from binary input or programmable logic etc.
9-10
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Item
199
50/51Q4.En1
200
50/51Q4.En2
201
50/51Q4.Blk
Description
Stage 4 of negative-sequence overcurrent protection enabling input 1, it
is triggered from binary input or programmable logic etc.
Stage 4 of negative-sequence overcurrent protection enabling input 2, it
is triggered from binary input or programmable logic etc.
Stage 4 of negative-sequence overcurrent protection blocking input, it is
triggered from binary input or programmable logic etc.
Overcurrent protection for VT circuit failure
202
50PVT1.En1
203
50PVT1.En2
204
50PVT1.Blk
205
50PVT2.En1
206
50PVT2.En2
207
50PVT2.Blk
208
50GVT1.En1
209
50GVT1.En2
210
50GVT1.Blk
211
50GVT2.En1
212
50GVT2.En2
213
50GVT2.Blk
Stage 1 of phase overcurrent protection for VT circuit failure enabling
input 1, it is triggered from binary input or programmable logic etc.
Stage 1 of phase overcurrent protection for VT circuit failure enabling
input 2, it is triggered from binary input or programmable logic etc.
Stage 1 of phase overcurrent protection for VT circuit failure blocking
input, it is triggered from binary input or programmable logic etc.
Stage 2 of phase overcurrent protection for VT circuit failure enabling
input 1, it is triggered from binary input or programmable logic etc.
Stage 2 of phase overcurrent protection for VT circuit failure enabling
input 2, it is triggered from binary input or programmable logic etc.
Stage 2 of phase overcurrent protection for VT circuit failure blocking
input, it is triggered from binary input or programmable logic etc.
Stage 1 of ground overcurrent protection for VT circuit failure enabling
input 1, it is triggered from binary input or programmable logic etc.
Stage 1 of ground overcurrent protection for VT circuit failure enabling
input 2, it is triggered from binary input or programmable logic etc.
Stage 1 of ground overcurrent protection for VT circuit failure blocking
input, it is triggered from binary input or programmable logic etc.
Stage 2 of ground overcurrent protection for VT circuit failure enabling
input 1, it is triggered from binary input or programmable logic etc.
Stage 2 of ground overcurrent protection for VT circuit failure enabling
input 2, it is triggered from binary input or programmable logic etc.
Stage 2 of ground overcurrent protection for VT circuit failure blocking
input, it is triggered from binary input or programmable logic etc.
Phase current SOTF protection
214
50PSOTF.En1
215
50PSOTF.En2
216
50PSOTF.Blk
Phase current SOTF protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Phase current SOTF protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Phase current SOTF protection blocking input, it is triggered from binary
input or programmable logic etc.
Residual SOTF protection
217
50GSOTF.En1
218
50GSOTF.En2
Residual current SOTF protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Residual current SOTF protection enabling input 2, it is triggered from
PCS-902 Line Distance Relay
9-11
Date: 2019-03-01
9 Configurable Function
No.
Item
Description
binary input or programmable logic etc.
219
50GSOTF.Blk
Residual current SOTF protection blocking input, it is triggered from
binary input or programmable logic etc.
Voltage protection
220
59P1.En1
221
59P1.En2
222
59P1.Blk
223
59P2.En1
224
59P2.En2
225
59P2.Blk
226
59P3.En1
227
59P3.En2
228
59P3.Blk
229
59Q.En1
230
59Q.En2
231
59Q.Blk
232
59G1.En1
233
59G1.En2
234
59G1.Blk
235
59G2.En1
236
59G2.En2
237
59G2.Blk
238
59G3.En1
Stage 1 of overvoltage protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Stage 1 of overvoltage protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Stage 1 of overvoltage protection blocking input, it is triggered from
binary input or programmable logic etc.
Stage 2 of overvoltage protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Stage 2 of overvoltage protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Stage 2 of overvoltage protection blocking input, it is triggered from
binary input or programmable logic etc.
Stage 3 of overvoltage protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Stage 3 of overvoltage protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Stage 3 of overvoltage protection blocking input, it is triggered from
binary input or programmable logic etc.
Negative-sequence overvoltage protection enabling input 1, it is
triggered from binary input or programmable logic etc.
Negative-sequence overvoltage protection enabling input 2, it is
triggered from binary input or programmable logic etc.
Negative-sequence overvoltage protection blocking input, it is triggered
from binary input or programmable logic etc.
Stage 1 of residual overvoltage protection enabling input 1, it is triggered
from binary input or programmable logic etc.
Stage 1 of residual overvoltage protection enabling input 2, it is triggered
from binary input or programmable logic etc.
Stage 1 of overvoltage protection blocking input, it is triggered from
binary input or programmable logic etc.)
Stage 2 of residual overvoltage protection enabling input 1, it is triggered
from binary input or programmable logic etc.
Stage 2 of residual overvoltage protection enabling input 2, it is triggered
from binary input or programmable logic etc.
Stage 2 of overvoltage protection blocking input, it is triggered from
binary input or programmable logic etc.)
Stage 3 of residual overvoltage protection enabling input 1, it is triggered
from binary input or programmable logic etc.
9-12
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Item
239
59G3.En2
240
59G3.Blk
241
27P1.En1
242
27P1.En2
243
27P1.Blk
244
27P2.En1
245
27P2.En2
246
27P2.Blk
247
27P3.En1
248
27P3.En2
249
27P3.Blk
Description
Stage 3 of residual overvoltage protection enabling input 2, it is triggered
from binary input or programmable logic etc.
Stage 3 of overvoltage protection blocking input, it is triggered from
binary input or programmable logic etc.)
Stage 1 of undervoltage protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Stage 1 of undervoltage protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Stage 1 of undervoltage protection blocking input, it is triggered from
binary input or programmable logic etc.
Stage 2 of undervoltage protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Stage 2 of undervoltage protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Stage 2 of undervoltage protection blocking input, it is triggered from
binary input or programmable logic etc.
Stage 3 of undervoltage protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Stage 3 of undervoltage protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Stage 3 of undervoltage protection blocking input, it is triggered from
binary input or programmable logic etc.
Frequency protection
250
81O.En1
251
81O.En2
252
81O.Blk
253
81U.En1
254
81U.En2
255
81U.Blk
Overfrequency protection enabling input 1, it is triggered from binary
input or programmable logic etc.
Overfrequency protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Overfrequency protection blocking input, it is triggered from binary input
or programmable logic etc.
Underfrequency protection enabling input 1, it is triggered from binary
input or programmable logic etc.
Underfrequency protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Underfrequency protection blocking input, it is triggered from binary input
or programmable logic etc.
Breaker failure protection
256
CBx.50BF.ExTrp3P_L
Input signal of three-phase tripping contact from line protection
257
CBx.50BF.ExTrp3P_GT
258
CBx.50BF.ExTrpA
Input signal of phase-A tripping contact from external device
259
CBx.50BF.ExTrpB
Input signal of phase-B tripping contact from external device
260
CBx.50BF.ExTrpC
Input signal of phase-C tripping contact from external device
Input signal of three-phase tripping contact from generator or
transformer protection
PCS-902 Line Distance Relay
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Date: 2019-03-01
9 Configurable Function
No.
Item
Description
Input signal of three-phase tripping contact from external device. Once it
261
CBx.50BF.ExTrp_WOI
is energized, normally closed auxiliary contact of circuit breaker is
chosen in addition to breaker failure current check to trigger breaker
failure timers.
262
CBx.50BF.En
Input signal of enabling breaker failure protection
Breaker failure protection blocking input, such as function blocking
263
CBx.50BF.Blk
binary input.
When the input is 1, breaker failure protection is reset and time delay is
cleared.
Thermal overload protection
264
49.Clr_Cmd
265
49.En
266
49.Blk
Input signal of clear thermal accumulation value
Thermal overload protection enabling input, it is triggered from binary
input or programmable logic etc.
Thermal overload protection blocking input, it is triggered from binary
input or programmable logic etc.
Stub differential protection
267
87STB.En1
268
87STB.En2
269
87STB.Blk
270
87STB.89b_DS
271
87STB.89b_DS_Rmt
Stub differential protection enabling input 1, it is triggered from binary
input or programmable logic etc.
Stub differential protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Stub differential protection blocking input, it is triggered from binary input
or programmable logic etc.
Normally closed auxiliary contact of line disconnector
Normally closed auxiliary contact of line disconnector in remote end
In general, it is configured as receiving the signal [87STB.On_Local]
from the remote end.
Dead zone protection
272
CBx.50DZ.En1
273
CBx.50DZ.En2
Dead zone protection enabling input 1, it can be binary inputs or logic
link.
Dead zone protection enabling input 2, it can be binary inputs or logic
link.
Dead zone protection blocking input, such as function blocking binary
274
CBx.50DZ.Blk
input. When the input is 1, dead zone protection is reset and time delay
is cleared.
275
CBx.50DZ.Init
Initiation signal input of the dead zone protection.
Pole discrepancy protection
276
CBx.62PD.En1
277
CBx.62PD.En2
278
CBx.62PD.Blk
Pole discrepancy protection enabling input 1, it is triggered from binary
input or programmable logic etc.
Pole discrepancy protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Pole discrepancy protection blocking input, it is triggered from binary
input or programmable logic etc.
9-14
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Item
Description
Broken conductor protection
279
46BC.En1
280
46BC.En2
281
46BC.Blk
Enable broken conductor protection input 1, it is triggered from binary
input or programmable logic etc.
Enable broken conductor protection input 2, it is triggered from binary
input or programmable logic etc.
Broken conductor protection blocking input, it is triggered from binary
input or programmable logic etc.
Reverse power protection
282
32R1.En
283
32R1.Blk
284
32R2.En
285
32R2.Blk
Enable stage 1 of reverse power protection input 1, it is triggered from
binary input or programmable logic etc.
Stage 1 of reverse power protection blocking input, it is triggered from
binary input or programmable logic etc.
Enable stage 2 of reverse power protection input 2, it is triggered from
binary input or programmable logic etc.
Stage 2 of reverse power protection blocking input, it is triggered from
binary input or programmable logic etc.
Synchrocheck
286
CBx.25.Blk_Chk
Input signal of blocking synchrocheck function for AR.
287
CBx.25.Blk_SynChk
288
CBx.25.Blk_DdChk
289
CBx.25.Start_Chk
290
CBx.25.Start_3PLvChk
291
CBx.25.Sel_SynChk
Synchronism check is selected.
292
CBx.25.Sel_DdL_DdB
Dead line and dead bus check is selected.
293
CBx.25.Sel_DdL_LvB
Dead line and live bus check is selected.
294
CBx.25.Sel_LvL_DdB
Live line and live bus check is selected.
295
CBx.25.Sel_NoChk
No check is selected.
296
CBx.25.Blk_VTS_Usyn
VT circuit supervision (Usyn) is blocked
297
CBx.25.Blk_VTS_Uref
VT circuit supervision (Uref) is blocked
298
25.MCB_VT_UL1
Binary input for VT MCB auxiliary contact (UL1)
299
25.MCB_VT_UL2
Binary input for VT MCB auxiliary contact (UL2)
300
25.MCB_VT_UB1
Binary input for VT MCB auxiliary contact (UB1)
301
25.MCB_VT_UB2
Binary input for VT MCB auxiliary contact (UB2)
302
25.NC_UL1DS
Normally closed contact of disconnector (UL1)
303
25.NO_UL1DS
Normally open contact of disconnector (UL1)
304
25.NC_UB1DS
Normally closed contact of disconnector (UB1)
305
25.NO_UB1DS
Normally open contact of disconnector (UB1)
306
25.NC_UL2DS
Normally closed contact of disconnector (UL2)
307
25.NO_UL2DS
Normally open contact of disconnector (UL2)
Input signal of blocking synchronism check for AR. If the value is “1”, the
output of synchronism check is “0”.
Input signal of blocking dead charge check for AR.
Input signal of starting synchronism check, usually it was starting signal
of AR from auto-reclosing module.
Input signal of starting live three-phase check, usually it was starting
signal of 1-pole AR
PCS-902 Line Distance Relay
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Date: 2019-03-01
9 Configurable Function
No.
Item
Description
308
25.NC_UB2DS
Normally closed contact of disconnector (UB2)
309
25.NO_UB2DS
Normally open contact of disconnector (UB2)
Auto-reclosing
Binary input for enabling AR. If the logic setting [79.En_ExtCtrl]=1,
310
CBx.79.En
311
CBx.79.Blk
312
CBx.79.Sel_1PAR
313
CBx.79.Sel_3PAR
314
CBx.79.Sel_1P/3PAR
315
CBx.79.Trp
Input signal of single-phase tripping from line protection to initiate AR
316
CBx.79.Trp3P
Input signal of three-phase tripping from line protection to initiate AR
317
CBx.79.TrpA
Input signal of A-phase tripping from line protection to initiate AR
318
CBx.79.TrpB
Input signal of B-phase tripping from line protection to initiate AR
319
CBx.79.TrpC
Input signal of C-phase tripping from line protection to initiate AR
enabling AR will be controlled by the external signal via binary input
Binary input for disabling AR. If the logic setting [79.En_ExtCtrl]=1,
disabling AR will be controlled by the external input
Input signal for selecting 1-pole AR mode of corresponding circuit
breaker
Input signal for selecting 3-pole AR mode of corresponding circuit
breaker
Input signal for selecting 1/3-pole AR mode of corresponding circuit
breaker
Input signal of blocking reclosing, usually it is connected with the
320
CBx.79.LockOut
operating signals of definite-time protection, transformer protection and
busbar differential protection, etc.
321
CBx.79.PLC_Lost
Input signal of indicating the alarm signal that signal channel is lost
322
CBx.79.WaitMaster
323
CBx.79.CB_Healthy
324
CBx.79.Clr_Counter
Clear the reclosing counter
325
CBx.79.Ok_Chk
Synchrocheck condition of AR is met
326
CBx.79.Ok_3PLvChk
Live three-phase check condition of AR is met
Input signal of waiting for reclosing permissive signal from master AR
(when reclosing multiple circuit breakers)
The input for indicating whether circuit breaker has enough energy to
perform the close function
Transfer trip
327
TT.Init
328
TT.En
329
TT.Blk
Input signal of initiating transfer trip after receiving transfer trip
Transfer trip enabling input, it is triggered from binary input or
programmable logic etc.
Transfer trip blocking input, it is triggered from binary input or
programmable logic etc.
Trip logic
330
Line.Enable
Input signal of enabling line trip logic
331
Line.Block
Input signal of blocking line trip logic
332
CBx.TRP.En
Trip enabling input, it is triggered from binary input or programmable
logic etc.
333
CBx.TRP.Blk
Trip blocking input, it is triggered from binary input or programmable
9-16
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Item
Description
logic etc.
Input signal of permitting three-phase tripping
334
CBx.PrepTrp3P
When this signal is valid, three-phase tripping will be adopted for any
kind of faults.
VT circuit supervision
335
VTS.En
336
VTS.Blk
337
VTNS.En
338
VTNS.Blk
339
VTS.MCB_VT
VT supervision enabling input, it is triggered from binary input or
programmable logic etc.
VT supervision blocking input, it is triggered from binary input or
programmable logic etc.
VT neutral point supervision enabling input, it is triggered from binary
input or programmable logic etc.
VT neutral point supervision blocking input, it is triggered from binary
input or programmable logic etc.
Binary input for VT MCB auxiliary contact
CT circuit supervision
340
CBx.CTS.En
341
CBx.CTS.Blk
CT circuit supervision enabling input, it is triggered from binary input or
programmable logic etc.
CT circuit supervision blocking input, it is triggered from binary input or
programmable logic etc.
Control and synchrocheck for manual closing
From receiving a closing command, this device will continuously check
whether the 2 voltages (Incoming voltage and reference voltage)
involved in synchronism check (or dead check) can meet the criteria.
342
MCBrd.CBx.25.Ok_Chk
Within the duration of [MCBrd.CBx.25.t_Wait_Chk], if the synchronism
check (or dead check) criteria are not met, [MCBrd.CBx.25.Ok_Chk] will
be set as “0”; if the synchronism check (or dead check) criteria are met,
[MCBrd.CBx.25.Ok_Chk] will be set as “1”.
343
CSWI01.CILO.EnOpn
344
CSWI01.CILO.EnCls
345
CSWI01.LocCtrl
It is used to indicate the interlock status of open output for binary output
No.01.
It is used to indicate the interlock status of closing output for binary
output No.01.
It is used to select the local control to binary output No.01. When the
local control is active, binary output No.01 can only be locally controlled.
It is used to select the remote control to binary output No.01. When the
346
CSWI01.RmtCtrl
remote control is active, binary output No.01 can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
347
CSWI01.CILO.Disable
the signal “CSWI01.CILO.Disable” is “1”, binary output No.01 will not be
blocked by interlock conditions.
348
CSWI02.CILO.EnOpn
349
CSWI02.CILO.EnCls
It is used to indicate the interlock status of open output for binary output
No.02.
It is used to indicate the interlock status of closing output for binary
PCS-902 Line Distance Relay
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Date: 2019-03-01
9 Configurable Function
No.
Item
Description
output No.02.
350
CSWI02.LocCtrl
It is used to select the local control to binary output No.02. When the
local control is active, binary output No.02 can only be locally controlled.
It is used to select the remote control to binary output No.02. When the
351
CSWI02.RmtCtrl
remote control is active, binary output No.02 can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
352
CSWI02.CILO.Disable
the signal “CSWI02.CILO.Disable” is “1”, binary output No.02 will not be
blocked by interlock conditions.
353
CSWI03.CILO.EnOpn
354
CSWI03.CILO.EnCls
355
CSWI03.LocCtrl
It is used to indicate the interlock status of open output for binary output
No.03.
It is used to indicate the interlock status of closing output for binary
output No.03.
It is used to select the local control to binary output No.03. When the
local control is active, binary output No.03 can only be locally controlled.
It is used to select the remote control to binary output No.03. When the
356
CSWI03.RmtCtrl
remote control is active, binary output No.03 can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
357
CSWI03.CILO.Disable
the signal “CSWI03.CILO.Disable” is “1”, binary output No.03 will not be
blocked by interlock conditions.
358
CSWI04.CILO.EnOpn
359
CSWI04.CILO.EnCls
360
CSWI04.LocCtrl
It is used to indicate the interlock status of open output for binary output
No.05.
It is used to indicate the interlock status of closing output for binary
output No.05.
It is used to select the local control to binary output No.04. When the
local control is active, binary output No.04 can only be locally controlled.
It is used to select the remote control to binary output No.04. When the
361
CSWI04.RmtCtrl
remote control is active, binary output No.04 can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
362
CSWI04.CILO.Disable
the signal “CSWI04.CILO.Disable” is “1”, binary output No.04 will not be
blocked by interlock conditions.
363
CSWI05.CILO.EnOpn
364
CSWI05.CILO.EnCls
365
CSWI05.LocCtrl
It is used to indicate the interlock status of open output for binary output
No.05.
It is used to indicate the interlock status of closing output for binary
output No.05.
It is used to select the local control to binary output No.05. When the
local control is active, binary output No.05 can only be locally controlled.
It is used to select the remote control to binary output No.05. When the
366
CSWI05.RmtCtrl
remote control is active, binary output No.05 can only be remotely
controlled from SCADA or control centers.
9-18
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Item
Description
It is used to disable the interlock blocking function for control output. If
367
CSWI05.CILO.Disable
the signal “CSWI05.CILO.Disable” is “1”, binary output No.05 will not be
blocked by interlock conditions.
368
CSWI06.CILO.EnOpn
369
CSWI06.CILO.EnCls
370
CSWI06.LocCtrl
It is used to indicate the interlock status of open output for binary output
No.06.
It is used to indicate the interlock status of closing output for binary
output No.06.
It is used to select the local control to binary output No.06. When the
local control is active, binary output No.01 can only be locally controlled.
It is used to select the remote control to binary output No.06. When the
371
CSWI06.RmtCtrl
remote control is active, binary output No.06 can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
372
CSWI06.CILO.Disable
the signal “CSWI06.CILO.Disable” is “1”, binary output No.06 will not be
blocked by interlock conditions.
373
CSWI07.CILO.EnOpn
374
CSWI07.CILO.EnCls
375
CSWI07.LocCtrl
It is used to indicate the interlock status of open output for binary output
No.07.
It is used to indicate the interlock status of closing output for binary
output No.07.
It is used to select the local control to binary output No.07. When the
local control is active, binary output No.07 can only be locally controlled.
It is used to select the remote control to binary output No.07. When the
376
CSWI07.RmtCtrl
remote control is active, binary output No.07 can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
377
CSWI07.CILO.Disable
the signal “CSWI07.CILO.Disable” is “1”, binary output No.07 will not be
blocked by interlock conditions.
378
CSWI08.CILO.EnOpn
379
CSWI08.CILO.EnCls
380
CSWI08.LocCtrl
It is used to indicate the interlock status of open output for binary output
No.08.
It is used to indicate the interlock status of closing output for binary
output No.08.
It is used to select the local control to binary output No.08. When the
local control is active, binary output No.08 can only be locally controlled.
It is used to select the remote control to binary output No.08. When the
381
CSWI08.RmtCtrl
remote control is active, binary output No.08 can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
382
CSWI08.CILO.Disable
the signal “CSWI08.CILO.Disable” is “1”, binary output No.08 will not be
blocked by interlock conditions.
383
CSWI09.CILO.EnOpn
384
CSWI09.CILO.EnCls
It is used to indicate the interlock status of open output for binary output
No.09.
It is used to indicate the interlock status of closing output for binary
output No.09.
PCS-902 Line Distance Relay
9-19
Date: 2019-03-01
9 Configurable Function
No.
385
Item
CSWI09.LocCtrl
Description
It is used to select the local control to binary output No.09. When the
local control is active, binary output No.09 can only be locally controlled.
It is used to select the remote control to binary output No.09. When the
386
CSWI09.RmtCtrl
remote control is active, binary output No.09 can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
387
CSWI09.CILO.Disable
the signal “CSWI09.CILO.Disable” is “1”, binary output No.09 will not be
blocked by interlock conditions.
388
CSWI10.CILO.EnOpn
389
CSWI10.CILO.EnCls
390
CSWI10.LocCtrl
It is used to indicate the interlock status of open output for binary output
No.10.
It is used to indicate the interlock status of closing output for binary
output No.10.
It is used to select the local control to binary output No.10. When the
local control is active, binary output No.10 can only be locally controlled.
It is used to select the remote control to binary output No.10. When the
391
CSWI10.RmtCtrl
remote control is active, binary output No.10 can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
392
CSWI10.CILO.Disable
the signal “CSWI10.CILO.Disable” is “1”, binary output No.10 will not be
blocked by interlock conditions.
393
CSWI11.CILO.EnOpn
394
CSWI11.CILO.EnCls
395
CSWI11.LocCtrl
It is used to indicate the interlock status of open output for binary output
No.11.
It is used to indicate the interlock status of closing output for binary
output No.11.
It is used to select the local control to binary output No.11. When the
local control is active, binary output No.11 can only be locally controlled.
It is used to select the remote control to binary output No.11. When the
396
CSWI11.RmtCtrl
remote control is active, binary output No.11 can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
397
CSWI11.CILO.Disable
the signal “CSWI11.CILO.Disable” is “1”, binary output No.11 will not be
blocked by interlock conditions.
398
CSWI12.CILO.EnOpn
399
CSWI12.CILO.EnCls
400
CSWI12.LocCtrl
It is used to indicate the interlock status of open output for binary output
No.12.
It is used to indicate the interlock status of closing output for binary
output No.12.
It is used to select the local control to binary output No.12. When the
local control is active, binary output No.12 can only be locally controlled.
It is used to select the remote control to binary output No.12. When the
401
CSWI12.RmtCtrl
remote control is active, binary output No.12 can only be remotely
controlled from SCADA or control centers.
402
CSWI12.CILO.Disable
It is used to disable the interlock blocking function for control output. If
the signal “CSWI12.CILO.Disable” is “1”, binary output No.12 will not be
9-20
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Item
Description
blocked by interlock conditions.
403
CSWI13.CILO.EnOpn
404
CSWI13.CILO.EnCls
405
CSWI13.LocCtrl
It is used to indicate the interlock status of open output for binary output
No.13.
It is used to indicate the interlock status of closing output for binary
output No.13.
It is used to select the local control to binary output No.13. When the
local control is active, binary output No.13 can only be locally controlled.
It is used to select the remote control to binary output No.13. When the
406
CSWI13.RmtCtrl
remote control is active, binary output No.13 can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
407
CSWI13.CILO.Disable
the signal “CSWI13.CILO.Disable” is “1”, binary output No.13 will not be
blocked by interlock conditions.
408
CSWI14.CILO.EnOpn
409
CSWI14.CILO.EnCls
410
CSWI14.LocCtrl
It is used to indicate the interlock status of open output for binary output
No.14.
It is used to indicate the interlock status of closing output for binary
output No.14.
It is used to select the local control to binary output No.14. When the
local control is active, binary output No.14 can only be locally controlled.
It is used to select the remote control to binary output No.14. When the
411
CSWI14.RmtCtrl
remote control is active, binary output No.14 can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
412
CSWI14.CILO.Disable
the signal “CSWI14.CILO.Disable” is “1”, binary output No.14 will not be
blocked by interlock conditions.
413
CSWI15.CILO.EnOpn
414
CSWI15.CILO.EnCls
415
CSWI15.LocCtrl
It is used to indicate the interlock status of open output for binary output
No.15.
It is used to indicate the interlock status of closing output for binary
output No.15.
It is used to select the local control to binary output No.15. When the
local control is active, binary output No.15 can only be locally controlled.
It is used to select the remote control to binary output No.15. When the
416
CSWI15.RmtCtrl
remote control is active, binary output No.15 can only be remotely
controlled from SCADA or control centers.
It is used to disable the interlock blocking function for control output. If
417
CSWI15.CILO.Disable
the signal “CSWI15.CILO.Disable” is “1”, binary output No.15 will not be
blocked by interlock conditions.
418
BIinput.LocCtrl
It is used to select the local control to all binary outputs. When the local
control is active, all binary outputs can only be locally controlled.
It is used to select the remote control to all binary outputs. When the
419
BIinput.RmtCtrl
remote control is active, all binary outputs can only be remotely
controlled from SCADA or control centers.
PCS-902 Line Distance Relay
9-21
Date: 2019-03-01
9 Configurable Function
No.
Item
Description
It is used to disable the interlock blocking function for control output. If
420
BIinput.CILO.Disable
the signal “BIinput.CILO.Disable” is “1”, all binary outputs will not be
blocked by interlock conditions.
When the condition of local
421
CSWI01.ManSynCls
control is met
and the signal
“CSWI01.ManSynCls” is “1”, the output contact [BO_CtrlCls01] is closed
to execute manually closing the circuit breaker with synchrocheck.
When the condition of local
422
CSWI01.ManOpn
control is met
and the signal
“CSWI01.ManOpn” is “1”, the output contact [BO_CtrlOpn01] is closed to
execute manually open the circuit breaker.
When the condition of local
423
CSWI02.ManSynCls
control is met
and the signal
“CSWI02.ManSynCls” is “1”, the output contact [BO_CtrlCls02] is closed
to execute manually closing the circuit breaker with synchrocheck. (for
double circuit breakers application)
When the condition of local
424
CSWI02.ManOpn
control is met
and the signal
“CSWI02.ManOpn” is “1”, the output contact [BO_CtrlOpn02] is closed to
execute manually open the circuit breaker. (for double circuit breakers
application)
425
MCBrd.CBx.25.Sel_SynChk
Synchronism check for manual closing is selected.
426
MCBrd.CBx.25.Sel_NoChk
No check for manual closing is selected.
9.3.2 Output Signal
All output signals of this device have been listed in the following table.
Table 9.3-2 Output signals
No.
Signal
Description
Circuit breaker position supervision
1
CBx.Alm_52b
Circuit breaker No.x position is abnormal
2
CBx.TCCS.Alm
Control circuit of circuit breaker No.x is abnormal
Fault detector
3
FD.Pkp
The device picks up
4
FD.DPFC.Pkp
DPFC current fault detector element operates.
5
FD.ROC.Pkp
Residual current fault detector element operates.
6
FD.NOC.Pkp
Negative-sequence fault detector element operates.
Auxiliary element
7
AuxE.St
Any auxiliary element of the device operates.
8
AuxE.OCD.St_DDO
Current change auxiliary element operates.
9
AuxE.OCD.On
Current change auxiliary element is enabled.
10
AuxE.ROC1.St
Stage 1 of residual current auxiliary element operates.
11
AuxE.ROC1.On
Stage 1 of residual current auxiliary element is enabled.
12
AuxE.ROC2.St
Stage 2 of residual current auxiliary element operates.
13
AuxE.ROC2.On
Stage 2 of residual current auxiliary element is enabled.
14
AuxE.ROC3.St
Stage 3 of residual current auxiliary element operates.
9-22
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Signal
Description
15
AuxE.ROC3.On
Stage 3 of residual current auxiliary element is enabled.
16
AuxE.OC1.St
Stage 1 of phase current auxiliary element operates.
17
AuxE.OC1.StA
Stage 1 of phase current auxiliary element operates (phase A).
18
AuxE.OC1.StB
Stage 1 of phase current auxiliary element operates (phase B).
19
AuxE.OC1.StC
Stage 1 of phase current auxiliary element operates (phase C).
20
AuxE.OC1.On
Stage 1 of phase current auxiliary element is enabled.
21
AuxE.OC2.St
Stage 2 of phase current auxiliary element operates.
22
AuxE.OC2.StA
Stage 2 of phase current auxiliary element operates (phase A).
23
AuxE.OC2.StB
Stage 2 of phase current auxiliary element operates (phase B).
24
AuxE.OC2.StC
Stage 2 of phase current auxiliary element operates (phase C).
25
AuxE.OC2.On
Stage 2 of phase current auxiliary element is enabled.
26
AuxE.OC3.St
Stage 3 of phase current auxiliary element operates.
27
AuxE.OC3.StA
Stage 1 of phase current auxiliary element operates (phase A).
28
AuxE.OC3.StB
Stage 1 of phase current auxiliary element operates (phase B).
29
AuxE.OC3.StC
Stage 1 of phase current auxiliary element operates (phase C).
30
AuxE.OC3.On
Stage 3 of phase current auxiliary element is enabled.
31
AuxE.UVD.St
Voltage change auxiliary element operates.
32
AuxE.UVD.St_DDO
Voltage change auxiliary element operates.
33
AuxE.UVD.On
Voltage change auxiliary element is enabled.
34
AuxE.UVG.St
Phase-to-ground under voltage auxiliary element operates.
35
AuxE.UVG.StA
Phase-to-ground under voltage auxiliary element operates (phase A).
36
AuxE.UVG.StB
Phase-to-ground under voltage auxiliary element operates (phase B).
37
AuxE.UVG.StC
Phase-to-ground under voltage auxiliary element operates (phase C).
38
AuxE.UVG.On
Phase-to-ground under voltage auxiliary element is enabled.
39
AuxE.UVS.St
Phase-to-phase under voltage auxiliary element operates.
40
AuxE.UVS.StAB
Phase-to-phase under voltage auxiliary element operates (phase AB).
41
AuxE.UVS.StBC
Phase-to-phase under voltage auxiliary element operates (phase BC).
42
AuxE.UVS.StCA
Phase-to-phase under voltage auxiliary element operates (phase CA).
43
AuxE.UVS.On
Phase-to-phase under voltage auxiliary element is enabled.
44
AuxE.ROV.St
Residual voltage auxiliary element operates.
45
AuxE.ROV.On
Residual voltage auxiliary element is enabled.
Distance protection
46
21D.Op
DPFC distance protection operates.
47
21D.On
DPFC distance protection is enabled.
48
LoadEnch.St
Measured impedance into the load area
49
LoadEnch.On
Load trapezoid characteristic is enabled.
50
21M1.On
Zone 1 of distance protection is enabled
51
21M1.Op
Zone 1 of distance protection operates
52
21Q1.On
Zone 1 of distance protection is enabled
53
21Q1.Op
Zone 1 of distance protection operates
54
21M2.On
Zone 2 of distance protection is enabled
55
21M2.Op
Zone 2 of distance protection operates
PCS-902 Line Distance Relay
9-23
Date: 2019-03-01
9 Configurable Function
No.
Signal
Description
56
21Q2.On
Zone 2 of distance protection is enabled
57
21Q2.Op
Zone 2 of distance protection operates
58
21M3.On
Zone 3 of distance protection is enabled
59
21M3.Op
Zone 3 of distance protection operates
60
21Q3.On
Zone 3 of distance protection is enabled
61
21Q3.Op
Zone 3 of distance protection operates
62
21M4.On
Zone 4 of distance protection is enabled
63
21M4.Op
Zone 4 of distance protection operates
64
21Q4.On
Zone 4 of distance protection is enabled
65
21Q4.Op
Zone 4 of distance protection operates
66
21M5.On
Zone 5 of distance protection is enabled
67
21M5.Op
Zone 5 of distance protection operates
68
21Q5.On
Zone 5 of distance protection is enabled
69
21Q5.Op
Zone 5 of distance protection operates
70
78.On
Out-of-step protection is enabled.
71
78.St
Out-of-step protection starts.
72
78.St_Zone
Zone detector element of out-of-step protection starts.
73
78.Op
Out-of-step protection operates.
74
21M1.Rls_PSBR
PSBR operates to release zone 1 (Mho characteristic)
75
21Q1.Rls_PSBR
PSBR operates to release zone 1 (Quad characteristic)
76
21M2.Rls_PSBR
PSBR operates to release zone 2 (Mho characteristic)
77
21Q2.Rls_PSBR
PSBR operates to release zone 2 (Quad characteristic)
78
21M3.Rls_PSBR
PSBR operates to release zone 3 (Mho characteristic)
79
21Q3.Rls_PSBR
PSBR operates to release zone 3 (Quad characteristic)
80
21M4.Rls_PSBR
PSBR operates to release zone 4 (Mho characteristic)
81
21Q4.Rls_PSBR
PSBR operates to release zone 4 (Quad characteristic)
82
21M5.Rls_PSBR
PSBR operates to release zone 5 (Mho characteristic)
83
21Q5.Rls_PSBR
PSBR operates to release zone 5 (Quad characteristic)
84
21M.Pilot.Rls_PSBR
PSBR operates to release pilot distance zone (Mho characteristic)
85
21Q.Pilot.Rls_PSBR
PSBR operates to release pilot distance zone (Quad characteristic)
86
21SOTF.Op
87
21SOTF.On
88
21SOTF.Op_PDF
Accelerate distance protection to trip when manual closing or
auto-reclosing to fault
Accelerate distance protection is enabled.
Accelerate distance protection to trip when another fault happening
under pole discrepancy conditions
Optical pilot channel
89
FOx.On
Channel x is enabled.
90
FOx.Recv1
Receiving signal 1 of channel x
91
FOx.Recv2
Receiving signal 2 of channel x
92
FOx.Recv3
Receiving signal 3 of channel x
93
FOx.Recv4
Receiving signal 4 of channel x
94
FOx.Recv5
Receiving signal 5 of channel x
9-24
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Signal
Description
95
FOx.Recv6
Receiving signal 6 of channel x
96
FOx.Recv7
Receiving signal 7 of channel x
97
FOx.Recv8
Receiving signal 8 of channel x
Receiving signal 9 of channel x (it is configured by fault as receiving
98
permissive signal via channel No.1, or receiving permissive signal of
FOx.Recv9
A-phase via channel No.1 (only for phase-segregated command
scheme))
Receiving signal 10 of channel x (it is configured by fault as receiving
99
FOx.Recv10
permissive
signal
of
B-phase
via
channel
No.1
(only
for
phase-segregated command scheme))
Receiving signal 11 of channel x (it is configured by fault as receiving
100
FOx.Recv11
permissive
signal
of
C-phase
via
channel
No.1
(only
for
phase-segregated command scheme))
Receiving signal 12 of channel x (it is configured by fault as receiving
101
FOx.Recv12
permissive signal 2 only for pilot directional earth-fault protection
adopting independent pilot channel 2)
102
FOx.Alm
Channel x is abnormal
103
FOx.Alm_ID
Received ID from the remote end is not as same as the setting
[FO.RmtID] of the device in local end
Pilot distance protection and pilot directional earth-fault protection
104
85-x.Z.On
105
85-x.ZX.On
106
85-x.Op_Z
107
85.Z.On
108
85.ZX.On
109
85.Op_Z
Pilot distance protection x is enabled. (x=1 or 2)
Zone extension protection of pilot distance protection x is enabled.
(x=1 or 2)
Pilot distance protection x operates. (x=1 or 2)
General pilot distance protection is enabled. Which is OR operation
between 85-1.Z.On and 85-2.Z.On
General zone extension protection is enabled, which is OR operation
between 85-1.ZX.On and 85-2.ZX.On
General pilot distance protection operates, which is OR operation
between 85-1.Op_Z and 85-2. Op_Z
Output signal of sending permissive signal 1 or sending A-phase
110
85-x.Send1
permissive
signal
of
pilot
distance
protection
x
(only
for
phase-segregated command scheme, x=1 or 2)
111
85-x.SendB
112
85-x.SendC
113
85-x.Op_ZX
114
85-x.ZX_St
115
85-x.Z.FwdDir
Output signal of sending B-phase permissive signal of pilot distance
protection x (only for phase-segregated command scheme, x=1 or 2)
Output signal of sending C-phase permissive signal of pilot distance
protection x (only for phase-segregated command scheme, x=1 or 2)
Zone extension protection of pilot distance protection x operates. (x=1
or 2)
Zone extension protection of pilot distance protection x starts (x=1 or
2)
Forward direction signal of pilot distance protection x (x=1 or 2)
PCS-902 Line Distance Relay
9-25
Date: 2019-03-01
9 Configurable Function
No.
Signal
Description
116
85-x.Z.RevDir
Reverse direction signal of pilot distance protection x (x=1 or 2)
117
85-x.DEF.FwdDir
118
85-x.DEF.RevDir
119
85-x.WI
120
85-x.UV_WI
121
85.DEF.On
122
85.Op_DEF
123
85.DEF_BlkAR
124
85-x.DEF.On
Pilot directional earth-fault protection x is enabled. (x=1 or 2)
125
85-x.Op_DEF
Pilot directional earth-fault protection x operates. (x=1 or 2)
126
85-x.DEF_BlkAR
Forward direction signal of pilot directional earth-fault protection x (x=1
or 2)
Reverse direction signal of pilot directional earth-fault protection x (x=1
or 2)
Operation signal of weak infeed logic of pilot distance protection x (x=1
or 2)
Undervoltage signal of weak infeed logic of pilot distance protection x
(x=1 or 2)
General pilot directional earth-fault protection is enabled. It is OR
operation between 85-1.DEF.On and 85-2.DEF.On
General pilot directional earth-fault protection operates. It is OR
operation between 85-1.Op_DEF and 85-2.Op_DEF
General pilot directional earth-fault protection operates to block AR. It
is OR operation between 85-1.DEF_BlkAR and 85-2.DEF_BlkAR
Pilot directional earth-fault protection x operates to block AR. (x=1 or
2)
Output signal of sending permissive signal 1 for pilot directional
127
85-x.Send1
earth-fault protection x when pilot directional earth-fault protection
sharing pilot channel 1 with pilot distance protection (x=1 or 2)
Output signal of sending permissive signal 2 for pilot directional
128
85-x.Send2
earth-fault protection x when pilot directional earth-fault protection
adopting independent pilot channel 2 (x=1 or 2)
Current direction
129
FwdDir_ROC
The forward direction of zero-sequence power
130
RevDir_ROC
The reverse direction of zero-sequence power
131
FwdDir_NegOC
The forward direction of negative-sequence power
132
RevDir_NegOC
The reverse direction of negative-sequence power
133
FwdDir_A
The forward direction of phase-A current
134
FwdDir_B
The forward direction of phase-B current
135
FwdDir_C
The forward direction of phase-C current
136
RevDir_A
The reverse direction of phase-A current
137
RevDir_B
The reverse direction of phase-B current
138
RevDir_C
The reverse direction of phase-C current
139
FwdDir_AB
The forward direction of phase-AB current
140
FwdDir_BC
The forward direction of phase-BC current
141
FwdDir_CA
The forward direction of phase-CA current
142
RevDir_AB
The reverse direction of phase-AB current
143
RevDir_BC
The reverse direction of phase-BC current
144
RevDir_CA
The reverse direction of phase-CA current
9-26
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Signal
Description
Phase overcurrent protection
145
50/51P1.On
Stage x of phase overcurrent protection is enabled.
146
50/51P1.Op
Stage x of phase overcurrent protection operates.
147
50/51P1.St
Stage x of phase overcurrent protection starts.
148
50/51P1.StA
Stage x of phase overcurrent protection starts (A-Phase).
149
50/51P1.StB
Stage x of phase overcurrent protection starts (B-Phase).
150
50/51P1.StC
Stage x of phase overcurrent protection starts (C-Phase).
151
50/51P2.On
Stage x of phase overcurrent protection is enabled.
152
50/51P2.Op
Stage x of phase overcurrent protection operates.
153
50/51P2.St
Stage x of phase overcurrent protection starts.
154
50/51P2.StA
Stage x of phase overcurrent protection starts (A-Phase).
155
50/51P2.StB
Stage 2 of phase overcurrent protection starts (B-Phase).
156
50/51P2.StC
Stage 2 of phase overcurrent protection starts (C-Phase).
157
50/51P3.On
Stage 3 of phase overcurrent protection is enabled.
158
50/51P3.Op
Stage 3 of phase overcurrent protection operates.
159
50/51P3.St
Stage 3 of phase overcurrent protection starts.
160
50/51P3.StA
Stage 3 of phase overcurrent protection starts (A-Phase).
161
50/51P3.StB
Stage 3 of phase overcurrent protection starts (B-Phase).
162
50/51P3.StC
Stage 3 of phase overcurrent protection starts (C-Phase).
163
50/51P4.On
Stage 4 of phase overcurrent protection is enabled.
164
50/51P4.Op
Stage 4 of phase overcurrent protection operates.
165
50/51P4.St
Stage 4 of phase overcurrent protection starts.
166
50/51P4.StA
Stage 4 of phase overcurrent protection starts (A-Phase).
167
50/51P4.StB
Stage 4 of phase overcurrent protection starts (B-Phase).
168
50/51P4.StC
Stage 4 of phase overcurrent protection starts (C-Phase).
Earth fault protection
169
50/51G1.On
Stage 1 of earth fault protection is enabled.
170
50/51G1.St
Stage 1 of earth fault protection starts.
171
50/51G1.Op
Stage 1 of earth fault protection operates.
172
50/51G2.On
Stage 2 of earth fault protection is enabled.
173
50/51G2.On_ShortDly
Short time delay for stage 2 of earth fault protection is enabled.
174
50/51G2.St
Stage 2 of earth fault protection starts.
175
50/51G2.Op
Stage 2 of earth fault protection operates.
176
50/51G3.On
Stage 3 of earth fault protection is enabled.
177
50/51G3.On_ShortDly
Short time delay for stage 3 of earth fault protection is enabled.
178
50/51G3.St
Stage 3 of earth fault protection starts.
179
50/51G3.Op
Stage 3 of earth fault protection operates.
180
50/51G4.On
Stage 4 of earth fault protection is enabled.
181
50/51G4.On_ShortDly
Short time delay for stage 4 of earth fault protection is enabled.
182
50/51G4.St
Stage 4 of earth fault protection starts.
183
50/51G4.Op
Stage 4 of earth fault protection operates.
Negative-sequence overcurrent protection
PCS-902 Line Distance Relay
9-27
Date: 2019-03-01
9 Configurable Function
No.
Signal
Description
184
50/51Q1.On
Stage 1 of negative-sequence overcurrent protection is enabled.
185
50/51Q1.St
Stage 1 of negative-sequence overcurrent protection starts.
186
50/51Q1.Op
Stage 1 of negative-sequence overcurrent protection operates.
187
50/51Q2.On
Stage 2 of negative-sequence overcurrent protection is enabled.
188
50/51Q2.St
Stage 2 of negative-sequence overcurrent protection starts.
189
50/51Q2.Op
Stage 2 of negative-sequence overcurrent protection operates.
190
50/51Q3.On
Stage 3 of negative-sequence overcurrent protection is enabled.
191
50/51Q3.St
Stage 3 of negative-sequence overcurrent protection starts.
192
50/51Q3.Op
Stage 3 of negative-sequence overcurrent protection operates.
193
50/51Q4.On
Stage 4 of negative-sequence overcurrent protection is enabled.
194
50/51Q4.St
Stage 4 of negative-sequence overcurrent protection starts.
195
50/51Q4.Op
Stage 4 of negative-sequence overcurrent protection operates.
196
50/51Q4.Alm
Stage 4 of negative-sequence overcurrent protection operates to
alarm.
Overcurrent protection for VT circuit failure
Stage 1 of phase overcurrent protection for VT circuit failure is
197
50PVT1.On
198
50PVT1.Op
Stage 1 of phase overcurrent protection for VT circuit failure operates.
199
50PVT1.St
Stage 1 of phase overcurrent protection for VT circuit failure starts.
200
50PVT1.StA
201
50PVT1.StB
202
50PVT1.StC
203
50PVT2.On
204
50PVT2.Op
Stage 2 of phase overcurrent protection for VT circuit failure operates.
205
50PVT2.St
Stage 2 of phase overcurrent protection for VT circuit failure starts.
206
50PVT2.StA
207
50PVT2.StB
208
50PVT2.StC
209
50GVT1.On
210
50GVT1.Op
Stage 1 of ground overcurrent protection for VT circuit failure operates.
211
50GVT1.St
Stage 1 of ground overcurrent protection for VT circuit failure starts.
212
50GVT2.On
213
50GVT2.Op
enabled.
Stage 1 of phase overcurrent protection for VT circuit failure starts
(A-Phase).
Stage 1 of phase overcurrent protection for VT circuit failure starts
(B-Phase).
Stage 1 of phase overcurrent protection for VT circuit failure starts
(C-Phase).
Stage 2 of phase overcurrent protection for VT circuit failure is
enabled.
Stage 2 of phase overcurrent protection for VT circuit failure starts
(A-Phase).
Stage 2 of phase overcurrent protection for VT circuit failure starts
(B-Phase).
Stage 2 of phase overcurrent protection for VT circuit failure starts
(C-Phase).
Stage 1 of ground overcurrent protection for VT circuit failure is
enabled.
Stage 2 of ground overcurrent protection for VT circuit failure is
enabled.
Stage 2 of ground overcurrent protection for VT circuit failure operates.
9-28
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
214
Signal
50GVT2.St
Description
Stage 2 of ground overcurrent protection for VT circuit failure starts.
Phase current SOTF protection
215
50PSOTF.On
Phase current SOTF protection is enabled.
216
50PSOTF.Op
Phase current SOTF protection operates.
217
50PSOTF.St
Phase current SOTF protection starts.
Residual SOTF protection
218
50GSOTF.On
Residual current SOTF protection is enabled.
219
50GSOTF.Op
Residual current SOTF protection operates.
220
50GSOTF.St
Residual current SOTF protection starts.
Voltage protection
221
59P1.On
Stage 1 of overvoltage protection is enabled.
222
59P1.Op
Stage 1 of overvoltage protection operates.
223
59P1.St
Stage 1 of overvoltage protection starts.
224
59P1.St1
Stage 1 of overvoltage protection starts (A or AB).
225
59P1.St2
Stage 1 of overvoltage protection starts (B or BC).
226
59P1.St3
Stage 1 of overvoltage protection starts (C or CA).
227
59P1.Op_InitTT
Stage 1 of overvoltage protection operates to initiate transfer trip.
228
59P1.Alm
Stage 1 of overvoltage protection alarms.
229
59P2.On
Stage 2 of overvoltage protection is enabled.
230
59P2.Op
Stage 2 of overvoltage protection operates.
231
59P2.St
Stage 2 of overvoltage protection starts.
232
59P2.St1
Stage 2 of overvoltage protection starts (A or AB).
233
59P2.St2
Stage 2 of overvoltage protection starts (B or BC).
234
59P2.St3
Stage 2 of overvoltage protection starts (C or CA).
235
59P2.Op_InitTT
Stage 2 of overvoltage protection operates to initiate transfer trip.
236
59P2.Alm
Stage 2 of overvoltage protection alarms.
237
59P3.On
Stage 3 of overvoltage protection is enabled.
238
59P3.Op
Stage 3 of overvoltage protection operates.
239
59P3.St
Stage 3 of overvoltage protection starts.
240
59P3.St1
Stage 3 of overvoltage protection starts (A or AB).
241
59P3.St2
Stage 3 of overvoltage protection starts (B or BC).
242
59P3.St3
Stage 3 of overvoltage protection starts (C or CA).
243
59P3.Op_InitTT
Stage 3 of overvoltage protection operates to initiate transfer trip.
244
59P3.Alm
Stage 3 of overvoltage protection alarms.
245
59Q.On
Negative-sequence overvoltage protection is enabled.
246
59Q.Op
Negative-sequence overvoltage protection operates.
247
59Q.St
Negative-sequence overvoltage protection starts.
248
59G1.On
Stage 1 of residual overvoltage protection is enabled.
249
59G1.Op
Stage 1 of residual overvoltage protection operates.
250
59G1.St
Stage 1 of residual overvoltage protection start.
251
59G2.On
Stage 2 of residual overvoltage protection is enabled.
252
59G2.Op
Stage 2 of residual overvoltage protection operates.
PCS-902 Line Distance Relay
9-29
Date: 2019-03-01
9 Configurable Function
No.
Signal
Description
253
59G2.St
Stage 2 of residual overvoltage protection start.
254
59G3.On
Stage 3 of residual overvoltage protection is enabled.
255
59G3.Op
Stage 3 of residual overvoltage protection operates.
256
59G3.St
Stage 3 of residual overvoltage protection start.
257
59G3.Alm
Stage 3 of residual overvoltage protection operates to alarm.
258
27P1.On
Stage 1 of undervoltage protection is enabled.
259
27P1.Op
Stage 1 of undervoltage protection operates.
260
27P1.Alm
Stage 1 of undervoltage protection alarms.
261
27P1.St
Stage 1 of undervoltage protection starts.
262
27P1.St1
Stage 1 of undervoltage protection starts (A or AB).
263
27P1.St2
Stage 1 of undervoltage protection starts (B or BC).
264
27P1.St3
Stage 1 of undervoltage protection starts (C or CA).
265
27P1.U_Absent
266
27P2.On
Stage 2 of undervoltage protection is enabled.
267
27P2.Op
Stage 2 of undervoltage protection operates.
268
27P2.Alm
Stage 2 of undervoltage protection alarms.
269
27P2.St
Stage 2 of undervoltage protection starts.
270
27P2.St1
Stage 2 of undervoltage protection starts (A or AB).
271
27P2.St2
Stage 2 of undervoltage protection starts (B or BC).
272
27P2.St3
Stage 2 of undervoltage protection starts (C or CA).
273
27P2.U_Absent
274
27P3.On
Stage 3 of undervoltage protection is enabled.
275
27P3.Op
Stage 3 of undervoltage protection operates.
276
27P3.Alm
Stage 3 of undervoltage protection alarms.
277
27P3.St
Stage 3 of undervoltage protection starts.
278
27P3.St1
Stage 3 of undervoltage protection starts (A or AB).
279
27P3.St2
Stage 3 of undervoltage protection starts (B or BC).
280
27P3.St3
Stage 3 of undervoltage protection starts (C or CA).
281
27P3.U_Absent
No AC voltage input after the device powered on for stage 1 of
undervoltage protection
No AC voltage input after the device powered on for stage 2 of
undervoltage protection
No AC voltage input after the device powered on for stage 3 of
undervoltage protection
Frequency protection
282
81O.OF1.On
Stage 1 of overfrequency protection is enabled.
283
81O.OF1.Op
Stage 1 of overfrequency protection operates.
284
81O.OF2.On
Stage 2 of overfrequency protection is enabled.
285
81O.OF2.Op
Stage 2 of overfrequency protection operates.
286
81O.OF3.On
Stage 3 of overfrequency protection is enabled.
287
81O.OF3.Op
Stage 3 of overfrequency protection operates.
288
81O.OF4.On
Stage 4 of overfrequency protection is enabled.
289
81O.OF4.Op
Stage 4 of overfrequency protection operates.
290
81O.St
Overfrequency protection starts.
9-30
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Signal
Description
291
81U.UF1.On
Stage 1 of underfrequency protection is enabled.
292
81U.UF1.Op
Stage 1 of underfrequency protection operates.
293
81U.UF2.On
Stage 2 of underfrequency protection is enabled.
294
81U.UF2.Op
Stage 2 of underfrequency protection operates.
295
81U.UF3.On
Stage 3 of underfrequency protection is enabled.
296
81U.UF3.Op
Stage 3 of underfrequency protection operates.
297
81U.UF4.On
Stage 4 of underfrequency protection is enabled.
298
81U.UF4.Op
Stage 4 of underfrequency protection operates.
299
81U.St
Underfrequency protection starts.
Breaker failure protection
300
CBx.50BF.On
Breaker failure protection is enabled
301
CBx.50BF.Op_ReTrpA
Breaker failure protection operates to re-trip phase-A circuit breaker
302
CBx.50BF.Op_ReTrpB
Breaker failure protection operates to re-trip phase-B circuit breaker
303
CBx.50BF.Op_ReTrpC
Breaker failure protection operates to re-trip phase-C circuit breaker
304
CBx.50BF.Op_ReTrp3P
305
CBx.50BF.Op_t1
Stage 1 of breaker failure protection operates
306
CBx.50BF.Op_t2
Stage 2 of breaker failure protection operates
Breaker failure protection operates to re-trip three-phase circuit
breaker
Thermal overload protection
307
49.On
Thermal overload protection is enabled.
308
49.St
Thermal overload protection starts.
309
49-1.Op
Stage 1 of thermal overload protection operates to trip.
310
49-2.Op
Stage 2 of thermal overload protection operates to trip.
311
49-1.Alm
Stage 1 of thermal overload protection operates to alarm.
312
49-2.Alm
Stage 2 of thermal overload protection operates to alarm.
Stub differential protection
Stub differential protection is enabled. (Based on disconnector position
313
87STB.On
314
87STB.On_Local
315
87STB.Op
Stub differential protection operates.
316
87STB.St
Stub differential protection starts.
317
87STB.StA
Phase A of stub differential protection starts.
318
87STB.StB
Phase B of stub differential protection starts.
319
87STB.StC
Phase C of stub differential protection starts.
320
87STB.Alm_Diff
The alarm signal of differential current abnormality
321
87STB.Alm_DS
The alarm signal of disconnector position abnormality
signal in both local end and remote end)
Stub differential protection is enabled. (Based on disconnector position
signal in local end)
Dead zone protection
322
CBx.50DZ.On
Dead zone protection is enabled.
323
CBx.50DZ.St
Dead zone protection starts.
324
CBx.50DZ.Op
Dead zone protection operates.
Pole discrepancy protection
PCS-902 Line Distance Relay
9-31
Date: 2019-03-01
9 Configurable Function
No.
Signal
Description
325
CBx.62PD.On
Pole discrepancy protection is enabled.
326
CBx.62PD.Op
Pole discrepancy protection operates to trip
327
CBx.62PD.St
Pole discrepancy protection starts
Broken conductor protection
328
46BC.On
Broken-conductor protection is enabled.
329
46BC.St
Broken-conductor protection starts
330
46BC.Op
Broken-conductor protection operates to trip.
331
46BC.Alm
Broken-conductor protection operates to alarm.
Reverse power protection
332
32R1.On
Stage 1 of reverse power protection is enabled.
333
32R1.St
Stage 1 of reverse power protection starts.
334
32R1.Op
Stage 1 of reverse power protection operates to trip.
335
32R1.Alm
Stage 1 of reverse power protection operates to alarm.
336
32R2.On
Stage 2 of reverse power protection is enabled.
337
32R2.St
Stage 2 of reverse power protection starts.
338
32R2.Op
Stage 2 of reverse power protection operates to trip.
Synchrocheck
339
CBx.UL1_Sel
To select voltage of Line 1
340
CBx.UL2_Sel
To select voltage of Line 2
341
CBx.UB1_Sel
To select voltage of Bus 1
342
CBx.UB2_Sel
To select voltage of Bus 2
343
CBx.Alm_Invalid_Sel
Voltage selection is invalid.
To indicate that frequency difference condition for synchronism check
344
CBx.25.Ok_fDiffChk
of AR is met, frequency difference between UB and UL is smaller than
[25.f_Diff].
To indicate that voltage difference condition for synchronism check of
345
CBx.25.Ok_UDiffChk
AR is met, voltage difference between UB and UL is smaller than
[25.U_Diff]
To indicate phase difference condition for synchronism check of AR is
346
CBx.25.Ok_phiDiffChk
met, phase difference between UB and UL is smaller than
[25.phi_Diff].
347
CBx.25.Ok_DdL_DdB
Dead line and dead bus condition is met
348
CBx.25.Ok_DdL_LvB
Dead line and live bus condition is met
349
CBx.25.Ok_LvL_DdB
Live line and dead bus condition is met
350
CBx.25.Chk_LvL
Line voltage is greater than the voltage setting [25.U_Lv]
351
CBx.25.Chk_DdL
Line voltage is smaller than the voltage setting [25.U_Dd]
352
CBx.25.Chk_LvB
Bus voltage is greater than the voltage setting [25.U_Lv]
353
CBx.25.Chk_DdB
Bus voltage is smaller than the voltage setting [25.U_Dd]
354
CBx.25.Ok_DdChk
To indicate that dead charge check condition of AR is met
355
CBx.25.Ok_SynChk
To indicate that synchronism check condition of AR is met
356
CBx.25.Ok_Chk
To indicate that synchrocheck condition of AR is met
357
CBx.25.Ok_3PLvChk
To indicate that live three-phase check condition is met
9-32
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Signal
Description
358
CBx.25.Alm_VTS_Uref
Reference voltage circuit is abnormal
359
CBx.25.Alm_VTS_Usyn
Synchronism voltage circuit is abnormal
360
CBx.25.f_Ref
Frequency of the voltage used by protection calculation
361
CBx.25.f_Syn
Frequency of the voltage used by synchrocheck
362
CBx.25.U_Diff
Voltage difference for synchronism check
363
CBx.25.f_Diff
Frequency difference for synchronism check
364
CBx.25.phi_Diff
Phase difference for synchronism check
Auto-reclosing
365
CBx.79.On
Automatic reclosure is enabled
366
CBx.79.Off
Automatic reclosure is disabled
367
CBx.79.Close
Output of auto-reclosing signal
368
CBx.79.Ready
Automatic reclosure have been ready for reclosing cycle
369
CBx.79.AR_Blkd
Automatic reclosure is blocked
370
CBx.79.Active
Automatic reclosing logic is actived
371
CBx.79.Inprog
Automatic reclosing cycle is in progress
372
CBx.79.Inprog_1P
The first 1-pole AR cycle is in progress
373
CBx.79.Inprog_3P
3-pole AR cycle is in progress
374
CBx.79.Inprog_3PS1
First 3-pole AR cycle is in progress
375
CBx.79.Inprog_3PS2
Second 3-pole AR cycle is in progress
376
CBx.79.Inprog_3PS3
Third 3-pole AR cycle is in progress
377
CBx.79.Inprog_3PS4
Fourth 3-pole AR cycle is in progress
378
CBx.79.WaitToSlave
379
CBx.79.Perm_Trp1P
380
CBx.79.Perm_Trp3P
Waiting signal of automatic reclosing which will be sent to slave (when
reclosing multiple circuit breakers)
Single-phase circuit breaker will be tripped once protection device
operates
Three-phase circuit breaker will be tripped once protection device
operates
Automatic reclosure status
381
CBx.79.Rcls_Status
0: AR is ready.
1: AR is in progress.
2: AR is successful.
382
CBx.79.Fail_Rcls
Auto-reclosing fails
383
CBx.79.Succ_Rcls
Auto-reclosing is successful
384
CBx.79.Fail_Chk
Synchrocheck for AR fails
385
CBx.79.Mode_1PAR
Output of 1-pole AR mode
386
CBx.79.Mode_3PAR
Output of 3-pole AR mode
387
CBx.79.Mode_1/3PAR
Output of 1/3-pole AR mode
Transfer trip
388
TT.Alm
Input signal of receiving transfer trip is abnormal
389
TT.Op
Transfer trip operates
390
TT.On
Transfer trip is enabled
Trip logic
PCS-902 Line Distance Relay
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Date: 2019-03-01
9 Configurable Function
No.
Signal
Description
391
Line.Trp3P_PSFail
Initiating three-phase tripping due to failure in fault phase selection
392
CBx.TRP.On
Tripping logic is enabled.
393
CBx.TrpA
Tripping A-phase circuit breaker
394
CBx.TrpB
Tripping B-phase circuit breaker
395
CBx.TrpC
Tripping C-phase circuit breaker
396
CBx.Trp
Tripping any phase circuit breaker
397
CBx.Trp3P
Tripping three-phase circuit breaker
398
CBx.BFI_A
399
CBx.BFI_B
400
CBx.BFI_ C
401
CBx.BFI
402
CBx.TRP.BlkAR
Protection tripping signal of A-phase configured to initiate BFP, BFI
signal shall be reset immediately after tripping signal drops off.
Protection tripping signal of B-phase configured to initiate BFP, BFI
signal shall be reset immediately after tripping signal drops off.
Protection tripping signal of C-phase configured to initiate BFP, BFI
signal shall be reset immediately after tripping signal drops off.
Protection tripping signal configured to initiate BFP, BFI signal shall be
reset immediately after tripping signal drops off.
Blocking auto-reclosing
VT circuit supervision
403
VTS.Alm
Alarm signal to indicate VT circuit fails
404
VTNS.Alm
Alarm signal to indicate VT neutral point fails
CT circuit supervision
405
CBx.CTS.Alm
Alarm signal to indicate CT circuit fails
Control and synchrocheck for manual closing
406
CSWI01.Op_Opn
Open output of binary output No.01.
407
CSWI01.Op_Cls
Closing output of binary output No.01.
408
CSWI02.Op_Opn
Open output of binary output No.02.
409
CSWI02.Op_Cls
Closing output of binary output No.02.
410
CSWI03.Op_Opn
Open output of binary output No.03.
411
CSWI03.Op_Cls
Closing output of binary output No.03.
412
CSWI04.Op_Opn
Open output of binary output No.04.
413
CSWI04.Op_Cls
Closing output of binary output No.04.
414
CSWI05.Op_Opn
Open output of binary output No.05.
415
CSWI05.Op_Cls
Closing output of binary output No.05.
416
CSWI06.Op_Opn
Open output of binary output No.06.
417
CSWI06.Op_Cls
Closing output of binary output No.06.
418
CSWI07.Op_Opn
Open output of binary output No.07.
419
CSWI07.Op_Cls
Closing output of binary output No.07.
420
CSWI08.Op_Opn
Open output of binary output No.08.
421
CSWI08.Op_Cls
Closing output of binary output No.08.
422
CSWI09.Op_Opn
Open output of binary output No.09.
423
CSWI09.Op_Cls
Closing output of binary output No.09.
424
CSWI10.Op_Opn
Open output of binary output No.10.
425
CSWI10.Op_Cls
Closing output of binary output No.10.
9-34
PCS-902 Line Distance Relay
Date: 2019-03-01
9 Configurable Function
No.
Signal
Description
426
CSWI11.Op_Opn
Open output of binary output No.11.
427
CSWI11.Op_Cls
Closing output of binary output No.11.
428
CSWI12.Op_Opn
Open output of binary output No.12.
429
CSWI12.Op_Cls
Closing output of binary output No.12.
430
CSWI13.Op_Opn
Open output of binary output No.13.
431
CSWI13.Op_Cls
Closing output of binary output No.13.
432
CSWI14.Op_Opn
Open output of binary output No.14.
433
CSWI14.Op_Cls
Closing output of binary output No.14.
434
CSWI15.Op_Opn
Open output of binary output No.15.
435
CSWI15.Op_Cls
Closing output of binary output No.15.
436
BIinput.LocCtrl
In order to be convenient to user configure control output, three same
437
BIinput.RmtCtrl
output signals with input signals are available. The relationship with 15
binary output have been configured inside the device. The user only
assigns a specific binary input to input signal, the relevant function can
438
BIinput.CILO.Disable
be gained. If some binary output need not be controlled by three
signals, please cancel the configuration by PCS-Explorer, and
configure it independently.
439
MCBrd.CBx.Alm_VTS
VT circuit of circuit breaker No.x is abnormal.
Faulty phase selection
440
PhSA
Phase-A is selected as faulty phase
441
PhSB
Phase-B is selected as faulty phase
442
PhSC
Phase-C is selected as faulty phase
443
GndFlt
Earth fault
PCS-902 Line Distance Relay
9-35
Date: 2019-03-01
9 Configurable Function
9-36
PCS-902 Line Distance Relay
Date: 2019-03-01
10 Communication
10 Communication
Table of Contents
10 Communication ............................................................................. 10-a
10.1 Overview ...................................................................................................... 10-1
10.2 Rear Communication Port Information ..................................................... 10-1
10.2.1 RS-485 Interface.............................................................................................................. 10-1
10.2.2 Ethernet Interface ............................................................................................................ 10-3
10.2.3 IEC60870-5-103 Communication .................................................................................... 10-4
10.2.4 DNP3.0 Communication .................................................................................................. 10-4
10.3 IEC60870-5-103 Interface over Serial Port ................................................ 10-4
10.3.1 Physical Connection and Link Layer ............................................................................... 10-5
10.3.2 Initialization ...................................................................................................................... 10-5
10.3.3 Time Synchronization ...................................................................................................... 10-5
10.3.4 Spontaneous Events ........................................................................................................ 10-5
10.3.5 General Interrogation ....................................................................................................... 10-6
10.3.6 General Service ............................................................................................................... 10-6
10.3.7 Disturbance Records ....................................................................................................... 10-6
10.4 Messages Description for IEC61850 Protocol .......................................... 10-6
10.4.1 Overview .......................................................................................................................... 10-6
10.4.2 Communication Profiles ................................................................................................... 10-7
10.4.3 MMS Communication Network Deployment ................................................................... 10-8
10.4.4 Server Data Organization ...............................................................................................10-11
10.4.5 Server Features and Configuration ............................................................................... 10-14
10.4.6 ACSI Conformance ........................................................................................................ 10-16
10.4.7 Logical Nodes ................................................................................................................ 10-19
10.5 DNP3.0 Interface........................................................................................ 10-22
10.5.1 Overview ........................................................................................................................ 10-22
PCS-902 Line Distance Relay
10-a
Date: 2015-05-19
10 Communication
10.5.2 Link Layer Functions...................................................................................................... 10-22
10.5.3 Transport Functions ....................................................................................................... 10-22
10.5.4 Application Layer Functions........................................................................................... 10-22
List of Figures
Figure 10.2-1 EIA RS-485 bus connection arrangements ..................................................... 10-2
Figure 10.2-2 Ethernet communication cable ........................................................................ 10-3
Figure 10.2-3 Ethernet communication structure .................................................................. 10-4
Figure 10.4-1 Dual-net full duplex mode sharing the RCB block instance ......................... 10-9
Figure 10.4-2 Dual-net hot-standby mode sharing the same RCB instance ..................... 10-10
Figure 10.4-3 Dual-net full duplex mode with 2 independent RCB instances .................. 10-11
10-b
PCS-902 Line Distance Relay
Date: 2015-05-19
10 Communication
10.1 Overview
This section outlines the remote communications interfaces of NR Relays. The protective device
supports a choice of three protocols via the rear communication interface (RS-485 or Ethernet),
selected via the model number by setting. The protocol provided by the protective device is
indicated in the menu “Settings→Device Setup→Comm Settings”.
The rear EIA RS-485 interface is isolated and is suitable for permanent connection of whichever
protocol is selected. The advantage of this type of connection is that up to 32 protective devices
can be “daisy chained” together using a simple twisted pair electrical connection.
It should be noted that the descriptions contained within this section do not aim to fully detail the
protocol itself. The relevant documentation for the protocol should be referred to for this
information. This section serves to describe the specific implementation of the protocol in the relay.
10.2 Rear Communication Port Information
10.2.1 RS-485 Interface
This protective device provides two rear RS-485 communication ports, and each port has three
terminals in the 12-terminal screw connector located on the back of the relay and each port has a
ground terminal for the earth shield of the communication cable. The rear ports provide RS-485
serial data communication and are intended for use with a permanently wired connection to a
remote control center.
10.2.1.1 EIA RS-485 Standardized Bus
The EIA RS-485 two-wire connection provides a half-duplex fully isolated serial connection to the
product. The connection is polarized and whilst the product’s connection diagrams indicate the
polarization of the connection terminals it should be borne in mind that there is no agreed
definition of which terminal is which. If the master is unable to communicate with the product, and
the communication parameters match, then it is possible that the two-wire connection is reversed.
10.2.1.2 Bus Termination
The EIA RS-485 bus must have 120Ω (Ohm) ½ Watt terminating resistors fitted at either end
across the signal wires (refer to Figure 10.2-1). Some devices may be able to provide the bus
terminating resistors by different connection or configuration arrangements, in which case
separate external components will not be required. However, this product does not provide such a
facility, so if it is located at the bus terminus then an external termination resistor will be required.
PCS-902 Line Distance Relay
10-1
Date: 2015-05-19
Master
EIA RS-485
10 Communication
120 Ohm
120 Ohm
Slave
Slave
Slave
Figure 10.2-1 EIA RS-485 bus connection arrangements
10.2.1.3 Bus Connections & Topologies
The EIA RS-485 standard requires that each device is directly connected to the physical cable that
is the communications bus. Stubs and tees are expressly forbidden, such as star topologies. Loop
bus topologies are not part of the EIA RS-485 standard and are forbidden by it also.
Two-core screened cable is recommended. The specification of the cable will be dependent on the
application, although a multi-strand 0.5mm 2 per core is normally adequate. Total cable length must
not exceed 500m. The screen must be continuous and connected to ground at one end, normally
at the master connection point; it is important to avoid circulating currents, especially when the
cable runs between buildings, for both safety and noise reasons.
This product does not provide a signal ground connection. If a signal ground connection is present
in the bus cable then it must be ignored, although it must have continuity for the benefit of other
devices connected to the bus. At no stage must the signal ground be connected to the cables
screen or to the product’s chassis. This is for both safety and noise reasons.
10.2.1.4 Biasing
It may also be necessary to bias the signal wires to prevent jabber. Jabber occurs when the signal
level has an indeterminate state because the bus is not being actively driven. This can occur when
all the slaves are in receive mode and the master is slow to turn from receive mode to transmit
mode. This may be because the master purposefully waits in receive mode, or even in a high
impedance state, until it has something to transmit. Jabber causes the receiving device(s) to miss
the first bits of the first character in the packet, which results in the slave rejecting the message
and consequentially not responding. Symptoms of these are poor response times (due to retries),
increasing message error counters, erratic communications, and even a complete failure to
communicate.
Biasing requires that the signal lines be weakly pulled to a defined voltage level of about 1V. There
should only be one bias point on the bus, which is best situated at the master connection point.
The DC source used for the bias must be clean; otherwise noise will be injected. Note that some
devices may (optionally) be able to provide the bus bias, in which case external components will
not be required.
10-2
PCS-902 Line Distance Relay
Date: 2015-05-19
10 Communication
NOTICE!
It is extremely important that the 120Ω termination resistors are fitted. Failure to do so
will result in an excessive bias voltage that may damage the devices connected to the
bus.
As the field voltage is much higher than that required, NR cannot assume responsibility
for any damage that may occur to a device connected to the network as a result of
incorrect application of this voltage.
Ensure that the field voltage is not being used for other purposes (i.e. powering logic
inputs) as this may cause noise to be passed to the communication network.
10.2.2 Ethernet Interface
This protective device can provide four rear Ethernet interfaces (optional) and they are unattached
each other. Parameters of each Ethernet port can be configured in the menu “Settings→Device
Setup→Comm Settings”.
10.2.2.1 Ethernet Standardized Communication Cable
It is recommended to use twisted screened eight-core cable as the communication cable. A picture
is shown bellow.
Figure 10.2-2 Ethernet communication cable
10.2.2.2 Connections and Topologies
Each equipment is connected with an exchanger via communication cable, and thereby it forms a
star structure network. Dual-network is recommended in order to increase reliability. SCADA is
also connected to the exchanger and will play a role of master station, so the every equipment
which has been connected to the exchanger will play a role of slave unit.
PCS-902 Line Distance Relay
10-3
Date: 2015-05-19
10 Communication
SCADA
Switch: Net A
Switch: Net B
……
Figure 10.2-3 Ethernet communication structure
10.2.3 IEC60870-5-103 Communication
The IEC specification IEC60870-5-103: Telecontrol Equipment and Systems, Part 5: Transmission
Protocols Section 103 defines the use of standards IEC60870-5-1 to IEC60870-5-5 to perform
communication with protective device. The standard configuration for the IEC60870-5-103
protocol is to use a twisted pair EIA RS-485 connection over distances up to 500m. It also supports
to use an Ethernet connection. The relay operates as a slave in the system, responding to
commands from a master station.
To use the rear port with IEC60870-5-103 communication, the relevant settings to the protective
device must be configured.
10.2.4 DNP3.0 Communication
The DNP3.0 (Distributed Network Protocol) protocol can support the OSI/EPA model of the ISO
(International Organization for Standards), and it includes four parts: application layer protocol,
transport functions, data link layer protocol and data object library. The DNP3.0 protocol is
recommended to use the Ethernet network. This relay operates as a slave in the system,
responding to commands from a master station.
10.3 IEC60870-5-103 Interface over Serial Port
The IEC60870-5-103 interface over serial port (RS-485) is a master/slave interface with the
protective device as the slave device. It is properly developed by NR.
The protective device conforms to compatibility level 3.
The following IEC60870-5-103 facilities are supported by this interface:

Initialization (reset)
10-4
PCS-902 Line Distance Relay
Date: 2015-05-19
10 Communication

Time synchronization

Event record extraction

General interrogation

General commands

Disturbance records
10.3.1 Physical Connection and Link Layer
Two EIA RS-485 standardized ports are available for IEC60870-5-103 in this protective device.
The transmission speed is optional: 4800 bit/s, 9600 bit/s, 19200 bit/s or 38400 bit/s.
The link layer strictly abides by the rules defined in the IEC60870-5-103.
10.3.2 Initialization
Whenever the protective device has been powered up, or if the communication parameters have
been changed, a reset command is required to initialize the communications. The protective
device will respond to either of the two reset commands (Reset CU or Reset FCB), the difference
is that the Reset CU will clear any unsent messages in the transmit buffer.
The protective device will respond to the reset command with an identification message ASDU 5,
the COT (Cause Of Transmission) of this response will be either Reset CU or Reset FCB
depending on the nature of the reset command.
10.3.3 Time Synchronization
The protective device time and date can be set using the time synchronization feature of the
IEC60870-5-103 protocol. The protective device will correct for the transmission delay as specified
in IEC60870-5-103. If the time synchronization message is sent as a send/confirm message then
the protective device will respond with a confirmation. Whether the time-synchronization message
is sent as a send confirmation or a broadcast (send/no reply) message, a time synchronization
class 1 event will be generated/produced.
If the protective device clock is synchronized using the IRIG-B input then it will not be possible to
set the protective device time using the IEC60870-5-103 interface. An attempt to set the time via
the interface will cause the protective device to create an event with the current date and time
taken from the IRIG-B synchronized internal clock.
10.3.4 Spontaneous Events
Events are categorized using the following information:

Type identification (TYP)

Function type (FUN)

Information number (INF)
Messages sent to substation automation system are grouped according to IEC60870-5-103
protocol. Operating elements are sent by ASDU2 (time-tagged message with relative time), and
PCS-902 Line Distance Relay
10-5
Date: 2015-05-19
10 Communication
status of binary signal and alarm element are sent by ASDU1 (time-tagged message). The cause
of transmission (COT) of these responses is 1.
All spontaneous events can be gained by printing, implementing submenu “IEC103 Info” in the
menu “Print”.
10.3.5 General Interrogation
The GI can be used to read the status of the relay, the function numbers, and information numbers
that will be returned during the GI cycle. The GI cycle strictly abides by the rules defined in the
IEC60870-5-103.
Refer the IEC60870-5-103 standard can get the enough details about general interrogation.
10.3.6 General Service
The generic functions can be used to read the setting and protection measurement of the
protective device, and modify the setting. Two supported type identifications are ASDU 21 and
ASDU 10. For more details about generic functions, see the IEC60870-5-103 standard.
All general classification service group numbers can be gained by printing, implementing submenu
“IEC103 Info” in the menu “Print”.
10.3.7 Disturbance Records
This protective device can store up to 32 disturbance records in its memory. A pickup of the fault
detector or an operation of the relay can make the protective device store the disturbance records.
The disturbance records are stored in uncompressed format and can be extracted using the
standard mechanisms described in IEC60870-5-103.
All channel numbers (ACC) of disturbance data can be gained by printing, implementing submenu
“IEC103 Info” in the menu “Print”.
10.4 Messages Description for IEC61850 Protocol
10.4.1 Overview
The IEC 61850 standard is the result of years of work by electric utilities and vendors of electronic
equipment to produce standardized communications systems. IEC 61850 is a series of standards
describing client/server and peer-to-peer communications, substation design and configuration,
testing, environmental and project standards. The complete set includes:

IEC 61850-1: Introduction and overview

IEC 61850-2: Glossary

IEC 61850-3: General requirements

IEC 61850-4: System and project management

IEC 61850-5: Communications and requirements for functions and device models
10-6
PCS-902 Line Distance Relay
Date: 2015-05-19
10 Communication

IEC 61850-6: Configuration description language for communication in electrical substations
related to IEDs

IEC 61850-7-1: Basic communication structure for substation and feeder equipment–
Principles and models

IEC 61850-7-2: Basic communication structure for substation and feeder equipment - Abstract
communication service interface (ACSI)

IEC 61850-7-3: Basic communication structure for substation and feeder equipment–
Common data classes

IEC 61850-7-4: Basic communication structure for substation and feeder equipment–
Compatible logical node classes and data classes




IEC 61850-8-1: Specific Communication Service Mapping (SCSM) – Mappings to MMS (ISO
9506-1 and ISO 9506-2) and to ISO/IEC 8802-3
IEC 61850-9-1: Specific Communication Service Mapping (SCSM) – Sampled values over
serial unidirectional multidrop point to point link
IEC 61850-9-2: Specific Communication Service Mapping (SCSM) – Sampled values over
ISO/IEC 8802-3
IEC 61850-10: Conformance testing
These documents can be obtained from the IEC (http://www.iec.ch). It is strongly recommended
that all those involved with any IEC 61850 implementation obtain this document set.
10.4.2 Communication Profiles
The PCS-900 series relay supports IEC 61850 server services over TCP/IP communication
protocol stacks. The TCP/IP profile requires the PCS-900 series to have an IP address to establish
communications. These addresses are located in the menu “Settings→Device Setup→Comm
Settings”.
1.
MMS protocol
IEC 61850 specifies the use of the Manufacturing Message Specification (MMS) at the upper
(application) layer for transfer of real-time data. This protocol has been in existence for a number
of years and provides a set of services suitable for the transfer of data within a substation LAN
environment. IEC 61850-7-2 abstract services and objects are mapped to actual MMS protocol
services in IEC61850-8-1.
2.
Client/server
This is a connection-oriented type of communication. The connection is initiated by the client, and
communication activity is controlled by the client. IEC61850 clients are often substation computers
running HMI programs or SOE logging software. Servers are usually substation equipment such
as protection relays, meters, RTUs, transformer, tap changers, or bay controllers.
3.
Peer-to-peer
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This is a non-connection-oriented, high speed type of communication usually between substation
equipment, such as protection relays, intelligent terminal. GOOSE is the method of peer-to-peer
communication.
4.
Substation configuration language (SCL)
A substation configuration language is a number of files used to describe IED configurations and
communication systems according to IEC 61850-5 and IEC 61850-7. Each configured device has
an IED Capability Description (ICD) file and a Configured IED Description (CID) file. The
substation single line information is stored in a System Specification Description (SSD) file. The
entire substation configuration is stored in a Substation Configuration Description (SCD) file. The
SCD file is the combination of the individual ICD files and the SSD file, moreover, add
communication system parameters (MMS, GOOSE, control block, SV control block) and the
connection relationship of GOOSE and SV to SCD file.
10.4.3 MMS Communication Network Deployment
In order to enhance the stability and reliability of SAS, dual-MMS Ethernet is widely adopted. This
section is applied to introduce the details of dual-MMS Ethernet technology. Generally,
single-MMS Ethernet is recommended to be adopted in the SAS of 110kV and lower voltage levels,
while dual-MMS Ethernet is recommended to be adopted in the SAS of voltage levels above
110kV.
Client-server mode is adopted: clients (SCADA, control center and etc.) communicate with the
IEDs via MMS communication network, and the IEDs operate as the servers. IEDs are connected
to clients passively, and they can interact with the clients according to the configuration and the
issued command of the clients.
Three modes for dual-MMS Ethernet (abbreviated as dual-net) are provided as below.
NOTICE!
Hereinafter, the normal operation status of net means the physical link and TCP link are
both ok. The abnormal operation status of net means physical link or TCP link is
broken.
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10.4.3.1 Dual-net Full Duplex Mode Sharing the Same RCB Instance
Client
Client
Net A
Net B
Net A
Net B
Report Instance 1
RptEna = true
Report Instance 1
RptEna = true
Report Control Block
Report Control Block
IED (Server)
IED (Server)
Normal operation status
Abnormal operation status
TCP Link
MMS Link
Figure 10.4-1 Dual-net full duplex mode sharing the RCB block instance
Net A and Net B share the same report control block (abbreviated as RCB) enabled by the client.
IED sends undifferentiated date through dual-net to the clients. If one net is physically
disconnected, the flag of RCB instance (i.e.: “RptEna” in above figure) is still “true”. Only when
both Net A and Net B are disconnected, the flag of the RCB instance will automatically change to
“false”.
In normal operation status of this mode, IED provides the same MMS service for Net A and Net B.
If one net is physically disconnected (i.e.: “Abnormal operation status” in above figure), the
working mode will switch to single-net mode seamlessly and immediately. Network communication
supervision is unnecessary here, and Buffered Report Control Block (abbreviated as BRCB) need
not to be used. On the other net, date alternation works normally. Therefore, MMS service can
interact normally without interruption. This mode ensures no data loss during one net is in
abnormal operation status.
In this mode, one report will be transmitted twice via dual nets for the same report instance, so the
client needs to distinguish whether two reports are same according to corresponding EntryIDs.
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10.4.3.2 Dual-net Hot-standby Mode Sharing the Same RCB Instance
Client
Net A
Client
Net B
Net A
Net B
Report Instance 1
RptEna = true
Report Instance 1
RptEna = true
Report Control Block
Report Control Block
IED (Server)
IED (Server)
Normal operation status
Abnormal operation status
TCP Link
Main MMS Link
Standby MMS Link
Figure 10.4-2 Dual-net hot-standby mode sharing the same RCB instance
In this mode, the MMS service is provided on main MMS link, no MMS service interacts on the
standby MMS link. The definitions of two links are as follows:

Main MMS Link: Physically connected, TCP level connected, MMS report service available.

Standby MMS Link: Physically connected, TCP level connected, MMS report service not
available.
If the main net fails to operate (i.e.: “Abnormal operation status” in the above figure), the IED will
set “RptEna” to “false”. Meanwhile the client will detect the failure by heartbeat message or
“keep-alive”, it will automatically enable the RCB instance by setting “RptEna” back to “true”
through standby MMS link. By the buffer function of BRCB, the IED can provide uninterrupted
MMS service on the standby net. However, the differences of BRCB standards among different
manufacturers may cause data loss. Moreover, if duration of net switch is too long, the data loss is
positively as the capacity of BRCB’s buffer function is limited.
NOTICE!
The first mode and second mode, Net A IED host address and Net B IED host address
must be the same.
For example, if the subnet mask is “255.255.0.0”, network prefix of Net A is
“198.120.0.0”, network prefix of Net B is “198.121.0.0”, Net A IP address of the IED is
“198.120.1.2”, and then Net B IP address of the IED must be configured as
“198.121.1.2”, i.e., Net A IED host address =1x256+2=258, Net B IED host address
=1x256+2=258, Net A IED host address equals to Net B IED host address.
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10.4.3.3 Dual-net Full Duplex Mode with 2 Independent RCB Instances
Client
Net A
Client
Net B
Report Instance 1
RptEna = true
Report Instance 2
RptEna = true
Net A
Net B
Report Instance 1
RptEna = true
Report Instance 2
RptEna = true
Report Control Block
Report Control Block
IED (Server)
IED (Server)
Normal operation status
Abnormal operation status
TCP Link
MMS Link
Figure 10.4-3 Dual-net full duplex mode with 2 independent RCB instances
In this mode, IED provides 2 report instances for each RCB, Net A and Net B work independently
from each other, failures of any net will not affect the other net at all. Tow report instances are
required for each client. Therefore, the IED may be unable to provide enough report instances if
there are too many clients.
Net A and Net B send the same report separately when they operates normally, To ensure no
repeated data is saved into database, massive calculation is required for the client.
Moreover, accurate clock synchronization of the IED is required to distinguish whether 2 reports
are the same report according to the timestamps. Clock synchronization error of the IED may lead
to report loss/redundancy.
As a conclusion, for the second mode, it’s difficult to realize seamless switchover between dual
nets, however, for the third mode, the IED may be unable to provide enough report instances if too
many clients are applied on site. Considering client treatment and IED implementation, the first
mode (Dual-net full duplex mode sharing the same report instance) is recommended for MMS
communication network deployment.
10.4.4 Server Data Organization
IEC61850 defines an object-oriented approach to data and services. An IEC61850 physical device
can contain one or more logical device(s) (for proxy). Each logical device can contain many logical
nodes. Each logical node can contain many data objects. Each data object is composed of data
attributes and data attribute components. Services are available at each level for performing
various functions, such as reading, writing, control commands, and reporting.
Each IED represents one IEC61850 physical device. The physical device contains one or more
logical device(s), and the logical device contains many logical nodes. The logical node LPHD
contains information about the IED physical device. The logical node LLN0 contains common
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information about the IED logical device.
10.4.4.1 Digital Status Values
The GGIO logical node is available in the PCS-900 series relays to provide access to digital status
points (including general I/O inputs and warnings) and associated timestamps and quality flags.
The data content must be configured before the data can be used. GGIO provides digital status
points for access by clients. It is intended that clients use GGIO in order to access digital status
values from the PCS-900 series relays. Clients can utilize the IEC61850 buffered reporting
features available from GGIO in order to build sequence of events (SOE) logs and HMI display
screens. Buffered reporting should generally be used for SOE logs since the buffering capability
reduces the chances of missing data state changes. All needed status data objects are transmitted
to HMI clients via buffered reporting, and the corresponding buffered reporting control block
(BRCB) is defined in LLN0.
10.4.4.2 Analog Values
Most of analog measured values are available through the MMXU logical nodes, and metering
values in MMTR, the else in MMXN, MSQI and so on. Each MMXU logical node provides data
from a IED current/voltage “source”. There is one MMXU available for each configurable source.
MMXU1 provides data from CT/VT source 1(usually for protection purpose), and MMXU2 provides
data from CT/VT source 2 (usually for monitor and display purpose). All these analog data objects
are transmitted to HMI clients via unbuffered reporting periodically, and the corresponding
unbuffered reporting control block (URCB) is defined in LLN0. MMXUx logical nodes provide the
following data for each source:

MMXU.MX.Hz: frequency

MMXU.MX.PPV.phsAB: phase AB voltage magnitude and angle

MMXU.MX.PPV.phsBC: phase BC voltage magnitude and angle

MMXU.MX.PPV.phsCA: Phase CA voltage magnitude and angle

MMXU.MX.PhV.phsA: phase AG voltage magnitude and angle

MMXU.MX.PhV.phsB: phase BG voltage magnitude and angle

MMXU.MX.PhV.phsC: phase CG voltage magnitude and angle

MMXU.MX.A.phsA: phase A current magnitude and angle

MMXU.MX.A.phsB: phase B current magnitude and angle

MMXU.MX.A.phsC: phase C current magnitude and angle
10.4.4.3 Protection Logical Nodes
The following list describes the protection elements for PCS-902 series relays. The specified relay
will contain a subset of protection elements from this list.

PDIS: Phase-to-phase distance, phase-to-ground distance and SOTF distance
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
PTUC: Undercurrent

PTOC: Phase overcurrent, zero-sequence overcurrent and overcurrent when VT circuit failure

PTTR: Thermal overload

PTUV: Undervoltage

PTOV: Overvoltage and auxiliary overvoltage

PTOF: Overfrequency

PTUF: Underfrequency

PPDP: Pole discrepancy

PSCH: Protection scheme

RBRF: Breaker failure

RPSB: Power swing detection/blocking

RREC: Automatic reclosing

RSYN: Synchronism-check

RFLO: Fault location
The protection elements listed above contain start (pickup) and operate flags, instead of any
element has its own start (pickup) flag separately, all the elements share a common start (pickup)
flags “PTRC.ST.Str.general”. The operate flag for PTOC1 is “PTOC1.ST.Op.general”. For
PCS-902 series relays protection elements, these flags take their values from related module for
the corresponding element. Similar to digital status values, the protection trip information is
reported via BRCB, and BRCB also locates in LLN0.
10.4.4.4 LLN0 and Other Logical Nodes
Logical node LLN0 is essential for an IEC61850 based IED. This LN shall be used to address
common issues for Logical Devices. Most of the public services, the common settings, control
values and some device oriented data objects are available here. The public services may be
BRCB, URCB and GSE control blocks and similar global defines for the whole device; the
common settings include all the setting items of communication settings, system settings and
some of the protection setting items, which can be configured to two or more protection elements
(logical nodes). In LLN0, the item Loc is a device control object, this Do item indicates the local
operation for complete logical device, when it is true, all the remote control commands to the IED
will be blocked and those commands make effective until the item Loc is changed to false. In
PCS-900 series relays, besides the logical nodes we describe above, there are some other logical
nodes below in the IEDs:

MMXU: This LN shall be used to acquire values from CTs and VTs and calculate measurands
such as r.m.s. values for current and voltage or power flows out of the acquired voltage and
current samples. These values are normally used for operational purposes such as power
flow supervision and management, screen displays, state estimation, etc. The requested
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accuracy for these functions has to be provided.
LPHD: Physical device information, the logical node to model common issues for physical

device.
PTRC: Protection trip conditioning, it shall be used to connect the “operate” outputs of one or

more protection functions to a common “trip” to be transmitted to XCBR. In addition or
alternatively, any combination of “operate” outputs of protection functions may be combined to
a new “operate” of PTRC.
RDRE: Disturbance recorder function. It triggers the fault wave recorder and its output refers

to the “IEEE Standard Format for Transient Data Exchange (COMTRADE) for Power System”
(IEC 60255-24). All enabled channels are included in the recording, independently of the
trigger mode.
10.4.5 Server Features and Configuration
10.4.5.1 Buffered/unbuffered Reporting
IEC61850 buffered and unbuffered reporting control blocks locate in LLN0, they can be configured
to transmit information of protection trip information (in the Protection logical nodes), binary status
values (in GGIO) and analog measured/calculated values (in MMXU, MMTR and MSQI). The
reporting control blocks can be configured in CID files, and then be sent to the IED via an
IEC61850 client. The following items can be configured.
TrgOps: Trigger options.

The following bits are supported by the PCS-900 series relays:
－ Bit 1: Data-change
－ Bit 4: Integrity
－ Bit 5: General interrogation
OptFlds: Option Fields.

The following bits are supported by the PCS-900 series relays:
－ Bit 1: Sequence-number
－ Bit 2: Report-time-stamp
－ Bit 3: Reason-for-inclusion
－ Bit 4: Data-set-name
－ Bit 5: Data-reference
－ Bit 7: EntryID (for buffered reports only)
－ Bit 8: Conf-revision
－ Bit 9: Segmentation
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
IntgPd: Integrity period.
10.4.5.2 File Transfer
MMS file services are supported to allow transfer of oscillography, event record or other files from
a PCS-900 series relay.
10.4.5.3 Timestamps
The Universal Time Coordinated(UTC for short) timestamp associated with all IEC61850 data
items represents the latest change time of either the value or quality flags of the data item.
10.4.5.4 Logical Node Name Prefixes
IEC61850 specifies that each logical node can have a name with a total length of 11 characters.
The name is composed of:

A five or six-character name prefix.

A four-character standard name (for example, MMXU, GGIO, PIOC, etc.).

A one or two-character instantiation index.
Complete names are of the form xxxxxxPTOC1, where the xxxxxx character string is configurable.
Details regarding the logical node naming rules are given in IEC61850 parts 6 and 7-2. It is
recommended that a consistent naming convention be used for an entire substation project.
10.4.5.5 GOOSE Services
IEC61850 specifies the type of broadcast data transfer services: Generic Object Oriented
Substation Events (GOOSE). IEC61850 GOOSE services provide virtual LAN (VLAN) support,
Ethernet priority tagging, and Ether-type Application ID configuration. The support for VLANs and
priority tagging allows for the optimization of Ethernet network traffic. GOOSE messages can be
given a higher priority than standard Ethernet traffic, and they can be separated onto specific
VLANs. Devices that transmit GOOSE messages also function as servers. Each GOOSE
publisher contains a “GOOSE control block” to configure and control the transmission.
The GOOSE transmission (including subscribing and publishing) is controlled by GOOSE logic link
settings in device.
The PCS-900 series relays support IEC61850 Generic Object Oriented Substation Event (GOOSE)
communication. All GOOSE messages contain IEC61850 data collected into a dataset. It is this
dataset that is transferred using GOOSE message services. The GOOSE related dataset is
configured in the CID file and it is recommended that the fixed GOOSE be used for
implementations that require GOOSE data transfer between PCS-900 series relays.
IEC61850 GOOSE messaging contains a number of configurable parameters, all of which must be
correct to achieve the successful transfer of data. It is critical that the configured datasets at the
transmission and reception devices are an exact match in terms of data structure, and that the
GOOSE addresses and name strings match exactly.
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10.4.6 ACSI Conformance
10.4.6.1 ACSI Basic Conformance Statement
Services
Client
Server
PCS-900 Series
B11
Server side (of Two-party Application-Association)
－
C1
Y
B12
Client side (of Two-party Application-Association)
C1
－
N
Client-Server Roles
SCSMS Supported
B21
SCSM: IEC 61850-8-1 used
Y
Y
Y
B22
SCSM: IEC 61850-9-1 used
N
N
N
B23
SCSM: IEC 61850-9-2 used
Y
N
Y
B24
SCSM: other
N
N
N
Generic Substation Event Model (GSE)
B31
Publisher side
－
O
Y
B32
Subscriber side
O
－
Y
Transmission Of Sampled Value Model (SVC)
B41
Publisher side
－
O
N
B42
Subscriber side
O
－
N
Where:
C1: Shall be "M" if support for LOGICAL-DEVICE model has been declared
O: Optional
M: Mandatory
Y:
Supported by PCS-900 series relays
N: Currently not supported by PCS-900 series relays
10.4.6.2 ACSI Models Conformance Statement
Services
Client
Server
PCS-900 Series
M1
Logical device
C2
C2
Y
M2
Logical node
C3
C3
Y
M3
Data
C4
C4
Y
M4
Data set
C5
C5
Y
M5
Substitution
O
O
Y
M6
Setting group control
O
O
Y
M7
Buffered report control
O
O
Y
M7-1
sequence-number
Y
Y
Y
M7-2
report-time-stamp
Y
Y
Y
M7-3
reason-for-inclusion
Y
Y
Y
M7-4
data-set-name
Y
Y
Y
M7-5
data-reference
Y
Y
Y
Reporting
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M7-6
buffer-overflow
Y
Y
N
M7-7
entryID
Y
Y
Y
M7-8
BufTm
N
N
N
M7-9
IntgPd
Y
Y
Y
M7-10
GI
Y
Y
Y
M8
Unbuffered report control
M
M
Y
M8-1
sequence-number
Y
Y
Y
M8-2
report-time-stamp
Y
Y
Y
M8-3
reason-for-inclusion
Y
Y
Y
M8-4
data-set-name
Y
Y
Y
M8-5
data-reference
Y
Y
Y
M8-6
BufTm
N
N
N
M8-7
IntgPd
N
Y
Y
M9
Log control
O
O
N
M9-1
IntgPd
N
N
N
M10
Log
O
O
N
M12
GOOSE
O
O
Y
M13
GSSE
O
O
N
M14
Multicast SVC
O
O
N
M15
Unicast SVC
O
O
N
M16
Time
M
M
Y
M17
File transfer
O
O
Y
Logging
GSE
Where:
C2: Shall be "M" if support for LOGICAL-NODE model has been declared
C3: Shall be "M" if support for DATA model has been declared
C4: Shall be "M" if support for DATA-SET, Substitution, Report, Log Control, or Time models has
been declared
C5: Shall be "M" if support for Report, GSE, or SMV models has been declared
M: Mandatory
Y:
Supported by PCS-900 series relays
N: Currently not supported by PCS-900 series relays
10.4.6.3 ACSI Services Conformance Statement
Services
Server/Publisher
PCS-902
M
Y
Server
S1
ServerDirectory
Application association
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S2
Associate
M
Y
S3
Abort
M
Y
S4
Release
M
Y
M
Y
Logical device
S5
LogicalDeviceDirectory
Logical node
S6
LogicalNodeDirectory
M
Y
S7
GetAllDataValues
M
Y
S8
GetDataValues
M
Y
S9
SetDataValues
M
Y
S10
GetDataDirectory
M
Y
S11
GetDataDefinition
M
Y
S12
GetDataSetValues
M
Y
S13
SetDataSetValues
O
Y
S14
CreateDataSet
O
N
S15
DeleteDataSet
O
N
S16
GetDataSetDirectory
M
Y
M
Y
Data
Data set
Substitution
S17
SetDataValues
Setting group control
S18
SelectActiveSG
M/O
Y
S19
SelectEditSG
M/O
Y
S20
SetSGValuess
M/O
Y
S21
ConfirmEditSGValues
M/O
Y
S22
GetSGValues
M/O
Y
S23
GetSGCBValues
M/O
Y
Reporting
Buffered report control block
S24
Report
M
Y
S24-1
data-change
M
Y
S24-2
qchg-change
M
N
S24-3
data-update
M
N
S25
GetBRCBValues
M
Y
S26
SetBRCBValues
M
Y
Unbuffered report control block
S27
Report
M
Y
S27-1
data-change
M
Y
S27-2
qchg-change
M
N
S27-3
data-update
M
N
S28
GetURCBValues
M
Y
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S29
SetURCBValues
M
Y
Logging
Log control block
S30
GetLCBValues
O
N
S31
SetLCBValues
O
N
S32
QueryLogByTime
O
N
S33
QueryLogAfter
O
N
S34
GetLogStatusValues
O
N
Log
Generic substation event model (GSE)
GOOSE control block
S35
SendGOOSEMessage
M
Y
S36
GetGoReference
O
Y
S37
GetGOOSEElementNumber
O
N
S38
GetGoCBValues
M
Y
S39
SetGoCBValuess
M
N
S51
Select
O
N
S52
SelectWithValue
M
Y
S53
Cancel
M
Y
S54
Operate
M
Y
S55
Command-Termination
O
Y
S56
TimeActivated-Operate
O
N
Control
File transfer
S57
GetFile
M/O
Y
S58
SetFile
O
N
S59
DeleteFile
O
N
S60
GetFileAttributeValues
M/O
Y
M
Y
Time
SNTP
10.4.7 Logical Nodes
10.4.7.1 Logical Nodes Table
The PCS-902 series relays support IEC61850 logical nodes as indicated in the following table.
Note that the actual instantiation of each logical node is determined by the product order code.
Nodes
PCS-902
L: System Logical Nodes
LPHD: Physical device information
YES
LLN0: Logical node zero
YES
P: Logical Nodes For Protection Functions
－
PDIF: Differential
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－
PDIR: Direction comparison
PDIS: Distance
YES
PDOP: Directional overpower
－
PDUP: Directional underpower
－
PFRC: Rate of change of frequency
－
PHAR: Harmonic restraint
－
PHIZ: Ground detector
－
PIOC: Instantaneous overcurrent
－
PMRI: Motor restart inhibition
－
PMSS: Motor starting time supervision
－
POPF: Over power factor
－
PPAM: Phase angle measuring
－
PSCH: Protection scheme
YES
PSDE: Sensitive directional earth fault
－
PTEF: Transient earth fault
－
PTOC: Time overcurrent
YES
PTOF: Overfrequency
YES
PTOV: Overvoltage
YES
PTRC: Protection trip conditioning
YES
PTTR: Thermal overload
YES
－
PTUC: Undercurrent
PPDP: Pole discrepancy
YES
PTUV: Undervoltage
YES
－
PUPF: Underpower factor
PTUF: Underfrequency
YES
PVOC: Voltage controlled time overcurrent
－
PVPH: Volts per Hz
－
PZSU: Zero speed or underspeed
－
R: Logical Nodes For Protection Related Functions
RDRE: Disturbance recorder function
YES
RADR: Disturbance recorder channel analogue
－
RBDR: Disturbance recorder channel binary
－
RDRS: Disturbance record handling
－
RBRF: Breaker failure
YES
－
RDIR: Directional element
RFLO: Fault locator
YES
RPSB: Power swing detection/blocking
YES
RREC: Autoreclosing
YES
RSYN: Synchronism-check or synchronizing
YES
C: Logical Nodes For Control
CALH: Alarm handling
－
CCGR: Cooling group control
－
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CILO: Interlocking
YES
－
CPOW: Point-on-wave switching
CSWI: Switch controller
YES
G: Logical Nodes For Generic References
GAPC: Generic automatic process control
YES
GGIO: Generic process I/O
YES
－
GSAL: Generic security application
I: Logical Nodes For Interfacing And Archiving
IARC: Archiving
－
IHMI: Human machine interface
－
ITCI: Telecontrol interface
－
ITMI: Telemonitoring interface
－
A: Logical Nodes For Automatic Control
ANCR: Neutral current regulator
－
ARCO: Reactive power control
－
ATCC: Automatic tap changer controller
－
AVCO: Voltage control
－
M: Logical Nodes For Metering And Measurement
MDIF: Differential measurements
－
MHAI: Harmonics or interharmonics
－
MHAN: Non phase related harmonics or interharmonic
－
MMTR: Metering
YES
MMXN: Non phase related measurement
YES
MMXU: Measurement
YES
MSQI: Sequence and imbalance
YES
－
MSTA: Metering statistics
S: Logical Nodes For Sensors And Monitoring
SARC: Monitoring and diagnostics for arcs
－
SIMG: Insulation medium supervision (gas)
－
SIML: Insulation medium supervision (liquid)
－
SPDC: Monitoring and diagnostics for partial discharges
－
X: Logical Nodes For Switchgear
TCTR: Current transformer
YES
TVTR: Voltage transformer
YES
Y: Logical Nodes For Power Transformers
YEFN: Earth fault neutralizer (Peterson coil)
－
YLTC: Tap changer
－
YPSH: Power shunt
－
YPTR: Power transformer
－
Z: Logical Nodes For Further Power System Equipment
ZAXN: Auxiliary network
－
ZBAT: Battery
－
PCS-902 Line Distance Relay
10-21
Date: 2015-05-19
10 Communication
ZBSH: Bushing
－
ZCAB: Power cable
－
ZCAP: Capacitor bank
－
ZCON: Converter
－
ZGEN: Generator
－
ZGIL: Gas insulated line
－
ZLIN: Power overhead line
－
ZMOT: Motor
－
ZREA: Reactor
－
ZRRC: Rotating reactive component
－
ZSAR: Surge arrestor
－
ZTCF: Thyristor controlled frequency converter
－
ZTRC: Thyristor controlled reactive component
－
10.5 DNP3.0 Interface
10.5.1 Overview
The descriptions given here are intended to accompany this relay. The DNP3.0 protocol is not
described here; please refer to the DNP3.0 protocol standard for the details about the DNP3.0
implementation. This manual only specifies which objects, variations and qualifiers are supported
in this relay, and also specifies what data is available from this relay via DNP3.0.
The relay operates as a DNP3.0 slave and supports subset level 3 of the protocol, plus some of
the features from level 4. The DNP3.0 communication uses the Ethernet ports (electrical or optical)
at the rear side of this relay.
10.5.2 Link Layer Functions
Please see the DNP3.0 protocol standard for the details about the linker layer functions.
10.5.3 Transport Functions
Please see the DNP3.0 protocol standard for the details about the transport functions.
10.5.4 Application Layer Functions
10.5.4.1 Function Code
Function Code
Function
0 (0x00)
Confirm
1 (0x01)
Read
2 (0x02)
Write
3 (0x03)
Select
4 (0x04)
Operate
5 (0x05)
Direct Operate
6 (0x06)
Direct Operate No Acknowledgment
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10 Communication
Function Code
Function
13 (0x0D)
Cold Restart
14 (0x0E)
Warm Restart
20 (0x14)
Enable Unsolicited Responses
21 (0x15)
Disable Unsolicited Responses
22 (0x16)
Assign Class
23 (0x17)
Delay Measurement
10.5.4.2 Supported Object List
The supported object groups and object variations are show in the following table.
Request: Master may issue/Outstation shall parse
Function code: decimalism
Qualifier code: hexadecimal
OBJECT GROUP & VARIATION
Group/Variation
REQUEST
Description
No.
Function code
Qualifier code
1 (read)
00, 01 (start ~ stop)
22 (assign class)
06 (no range, or all)
1
0
Binary Input: Any Variation
1
1
Binary Input: Packed format
1 (read)
1
2
Binary Input: With flags
1 (read)
2
0
Binary Input Event: Any Variation
1 (read)
2
1
Binary Input Event: Without time
1 (read)
2
2
Binary Input Event: With absolute time
1 (read)
2
3
Binary Input Event: With relative time
1 (read)
10
0
Binary output: Any Variation
1 (read)
10
0
Binary output: Any Variation
1 (read)
10
1
Binary output: Packed format
2 (write)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
06 (no range, or all)
07, 08 (limited qty)
06 (no range, or all)
07, 08 (limited qty)
06 (no range, or all)
07, 08 (limited qty)
06 (no range, or all)
07, 08 (limited qty)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
3 (select)
12
30
1
0
Binary Command: Control relay output block
4 (operate)
(CROB)
5 (direct op)
Analog Input: Any Variation
PCS-902 Line Distance Relay
17, 28 (index)
6 (dir. op, no ack)
17, 28 (index)
1 (read)
00, 01 (start ~ stop)
22 (assign class)
06 (no range, or all)
10-23
Date: 2015-05-19
10 Communication
OBJECT GROUP & VARIATION
Group/Variation
REQUEST
Description
No.
Function code
30
1
Analog Input: 32 ~ bit with flag
1 (read)
30
2
Analog Input: 16 ~ bit with flag
1 (read)
30
3
Analog Input: 32 ~ bit without flag
1 (read)
30
4
Analog Input: 16 ~ bit without flag
1 (read)
30
5
Analog Input: Single ~ prec flt ~ pt with flag
1 (read)
32
0
Analog Input Event: Any Variation
1 (read)
32
1
Analog Input Event: 32 ~ bit without time
1 (read)
32
2
Analog Input Event: 16 ~ bit without time
1 (read)
32
5
34
0
Analog Input Event: Single ~ prec flt ~ pt
without time
Analog Input Deadband: Any Variation
1 (read)
1 (read)
1 (read)
34
1
Analog Input Deadband: 16 ~ bit
2 (write)
1 (read)
34
2
Analog Input Deadband: 32 ~ bit
2 (write)
1 (read)
34
3
Analog Input Deadband: Single ~ prec flt ~ pt
2 (write)
40
0
Analog Output Status: Any Variation
1 (read)
40
1
Analog Output Status: 32 ~ bit with flag
1 (read)
40
2
Analog Output Status: 16 ~ bit with flag
1 (read)
40
3
Analog Output Status: single ~ prec flt ~ pt with
flag
10-24
1 (read)
Qualifier code
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
06 (no range, or all)
07,08 (limited qty)
06 (no range, or all)
07,08 (limited qty)
06 (no range, or all)
07,08 (limited qty)
06 (no range, or all)
07,08 (limited qty)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
17,28 (index)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
17,28 (index)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
17,28 (index)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
PCS-902 Line Distance Relay
Date: 2015-05-19
10 Communication
OBJECT GROUP & VARIATION
Group/Variation
REQUEST
Description
No.
Function code
Qualifier code
3 (select)
41
1
4 (operate)
Analog Output: 32 ~ bit
17,28 (index)
5 (direct op)
6 (dir. Op, no ack)
17,28 (index)
3 (select)
41
2
4 (operate)
Analog Output: 16 ~ bit
17,28 (index)
5 (direct op)
6 (dir. Op, no ack)
17,28 (index)
3 (select)
41
3
50
1
50
3
51
1
51
2
60
1
Analog Output: Single ~ prec ft ~ pt
Time and Data: Absolute time
Time and Data: Absolute time at last recorded
time
4 (operate)
5 (direct op)
6 (dir. Op, no ack)
17,28 (index)
1 (read)
07 (limited qty = 1)
2 (write)
07 (limited qty = 1)
2 (write)
07 (limited qty = 1)
Time and Data CTO: Absolute time,
synchronized
Time and Data CTO: Absolute time,
unsynchronized
1 (read)
Class Objects: Class 0 data
22 (assign class)
1 (read)
60
2
17,28 (index)
Class Objects: Class 1 data
06 (no range, or all)
06 (no range, or all)
07,08 (limited qty)
20 (enable unsol.)
21 (disable unsol.)
06 (no range, or all)
22 (assign class)
1 (read)
60
3
Class Objects: Class 2 data
06 (no range, or all)
07,08 (limited qty)
20 (enable unsol.)
21 (disable unsol.)
06 (no range, or all)
22 (assign class)
1 (read)
60
4
Class Objects : Class 3 data
06 (no range, or all)
07,08 (limited qty)
20 (enable unsol.)
21 (disable unsol.)
06 (no range, or all)
22 (assign class)
Response: Master shall parse\Outstation may issue
Function code: decimalism
PCS-902 Line Distance Relay
10-25
Date: 2015-05-19
10 Communication
Qualifier code: hexadecimal
OBJECT GROUP & VARIATION
Group/Variation
RESPONSE
Description
No.
Function code
Qualifier code
1
0
Binary Input: Any Variation
1
1
Binary Input: Packed format
129 (response)
00, 01 (start ~ stop)
1
2
Binary Input: With flags
129 (response)
00, 01 (start ~ stop)
2
0
Binary Input Event: Any Variation
2
1
Binary Input Event: Without time
2
2
Binary Input Event: With absolute time
2
3
Binary Input Event: With relative time
10
0
Binary output: Any Variation
10
0
Binary output: Any Variation
10
1
Binary output: Packed format
12
1
30
0
Analog Input: Any Variation
30
1
30
129 (response)
130 (unsol. resp)
129 (response)
130 (unsol. resp)
129 (response)
130 (unsol. resp)
17, 28 (index)
17, 28 (index)
17, 28 (index)
129 (response)
echo of request
Analog Input: 32 ~ bit with flag
129 (response)
00, 01 (start ~ stop)
2
Analog Input: 16 ~ bit with flag
129 (response)
00, 01 (start ~ stop)
30
3
Analog Input: 32 ~ bit without flag
129 (response)
00, 01 (start ~ stop)
30
4
Analog Input: 16 ~ bit without flag
129 (response)
00, 01 (start ~ stop)
30
5
Analog Input: Single ~ prec flt ~ pt with flag
129 (response)
00, 01 (start ~ stop)
32
0
Analog Input Event: Any Variation
32
1
Analog Input Event: 32 ~ bit without time
32
2
Analog Input Event: 16 ~ bit without time
32
5
34
0
Analog Input Deadband: Any Variation
34
1
Analog Input Deadband: 16 ~ bit
34
2
Analog Input Deadband: 32 ~ bit
34
3
Analog Input Deadband: Single ~ prec flt ~ pt
40
0
Analog Output Status: Any Variation
40
1
40
2
Binary Command: Control relay output block
(CROB)
129 (response)
130 (unsol. resp)
129 (response)
130 (unsol. resp)
Analog Input Event: Single ~ prec flt ~ pt without
129 (response)
time
130 (unsol. resp)
17,28 (index)
17,28 (index)
17,28 (index)
129 (response)
00, 01 (start ~ stop)
129 (response)
00, 01 (start ~ stop)
129 (response)
00, 01 (start ~ stop)
Analog Output Status: 32 ~ bit with flag
129 (response)
00, 01 (start ~ stop)
Analog Output Status: 16 ~ bit with flag
129 (response)
00, 01 (start ~ stop)
10-26
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Date: 2015-05-19
10 Communication
OBJECT GROUP & VARIATION
Group/Variation
Description
No.
Function code
Analog Output Status: single ~ prec flt ~ pt with
40
3
41
1
41
2
41
3
50
1
50
3
51
1
51
2
60
1
Class Objects: Class 0 data
60
2
Class Objects: Class 1 data
60
3
Class Objects: Class 2 data
60
4
Class Objects : Class 3 data
RESPONSE
flag
Analog Output:
Qualifier code
129 (response)
00, 01 (start ~ stop)
129 (response)
echo of request
129 (response)
echo of request
129 (response)
echo of request
129 (response)
07 (limited qty = 1)
32 ~ bit
Analog Output:
16 ~ bit
Analog Output:
Single ~ prec ft ~ pt
Time and Data: Absolute time
Time and Data: Absolute time at last recorded
time
Time and Data CTO: Absolute time,
129 (response)
synchronized
130 (unsol. resp)
Time and Data CTO: Absolute time,
129 (response)
unsynchronized
130 (unsol. resp)
07 (limited qty = 1)
07 (limited qty = 1)
10.5.4.3 Communication Table Configuration
This relay now supports 4 Ethernet clients and 2 serial port clients. Each client can be set the DNP
related communication parameters respectively and be selected the user-defined communication
table. This relay supports a default communication table and 4 user-defined communication tables,
and the default communication table is fixed by the manufacturer and not permitted to configure by
the user.
The user can configure the user-defined communication table through the PCS-Explorer
configuration tool auxiliary software. The object groups “Binary Input”, “Binary Output”, “Analog
Input” and “Analog Output” can be configured according to the practical engineering demand.
10.5.4.4 Analog Input and Output Configuration
To the analog inputs, the attributes “deadband” and “factor” of each analog input can be configured
independently. To the analog outputs, only the attribute “factor” of each analog output needs to be
configured. If the integer mode is adopted for the data formats of analog values (to “Analog Input”,
“Object Variation” is 1, 2 and 3; to “Analog Output”, “Object Variation” is 1 and 2.), the analog
values will be multiplied by the “factor” respectively to ensure their accuracy. And if the float mode
PCS-902 Line Distance Relay
10-27
Date: 2015-05-19
10 Communication
is adopted for the data formats of analog values, the actual float analog values will be sent directly.
The judgment method of the analog input change is as below: Calculate the difference between
the current new value and the stored history value and make the difference value multiply by the
“factor”, then compare the result with the “deadband” value. If the result is greater than the
“deadband” value, then an event message of corresponding analog input change will be created.
In normal communication process, the master can online read or modify a “deadband” value by
reading or modifying the variation in “Group34”.
10.5.4.5 Binary Output Configuration
The remote control signals, logic links and external extended output commands can be configured
into the “Binary Output” group. The supported control functions are listed as below.
Information Point
Pulse On/Null
Pulse On/Close
Pulse On/Trip
Latch On/Null
Latch Off/Null
Remote Control
Not supported
Close
Trip
Close
Trip
Logic Link
Not supported
Set
Clear
Set
Clear
Extended Output
See following description
To an extended output command, if a selected command is controlled remotely, this command
point will output a high ~ level pulse. The pulse width can be decided by the “On ~ time” in the
related “Binary Command” which is from the DNP3.0 master. If the “On ~ time” is set as “0”, the
default pulse width is 500ms.
10.5.4.6 Unsolicited Messages
This relay does not transmit the unsolicited messages if the related logic setting is set as “0”. If the
unsolicited messages want to be transmitted, the related logic setting should be set as “1” or the
DNP3.0 master will transmit “Enable Unsolicited” command to this relay through “Function Code
20” (Enable Unsolicited Messages). If the “Binary Input” state changes or the difference value of
the “Analog Input” is greater than the “deadband” value, this device will transmit unsolicited
messages. If the DNP3.0 master needs not to receive the unsolicited messages, it should forbid
this relay to transmit the unsolicited messages by setting the related logic setting as “0” or through
the “Function Code 21” (Disable Unsolicited Messages).
10.5.4.7 Class Configuration
If the DNP3.0 master calls the Class0 data, this relay will transmit all actual values of the “Analog
Input”, “Binary Input” and “Analog Output”. The classes of the “Analog Input” and “Binary Input”
can be defined by modifying relevant settings. In communication process, the DNP3.0 master can
online modify the class of an “Analog Input” or a “Binary Input” through “Function Code 22” (Assign
Class).
10-28
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Date: 2015-05-19
11 Installation
11 Installation
Table of Contents
11 Installation ...................................................................................... 11-a
11.1 Overview ....................................................................................................... 11-1
11.2 Safety Information ........................................................................................ 11-1
11.3 Checking Shipment ...................................................................................... 11-2
11.4 Material and Tools Required ........................................................................ 11-2
11.5 Device Location and Ambient Conditions .................................................. 11-2
11.6 Mechanical Installation ................................................................................ 11-3
11.7 Electrical Installation and Wiring ................................................................ 11-4
11.7.1 Grounding Guidelines .......................................................................................................11-4
11.7.2 Cubicle Grounding ............................................................................................................11-4
11.7.3 Ground Connection on the Device ...................................................................................11-5
11.7.4 Grounding Strips and their Installation ..............................................................................11-5
11.7.5 Guidelines for Wiring.........................................................................................................11-6
11.7.6 Wiring for Electrical Cables ...............................................................................................11-6
List of Figures
Figure 11.6-1 Dimensions and panel cut-out of PCS-902 ..................................................... 11-3
Figure 11.6-2 Demonstration of plugging a board into its corresponding slot .................. 11-3
Figure 11.7-1 Cubicle grounding system ................................................................................ 11-5
Figure 11.7-2 Ground terminal of this relay ............................................................................ 11-5
Figure 11.7-3 Ground strip and termination ........................................................................... 11-6
Figure 11.7-4 Glancing demo about the wiring for electrical cables ................................... 11-7
PCS-902 Line Distance Relay
11-a
Date: 2015-05-19
11 Installation
11-b
PCS-902 Line Distance Relay
Date: 2015-05-19
11 Installation
11.1 Overview
The device must be shipped, stored and installed with the greatest care. Choose the place of
installation such that the communication interface and the controls on the front of the device are
easily accessible.
Air must circulate freely around the equipment. Observe all the requirements regarding place of
installation and ambient conditions given in this instruction manual.
Take care that the external wiring is properly brought into the equipment and terminated correctly
and pay special attention to grounding. Strictly observe the corresponding guidelines contained in
this section.
11.2 Safety Information
Modules and units may only be replaced by correspondingly trained personnel. Always observe
the basic precautions to avoid damage due to electrostatic discharge when handling the
equipment.
In certain cases, the settings have to be configured according to the demands of the engineering
configuration after replacement. It is therefore assumed that the personnel who replace modules
and units are familiar with the use of the operator program on the service PC.
WARNING!
ONLY insert or withdraw a module while the device power supply is switched off. To this
end, disconnect the power supply cable that connects with the PWR module.
NOTICE!
Industry packs and ribbon cables may ONLY be replaced on a workbench for electronic
equipment. Electronic components are sensitive to electrostatic discharge when not in
the unit's housing.
Jumper links may ONLY be changed on a workbench for electronic equipment.
Electronic components are sensitive to electrostatic discharge when not in the unit's
housing.
A module can ONLY be inserted in the slot designated in the chapter 6. Components
can be damaged or destroyed by inserting module in a wrong slot.
The basic precautions to guard against electrostatic discharge are as follows:
1.
Should boards have to be removed from this relay installed in a grounded cubicle in an HV
switchgear installation, please discharge yourself by touching station ground (the cubicle)
beforehand.
2.
Only hold electronic boards at the edges, taking care not to touch the components.
3.
Only works on boards that have been removed from the cubicle on a workbench designed for
PCS-902 Line Distance Relay
11-1
Date: 2015-05-19
11 Installation
electronic equipment and wear a grounded wristband. Do not wear a grounded wristband,
however, while inserting or withdrawing units.
4.
Always store and ship the electronic boards in their original packing. Place electronic parts in
electrostatic screened packing materials.
11.3 Checking Shipment
Check that the consignment is complete immediately upon receipt. Notify the nearest NR
Company or agent, should departures from the delivery note, the shipping papers or the order be
found.
Visually inspect all the material when unpacking it. When there is evidence of transport damage,
lodge a claim immediately in writing with the last carrier and notify the nearest NR Company or
agent.
If the equipment is not going to be installed immediately, store all the parts in their original packing
in a clean dry place at a moderate temperature. The humidity at a maximum temperature and the
permissible storage temperature range in dry air are listed in Chapter “Technical Data”.
11.4 Material and Tools Required
The necessary mounting kits will be provided, including screws, pincers and assembly
instructions.
A suitable drill and spanners are required to secure the cubicles to the floor using the plugs
provided (if this relay is mounted in cubicles).
11.5 Device Location and Ambient Conditions
NOTICE!
Excessively high temperature can appreciably reduce the operating life of this device.
The place of installation should permit easy access especially to front of the device, i.e. to the
human machine interface of the equipment.
There should also be free access at the rear of the equipment for additions and replacement of
electronic boards.
Since every piece of technical equipment can be damaged or destroyed by inadmissible ambient
conditions, such as:
1.
The location should not be exposed to excessive air pollution (dust, aggressive substances).
2.
Severe vibration, extreme changes of temperature, high levels of humidity, surge voltages of
high amplitude and short rise time and strong induced magnetic fields should be avoided as
far as possible.
3.
Air must not be allowed to circulate freely around the equipment.
The equipment can in principle be mounted in any attitude, but it is normally mounted vertically
11-2
PCS-902 Line Distance Relay
Date: 2015-05-19
11 Installation
(visibility of markings).
11.6 Mechanical Installation
NOTICE!
It is necessary to leave enough space top and bottom of the cut-out in the cubicle for
heat emission of this device.
The device adopts IEC standard chassis and is rack with modular structure. It uses an integral
faceplate and plug terminal block on backboard for external connections. PCS-902 series is IEC
4U high, and Figure 11.6-1 shows its dimensions and panel cut-out.
Front
Side
Cut-Out
Figure 11.6-1 Dimensions and panel cut-out of PCS-902
The safety instructions must be abided by when installing the boards, please see Section 11.2 for
the details.
Following figure shows the installation way of a module being plugged into a corresponding slot.
Figure 11.6-2 Demonstration of plugging a board into its corresponding slot
PCS-902 Line Distance Relay
11-3
Date: 2015-05-19
11 Installation
In the case of equipment supplied in cubicles, place the cubicles on the foundations that have
been prepared. Take care while doing so not to jam or otherwise damage any of the cables that
have already been installed. Secure the cubicles to the foundations.
11.7 Electrical Installation and Wiring
11.7.1 Grounding Guidelines
NOTICE!
All these precautions can only be effective if the station ground is of good quality.
Switching operations in HV installations generate transient over voltages on control signal cables.
There is also a background of electromagnetic RF fields in electrical installations that can induce
spurious currents in the devices themselves or the leads connected to them.
All these influences can influence the operation of electronic apparatus.
On the other hand, electronic apparatus can transmit interference that can disrupt the operation of
other apparatus.
In order to minimize these influences as far as possible, certain standards have to be observed
with respect to grounding, wiring and screening.
11.7.2 Cubicle Grounding
The cubicle must be designed and fitted out such that the impedance for RF interference of the
ground path from the electronic device to the cubicle ground terminal is as low as possible.
Metal accessories such as side plates, blanking plates etc., must be effectively connected
surface-to-surface to the grounded frame to ensure a low-impedance path to ground for RF
interference. The contact surfaces must not only conduct well, they must also be non-corroding.
NOTICE!
If the above conditions are not fulfilled, there is a possibility of the cubicle or parts of it
forming a resonant circuit at certain frequencies that would amplify the transmission of
interference by the devices installed and also reduce their immunity to induced
interference.
Movable parts of the cubicle such as doors (front and back) or hinged equipment frames must be
effectively grounded to the frame by three braided copper strips (see Figure 11.7-1).
The metal parts of the cubicle housing and the ground rail are interconnected electrically
conducting and corrosion proof. The contact surfaces shall be as large as possible.
NOTICE!
For metallic connections please observe the voltage difference of both materials
according to the electrochemical code.
The cubicle ground rail must be effectively connected to the station ground rail by a
grounding strip (braided copper).
11-4
PCS-902 Line Distance Relay
Date: 2015-05-19
11 Installation
Door or hinged
equipment frame
Cubicle ground
rail close to floor
Braided
copper strip
Station
ground
Conducting
connection
Figure 11.7-1 Cubicle grounding system
11.7.3 Ground Connection on the Device
There is a ground terminal on the rear panel, and the ground braided copper strip can be
connected with it. Take care that the grounding strip is always as short as possible. The main thing
is that the device is only grounded at one point. Grounding loops from unit to unit are not allowed.
There are some ground terminals on some connectors of this relay, and the sign is “GND”. All the
ground terminals are connected in the cabinet of this relay. So, the ground terminal on the rear
panel (see Figure 11.7-2) is the only ground terminal of this device.
Figure 11.7-2 Ground terminal of this relay
11.7.4 Grounding Strips and their Installation
High frequency currents are produced by interference in the ground connections and because of
skin effect at these frequencies, only the surface region of the grounding strips is of consequence.
The grounding strips must therefore be of (preferably tinned) braided copper and not round copper
conductors, as the cross-section of round copper would have to be too large.
Proper terminations must be fitted to both ends (press/pinch fit and tinned) with a hole for bolting
them firmly to the items to be connected.
The surfaces to which the grounding strips are bolted must be electrically conducting and
non-corroding.
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The following figure shows the ground strip and termination.
Press/pinch fit
cable terminal
Braided
copper strip
Terminal bolt
Contact surface
Figure 11.7-3 Ground strip and termination
11.7.5 Guidelines for Wiring
There are several types of cables that are used in the connection of this relay: braided copper
cable, serial communication cable etc. Recommendation of each cable:

Grounding: braided copper cable, 2.5mm2 ~ 6.0mm 2

Power supply, binary inputs & outputs: stranded conductor, 1.0mm 2 ~ 2.5mm 2

AC voltage inputs: stranded conductor, 1.5mm 2

AC current inputs: stranded conductor, 2.5mm 2

Serial communication: 4-core shielded cable

Ethernet communication: 4-pair twisted shielded cable (category 5E)
11.7.6 Wiring for Electrical Cables
DANGER!
NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously high
voltage that cause death.
A female connector is used for connecting the wires with it, and then a female connector plugs into
a corresponding male connector that is in the front of one board. See Chapter “Hardware” for
further details about the pin defines of these connectors.
The following figure shows the glancing demo about the wiring for the electrical cables.
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11 Installation
Tighten
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
01
Figure 11.7-4 Glancing demo about the wiring for electrical cables
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12 Commissioning
12 Commissioning
Table of Contents
12 Commissioning ............................................................................. 12-a
12.1 Overview ...................................................................................................... 12-1
12.2 Safety Instructions ...................................................................................... 12-1
12.3 Commission Tools ...................................................................................... 12-2
12.3.1 Minimum Equipment Required ........................................................................................ 12-2
12.3.2 Optional Equipment ......................................................................................................... 12-2
12.4 Setting Familiarization ................................................................................ 12-2
12.5 Product Checks ........................................................................................... 12-3
12.5.1 With the Relay De-energized........................................................................................... 12-3
12.5.2 With the Relay Energized ................................................................................................ 12-5
12.5.3 Print Fault Report............................................................................................................. 12-8
12.5.4 On-load Checks ............................................................................................................... 12-8
12.6 Final Checks ................................................................................................ 12-9
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12.1 Overview
This device is fully numerical in their design, implementing all protection and non-protection
functions in software. The relay employs a high degree of self-checking and in the unlikely event of
a failure, will give an alarm. As a result of this, the commissioning test does not need to be as
extensive as with non-numeric electronic or electro-mechanical relays.
To commission numerical relays, it is only necessary to verify that the hardware is functioning
correctly and the application-specific software settings have been applied to the relay.
Blank commissioning test and setting records are provided at the end of this manual for
completion as required.
Before carrying out any work on the equipment, the user should be familiar with the contents of the
safety and technical data sections and the ratings on the equipment’s rating label.
12.2 Safety Instructions
DANGER!
Current transformer secondary circuits MUST be short-circuited BEFORE the current
leads to the device are disconnected.
WARNING!
ONLY qualified personnel should work on or in the vicinity of this device. This personnel
MUST be familiar with all safety regulations and service procedures described in this
manual. During operating of electrical device, certain part of the device is under high
voltage. Severe personal injury and significant device damage could result from
improper behavior.
Particular attention must be drawn to the following:
1.
The earthing screw of the device must be connected solidly to the protective earth conductor
before any other electrical connection is made.
2.
Hazardous voltages can be present on all circuits and components connected to the supply
voltage or to the measuring and test quantities.
3.
Hazardous voltages can be present in the device even after disconnection of the supply
voltage (storage capacitors!)
4.
The limit values stated in the Chapter “Technical Data” must not be exceeded at all, not even
during testing and commissioning.
5.
When testing the device with secondary test equipment, make sure that no other
measurement quantities are connected. Take also into consideration that the trip circuits and
maybe also close commands to the circuit breakers and other primary switches are
disconnected from the device unless expressly stated.
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12.3 Commission Tools
NOTICE!
Modern test set may contain many of the above features in one unit.
12.3.1 Minimum Equipment Required
1.
Multifunctional dynamic current and voltage injection test set with interval timer.
2.
Multimeter with suitable AC current range and AC/DC voltage ranges of 0~440Vac and
0~250Vdc respectively.
3.
Continuity tester (if not included in the multimeter).
4.
Phase angle meter.
5.
Phase rotation meter.
12.3.2 Optional Equipment
1.
An electronic or brushless insulation tester with a DC output not exceeding 500V (for
insulation resistance test when required).
2.
A portable PC, with appropriate software (this enables the rear communications port to be
tested, if this is to be used, and will also save considerable time during commissioning).
3.
EIA RS-485 to EIA RS-232 converter (if EIA RS-485 IEC60870-5-103 port is being tested).
4.
PCS-900 serials dedicated protection tester HELP-9000.
12.4 Setting Familiarization
When commissioning this device for the first time, sufficient time should be allowed to become
familiar with the method by which the settings are applied. A detailed description of the menu
structure of this relay is contained in Chapter “Operation Theory” and Chapter “Settings”.
With the front cover in place all keys are accessible. All menu cells can be read. The LED
indicators and alarms can be reset. Protection or configuration settings can be changed, or fault
and event records cleared. However, menu cells will require the appropriate password to be
entered before changes can be made.
Alternatively, if a portable PC is available together with suitable setting software (such as
PCS-9700 HMI software), the menu can be viewed one page at a time to display a full column of
data and text. This PC software also allows settings to be entered more easily, saved to a file on
disk for future reference or printed to produce a setting record. Refer to the PC software user
manual for details. If the software is being used for the first time, allow sufficient time to become
familiar with its operation.
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12.5 Product Checks
These product checks cover all aspects of the relay which should be checked to ensure that it has
not been physically damaged prior to commissioning, is functioning correctly and all input quantity
measurements are within the stated tolerances.
If the application-specific settings have been applied to the relay prior to commissioning, it is
advisable to make a copy of the settings so as to allow them restoration later. This could be done
by extracting the settings from the relay itself via printer or manually creating a setting record.
12.5.1 With the Relay De-energized
This relay is fully numerical and the hardware is continuously monitored. Commissioning tests can
be kept to a minimum and need only include hardware tests and conjunctive tests. The function
tests are carried out according to user’s correlative regulations.
The following tests are necessary to ensure the normal operation of the equipment before it is first
put into service.
1.
Hardware tests
These tests are performed for the following hardware to ensure that there is no hardware defect.
Defects of hardware circuits other than the following can be detected by self-monitoring when the
DC power is supplied.
2.
User interfaces test
3.
Binary input circuits and output circuits test
4.
AC input circuits test
5.
Function tests
These tests are performed for the following functions that are fully software-based. Tests of the
protection schemes and fault locator require a dynamic test set.
6.
Measuring elements test
7.
Timers test
8.
Measurement and recording test
9.
Conjunctive tests
The tests are performed after the relay is connected with the primary equipment and other external
equipment.
10. On load test
11. Phase sequence check and polarity check
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12.5.1.1 Visual Inspection
After unpacking the product, check for any damage to the relay case. If there is any damage, the
internal module might also have been affected, contact the vendor. The following items listed is
necessary.
1.
Protection panel
Carefully examine the protection panel, protection equipment inside and other parts inside to see
that no physical damage has occurred since installation.
The rated information of other auxiliary protections should be checked to ensure it is correct for the
particular installation.
2.
Panel wiring
Check the conducting wire which is used in the panel to assure that their cross section meeting the
requirement.
Carefully examine the wiring to see that they are no connection failure exists.
3.
Label
Check all the isolator binary inputs, terminal blocks, indicators, switches and push buttons to make
sure that their labels meet the requirements of this project.
4.
Device plug-in modules
Check each plug-in module of the device on the panel to make sure that they are well installed into
the equipment without any screw loosened.
5.
Earthing cable
Check whether the earthing cable from the panel terminal block is safely screwed to the panel
steel sheet.
6.
Switch, keypad, isolator binary inputs and push button
Check whether all the switches, equipment keypad, isolator binary inputs and push buttons work
normally and smoothly.
12.5.1.2 Insulation Test
Insulation resistance tests are only necessary during commissioning if it is required for them to be
done and they have not been performed during installation.
Isolate all wiring from the earth and test the isolation with an electronic or brushless insulation
tester at a DC voltage not exceeding 500V, The circuits need to be tested should include:
1.
Voltage transformer circuits
2.
Current transformer circuits
3.
DC power supply
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12 Commissioning
4.
Optic-isolated control inputs
5.
Output contacts
6.
Communication ports
The insulation resistance should be greater than 100MΩ at 500V.
Test method:
To unplug all the terminals sockets of this relay, and do the Insulation resistance test for each
circuit above with an electronic or brushless insulation tester.
On completion of the insulation resistance tests, ensure all external wiring is correctly reconnected
to the protection.
12.5.1.3 External Wiring
Check that the external wiring is correct to the relevant relay diagram and scheme diagram.
Ensure as far as practical that phasing/phase rotation appears to be as expected.
Check the wiring against the schematic diagram for the installation to ensure compliance with the
customer’s normal practice.
12.5.1.4 Auxiliary Power Supply
WARNING!
Energize this device ONLY if the power supply is within the specified operating range in
Chapter “Technical Data”.
The relay only can be operated under the auxiliary power supply depending on the relay’s nominal
power supply rating.
The incoming voltage must be within the operating range specified in Chapter “Technical Data”,
before energizing the relay, measure the auxiliary supply to ensure it within the operating range.
Other requirements to the auxiliary power supply are specified in Chapter “Technical Data”. See
this section for further details about the parameters of the power supply.
12.5.2 With the Relay Energized
The following groups of checks verify that the relay hardware and software is functioning correctly
and should be carried out with the auxiliary supply applied to the relay.
The current and voltage transformer connections must remain isolated from the relay for these
checks. The trip circuit should also remain isolated to prevent accidental operation of the
associated circuit breaker.
12.5.2.1 Front Panel LCD Display
Connect the relay to DC power supply correctly and turn the relay on. Check program version and
forming time displayed in command menu to ensure that are corresponding to what ordered.
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12.5.2.2 Date and Time
If the time and date is not being maintained by substation automation system, the date and time
should be set manually.
Set the date and time to the correct local time and date using menu item “Clock”.
In the event of the auxiliary supply failing, with a super capacitor fitted on MON board, the time and
date will be maintained. Therefore when the auxiliary supply is restored the time and date will be
correct and not need to set again.
To test this, remove the auxiliary supply from the relay for approximately 30s. After being
re-energized, the time and date should be correct.
12.5.2.3 Light Emitting Diodes (LEDs)
On power up, the green LED “HEALTHY” should have illuminated and stayed on indicating that
the relay is healthy.
The relay has latched signal relays which remember the state of the trip, auto-reclose when the
relay was last energized from an auxiliary supply. Therefore these indicators may also illuminate
when the auxiliary supply is applied. If any of these LEDs are on then they should be reset before
proceeding with further testing. If the LED successfully reset, the LED goes out. There is no testing
required for that that LED because it is known to be operational.
It is likely that alarms related to voltage transformer supervision will not reset at this stage.
12.5.2.4 Testing HEALTHY and ALARM LEDs
Apply the rated DC power supply and check that the “HEALTHY” LED is lighting in green. We
need to emphasize that the “HEALTHY” LED is always lighting in operation course except that the
equipment find serious errors in it.
Produce one of the abnormal conditions listed in Chapter “Supervision”, the “ALARM” LED will
light in yellow. When abnormal condition reset, the “ALARM” LED extinguishes.
12.5.2.5 Testing AC Current Inputs
NOTICE!
The closing circuit should remain isolated during these checks to prevent accidental
operation of the associated circuit breaker.
This test verified that the accuracy of current measurement is within the acceptable tolerances.
Apply rated current to each current transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the relays menu.
The verification of measurement accuracy shall be coincided with the required technical data.
However, an additional allowance must be made for the accuracy of the test equipment being
used.
Group No.
Item
Input Value
Input Angle
12-6
Display Value
Display Angle
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Group No.
Item
Input Value
Input Angle
Display Value
Display Angle
Ia
Three-phase current 1
Ib
Ic
Ia
Three-phase current 2
Ib
Ic
Ia
Three-phase current 3
Ib
Ic
Ia
Three-phase current ……
Ib
Ic
Residual current 1
3I0
Residual current 2
3I0
Residual current 3
3I0
Residual current ……
3I0
12.5.2.6 Testing AC Voltage Inputs
NOTICE!
The closing circuit should remain isolated during these checks to prevent accidental
operation of the associated circuit breaker.
This test verified that the accuracy of voltage measurement is within the acceptable tolerances.
Apply rated voltage to each voltage transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the relays menu.
The verification of measurement accuracy shall be coincided with the required technical data.
However an additional allowance must be made for the accuracy of the test equipment being
used.
Group No.
Item
Input Value
Input Angle
Display Value
Display Angle
Ua
Three-phase voltage 1
Ub
Uc
Ua
Three-phase voltage 2
Ub
Uc
Ua
Three-phase voltage 3
Ub
Uc
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Group No.
Item
Input Value
Input Angle
Display Value
Display Angle
Ua
Three-phase voltage……
Ub
Uc
Residual voltage 1
3U0
Residual voltage 2
3U0
Residual voltage 3
3U0
Residual voltage ……
3U0
12.5.2.7 Testing Binary Inputs
This test checks that all the binary inputs on the device are functioning correctly. The binary inputs
should be energized one at a time, see external connection diagrams for terminal numbers.
Ensure that the voltage applied on the binary input must be within the operating range. The status
of each binary input can be viewed using relay menu. Sign “1” denotes an energized input and
sign “0” denotes a de-energized input.
Terminal No.
Signal Name
BI Status on LCD
Correct?
12.5.3 Print Fault Report
In order to acquire the details of protection operation, it is convenient to print the fault report of
protection device. The printing work can be easily finished when operator presses the print button
on panel of protection device to energize binary input [BI_Print] or operate control menu. What
should be noticed is that only the latest fault report can be printed if operator presses the print
button. A complete fault report includes the content shown as follows.
1. Trip event report
2. Binary input when protection devices start
3. Self-check and the transition of binary input in the process of devices start
4. Fault wave forms compatible with COMTRADE
5. The setting value when the protection device trips
12.5.4 On-load Checks
The objectives of the on-load checks are:
1. Confirm the external wiring to the current and voltage inputs is correct.
2. Measure the magnitude of on-load current and voltage (if applicable).
3. Check the polarity of each current transformer.
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However, these checks can only be carried out if there are no restrictions preventing the
tenderization of the plant being protected.
Remove all test leads, temporary shorting leads, etc. and replace any external wiring that has
been removed to allow testing.
If it has been necessary to disconnect any of the external wiring from the protection in order to
perform any of the foregoing tests, it should be ensured that all connections are replaced in
accordance with the relevant external connection or scheme diagram. Confirm current and voltage
transformer wiring.
12.6 Final Checks
After the above tests are completed, remove all test or temporary shorting leads, etc. If it has been
necessary to disconnect any of the external wiring from the protection in order to perform the
wiring verification tests, it should be ensured that all connections are replaced in accordance with
the relevant external connection or scheme diagram.
Ensure that the protection has been restored to service.
If the protection is in a new installation or the circuit breaker has just been maintained, the circuit
breaker maintenance and current counters should be zero. If a test block is installed, remove the
test plug and replace the cover so that the protection is put into service.
Ensure that all event records, fault records, disturbance records and alarms have been cleared
and LED’s has been reset before leaving the protection.
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13 Maintenance
13 Maintenance
Table of Contents
13 Maintenance .................................................................................. 13-a
13.1 Overview ...................................................................................................... 13-1
13.2 Appearance Check ...................................................................................... 13-1
13.3 Failure Tracing and