Part II
Lectures 8-14
Bipolar Junction Transistors
(BJTs) and Circuits
University of Technology
Electrical and Electronic Engineering Department
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Bipolar Junction Transistors
Lecture Eight - Page 1 of 8
Dr. Ahmed Saadoon Ezzulddin
Bipolar Junction Transistors (BJTs)
Basic Construction:
The transistor is a three-layer semiconductor device consisting of either two n- and one
p-type layers of material or two p- and one n-type layers of material. The former is
called an npn transistor, while the latter is called a pnp transistor. Both (with symbols)
are shown in Fig. 8-1. The middle region of each transistor type is called the base (B)
of the transistor. Of the remaining two regions, one is called emitter (E) and the other is
called the collector (C) of the transistor. For each transistor type, a junction is created at
each of the two boundaries where the material changes from one type to the other.
Therefore, there are two junctions: emitter-base (E-B) junction and collector-base
(C-B) junction. The outer layers of the transistor are heavily doped semiconductor
materials having widths much greater than those of the sandwiched p- or n-type
material. The doping of the sandwiched layer is also considerably less than that of the
outer layers (typically 10:1 or less). This lower doping level decreases the conductivity
(increases the resistance) of this material by limiting the number of "free" carriers.
n
E
p
n
C
(Emitter)
p n
E
p
C
(Collector)
E-B junction
C-B junction
B
B
(Base)
C
E
C
E
B
Fig. 8-1
B
The dc biasing is necessary to establish the proper region of operation for ac
amplification or switching purposes. Table 8-1 shows the transistor operation regions
and the purpose with respect to the biasing of the E-B and C-B junctions.
Table 8-1
Operation region
Purpose
1 Active region
2 Cutoff region
3 Saturation region
Amplification
Switching
Junctions biasing
E-B junction bias C-B junction bias
Forward-biased
Reverse-biased
Forward-biased
Reverse-biased
Reverse-biased
Forward-biased
The abbreviation BJT, from bipolar junction transistor, is often applied to this
three-terminal device. The term bipolar reflects the fact that holes and electrons
participate in the injection process into the oppositely polarized material. If only one
carrier is employed (electron or hole), it is considered a unipolar device. Such a device
is the field-effect transistor (FET).
University of Technology
Electrical and Electronic Engineering Department
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Bipolar Junction Transistors
Lecture Eight - Page 2 of 8
Dr. Ahmed Saadoon Ezzulddin
Active Region Operation:
The basic operation of the transistor will now be described using the pnp transistor of
Fig. 8-2. The operation of the npn transistor is exactly the same if the roles played by
the electron and hole are interchanged. When the E-B junction is forward-biased, a
large number of majority carriers will diffuse across the forward-biased p-n junction
into the n-type material (base). Since the base is very thin and has a low conductivity
(lightly doping), a very small number of these carriers will take this path of high
resistance to the base terminal. The larger number of these majority carriers will diffuse
across the reverse-biased C-B junction into the p-type material (collector). The reason
for the relative ease with which the majority carriers can cross the reverse-biased
C-B junction is easily understood if we consider that for the reverse-biased diode the
injected majority carriers will appear as minority carriers in the n-type base region
material. Combining this with the fact that all the minority carriers in the depletion
region will cross the reverse-biased junction of a diode accounts for the flow indicated
in Fig. 8-2.
Fig. 8-2
Applying Kirchhoff's current law to the transistor of Fig. 8-2, we obtain
I E = IC + I B
[8.1]
The collector current, however, is comprised of two components: the majority and
minority carriers as indicated in Fig. 8-2. The minority-current component is called the
leakage current and is given the symbol ICO (IC current with emitter terminal Open).
The collector current, therefore, is determined in total by Eq. [8.2].
I C = IC majority + ICO minority
[8.2]
University of Technology
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Bipolar Junction Transistors
Lecture Eight - Page 3 of 8
Dr. Ahmed Saadoon Ezzulddin
Common-Base (CB) Configuration:
The common-base configuration with npn and pnp transistors are indicated in Fig. 8-3.
The common-base terminology is derived from the fact that the base is common to both
input and output sides of the configuration. In addition, the base is usually terminal
closest to, or at, the ground potential.
IE
C
E
−
IE
+
VBE
VEE
IC
+
B
IB
VCB
−
C IC
E
−
+
VCC
VEE
VEB
IB
−
VBC
+
VCC
B
Fig. 8-3
In the dc mode the levels of IC and IE due to the majority carriers are related by a
quantity called alpha (αdc) and defined by the following equation:
α dc =
IC
IE
[8.3]
Where IC and IE are the levels of current at the point of operation and αdc ≈ 1, or for
practical devices: 0.900 ≤ αdc ≤ 0.998.
Since alpha is defined solely for the majority
carriers and from Fig. 8-4, Eq. [8.2] becomes
I C = αI E + I CBO
[8.4]
Fig. 8-4
The input (emitter) characteristics for a CB
configuration are a plot of the emitter (input)
current (IE) versus the base-to-emitter (input)
voltage (VBE) for a rage of values of the collectorto-base (output) voltage (VCB) as shown in Fig. 8-5.
Since, the exact shape of this IE-VBE carve will
depend on the reverse-biasing output voltage, VCB.
The reason for this dependency is that the grater the
value of VCB, the more readily minority carriers in
the base are swept through the C-B junction. The
increase in emitter-to-collector current resulting
from an increase in VCB means the emitter current
will be greater for a given value of base-to-emitter
voltage (VBE).
Fig. 8-5
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Bipolar Junction Transistors
Lecture Eight - Page 4 of 8
Dr. Ahmed Saadoon Ezzulddin
The output (collector) characteristics for
CB configuration will be a plot of the collector
(output) current (IC) versus collector-to-base
(output) voltage (VCB) for a range of values of
emitter (input) current (IE) as shown in Fig. 8-6.
The collector characteristics have three basic
region of interest, as indicated in Fig. 8-6, the
active, cutoff, and saturation regions.
W Active region:
VCB > 0 and I C = αI E .
W Cutoff region:
IE = 0 and I C = I CBO .
W Saturation region:
Fig. 8-6
VCB < 0 and I C ( sat .) ≈ I E ( sat .) .
For ac situations where the point of operation moves on the characteristic carve,
an ac alpha (αac) is defined by
α ac =
ΔI C
ΔI E
[8.5]
VCB =const .
The ac alpha is formally called the common-base, short-circuit, amplification factor,
and for most situations the magnitudes of αac and αdc are quite close, permitting the use
of the magnitude of one for other.
Fig. 8-7 shows how the common-base
output characteristics appear when the
effects of breakdown are included. Note the
sudden upward swing of each curve at a
large value of VCB. The collector-to-base
breakdown voltage when IE = 0 (emitter
open) is designed BVCBO.
Fig. 8-7
Transistor Amplification Action:
The basic voltage-amplifying action of the CB configuration can now be described
using the circuit of Fig. 8-8. The dc biasing does not appear in the figure since our
interest will be limited to the ac response. For the CB configuration, the input resistance
between the emitter and the base of a transistor will typically vary from 10 to 100 Ω,
while the output resistance may vary from 100 kΩ to 1 MΩ. The difference in
resistance is due to the forward-biased junction at the input (base to emitter) and the
reverse-biased junction at the output (base to collector). Using effective values and a
common value of 20 Ω for the input resistance, we find that
University of Technology
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Bipolar Junction Transistors
Lecture Eight - Page 5 of 8
Dr. Ahmed Saadoon Ezzulddin
I i = Vi / Ri = 200mV / 20Ω = 10mA .
If we assume for the moment that
αac = 1 (Ic = Ie),
I L = I i = 10 mA
and VL = I L R = (10 mA)(5kΩ) = 50V .
The voltage amplification is
Fig. 8-8
Av = VL / Vi = 50V / 200mV = 250 .
Typical values of voltage amplification for the common-base configuration vary
from 50 to 300. The current amplification (IC/IE) is always less than 1 for the CB
configuration. This latter characteristic should be obvious since IC = αIE and α is always
less than 1.
The basic amplifying action was produced by transferring a current I from a
low-to a high-resistance circuit. The combination of the two terms in italics results in
the label transistor; that is, transfer + resistor → transistor.
Common-Emitter (CE) Configuration:
The common-emitter configuration with npn and pnp transistors are indicated in
Fig. 8-9. The external voltage source VBB is used to forward bias the E-B junction and
the external voltage source VCC is used to reverse bias C-B junction. The magnitude of
VCC must be greater than VBB to ensure the C-B junction remains reverse biased, since,
as can be seen in the Fig. 8-9, VCB = VCC − VBB .
IC
C
+
IB
VCB
B −
+
VCE
+
VBB
−
VBE
−
IC
E
C
−
IB
VCC
VBC
+
B
−
VEC
−
IE
VBB
+
VEB
+
E
IE
Fig. 8-9
From Eqs. [8.1] and [8.4], we obtain
I C = α ( I C + I B ) + I CBO
Rearranging yields
I
αI
[8.6]
I C = B + CBO
1−α 1−α
From Fig. 8-10, Eq. [8.6] becomes
I CEO =
I CBO
1−α
[8.7]
I B =0
Fig. 8-10
VCC
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Bipolar Junction Transistors
Lecture Eight - Page 6 of 8
Dr. Ahmed Saadoon Ezzulddin
In the dc mode the levels of IC and IB are related by a quantity called beta (βdc)
and defined by the following equation:
β dc =
IC
IB
[8.8]
Where IC and IB are the levels of current at the point of operation. For practical devices
the levels of βdc typically ranges from about 50 to over 500, with most in the mid range.
On specification sheets βdc is usually included as hFE with h derived from an ac hybrid
equivalent circuit.
For ac situation an ac beta (βac) has been defined as follows:
β ac =
ΔI C
ΔI B
[8.9]
VCE =const .
The formal name for βac is common-emitter, forward-current, amplification factor
and on specification sheets βac is usually included as hfe.
A relationship can be developed between β and α using the basic relationships
introduced thus far. Using β = I C / I B we have I B = I C / β , and from α = I C / I E
we have I E = I C / α . Substituting into I E = I C + I B we have I C / α = I C + I C / β and
dividing both sides of the equation by IC will result in 1 / α = 1 + 1 / β or
β = αβ + α = ( β + 1)α so that
α=
β
β +1
or β =
α
1−α
[8.10]
In addition, recall that I CEO = I CBO /(1 − α ) but using an equivalence of
1 /(1 − α ) = β + 1 derived from the above, we find that I CEO = ( β + 1) I CBO or
I CEO ≅ βI CBO
[8.11]
Beta is particularly important parameter because it provides a direct link between
current levels of the input and output circuits for CE configuration. That is,
I C = βI B + I CEO ≈ βI B
[8.12]
and since I E = I C + I B = βI B + I B we have
I E = ( β + 1) I B
[8.13]
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Bipolar Junction Transistors
Lecture Eight - Page 7 of 8
Dr. Ahmed Saadoon Ezzulddin
The input (base) characteristics for the CE configuration are a plot of the base
(input) current (IB) versus the base-to-emitter (input) voltage (VBE) for a range of values
of collector-to-emitter (output) voltage (VCE) as shown in Fig. 8-11. Note that IB
increases as VCE decreases, for a fixed value of VBE. A large value of VCE results in a
large reverse bias of the C-B junction, which widens the depletion region and makes the
base smaller. When the base is smaller, there are fewer recombinations of injected
minority carriers and there is a corresponding reduction in base current (IB).
Fig. 8-11
Fig. 8-12
The output (collector) characteristics for CE configuration are a plot of the
collector (output) current (IC) versus collector-to-emitter (output) voltage (VCE) for a
range of values of base (input) current (IB) as shown in Fig. 8-12. The collector
characteristics have three basic region of interest, as indicated in Fig. 8-12, the active,
cutoff, and saturation regions.
W Active region: IB > 0 and I C = βI B .
W Cutoff region: IB = 0 and I C = I CEO .
W Saturation region: VCE ≈ 0 and I B ( sat .) = I C ( sat .) / β .
Common-Collector (CC) Configuration:
The third and final transistor configuration is the common-collector configuration,
shown in Fig. 8-13 with npn and pnp transistors. The CC configuration is used
primarily for impedance-matching purposes since it has a high input impedance and
low output impedance, opposite to that which is true of the common-base and
common-emitter configurations.
From a design viewpoint, there is no need for a set of common-collector
characteristics to choose the circuit parameters. The circuit can be designed using the
common-emitter characteristics. For all practical purposes, the output characteristics
of the CC configuration are the same as for the CE configuration. For the CC
configuration the output characteristics are a plot of emitter (output) current (IE)
versus collector-to-emitter (output) voltage (VCE), for a range of values of base (input)
University of Technology
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Bipolar Junction Transistors
Lecture Eight - Page 8 of 8
Dr. Ahmed Saadoon Ezzulddin
current (IB). The output current, therefore, is the same for both the common-emitter
and common-collector characteristics. There is an almost unnoticeable change in the
vertical scale of IC of the common-emitter characteristics if IC is replaced by IE for the
common-collector characteristics (since α ≅ 1 , I E ≈ I C ).
IE
E
−
IB
VBE
+
B
−
VCE
−
VBB
+
VCB
+
IE
C
E
+
IB
VCC
VEB
−
B
+
VEC
+
VBB
IC
−
VBC
−
C
VCC
IC
Fig. 8-13
Transistor Casing and Terminal Identification:
Whenever possible, the transistor casing will have some marking to indicate which
leads are connected to the emitter, collector, or base of a transistor. A few of the
methods commonly used are indicated in Fig. 8-14.
Fig. 8-14
Exercises:
1. Given an αdc of 0.998, determine IC if IE = 4 mA.
2. Determine αdc if IE = 2.8 mA and IB = 20 µA.
3. Find IE if IB = 40 µA and αdc is 0.98.
4. Given that αdc = 0.987, determine the corresponding value of β.
5. Given βdc = 120, determine the corresponding value of α.
6. Given that βdc = 180 and IC = 2.0 mA, find IE and IB.
7. A transistor has ICBO = 48 nA and α = 0.992.
i. Find β and ICEO.
ii. Find its (exact) collector current (IC) when IB = 30 μA.
iii. Find the approximate collector current, neglecting leakage current.
University of Technology
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DC Biasing Circits of BJTs
Lecture Nine - Page 1 of 10
Dr. Ahmed Saadoon Ezzulddin
DC Biasing Circuits of BJTs
Basic Concepts:
The analysis or design of a transistor amplifier requires a knowledge of both the dc and
ac response of the system. Too often it is assumed that the transistor is a magical device
that can raise the level of the applied ac input without the assistance of an external
energy source. In actuality, the improved output ac power level is the result of a
transfer of energy from the applied dc supplies. The analysis or design of any electronic
amplifier therefore has two components: the dc portion and the ac portion. Fortunately,
the superposition theorem is applicable and the investigation of the dc conditions can
be totally separated from the ac response. However, one must keep in mind that during
the design or synthesis stage the choice of parameters for the required dc levels will
affect the ac response, and vice versa.
The term biasing appearing in the title of this lecture is an all-inclusive term for
the application of dc voltages to establish a fixed level of current and voltage. For
transistor amplifiers the resulting dc current and voltage establish an operating point on
the characteristics that define the region that will be employed for amplification of the
applied signal. Since the operating point is a fixed point on the characteristics, it is also
called the quiescent point (abbreviated Q-point). By definition, quiescent means quiet,
still, inactive. Fig. 9-1 shows a general output device characteristic with four operating
points indicated. The biasing circuit can be designed to set the device operation at any
of these points or others within the active region. The maximum ratings are indicated
on the characteristics of Fig. 9-1 by a horizontal line for the maximum collector current
ICmax and a vertical line at the maximum collector-to-emitter voltage VCEmax. The
maximum power constraint is defined by the curve PCmax in the same figure. At the
lower end of the scales are the cutoff region, defined by IB ≤ 0 μA, and the saturation
region, defined by VCE ≤ VCE(sat).
Fig. 9-1
University of Technology
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DC Biasing Circits of BJTs
Lecture Nine - Page 2 of 10
Dr. Ahmed Saadoon Ezzulddin
Standard Biasing Circuits:
1. Fixed-Bias Circuit:
Fig. 9-2a shows a fixed-bias circuit.
Analysis:
W For the input (base-emitter circuit) loop
as shown in Fig. 9-2b:
+ VCC − I B RB − VBE = 0
V − VBE
I B = CC
[9.1a]
RB
W For the output (collector-emitter circuit)
loop as shown in Fig. 9-2c:
I C = βI B
+ VCE + I C RC − VCC = 0
VCE = VCC − I C RC
[9.1b]
W For the transistor terminal voltages:
VE = 0V
[9.1c]
VB = VCC − I B RB = VBE
(a)
VC = VCC − I C RC = VCE
(b)
Load-Line Analysis:
From Eq. [9.1b] and Fig. 9-3:
W At cutoff region:
VCE = VCC I =0
[9.2a]
(c)
Fig. 9-2
C
W At saturation region:
V
I C = CC
RC V =0
[9.2b]
CE
Design:
For an optimum design:
1
VCEQ = VCC
2
V
1
I CQ = I C ( sat ) = CC
2
2 RC
ICQ
[9-3]
VCEQ
Fig. 9-3
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DC Biasing Circits of BJTs
Lecture Nine - Page 3 of 10
Dr. Ahmed Saadoon Ezzulddin
2. Emitter-Stabilized Bias Circuit:
Fig. 9-4a shows an emitter-stabilized bias circuit.
Analysis:
W For the input (base-emitter circuit) loop
as shown in Fig. 9-4b:
+ VCC − I B RB − VBE − I E RE = 0
I E = ( β + 1) I B
VCC − VBE
IB =
[9.4a]
RB + ( β + 1) RE
W For the output (collector-emitter circuit)
loop as shown in Fig. 9-4c:
+ I E RE + VCE + I C RC − VCC = 0
I E ≅ IC
VCE = VCC − I C ( RC + RE )
[9.4b]
W For the transistor terminal voltages:
VE = I E R E
[9.4c]
VB = VCC − I B RB = VE + VBE
VC = VCC − I C RC = VE + VCE
Load-Line Analysis:
From Eq. [9.4b] and Fig. 9-5:
W At cutoff region:
VCE = VCC I =0
C
W At saturation region:
VCC
IC =
RC + RE V =0
(a)
(b)
(c)
Fig. 9-4
[9.5a]
[9.5b]
CE
Design:
For an optimum design:
1
VCEQ = VCC
2
VCC
1
I CQ = I C ( sat ) =
2
2( RC + RE )
VE =
1
VCC
10
ICQ
VCEQ
[9-6]
Fig. 9-5
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DC Biasing Circits of BJTs
Lecture Nine - Page 4 of 10
Dr. Ahmed Saadoon Ezzulddin
3. Voltage-Divider Bias Circuit:
Fig. 9-6a shows a voltage-divider bias circuit.
Analyses:
W For the input (base-emitter circuit) loop:
Exact Analysis:
From Fig. 9-6b:
RTh = R1 R2
[9.7a]
From Fig. 9-6c:
RV
ETh = VR2 = 2 CC
[9.7b]
R1 + R2
From Fig. 9-6d:
+ ETh − I B RTh − VBE − I E RE = 0
I E = ( β + 1) I B
ETh − VBE
IB =
[9.7c]
RTh + ( β + 1) RE
I C = βI B
Approximate Analysis:
From Fig. 9-6e:
If Ri >> R2 => I 2 >> I B .
Since I B ≈ 0 => I1 ≅ I 2 .
Thus R1 in series with R2.
That is,
RV
VB = 2 CC
[9.8a]
R1 + R2
Since Ri = ( β + 1) RE ≅ βRE the condition
that will define whether the approximation
approach can be applied will be the
following:
βRE ≥ 10R2
[9.8b]
and
VE = VB − VBE
[9.8c]
V
IC ≅ I E = E
RE
W For the output (collector-emitter circuit) loop:
VCE = VCC − I C ( RC + RE )
[9.9]
(a)
(b)
(c)
(d)
(e)
Fig. 9-6
University of Technology
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DC Biasing Circits of BJTs
Lecture Nine - Page 5 of 10
Dr. Ahmed Saadoon Ezzulddin
Load-Line Analysis:
The similarities with the output circuit of the emitter-biased configuration result in the
same intersections for the load line of the voltage-divider configuration. The load line
will therefore have the same appearance as that of Fig. 9-5. The level of IB is of course
determined by a different equation for the voltage-divider bias and the emitter-bias
configuration.
Design:
For an optimum design:
1
VCEQ = VCC
2
VCC
1
I CQ = I C ( sat ) =
2
2( RC + RE )
1
VE = VCC
10
1
R2 ≤ βRE
10
[9.10]
Example 9-1:
Determine the dc bias voltage VCE and the current IC for the voltage-divider
configuration of Fig. 9-6a with the following parameters: VCC = +22 V, β = 140,
R1 = 39 kΩ, R2 = 3.9 kΩ, RC = 10 kΩ, and RE = 1.5 kΩ.
Solution:
Exact:
RTh = R1 R2 = 39k 3.9k = 3.55Ω
RV
(3.9k )(22)
ETh = 2 CC =
= 2V
R1 + R2 39k + 3.9k
ETh − VBE
IB =
RTh + ( β + 1) RE
2 − 0.7
=
= 6.05μA
3.55k + (141)(1.5k )
I CQ = βI B = (140)(6.05μ ) = 0.85mA
VCEQ = VCC − I C ( RC + RE )
= 22 − (0.85m)(10k + 1.5k )
= 12.23V
Approximate:
Testing:
βRE ≥ 10R2
(140)(1.5k ) ≥ 10(3.9k )
210kΩ > 39kΩ (satisfied)
RV
(3.9k )(22)
VB = 2 CC =
= 2V
R1 + R2 39k + 3.9k
VE = VB − VBE = 2 − 0.7 = 1.3V
V
1.3
I CQ = I E = E =
= 0.867 mA
RE 1.5k
VCEQ = VCC − I C ( RC + RE )
= 22 − (0.867 m)(10k + 1.5k )
= 12.03V
University of Technology
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DC Biasing Circits of BJTs
Lecture Nine - Page 6 of 10
Dr. Ahmed Saadoon Ezzulddin
4. Voltage-Feedback Bias Circuit:
Fig. 9-7a shows a voltage-feedback bias circuit.
Analysis:
W For the input (base-emitter circuit) loop
as shown in Fig. 9-7b:
+ VCC − I C′ RC − I B RB − VBE − I E RE = 0
I C′ = I C + I B = I E ≅ I C = βI B
+ VCC − βI B RC − I B RB − VBE − βI B RE = 0
VCC − VBE
IB =
[9.11a]
RB + β ( RC + RE )
W For the output (collector-emitter circuit)
loop as shown in Fig. 9-7c:
+ I E RE + VCE + I C′ RC − VCC = 0
I C′ = I E ≅ I C
VCE = VCC − I C ( RC + RE )
[9.11b]
(a)
Load-Line Analysis:
Continuing with the approximation I C′ = I C will result
in the same load line defined for the voltage-divider and
emitter-biased configurations. The levels of IBQ will be
defined by the chosen base configuration.
(b)
Design:
For an optimum design:
1
VCEQ = VCC
2
VCC
1
I CQ = I C ( sat ) =
2
2( RC + RE )
[9-12]
1
VCC
10
RB ≤ β ( RC + RE )
VE =
(c)
Fig. 9-7
University of Technology
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DC Biasing Circits of BJTs
Lecture Nine - Page 7 of 10
Dr. Ahmed Saadoon Ezzulddin
Other Biasing Circuits:
Example 9-2: (Negative Supply)
Determine VC and VB for the circuit of Fig. 9-8.
Solution:
− I B RB − VBE + VEE = 0
(KVL)
V − VBE 9 − 0.7
I B = EE
=
= 83μA
RB
100k
I C = βI B = (45)(83μ ) = 3.735mA
VC = − I C RC = −(3.735m)(1.2k ) = −4.48V
VB = − I B RB = −(83μ )(100k ) = −8.3V
Fig. 9-8
Example 9-3: (Two Supplies)
Determine VC and VB for the circuit of Fig. 9-9a.
Solution:
From Fig. 9-9b:
RTh = R1 R2 = 8.2k 2.2k = 1.73kΩ
V + VEE
20 + 20
I = CC
=
= 3.85mA
R1 + R2
8.2k + 2.2k
ETh = IR2 − VEE = (3.85m)(2.2k ) − 20 = −11.53V
From Fig. 9-9c:
− ETh − I B RTh − VBE − I E RE + VEE = 0 (KVL)
I E = ( β + 1) I B
V − ETh − VBE
I B = EE
RTh + ( β + 1) RE
20 − 11.53 − 0.7
=
= 35.39 μA
1.73k + (121)(1.8k )
I C = βI B = (120)(35.39μ ) = 4.25mA
VC = VCC − I C RC = 20 − (4.25m)(2.7k ) = 8.53V
VB = − ETh − I B RTh = −(11.53) − (35.39 μ )(1.73k )
= −11.59V
(a)
(b)
(c)
Fig. 9-9
University of Technology
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DC Biasing Circits of BJTs
Lecture Nine - Page 8 of 10
Dr. Ahmed Saadoon Ezzulddin
Example 9-4: (Common-Base)
Determine VCB and IB for the common-base configuration of Fig. 9-10.
Solution:
Applying KVL to the input circuit:
− VEE + I E RE + VBE = 0
V − VBE 4 − 0.7
I E = EE
=
= 2.75mA
RE
1.2k
Applying KVL to the output circuit:
+ VCB + I C RC − VCC = 0
VCB = VCC − I C RC
with I C ≅ I E
VCB = 10 − (2.75m)(2.4k ) = 3.4V
I
2.75m
IB = C =
= 45.8μA
β
60
Fig. 9-10
Example 9-5: (Common-Collector)
Determine IE and VCE for the common-collector (emitter-follower) configuration of
Fig. 9-11.
Solution:
Applying KVL to the input circuit:
− I B RB − VBE − I E RE + VEE = 0
I E = ( β + 1) I B
VEE − VBE
IB =
RB + ( β + 1) RE
20 − 0.7
=
= 45.73μA
240k + (91)(2k )
I E = ( β + 1) I B = (91)(45.73μ ) = 4.16mA
Applying KVL to the output circuit:
− VEE + I E RE + VCE = 0
VCE = VEE − I E RE = 20 − (4.16m)(2k ) = 11.68V
Fig. 9-11
University of Technology
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Second Year, Electronics I, 2009 - 2010
DC Biasing Circits of BJTs
Lecture Nine - Page 9 of 10
Dr. Ahmed Saadoon Ezzulddin
Example 9-6: (PNP Transistor)
Determine VCE for the voltage-divider bias configuration of Fig. 9-12.
Solution:
Testing:
βRE ≥ 10R2
(120)(1.1k ) ≥ 10(10k )
132kΩ ≥ 100kΩ( satisfied )
RV
(10k )(−18)
VB = 2 CC =
= −3.16V
R1 + R2 47 k + 10k
VE = VB − VBE = −3.16 − (−0.7) = −2.46V
V
2.46
IC = I E = E =
= 2.24mA
RE 1.1k
− I E RE + VCE − I C RC + VCC = 0 (KVL)
VCE = −VCC + I C ( RC + RE )
= −18 + (2.24m)(2.4k + 1.1k ) = −10.16V
Fig. 9-12
Exercises:
1. For the fixed-biased configuration of Fig. 9-2a with the following parameters:
VCC = +12 V, β = 50, RB = 240 kΩ, and RC = 2.2 kΩ, determine:
IBQ, ICQ, VCEQ, VB, VC, and VBC.
2. Given the device characteristics of Fig. 9-13a, determine VCC, RB, and RC for the
fixed-bias configuration of Fig. 9-13b.
(a)
(b)
Fig. 9-13
University of Technology
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DC Biasing Circits of BJTs
Lecture Nine - Page 10 of 10
Dr. Ahmed Saadoon Ezzulddin
3. For the emitter bias circuit of Fig. 9-4a with the following parameters:
VCC = +20 V, β = 50, RB = 430 kΩ, RC = 2 kΩ, and RE = 1 kΩ, determine:
IB, IC, VCE, VC, VE, VB and VBC.
4. Design an emitter-stabilized circuit (Fig. 9-4a) at ICQ = 2 mA. Use VCC = +20 V
and an npn transistor with β =150.
5. Determine the dc bias voltage VCE and the current IC for the voltage-divider
configuration of Fig. 9-6a with the following parameters: VCC = +18 V, β = 50,
R1 = 82 kΩ, R2 = 22 kΩ, RC = 5.6 kΩ, and RE = 1.2 kΩ.
6. Design a beta-independent (voltage-divider) circuit to operate at VCEQ = 8 V and
ICQ = 10 mA. Use a supply of VCC = +20 V and an npn transistor with β = 80.
7. Determine the quiescent levels of ICQ and VCEQ for the voltage-feedback circuit
of Fig. 9-7a with the following parameters: VCC = +10 V, β = 90, RB = 250 kΩ,
RC = 4.7 kΩ, and RE = 1.2 kΩ.
8. Prove that RB ≤ β ( RC + RE ) is the required condition for an optimum design of
the voltage-feedback circuit.
9. Prove mathematically that ICQ for the voltage-feedback bias circuit is approximately
independent of the value of beta.
10. Fig. 9-14 shows a three-stage circuit with a VCC supply of +20 V. GND stands for
ground. If all transistors have a β of 100, what are the IC and VCE of each stage?
+ 20V
10μF
2kΩ
vi
3kΩ
10μF
10μF
100kΩ
0.56kΩ
8kΩ
3kΩ
50kΩ
10μF
vo
0.68kΩ
GND
Fig. 9-14
University of Technology
Electrical and Electronic Engineering Department
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Bias Stabilization
Lecture Ten - Page 1 of 5
Dr. Ahmed Saadoon Ezzulddin
Bias Stabilization
Basic Definitions:
The stability of system is a measure of sensitivity of a circuit to variations in its
parameters. In any amplifier employing a transistor the collector current IC is sensitive
to each of the following parameters:
W ICO (reverse saturation current): doubles in value for every 10oC increase in
temperature.
W |VBE| (base-to-emitter voltage): decrease about 7.5 mV per 1oC increase in
temperature.
W β (forward current gain): increase with increase in temperature.
Any or all of these factors can cause the bias point to drift from the design point of
operation.
Stability Factors, S(ICO), S(VBE), and S(β):
A stability factor, S, is defined for each of the parameters affecting bias stability as
listed below:
S ( I CO ) =
S (VBE ) =
S (β ) =
ΔI C
∂I
= C
ΔI CO ∂I CO
∂I
ΔI C
= C
ΔVBE ∂VBE
ΔI C ∂I C
=
Δβ
∂β
[10.1a]
VBE , β =const .
[10.1b]
I CO , β =const .
[10.1c]
I CO ,VBE =const .
Generally, networks that are quite stable and relatively insensitive to temperature
variations have low stability factors. In some ways it would seem more appropriate to
consider the quantities defined by Eqs. [10.1a - 10.1c] to be sensitivity factors because:
the higher the stability factor, the more sensitive the network to variations in that
parameter.
The total effect on the collector current can be determined using the following
equation:
ΔI C = S ( I CO )ΔI CO + S (VBE )ΔVBE + S ( β )Δβ
[10.2]
University of Technology
Electrical and Electronic Engineering Department
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Bias Stabilization
Lecture Ten - Page 2 of 5
Dr. Ahmed Saadoon Ezzulddin
Derivation of Stability Factors for Standard Bias Circuits:
For the voltage-divider bias circuit, the exact analysis (using Thevenin theorem) for the
input (base-emitter) loop will result in:
and
and
or
ETh − I B RTh − VBE − I E RE = 0 ,
I E = I C + I B =>
I C RE + I B ( RE + RTh ) + VBE = ETh ,
I C = βI B + ( β + 1) I CO ,
I
β +1
IB = C −
I CO =>
β
β
⎡ ( β + 1) RE + RTh ⎤
⎡ ( β + 1)( RE + RTh ) ⎤
IC ⎢
− I CO ⎢
⎥
⎥ + VBE = ETh
β
β
⎣
⎦
⎣
⎦
[10.3]
The partial derivation of the Eq. [10.3] with respect to ICO will result:
∂I C ( β + 1) RE + RTh ( β + 1)( RE + RTh )
=0
⋅
−
∂I CO
β
β
S ( I CO ) =
( β + 1)( RE + RTh )
( β + 1) RE + RTh
[10.4a]
Also, the partial derivation of the Eq. [10.3] with respect to VBE will result:
∂I C ( β + 1) RE + RTh
+1 = 0
⋅
∂VBE
β
S (VBE ) =
−β
( β + 1) RE + RTh
[10.4b]
The mathematical development of the last stability factor S(β) is more complex than
encountered for S(ICO) and S(VBE). Thus, S(β) is suggested by the following equation:
S (β ) =
( I C 1 / β1 )( RE + RTh )
( β 2 + 1) RE + RTh
[10.4c]
University of Technology
Electrical and Electronic Engineering Department
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Bias Stabilization
Lecture Ten - Page 3 of 5
Dr. Ahmed Saadoon Ezzulddin
For the emitter-stabilized bias circuit, the stability factors are the same as these
obtained above for the voltage-divider bias circuit except that RTh will replaced by RB.
These are:
S ( I CO ) =
( β + 1)( RE + RB )
( β + 1) RE + RB
[10.5a]
S (VBE ) =
−β
( β + 1) RE + RB
[10.5b]
S (β ) =
result:
( I C 1 / β1 )( RE + RB )
( β 2 + 1) RE + RB
[10.5c]
For the fixed-bias circuit, if we plug in RE = 0 the following equation will
S ( I CO ) = β + 1
S (VBE ) = −
S (β ) =
β
RB
IC 1
β1
[10.6a]
[10.6b]
[10.6c]
Finally, for the case of the voltage-feedback bias circuit, the following equation
will result:
S ( I CO ) =
( β + 1)( RC + RE + RB )
( β + 1)( RC + RE ) + RB
[10.7a]
S (VBE ) =
−β
( β + 1)( RC + RE ) + RB
[10.7b]
S (β ) =
( I C 1 / β1 )( RC + RE + RB )
( β 2 + 1)( RC + RE ) + RB
[10.7c]
University of Technology
Electrical and Electronic Engineering Department
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Bias Stabilization
Lecture Ten - Page 4 of 5
Dr. Ahmed Saadoon Ezzulddin
Example 10-1:
1. Design a voltage-divider bias circuit using a VCC supply of +18 V, and an npn silicon
transistor with β of 80. Choose RC = 5RE, and set IC at 1 mA and the stability factor
S(ICO) at 3.8.
2. For the circuit designed in part (1), determine the change in IC if a change in
operating conditions results in ICO increasing from 0.2 to 10 μA, VBE drops from
0.7 to 0.5 V, and β increases 25%.
3. Calculate the change in IC from 25o to 75oC for the same circuit designed in part (1),
if ICO = 0.2 μA and VBE = 0.7 V.
Solution:
VCC
+ 18V
Part 1:
VCE = VCC / 2 = 18 / 2 = 9V .
RC 7.5kΩ
Co
R1 36kΩ
VCE = VCC − I C ( RC + RE ) , RC = 5 RE =>
9 = 18 − (1m)(5RE + RE ) => RE = 1.5kΩ .
Ci
RC = 5(1.5k ) = 7.5kΩ .
vi
β = 80
I E ≅ I C = 1mA , VE = I E RE = (1m)(1.5k ) = 1.5V .
VB = VE + VBE = 1.5 + 0.7 = 2.2V .
R2 5kΩ
RE 1.5kΩ
R2
VB 2.2
R2VCC
=
=
VB =
=>
[10.8a]
R1 + R2 VCC 18
R1 + R2
( β + 1)( RE + RTh )
S ( I CO ) =
=>
Fig. 10-1
( β + 1) RE + RTh
(81)(1.5k + RTh )
3.8 =
=> RTh = 4.4kΩ .
(81)(1.5k ) + RTh
R
R2
4.4k
RR
= Th =
RTh = 1 2 =>
[10.8b]
R1 + R 2
R1
R1
R1 + R2
From Eqs. [10.8a] and [10.8b]:
4.4k 2.2
=
=> R1 = 36kΩ .
18
R1
From Eq. [10.8a]:
R2
2.2
=
=> R2 = 5kΩ .
36k + R2 18
Fig. 10-1 shows the final circuit.
vo
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
Bias Stabilization
Lecture Ten - Page 5 of 5
Dr. Ahmed Saadoon Ezzulddin
Part 2:
S ( I CO ) = 3.8 ,
ΔI CO = 10 μ − 0.2 μ = 9.8μA .
− 80
−β
S (VBE ) =
=
= −0.635mS ,
( β + 1) RE + RTh (81)(1.5k ) + 4.4k
ΔVBE = 0.5 − 0.7 = −0.2V .
β 2 = β1 (1 + 25 / 100) = 1.25β1 = 1.25(80) = 100 ,
( I C 1 / β1 )( RE + RTh ) (1m / 80)(1.5k + 4.4k )
S (β ) =
=
= 0.473μA ,
( β 2 + 1) RE + RTh
(101)(1.5k ) + 4.4k
Δβ = 100 − 80 = 20 .
ΔI C = S ( I CO )ΔI CO + S (VBE )ΔVBE + S ( β )Δβ
= (3.8)(9.8μ ) + (−0.635m)(−0.2) + (0.473μ )(20) = 0.174mA .
Part 3:
Since ICO, doubles in value for every 10oC increase in temperature.
ΔT 75 − 25
Thus N =
=
= 5 , I CO (75 o C ) = 2 N ⋅ I CO (25 o C ) = (2 5 )(0.2 μ ) = 6.4 μA .
10
10
ΔI CO = 6.4 μ − 0.2 μ = 6.2 μA .
Since VBE, decreases about 7.5 mV per 1oC increase in temperature.
Thus ΔT = 75 − 25 = 50 o C , VBE (25o C ) = 0.7V =>
VBE (75o C ) = 0.7 − 50(7.5m) = 0.325V .
ΔI C = S ( I CO )ΔI CO + S (VBE )ΔVBE
= (3.8)(6.2 μ ) + (−0.635m)(−0.375) = 0.262mA .
Exercises:
1. Derive a mathematical expression to determine the
S (VCC ) = ΔI C ΔVCC for the emitter-stabilized bias circuit.
stability
factor
2. Discuss and compare (by equations) between the relative levels of stability for the
following biasing circuits:
i. the fixed-bias circuit,
ii. the emitter-stabilized bias circuit,
iii. the voltage-divider bias circuit, and
iv. the voltage-feedback circuit.
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
BJT Switching Circuits
Lecture Eleven - Page 1 of 3
Dr. Ahmed Saadoon Ezzulddin
BJT Switching Circuits
Basic Concepts:
The application of transistors is not limited solely to the amplification of signals.
Through proper design it can be used as a switch for computer and control applications.
The circuit of Fig. 11-1a can be employed as an inverter in computer logic circuitry.
Note that the output voltage VC is opposite to that applied to the base or input terminal.
In addition, note the absence of a dc supply connected to the base circuit. The only dc
source is connected to the collector or output side and for computer applications is
typically equal to the magnitude of the "high" side of the applied signal-in this case 5V.
VCC + 5V
RC
VC
+ 5V
0V
Vi
RB
+
+
VBE
(a)
+ 5V
0V
VCE
−
−
(b)
Fig. 11-1
Proper design for the inversion process requires that the operating point switch
from cutoff to saturation along the load line depicted in Fig. 11-1b. For our purposes
we will assume that I C = I CEO ≈ 0 mA when I B = 0 μA (an excellent approximation
in light of improving construction techniques), as shown in Fig. 11-1b. In addition, we
will assume that VCE = VCE ( sat ) ≈ 0 V rather than the typical 0.1 to 0.3 V level.
When Vi = 5 V, the transistor will be "on" and the design must ensure that the
circuit is heavily saturated by a level of IB greater than that associated with the IB
curve appearing near the saturation level.
The base current IB for the circuit of Fig. 11-1a is determined by
V − VBE
IB = i
[11.1]
RB
The saturation level for collector current IC(sat) for the same circuit is defined by
V
I C ( sat ) = CC
[11.2]
RC
The level of IB in the active region just before saturation results can be approximated
by the following equation:
I C ( sat )
I B (max) ≅
[11.3]
β
For the saturation level we must therefore ensure that the following is satisfied:
I B > I B (max)
[11.4]
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
BJT Switching Circuits
Lecture Eleven - Page 2 of 3
Dr. Ahmed Saadoon Ezzulddin
Example 11-1:
Verify that the circuit shown in Fig. 11-2 behaves like an inverter when the input
switches between 0 V and +10 V. Assume that the transistor is silicon and that β = 50.
Solution:
It is only necessary to verify that the transistor is
saturated when Vi = +10 V.
V − VBE 10 − 0.7
IB = i
= 42.3μA .
=
RB
220k
I C ( sat ) VCC
10
I B (max) =
=
=
= 32.3μA .
β
βRC (50)(6.2k )
Thus, we have I B > I B (max) , therefore the transistor is
saturated, and the circuit is inverter.
VCC + 10V
RC 6.2kΩ
Vo
RB
Vi
β = 50
220kΩ
Fig. 11-2
Example 11-2:
Verify that the circuit shown in Fig. 11-3 is an inverter when the input switches
between 0 V and -5 V. What minimum value of β is required? Assume that the
transistor is silicon.
Solution:
(4)(5k )
= 0.8V , hence the
20k + 5k
transistor is at cutoff, so that D1 and D2 are on and
Vo = −4 − 0.7 − 0.3 = −5V .
When Vi = −5V , RTh = 5k 20k = 4kΩ ,
(+4)(5k ) (−5)(20k )
ETh =
+
= −3.2V ,
20k + 5k 20k + 5k
E − VBE 3.2 − 0.7
I B = Th
=
= 625μA .
RTh
4k
We assume the transistor is at saturation, Vo = 0V ,
so that D1 and D2 are off and
V
20
I C ( sat ) = CC =
= 12.5mA ,
RC 1.6k
I B (max) = I C ( sat ) / β = 12.5mA / β .
VCC − 20V
When Vi = 0V , VB =
For the transistor to be in saturation,
I C ( sat ) 12.5m
=
= 20 .
I B > I B (max) => β >
IB
625μ
− 4V
Vi
R1
D1 D2
Si
RC 1.6kΩ
Ge
5kΩ
R2 20kΩ
+ 4V
Fig. 11-3
Vo
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
BJT Switching Circuits
Lecture Eleven - Page 3 of 3
Dr. Ahmed Saadoon Ezzulddin
Exercise:
1. Design the transistor inverter of Fig. 11-4 to operate with a saturation current of
8 mA using a transistor with a beta of 100. Use a level of IB equal to 120% of
IB(max) and standard resistor values.
VCC + 5V
RC
Vi
Vo
5
Vi
0
RB
β = 100
t
Fig. 11-4
2. Verify that the circuit shown in Fig. 11-5 is a positive NAND when the input
switches between 0 V and +12 V. Neglect source impedance and junction saturation
voltages and diode voltages in forward direction. Find the minimum value of β.
+ 12V
VA
VB
VCC
+ 12V
RC
2.2kΩ
Vo
R1 15kΩ
D1
R2
D2
15kΩ
R3
100kΩ
− 12V
Fig. 11-5
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
BJT Modeling and AC Equivalent Circuit
Lecture Twelve - Page 1 of 9
Dr. Ahmed Saadoon Ezzulddin
BJT Modeling and AC Equivalent Circuit
Basic Concepts:
The key to the transistor small-signal analysis is the use of ac equivalent circuits or
models. A model is the combination of circuit elements, properly chosen, that best
approximates the actual behavior of a semiconductor device (BJT) under specific
operating conditions. Once the ac equivalent circuit has been determined, the graphical
symbol of the device can be replaced in the schematic by this circuit and the basic
methods of ac circuit analysis (mesh analysis, nodal analysis, and Thevenin's theorem)
can be applied to determine the response of the circuit. There are two schools of
thought in prominence today regarding the equivalent circuit to be substituted for the
transistor: hybrid and re model.
In summary, the ac equivalent circuit of the BJT amplifier is obtained by
(see Fig. 12-1):
1. Setting all dc sources to zero and replacing them by a short-circuit equivalent.
2. Replacing all capacitors by a short-circuit equivalent.
3. Removing all elements bypassed by the short-circuit equivalents introduced by
stapes 1 and 2.
4. Redrawing the circuit in a more convenient and logical form.
5. Use the hybrid or re equivalent circuit of the BJT to complete the equivalent circuit
of the amplifier.
6. Finally, the following parameters are determined for the amplifier:
a. Input impedance (Zi). b. Output impedance (Zo). c. Voltage gain (Av).
d. Current gain (Ai).
e. Phase relationship (θ).
(a)
(b)
(c)
Fig. 12-1
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
BJT Modeling and AC Equivalent Circuit
Lecture Twelve - Page 2 of 9
Dr. Ahmed Saadoon Ezzulddin
The Hybrid (h-parameters) Equivalent Model:
For the general hybrid two-port system of Fig. 12-2:
Vi = h11 I i + h12Vo
I o = h21 I i + h22Vo
[12.1a]
[12.1b]
Fig. 12-2
where
h11 =
h12 =
h21 =
h22 =
Vi
Ii
Vi
Vo
Io
Ii
Io
Vo
= hi (Ω) , short-circuit input impedance parameter.
Vo =0
= hr (unitless ) , open-circuit reverse transfer voltage ratio parameter.
I i =0
= h f (unitless ) , short-circuit forward transfer current ratio parameter.
Vo =0
= ho ( S ) , open-circuit output admittance parameter.
Ii =0
From the BJT hybrid equivalent circuit of Fig. 12-3, Eqs. [12.1a] and [12.1b] becomes:
Vi = hi I i + hrVo
I o = h f I i + hoVo
[12.2a]
[12.2b]
Fig. 12-3
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
BJT Modeling and AC Equivalent Circuit
Lecture Twelve - Page 3 of 9
Dr. Ahmed Saadoon Ezzulddin
Gain and Impedance Computation of the Complete Hybrid Equivalent Circuit:
For the circuit of Fig. 12-4,
RS
+
VS
−
Ii
+
Vi
−
Io
hi
Zi
hrVo
+
h f Ii
−
Zo
1 / ho
+
Vo
−
RL
Fig. 12-4
the voltage gain (Av = Vo/Vi);
V
V − hrVo
, I o = − o , and I o = h f I i + hoVo =>
Ii = i
hi
RL
− h f RL
V
Av = o =
[12.3a]
Vi hi + (hi ho − h f hr ) RL
the current gain (Ai = Io/Ii);
h f Ii
1 ho
Io = h f Ii
=
=>
1 ho + RL 1 + ho RL
hf
I
Ai = o =
I i 1 + ho RL
[12.3b]
the input impedance (Zi = Vi/Ii);
Vi
V
V
I
= hi + hr o , and Vo = − I o RL => i = hi − hr RL o = hi − hr RL Ai =>
Ii
Ii
Ii
Ii
h f hr RL
V
Z i = i = hi −
[12.3c]
Ii
1 + ho RL
the output impedance (Zo = Vo/Io when VS = 0 V);
hV
VS = I i ( RS + hi ) + hrVo = 0 => I i = − r o , and I o = h f I i + hoVo =>
RS + hi
h f hr
I o = hoVo −
Vo =>
RS + hi
V
1
Zo = o =
[12.3d]
h f hr
Io
ho −
RS + hi
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
BJT Modeling and AC Equivalent Circuit
Lecture Twelve - Page 4 of 9
Dr. Ahmed Saadoon Ezzulddin
Types of Hybrid Parameters:
Since there are three types of BJT configuration (CE, CC, and CB), there are three
different ways that the input and output can be defined and therefore three
corresponding sets of h-parameters as shown in Table 12-1. If all of the h-parameters
values in one configuration are known, then the values corresponding to any other
configuration can be determined. The common-emitter values of the h-parameters are
the ones most often given.
Table 12-1
BJT configuration
h-parameters sets
1
2
3
Common-Emitter
Common-Collector
Common-Base
hie , hfe , hre , hoe
hic , hfc , hrc , hoc
hib , hfb , hrb , hob
The hybrid equivalent circuits of the CE and CB transistor configuration are
shown in Fig. 12-5 (a) and (b) respectively.
(a)
(b)
Fig. 12-5
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
BJT Modeling and AC Equivalent Circuit
Lecture Twelve - Page 5 of 9
Dr. Ahmed Saadoon Ezzulddin
Table 12-2 lists typical parameter values in each of the three transistor
configurations (CE, CC, and CB) for the broad range of transistors available today.
h-parameters
hi
hr
hf
ho
1/ho
Table 12-2
CE
CC
1kΩ
2.5×10-4
50
25 μS
40 kΩ
1kΩ
≈1
−50
25 μS
40 kΩ
CB
20kΩ
3.0×10-4
−0.98
0.5 μS
2 MΩ
Graphical Determination of the CE Hybrid Parameters:
The parameters hie and hre are determined from the input or base characteristics, while
the parameters hfe and hoe are obtained from the output or collector characteristics as
shown in Fig. 12-6.
hie =
h fe =
Δvbe
Δib
Δic
Δib
= 1.5kΩ
hre =
VCE =const .
= 100
hoe =
VCE =const .
Fig. 12-6
Δvbe
Δvce
Δic
Δvce
= 4 × 10− 4
I B = const .
= 33μS
I B =const .
University of Technology
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BJT Modeling and AC Equivalent Circuit
Lecture Twelve - Page 6 of 9
Dr. Ahmed Saadoon Ezzulddin
For the transistor whose characteristics have appeared in Fig. 12-6, the resulting
hybrid small-signal equivalent circuit is shown in Fig. 12-7.
Fig. 12-7
The typical values of h-parameters for CE transistor configuration are shown in
Table 12-3.
Table 12-3
hxe parameters
Min.
Input impedance
Voltage feedback ratio
Small-signal current gain
Output admittance
hie
hre
hfe
hoe
Max.
Unit
7.5
8.0
250
30
kΩ
×10-4
−
μS
0.5
0.1
20
1.0
Approximate CE Hybrid Equivalent Model:
Since hre is normally a relatively small quantity, its removal is approximated by hre ≈ 0
and hreVce = 0, resulting in a short-circuit equivalent for the feedback element. The
resistance determined by 1/hoe is often large enough to be ignored in comparison to a
parallel load permitting its replacement by an open-circuit equivalent for the CE model
as shown in Fig. 12-8.
b
+
Vi
Ib
Ic
c
Zi
Zo
+
−
hie
h fe I b
e
Vo
−
Io
Z o′
RL
e
Fig. 12-8
For the circuit of Fig. 12-8,
Z i = hie , and Z o = ∞ .
V
I R
I R
Z′
R
I
Ai = c = h fe , and Av = o = − o L = − c L = − h fe L = − Ai o .
Ib
Vi
I b hie
I b hie
hie
Zi
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BJT Modeling and AC Equivalent Circuit
Lecture Twelve - Page 7 of 9
Dr. Ahmed Saadoon Ezzulddin
The re Equivalent Model:
CB Transistor Configuration:
From Fig. 12-9, the input impedance at the emitter of CB transistor configuration
(dynamic resistance of the forward diode) can de determined by:
re =
26mV
IE
[12.4]
the output impedance at the collector (dynamic resistance of the reverse diode) is:
ro ≈ ∞
also;
Z i = re , and Z o = ∞ .
Vo = − I o RL = −(− I c ) RL = αI e RL , and Vi = I e Z i = I e re =>
V αR
R
Av = o = L ≈ L .
Vi
re
re
I
I
I c = αI e , and Ai = o = − c =>
Ii
Ie
Ai = −α ≈ −1 .
(a)
(b)
(d)
(c)
(e)
Fig. 12-9
University of Technology
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BJT Modeling and AC Equivalent Circuit
Lecture Twelve - Page 8 of 9
Dr. Ahmed Saadoon Ezzulddin
CE Transistor Configuration:
From Fig. 12-10;
I c = βI b , I e = I c + I b = βI b + I b = ( β + 1) I b ≈ βI b , and
Vbe = I e re ≈ βI b re .
V V
Z i = i = be = β ⋅ re .
Ii Ib
Z o = ro ≈ ∞ .
Vo = − I o RL = − I c RL = − βI b RL ,
βI R
V
V
R
Av = o = o = − b L = − L .
Vi Vbe
βI b re
re
Ai =
I o I c βI b
= =
=β .
Ii Ib
Ib
(a)
(b)
(c)
(d)
(e)
(g)
Fig. 12-10
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BJT Modeling and AC Equivalent Circuit
Lecture Twelve - Page 9 of 9
Dr. Ahmed Saadoon Ezzulddin
Hybrid Versus re Model:
The hybrid versus re model for CE and CB transistor configurations are shown in
Figs. 12-11 (a) and (b) respectively.
(a)
(b)
Fig. 12-11
Approximate Conversion Formulas for Hybrid and re Models:
The approximate conversion formulas for hybrid and re models for CB and CC
configurations are listed in Table 12-4.
Table 12-4
CB Configuration
hib ≅ hie (1 + h fe ) ≅ re
hrb ≅ hie hoe (1 + h fe ) − hre
CC Configuration
hic ≅ hie ≅ βre
h fb ≅ − h fe (1 + h fe ) ≅ −α
hrc ≅ 1 − hre ≅ 1
h fc ≅ −(1 + h fe ) ≅ − β
hob ≅ hoe (1 + h fe )
hoc ≅ hoe ≅ 1 / ro
Exercise:
Given IE = 1.3 mA, β = 100, and ro = 40 kΩ, sketch:
1. The CE and CB hybrid equivalent models.
2. The CE and CB re equivalent models.
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BJT Small-Signal Analysis
Lecture Thirteen - Page 1 of 12
Dr. Ahmed Saadoon Ezzulddin
BJT Small-Signal Analysis
Common-Emitter Configuration:
The voltage divider circuit of Fig. 13-1 includes an emitter resistor (RE) that may or
may not be bypassed by an emitter capacitor (CE) in the ac domain.
+ VCC
R1
I i CS
RS
Vs
C
B
Zi
Zb
Vi
R2
+
+
RC C
C Io
−
Zo
+
Vo
−
Z o′
RL
E
RE
−
CE
Z in
Fig. 13-1
Bypassed (absence of RE):
For the ac equivalent circuit of Fig. 13-2,
b Ib
Ii
RS
+
Vs
Zi
+
Vi
−
Zb
R′
Ic
βre
βI b
ro
hie e
h fe I b
1 / hoe
−
Z in
Fig. 13-2
Using re equivalent model:
Input impedance:
R′ = R1 R2
Z b = β re
Z i = R′ Z b = R′ βre
Z in = RS + Z i = RS + ( R′ βre )
Io
c
Zo
+
RC Vo
−
Z o′
RL
University of Technology
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Output impedance:
Approximate (neglecting ro);
Z o = RC
Z o′ = RL Z o = RL RC
Voltage gain:
Approximate (neglecting ro);
Vo = − I c Z o′ = − βI b ( RL RC )
BJT Small-Signal Analysis
Lecture Thirteen - Page 2 of 12
Dr. Ahmed Saadoon Ezzulddin
Exact (including ro);
Z o = RC ro
Z o′ = RL RC ro
Exact (including ro);
R R r
Av = − L C o
re
Vi
V
= i
Z b βre
R R
V
Av = o = − L C
Vi
re
V V V
Zi
Avs = o = o ⋅ i = Av ⋅
Vs Vi Vs
Z i + RS
Ib =
Current gain:
Approximate (neglecting ro);
I
I I I
Ai = o = o ⋅ c ⋅ b
Ii Ic Ib Ii
RC
R′
=
⋅β ⋅
RC + RL
R′ + Z b
βRC R′
=
( RC + RL )( R′ + βre )
I
I I
RS
Ais = o = o ⋅ i = Ai ⋅
I s Ii I s
RS + Z i
Exact (including ro);
βro RC R′
Ai =
[ro + ( RC RL )]( RC + RL )( R′ + βre )
As an option:
V
−I R
I R
R
Av = o = o L = − o ⋅ L = − Ai ⋅ L
Vi
Ii Zi
Ii Zi
Zi
I
− Vo RL
V Z
Z
Ai = o =
= − o ⋅ i = − Av ⋅ i
Ii
Vi Z i
Vi RL
RL
Phase relationship:
The negative sign in the resulting equation for Av reveals that a 180o phase shift
occurs between the input and output voltage signals.
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BJT Small-Signal Analysis
Lecture Thirteen - Page 3 of 12
Dr. Ahmed Saadoon Ezzulddin
Using hybrid equivalent model:
Approximate (neglecting hoe);
Z b = hie
h fe ( RL RC )
Av = −
hie
h fe RC R′
Ai =
( RC + RL )( R′ + hie )
Exact (including hoe);
Av = −
Ai =
h fe ( RL RC 1 / hoe )
hie
h fe RC R′ / hoe
[1 / hoe + ( RC RL )]( RC + RL )( R′ + hie )
Unbypassed (include of RE):
For the approximate ac equivalent circuit ( ro = 1 / hoe ≈ ∞Ω ) of Fig. 13-3,
b Ib
Ii
RS
+
Vs
Zi
+
Vi
−
Zb
R′
−
Ic
βre
hie
βI b
e
h fe I b
Io
c
Zo
RC Vo
Ie
RE
Fig. 13-3
Using re equivalent model:
Input impedance:
Vi = I b βre + I e RE = I b [ βre + ( β + 1) RE ]
V
Z b = i = βre + ( β + 1) RE ≈ β (re + RE ) ≈ βRE
Ib
Z i = R′ Z b = R′ [ β re + ( β + 1) RE ] ≈ R′ β (re + RE ) ≈ R′ β RE
Output impedance:
Z o = RC
Z o′ = RL Z o = RL RC
Voltage gain:
Vo = − I c Z o′ = − βI b ( RL RC )
V
Vi
Ib = i =
Z b β (re + RE )
+
−
Z o′
RL
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Av =
BJT Small-Signal Analysis
Lecture Thirteen - Page 4 of 12
Dr. Ahmed Saadoon Ezzulddin
R R
R R
Vo
=− L C ≈− L C
Vi
re + RE
RE
Current gain:
I
I I I
Ai = o = o ⋅ c ⋅ b
Ii Ic Ib Ii
RC
R′
=
⋅β ⋅
RC + RL
R′ + Z b
βRC R′
βRC R′
=
≈
( RC + RL )[ R′ + β (re + RE )] ( RC + RL )( R′ + β RE )
Phase relationship:
Vo and Vi are out-of-phase by 180o.
Using hybrid equivalent model:
Z b = hie + (h fe + 1) RE ≈ hie + h fe RE ≈ h fe RE
Av = −
Ai =
h fe ( RL RC )
hie + h fe RE
≈−
RL RC
RE
h fe RC R′
h fe RC R′
≈
( RC + RL )( R′ + hie + h fe RE ) ( RC + RL )( R′ + h fe RE )
Common-Base Configuration:
The common-base configuration of Fig. 13-4 is characterized as having a relatively
low input and a high output impedance and a current gain less than 1. The voltage gain,
however, can be quite large.
I i CS
RS
+
Vs
−
E
Zi
+
Vi
−
Zb
RE
C
B
VEE
CC I
o
Zo
RC
VCC
Fig. 13-4
+
Vo
−
Z o′
RL
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BJT Small-Signal Analysis
Lecture Thirteen - Page 5 of 12
Dr. Ahmed Saadoon Ezzulddin
Using re equivalent model:
For the approximate ac equivalent circuit ( ro ≈ ∞Ω ) of Fig. 13-5,
Input impedance:
Z b = re
Z i = RE re [low]
Zi
RS
Output impedance:
Z o = RC
[high]
Z o′ = RL RC
e Ie
Ii
+
Vi
+
Vs
−
Ic
Zb
Zo
αI e
re
RE
+
RC Vo
−
b
−
Io
c
Z o′
RL
Fig. 13-5
Voltage gain:
Vo = I c Z o′ = αI e ( RL RC )
I e = Vi / re
α ( R L RC ) R L RC
Av =
≅
re
re
[high]
Current gain:
I
I I I
RC
RE
Ai = o = o ⋅ c ⋅ e = −
⋅α ⋅
Ii Ic Ie Ii
RC + RL
RE + re
αRC RE
=−
[less than 1]
( RC + RL )( RE + re )
Phase relationship:
Vo and Vi are in-phase.
Using hybrid equivalent model:
For the approximate ac equivalent circuit (1 / hob ≈ ∞Ω ) of Fig. 13-6,
Z b = hib
Z i = RE hib
Av = −
Ai =
h fb ( RL RC )
hib
h fb RC RE
RS
+
Vs
−
( RC + RL )( RE + hib )
[hfb: -ve quantity]
Ic
e Ie
Ii
Zi
+
Vi
−
Zb
RE
Io
c
Zo
h fb I e
hib
b
Fig. 13-6
+
RC Vo
−
Z o′
RL
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BJT Small-Signal Analysis
Lecture Thirteen - Page 6 of 12
Dr. Ahmed Saadoon Ezzulddin
Common-Collector (Emitter-Follower] Configuration:
When the output is taken from the emitter terminal of the transistor, an amplifier
circuit is referred to as emitter-follower as shown in Fig. 13-7. The emitter-follower
configuration is frequently used for impedance-matching purposes. It presents a high
impedance at the input and a low impedance at the output. Also, the output voltage is
always slightly less than the input signal with an in-phase relationship between them.
+ VCC
RB
I i CS
B
Zi
RS
+
Zb
Vi
+
Vs
C
−
−
CC
E
Zo
RE
Io
Z o′
RL
+
Vo
−
Fig. 13-7
Using re equivalent model:
For the ac equivalent circuit of Fig. 13-8,
b Ib
Ii
RS
+
Vs
Zi
+
Vi
−
Zb
Ic
βre
hie
RB
−
βI b
Input impedance:
R ′ = RL RE
Vi = I b βre + I e R′ = I b [ βre + ( β + 1) R′]
Z b = Vi / I b = β re + ( β + 1) R′
≈ β (re + R′) ≈ β R′
[high]
Z i = RB Z b
h fe I b
e
Ie
RE
Fig. 13-8
c
Io
Zo
+
Vo
−
RL
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BJT Small-Signal Analysis
Lecture Thirteen - Page 7 of 12
Dr. Ahmed Saadoon Ezzulddin
Output impedance:
[KVL]
Vs − I i RS − I b βre − I e R′ = 0
For the circuit of Fig. 13-9a,
VR
RTh = RS RB , and ETh = s B
RS + R B
where RB >> RS =>
RTh ≈ RS , ETh ≈ Vs , and I i ≈ I b
Vs − I b RS − I b β re − I b ( β + 1) R′ = 0
Vs
Ib =
RS + βre + ( β + 1) R′
( β + 1)Vs
I e = ( β + 1) I b =
RS + β re + ( β + 1) R′
Vs
≈
RS / β + re + R′
RS
RB
+
Vs
−
Thevenin
(a)
RS / β
+
RS / h fe
Vs
−
re
+
Ie
hie / h fe
Vi
Z o = RE ( RS / β + re )
Z o′ = RL Z o
[low]
Voltage gain:
V
I e R′
R′
=
Av = o =
Vi I e ( R′ + re ) R′ + re
Avs =
[less than 1]
Vo
R′
=
Vs R′ + Rs / β + re
Current gain:
I
I I I
RE
RB
Ai = o = o ⋅ e ⋅ b = −
⋅ ( β + 1) ⋅
Ii Ie Ib Ii
RE + RL
RB + Z b
β RE RB
[high]
≈−
( RE + RL )( RB + β R ′)
Phase relationship:
Vo and Vi are in-phase.
Zo +
RE Vo
−
−
(b)
Fig. 13-9
Drawing the circuit to "fit" the above last
equation will result in the configuration
of Fig. 13-9b. Thus
Io
Z o′
RL
University of Technology
Electrical and Electronic Engineering Department
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BJT Small-Signal Analysis
Lecture Thirteen - Page 8 of 12
Dr. Ahmed Saadoon Ezzulddin
Using hybrid equivalent model:
Z b = hie + (h fe + 1) R′ ≈ h fe R′
Z o = RE ( RS + hie ) / h fe
R′
Av =
R′ + hie / h fe
R′
Avs =
R′ + ( Rs + hie ) / h fe
Ai = −
h fe RE RB
( RE + RL )( RB + h fe R′)
Example 13-1:
For the BJT amplifier circuit of Fig. 13-10 with the following parameters:
VBE = 0.7 V, β = hfe ≈ 250, and ro = 1/hoe ≈ ∞ Ω, determine:
(a) re, and dc output voltage (VC).
(b) hie, Zb, Zi, Zo, and Z o′ .
(c) Av = Vo/Vi, and Ai = Io/Ii.
(d) Avs = Vo / Vs , and ac output voltage (Vo).
VCC + 20V
R1 91kΩ
RC
I i CS
RS 750Ω
+
Vs
−
25mV
3kΩ C
Zo
Zi
+
Io
C
+
Vo RL
−
Zb
Vi R2 10kΩ RE1 180Ω
−
RE 2
Fig. 13-10
820Ω
CE
Z o′
12kΩ
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BJT Small-Signal Analysis
Lecture Thirteen - Page 9 of 12
Dr. Ahmed Saadoon Ezzulddin
Solution:
Testing: βRE ≥ 10R2 , RE = RE1 + RE 2 = 0.18k + 0.82k = 1kΩ ,
250(1k ) ≥ 10(10k ) , 250k > 100k Satisfied,
V ⋅R
V − VBE 1.98 − 0.7
20(10k )
= 1.28mA ,
= 1.98V , I E = B
=
VB = CC 2 =
R1 + R2 10k + 91k
RE
1k
26mV
26m
re =
=
= 20.3Ω , I C ≈ I E = 1.28mA , and
IE
1.28m
VC = VCC − I C RC = 20 − 1.28m(3k ) = 16.16V .
hie = βre = 250(20.3) = 5.075kΩ ,
Z b = hie + (h fe + 1) RE1 = 5.075k + 251(0.18k ) = 50.26kΩ ,
R′ = R1 R2 = 91k 10k = 9.01kΩ , Z i = R′ Z b = 9.01k 50.26k = 7.64kΩ ,
Z o = RC = 3kΩ , and Z o′ = RL RC = 12k 3k = 2.4kΩ .
h fe Z o′
Z
250(2.4k )
11.94(7.64k )
Av = −
=−
= −11.94 , and Ai = − Av i =
= 7.6.
Zb
50.26k
RL
12k
Zi
V
− 11.94(7.64k )
Avs = Av i = Av
=
= −10.87 , and
Vs
Z i + RS 7.64k + 0.75k
Vo = Avs ⋅ Vs = −10.87(25m) = −271.75mV .
Example 13-2:
Design the BJT amplifier circuit shown in Fig. 13-11 to have a voltage gain magnitude
of 4, Zi = 3.37 kΩ, Zo = 3 kΩ, and Z o′ = 2kΩ. Assume that the transistor is silicon
with β = 100 , hie = 1 kΩ, ro = 1/hoe ≈ ∞ Ω, and βRE > 10R2 .
VCC + 20V
R1
RC C
C Io
I i CS
RS
+
Vs
Zo
Zi
Zb
Vi
R2
+
−
+
Vo
−
RE
−
Fig. 13-11
Z o′
RL
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BJT Small-Signal Analysis
Lecture Thirteen - Page 10 of 12
Dr. Ahmed Saadoon Ezzulddin
Solution:
RC = Z o = 3kΩ , Z o′ = RL RC ⇒ 2k = RL 3k ⇒ RL = 6kΩ .
Z′
2
Av ≈ o ⇒ 4 ≈
⇒ RE ≈ 0.5kΩ .
RE
RE
26mV
26m
hie = β re ⇒ 1k = 100re ⇒ re = 10Ω , re =
⇒ 10 =
⇒ I E = 2.6mA .
IE
IE
VE = I E RE = 2.6m(0.5k ) = 1.3V , VB = VE + VBE = 1.3 + 0.7 = 2V .
V
R2
R2
R2
2
Q βRE > 10 R2 ⇒ B =
⇒
=
⇒
= 0.1 ----- [a]
VCC R1 + R2
20 R1 + R2
R1 + R2
Z b = hie + ( β + 1) RE = 1k + 101(0.5k ) = 51.5kΩ .
Z i = R′ Z b ⇒ 3.37 k = R′ 51.5k ⇒ R′ = 3.6kΩ .
RR
R2
3.6k
R′ = R1 R2 = 1 2 ⇒
=
----- [b]
R1 + R2
R1
R1 + R2
3.6k
= 0.1 ⇒ R1 = 36kΩ .
From Eqs. [a] and [b]:
R1
R2
From Eq. [a]:
= 0.1 ⇒ R2 = 4kΩ .
36k + R2
Example 13-3:
Complete the design of the BJT amplifier circuit shown in Fig. 13-12 for a voltage
gain of 125, Zo = 2.4 kΩ, Z o′ = 2 kΩ. Assume that α = 0.985 , |VBE| = 0.7 V, and
ro = 1/hob ≈ ∞ Ω. Calculate Avs , and Vo.
VCC
− 9V
RC
RS
+
Vs
−
20Ω
10mV
CC
Zo
CS
+
Vo
−
Zi
+
Vi
−
RE
VEE + 4V
Fig. 13-12
Zo
RL
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BJT Small-Signal Analysis
Lecture Thirteen - Page 11 of 12
Dr. Ahmed Saadoon Ezzulddin
Solution:
RC = Z o = 2.4kΩ .
Z o′ = RL RC ⇒ 2k = RL 2.4k ⇒ RL = 12kΩ .
αZ ′
0.985(2k )
Av = o ⇒ 125 =
⇒ re = 15.76Ω .
re
re
26mV
26m
re =
⇒ 15.76 =
⇒ I E = 1.65mA .
IE
IE
V − VBE 4 − 0.7
RE = EE
=
= 2kΩ .
IE
1.65m
Z i = re RE = 15.76 2k = 15.64Ω .
Zi
125(15.64)
=
= 55 .
Avs = Av
Z i + Rs 15.64 + 20
Vo = Avs ⋅ Vs = 55(10m) = 550mV .
Exercises:
1. For each one of the circuits shown in Fig. 13-13, write a mathematical expression
to determine each of the following parameters by using hybrid or re equivalent
model.
(b) Zo and Z o′ .
(c) Ai and Av.
(a) Zb and Zi.
+ VCC
RF 1
RF 2
CF
I i CS
RC
+ VCC
CC I o
Zo
Z o′
RL
+
Vo
−
RS
+
Vs
Zi
+
Zb
Vi
R1
I i CS
RS
+
−
RE
−
CE
RC
Vs
Zi
Zb
Vi
R2
+
−
−
(a)
(b)
Fig. 13-13
CC I o
Zo
RE
+
Vo
−
Z o′
RL
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BJT Small-Signal Analysis
Lecture Thirteen - Page 12 of 12
Dr. Ahmed Saadoon Ezzulddin
2. For the common-base amplifier of Fig. 13-14, determine the following parameters
using the complete hybrid equivalent model and compare the results to these
obtained using the approximate model.
(a) Zb and Zi.
(b) Zo and Z o′ .
(c) Ai and Avs . (d) Ai and Ais .
CS
Ii
RS 1kΩ
+
Vs
−
hie = 1.6kΩ
hre = 2 × 10 −4
Zi
+
Vi RE
−
VEE
h fe = 110
hoe = 20 μS
Zb
CC
Zo
3kΩ
RC
VCC
6V
Io
Z o′
+
3kΩ V R
o
L
−
12V
8.2kΩ
Fig. 13-14
3. Complete the design of the BJT amplifier circuit shown in Fig. 13-15 for a voltage
gain magnitude of 205, Zi =1.5k Ω, and Z o′ = 3.2 kΩ. Assume that β = 100 ,
VBE = 0.7 V, RF1/RF2 =1.95, and ro = 1/hoe ≈ ∞ Ω. Sketch Vo to the same time
scale as Vs.
VCC
RF 1
RS
+
Vs
−
CF
I i CS
1kΩ
2Sinwt mV
RF 2
+ 10V
RC
CC I o
Zo
+
Vo
−
Zi
+
Zb
Vi
−
Fig. 13-15
Z o′
RL
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
Frequency Response of BJT Amplifiers
Lecture Fourteen - Page 1 of 8
Dr. Ahmed Saadoon Ezzulddin
Frequency Response of BJT Amplifiers
Low-Frequency Response of BJT Amplifiers:
For the high-pass filter circuit of Fig. 14-1a, the output and the input voltages are
related by the voltage-divider rule in the following manner:
RVi
Vo =
,
R + XC
with the magnitude of Vo determined by
R ⋅ Vi
.
Vo =
2
2
R + XC
For special case where XC = R,
1
Vo =
Vi , and
2
V
1
= 0.707 X = R .
Av = o =
C
Vi
2
In "deciBel" (dB):
G (dB) = 20 log 10 Av = 20 log10
1
= −3dB .
2
Av , G ( dB)
C
+
+
Vi
R
−
1,0dB
0.707,−3dB
Vo
−
fL
(a)
f (Hz )
(b)
Fig. 14-1
At the frequency of witch XC = R, the output will be 70.7 % of the input
(a 3 dB drop in gain, see Fig. 14-1b) for the RC circuit. The frequency (fL) at witch this
occurs is determined from:
1
1
XC =
=
= R =>
ωC 2πfC
fL =
1
2πRC
fL: the low-cutoff frequency.
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
Frequency Response of BJT Amplifiers
Lecture Fourteen - Page 2 of 8
Dr. Ahmed Saadoon Ezzulddin
The Capacitors CS, CC, and CE will determine the lower-cutoff frequency (fL)
of the loaded voltage divider BJT bias configuration shown in Fig. 14-2, but the results
can be applied to any BJT configuration.
For the amplifier circuit of Fig. 14-2:
+ VCC
The cutoff-frequency of CS,
f LS
1
=
2π ( RS + Ri )C S
where Ri = R′ hie , and
R′ = R1 R2 .
The cutoff-frequency of CC,
f LC
1
=
2π ( RL + Ro )CC
where Ro = RC 1 / hoe .
The cutoff-frequency of CE,
f LE =
1
2πRe C E
where Re = RE
RS′ + hie
, and
h fe + 1
RS′ = RS R′ .
The lower-cutoff frequency,
f L = Max.[ f LS , f LC , f LE ]
R1
I i CS
RS
+
Vs
RC C
C Io
C
B
+
−
+
Vo
−
Ri
Vi
Ro
R2
E
−
RE
Re
Fig. 14-2
CE
RL
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
Frequency Response of BJT Amplifiers
Lecture Fourteen - Page 3 of 8
Dr. Ahmed Saadoon Ezzulddin
Miller's Theorem and Its Dual:
For the circuit of Fig. 14-3a,
V
V − Vo Vi − AvVi (1 − Av )Vi
Vi
V
=
=
.
I i = i , I1 = i , and I 2 = i
=
Zi
Ri
ZF
ZF
ZF
Z F /(1 − Av )
V V
Vi
1
1
1
=
+
I i = I1 + I 2 => i = i +
=>
.
Z i Ri Z F /(1 − Av )
Z i Ri Z F /(1 − Av )
R
1
1
1
when Z F = RF =>
, where RM i = F .
=
+
Z i Ri RM i
1 − Av
As shown in Fig. 14-3b,
X CF
1
1
1
1
when Z F = X CF =>
=
+
, where X CM =
=>
=
i
Z i Ri X CM
1 − Av ω (1 − Av )C F
i
C M i = (1 − Av )C F
I2
Ii
I1
Vi Z i
Ri
+
−
CF
ZF
Ii
Io
Av =
Vo
Vi
Ro
+
+
Zo V
Vi
o
−
−
Io
CM i
(a)
Av =
Vo
Vi
CM o
+
Vo
−
(b)
Fig. 14-3
In a similar way,
RF
1
1
1
=
+
=> RM o =
, and
Z o Ro Z F /(1 − 1 / Av )
1 − 1 / Av
X CF
1
=>
X CM =
=
o
1 − 1 / Av ω (1 − 1 / Av )C F
C M o = (1 − 1 / Av )C F
The above shows us that:
For any inverting amplifier (phase shift of 180o between input and output
resulting in a negative value for Av), the input and output capacitance will be increased
by a Miller effect capacitance sensitive to the gain of the amplifier and the
interelectrode capacitance connected between the input and output terminals of the
active device.
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
Frequency Response of BJT Amplifiers
Lecture Fourteen - Page 4 of 8
Dr. Ahmed Saadoon Ezzulddin
High-Frequency Response of BJT Amplifiers:
A frequency response of the low-pass filter circuit of Fig. 14-4a is given by Fig. 14-4b,
where the high-cutoff frequency is determined from:
fH =
1
2πRC
fH: the high-cutoff frequency.
Av , G ( dB)
R
+
+
C
Vi
1,0dB
0.707,−3dB
Vo
−
−
f (Hz )
fH
(a)
(b)
Fig. 14-4
At the high-frequency end, there are two factors that will define the -3 dB point:
the circuit capacitance (parasitic and introduced) and the frequency dependence of hfe.
Circuit (Capacitances) Parameters:
In high-frequency region the capacitive elements of the importance are the
inter-electrode (between terminals) capacitances internal to the active device and the
wiring capacitance between leads of the circuit. In Fig. 14-5, the various parasitic
capacitances (Cbe, Cbc, and Cce) of the transistor have been included with the wiring
capacitances ( CWi and CWo ) introduced during construction.
+ VCC
RC
R1
CS
CC
Cbc
C
B
RS
+
Vs
−
Cce
CWo
E
R2
Cbe
CWi
RE
Fig. 14-5
CE
RL
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
Frequency Response of BJT Amplifiers
Lecture Fourteen - Page 5 of 8
Dr. Ahmed Saadoon Ezzulddin
The high-frequency equivalent model for the amplifier circuit of Fig. 14-5
appears in Fig. 14-6. Note the absence of the capacitors CS, CC, and CE, which are all
assumed to be in the short circuit state at these frequencies.
RS
Vo
+
Vs
Ri
RThi
−
Ci
βI b
Ro
RThi
+
RTho
+
ETho
Ci
−
−
Fig. 14-6
For the circuit of Fig. 14-6:
The input high cutoff frequency,
f Hi =
1
2πRThi Ci
where RThi = RS Ri , and Ri = R1 R 2 hie .
Ci = CWi + Cbe + C M i = CWi +C be +(1 − Av )Cbc .
The output high cutoff frequency,
f Ho =
1
2πRTho Co
where RTho = RL Ro , and Ro = RC 1 / hoe
Co = CWo + Cce + C M o = CWo +C ce +(1 − 1 / Av )Cbc .
The higher-cutoff frequency,
f H = Min.[ f H i , f H o ]
Co
C o = CWo + C ce + C M o
Ci = CWi + Cbe + C M i
EThi
RL
RTho
Co
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
Frequency Response of BJT Amplifiers
Lecture Fourteen - Page 6 of 8
Dr. Ahmed Saadoon Ezzulddin
hfe (β) Variation:
The beta cutoff frequency (fβ) is another important transistor cutoff frequency. The fβ,
the frequency where the β of the transistor drop to 0.707 of its low-frequency value,
is given by
fβ ≅
1
2πβre (Cbe + Cbc )
If the frequency of operation is increased above the fβ of the transistor, the β
will continue to decrease. Eventually, we find a frequency where the β = 1; this
frequency is called the fT of the transistor. The fT of a transistor is much higher than
the fβ. The relation between these two frequencies is
f T ≅ β ⋅ f β ≈ h fe ⋅ BW
fT: the gain-bandwidth product frequency.
Finally, in data sheet, the CB high-frequency parameters rather than CE
parameters are often specified for a transistor. The following equation permits a direct
conversion for determining fβ if fα and α are specified.
f β = fα (1 − α )
Example 14-1:
For the BJT amplifier circuit shown in Fig. 14-7, with the following parameters:
Cbe = 36 pF, Cbc = 4 pF, Cce = 1 pF, CWi = 6 pF, CWo = 8 pF, and ro = 1/hoe = ∞ Ω.
1. Determine fL, fH, BW, fβ, and fT.
2. Sketch the frequency response.
VCC + 20V
R1 40kΩ
RC
1μF
β = 100
CS
RS 1kΩ 10 μF
+
Vs
−
4kΩ C
C
R2 10kΩ
RE 2kΩ C E
Fig. 14-7
RL
2.2kΩ
20μF
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
Frequency Response of BJT Amplifiers
Lecture Fourteen - Page 7 of 8
Dr. Ahmed Saadoon Ezzulddin
Solution:
Testing: βRE ≥ 10 R2 , 100(2k ) ≥ 10(10k ) , 200kΩ > 100kΩ Satisfied.
V ⋅R
V
V − VEB 4 − 0.7
20(10k )
VB = CC 2 =
= 4V , I E = E = B
=
= 1.65mA.
R1 + R2 40k + 10k
RE
RE
2k
26mV
26m
=
= 15.76Ω , hie = βre = 100(15.76) = 1.58kΩ .
re =
IE
1.65m
2.2k 4k
R R
Avmid = − L C = −
= −90 .
re
15.76
Ri = R1 R2 hie = 40k 10k 1.58k = 1.32kΩ ,
1
1
f LS =
=
= 7 Hz .
2π ( RS + Ri )C S 2π (1k + 1.32k )(10μ )
Ro = RC 1 / hoe = 4kΩ ,
1
1
f LC =
=
= 26 Hz .
2π ( RL + Ro )CC 2π (2.2k + 4k )(1μ )
RS′ = RS R1 R2 = 1k 40k 10k = 0.89kΩ ,
R′
0.89k
Re = RE [ S + re ] = 2k [
+ 15.76] = 24.35Ω .
100
β
1
1
f LE =
=
= 327 Hz .
2πRe C E 2π (24.35)(20 μ )
The lower-cutoff frequency, f L = Max.[ f LS , f LC , f LE ]
= Max.[7,26,327] = 327 Hz .
RThi = RS Ri = 1k 1.32k = 0.57 kΩ .
Ci = CWi + Cbe + C M i = CWi +C be +(1 − Av )Cbc = 6 p + 36 p + (1 + 90)(4 p ) = 406 pF .
f Hi =
1
1
=
= 687.732kHz .
2πRThi Ci 2π (0.57 k )(406 p )
RTho = RL Ro = 2.2k 4k = 1.42kΩ .
Co = CWo + Cce + C M o = CWo +C ce +(1 − 1 / Av )Cbc = 8 p + 1 p + (1 + 1 / 90)(4 p ) = 13 pF .
f Ho =
1
1
=
= 8.622 MHz .
2πRTho Co 2π (1.42k )(13 p )
The higher-cutoff frequency, f H = Min.[ f H i , f H o ]
= Min.[687.732k ,8.622 M ] = 687.732kHz .
The bandwidth, BW = f H − f L = 687.732k − 327 = 687.405kHz .
University of Technology
Electrical and Electronic Engineering Department
Second Year, Electronics I, 2009 - 2010
Frequency Response of BJT Amplifiers
Lecture Fourteen - Page 8 of 8
Dr. Ahmed Saadoon Ezzulddin
1
2πβre (Cbe + Cbc )
1
=
= 2.52 MHz .
2π (100)(15.76)(36 p + 4 p )
The beta cutoff frequency, f β =
The gain-bandwidth product, f T = β ⋅ f β = 100(2.52 M ) = 252 MHz .
The frequency response for the low- and high-frequency regions, bandwidth, beta
cutoff frequency, and gain-bandwidth product frequency are shown in Fig. 14-8.
Av
Avmid
dB
f LS f LC
1
10
f Hi
f LE
100
1k
10k
100k
1M
fβ
fT
10M 100M
0
- 3 dB
fL
-5
f (log scale)
fH
f Ho
BW
- 10
- 15
Fig. 14-8
Exercise:
For the BJT amplifier circuit of Fig. 14-9, determine the lower- and higher-cutoff
frequencies.
Cbc = 18 pF
CWi = 8 pF
Cbe = 24 pF
CS
RS
+
Vs
−
Cce = 12 pF
10 μF
0.1kΩ
RE
VEE
β = 80
CWo = 10 pF
CC
10 μF
1.2kΩ
4V
RC
VCC
Fig. 14-9
3.3kΩ
16V
RL
4.7 kΩ