! 0RACTICAL 'UIDE TO (IGH 3PEED 0RINTED #IRCUIT "OARD ,AYOUT "Y *OHN !RDIZZONI ;JOHNARDIZZONI ANALOGCOM= $ESPITE ITS CRITICAL NATURE IN HIGH SPEED CIRCUITRY PRINTED CIRCUIT BOARD 0#" LAYOUT IS OFTEN ONE OF THE LAST STEPS IN THE DESIGN PROCESS 4HERE ARE MANY ASPECTS TO HIGH SPEED 0#" LAYOUT VOLUMES HAVE BEEN WRITTEN ON THE SUBJECT 4HIS ARTICLE ADDRESSES HIGH SPEED LAYOUT FROM A PRACTICAL PERSPECTIVE ! MAJOR AIM IS TO HELP SENSITIZE NEWCOMERS TO THE MANY AND VARIOUS CONSIDERATIONS THEY NEED TO ADDRESS WHEN DESIGNING BOARD LAYOUTS FOR HIGH SPEED CIRCUITRY "UT IT IS ALSO INTENDED AS A REFRESHER TO BENElT THOSE WHO HAVE BEEN AWAY FROM BOARD LAYOUT FOR A WHILE .OT EVERY TOPIC CAN BE COVERED IN DETAIL IN THE SPACE AVAILABLE HERE BUT WE ADDRESS KEY AREAS THAT CAN HAVE THE GREATEST PAYOFF IN IMPROVING CIRCUIT PERFORMANCE REDUCING DESIGN TIME AND MINIMIZING TIME CONSUMING REVISIONS !LTHOUGH THE FOCUS IS ON CIRCUITS INVOLVING HIGH SPEED OP AMPS THE TOPICS AND TECHNIQUES DISCUSSED HERE ARE GENERALLY APPLICABLE TO LAYOUT OF MOST OTHER HIGH SPEED ANALOG CIRCUITS 7HEN OP AMPS OPERATE AT HIGH 2& FREQUENCIES CIRCUIT PERFORMANCE IS HEAVILY DEPENDENT ON THE BOARD LAYOUT ! HIGH PERFORMANCE CIRCUIT DESIGN THAT LOOKS GOOD hON PAPERv CAN RENDER MEDIOCRE PERFORMANCE WHEN HAMPERED BY A CARELESS OR SLOPPY LAYOUT 4HINKING AHEAD AND PAYING ATTENTION TO SALIENT DETAILS THROUGHOUT THE LAYOUT PROCESS WILL HELP ENSURE THAT THE CIRCUIT PERFORMS AS EXPECTED 4HE 3CHEMATIC GROUND ANALOG DIGITAL AND 2& WHICH SIGNALS NEED TO BE ON EACH LAYER WHERE THE CRITICAL COMPONENTS NEED TO BE LOCATED THE EXACT LOCATION OF BYPASSING COMPONENTS WHICH TRACES ARE CRITICAL WHICH LINES NEED TO BE CONTROLLED IMPEDANCE LINES WHICH LINES NEED TO HAVE MATCHED LENGTHS COMPONENT SIZES WHICH TRACES NEED TO KEPT AWAY FROM OR NEAR EACH OTHER WHICH CIRCUITS NEED TO BE KEPT AWAY FROM OR NEAR EACH OTHER WHICH COMPONENTS NEED TO BE CLOSE TO OR AWAY FROM EACH OTHER WHICH COMPONENTS GO ON THE TOP AND THE BOTTOM OF THE BOARD 9OULL NEVER GET A COMPLAINT FOR GIVING SOMEONE TOO MUCH INFORMATIONTOO LITTLE YES TOO MUCH NO ! LEARNING EXPERIENCE !BOUT YEARS AGO ) DESIGNED A MULTILAYER SURFACE MOUNTED BOARDWITH COMPONENTS ON BOTH SIDES OF THE BOARD 4HE BOARD WAS SCREWED INTO A GOLD PLATED ALUMINUM HOUSING WITH MANY SCREWS BECAUSE OF A STRINGENT VIBRATION SPEC "IAS FEED THROUGH PINS POKED UP THROUGH THE BOARD 4HE PINS WERE WIRE BONDED TO THE 0#" )T WAS A COMPLICATED ASSEMBLY 3OME OF THE COMPONENTS ON THE BOARD WERE TO BE 3!4 SET AT TEST "UT ) HADNT SPECIlED WHERE THESE COMPONENTS SHOULD BE #AN YOU GUESS WHERE SOME OF THEM WERE PLACED 2IGHT /N THE BOTTOM OF THE BOARD 4HE PRODUCTION ENGINEERS AND TECHNICIANS WERE NOT VERY HAPPY WHEN THEY HAD TO TEAR THE ASSEMBLY APART SET THE VALUES AND THEN REASSEMBLE EVERYTHING ) DIDNT MAKE THAT MISTAKE AGAIN ,OCATION ,OCATION ,OCATION !S IN REAL ESTATE LOCATION IS EVERYTHING 7HERE A CIRCUIT IS PLACED ON A BOARD WHERE THE INDIVIDUAL CIRCUIT COMPONENTS ARE LOCATED AND WHAT OTHER CIRCUITS ARE IN THE NEIGHBORHOOD ARE ALL CRITICAL !LTHOUGH THERE IS NO GUARANTEE A GOOD LAYOUT STARTS WITH A GOOD SCHEMATIC "E THOUGHTFUL AND GENEROUS WHEN DRAWING A SCHEMATIC AND THINK ABOUT SIGNAL mOW THROUGH THE CIRCUIT ! SCHEMATIC THAT HAS A NATURAL AND STEADY mOW FROM LEFT TO RIGHT WILL TEND TO HAVE A GOOD mOW ON THE BOARD AS WELL 0UT AS MUCH USEFUL INFORMATION ON THE SCHEMATIC AS POSSIBLE 4HE DESIGNERS TECHNICIANS AND ENGINEERS WHO WILL WORK ON THIS JOB WILL BE MOST APPRECIATIVE INCLUDING US AT TIMES WE ARE ASKED BY CUSTOMERS TO HELP WITH A CIRCUIT BECAUSE THE DESIGNER IS NO LONGER THERE 4YPICALLY INPUT OUTPUT AND POWER LOCATIONS ARE DElNED BUT WHAT GOES ON BETWEEN THEM IS hUP FOR GRABSv 4HIS IS WHERE PAYING ATTENTION TO THE LAYOUT DETAILS WILL YIELD SIGNIlCANT RETURNS 3TART WITH CRITICAL COMPONENT PLACEMENT IN TERMS OF BOTH INDIVIDUAL CIRCUITS AND THE ENTIRE BOARD 3PECIFYING THE CRITICAL COMPONENT LOCATIONS AND SIGNAL ROUTING PATHS FROM THE BEGINNING HELPS ENSURE THAT THE DESIGN WILL WORK THE WAY ITS INTENDED TO 'ETTING IT RIGHT THE lRST TIME LOWERS COST AND STRESSAND REDUCES CYCLE TIME 7HAT KIND OF INFORMATION BELONGS ON A SCHEMATIC BESIDES THE USUAL REFERENCE DESIGNATORS POWER DISSIPATIONS AND TOLERANCES (ERE ARE A FEW SUGGESTIONS THAT CAN TURN AN ORDINARY SCHEMATIC INTO A SUPERSCHEMATIC !DD WAVEFORMS MECHANICAL INFORMATION ABOUT THE HOUSING OR ENCLOSURE TRACE LENGTHS KEEP OUT AREAS DESIGNATE WHICH COMPONENTS NEED TO BE ON TOP OF THE BOARD INCLUDE TUNING INFORMATION COMPONENT VALUE RANGES THERMAL INFORMATION CONTROLLED IMPEDANCE LINES NOTES BRIEF CIRCUIT OPERATING DESCRIPTIONS x AND THE LIST GOES ON "YPASSING THE POWER SUPPLY AT THE AMPLIlERS SUPPLY TERMINALS TO MINIMIZE NOISE IS A CRITICAL ASPECT OF THE 0#" DESIGN PROCESSBOTH FOR HIGH SPEED OP AMPS AND ANY OTHER HIGH SPEED CIRCUITRY 4HERE ARE TWO COMMONLY USED CONlGURATIONS FOR BYPASSING HIGH SPEED OP AMPS 4RUST .O /NE )F YOURE NOT DOING YOUR OWN LAYOUT BE SURE TO SET ASIDE AMPLE TIME TO GO THROUGH THE DESIGN WITH THE LAYOUT PERSON !N OUNCE OF PREVENTION AT THIS POINT IS WORTH MORE THAN A POUND OF CURE $ONT EXPECT THE LAYOUT PERSON TO BE ABLE TO READ YOUR MIND 9OUR INPUTS AND GUIDANCE ARE MOST CRITICAL AT THE BEGINNING OF THE LAYOUT PROCESS 4HE MORE INFORMATION YOU CAN PROVIDE AND THE MORE INVOLVED YOU ARE THROUGHOUT THE LAYOUT PROCESS THE BETTER THE BOARD WILL TURN OUT 'IVE THE DESIGNER INTERIM COMPLETION POINTSAT WHICH YOU WANT TO BE NOTIlED OF THE LAYOUT PROGRESS FOR A QUICK REVIEW 4HIS hLOOP CLOSUREv PREVENTS A LAYOUT FROM GOING TOO FAR ASTRAY AND WILL MINIMIZE REWORKING THE BOARD LAYOUT 9OUR INSTRUCTIONS FOR THE DESIGNER SHOULD INCLUDE A BRIEF DESCRIPTION OF THE CIRCUITS FUNCTIONS A SKETCH OF THE BOARD THAT SHOWS THE INPUT AND OUTPUT LOCATIONS THE BOARD STACK UP IE HOW THICK THE BOARD WILL BE HOW MANY LAYERS DETAILS OF SIGNAL LAYERS AND PLANESPOWER !NALOG $IALOGUE 3EPTEMBER 0OWER 3UPPLY "YPASSING 2AILS TO GROUND 4HIS TECHNIQUE WHICH WORKS BEST IN MOST CASES USES MULTIPLE PARALLEL CAPACITORS CONNECTED FROM THE OP AMPS POWER SUPPLY PINS DIRECTLY TO GROUND 4YPICALLY TWO PARALLEL CAPACITORS ARE SUFlCIENTBUT SOME CIRCUITS MAY BENElT FROM ADDITIONAL CAPACITORS IN PARALLEL 0ARALLELING DIFFERENT CAPACITOR VALUES HELPS ENSURE THAT THE POWER SUPPLY PINS SEE A LOW AC IMPEDANCE ACROSS A WIDE BAND OF FREQUENCIES 4HIS IS ESPECIALLY IMPORTANT AT FREQUENCIES WHERE THE OP AMP POWER SUPPLY REJECTION 032 IS ROLLING OFF 4HE CAPACITORS HELP COMPENSATE FOR THE AMPLIlERS DECREASING 032 -AINTAINING A LOW IMPEDANCE PATH TO GROUND FOR MANY DECADES OF FREQUENCY WILL HELP ENSURE THAT UNWANTED NOISE DOESNT lND ITS WAY INTO THE OP AMP &IGURE SHOWS THE BENElTS OF MULTIPLE PARALLEL CAPACITORS !T LOWER FREQUENCIES THE LARGER CAPACITORS OFFER A LOW IMPEDANCE PATH TO GROUND /NCE THOSE CAPACITORS REACH SELF RESONANCE THE CAPACITIVE QUALITY DIMINISHES AND THE CAPACITORS BECOME INDUCTIVE 4HAT IS WHY IT IS IMPORTANT TO USE MULTIPLE CAPACITORS WHEN ONE CAPACITORS FREQUENCY RESPONSE IS ROLLING OFF ANOTHER IS BECOMING SIGNIlCANT THEREBY MAINTAINING A LOW AC IMPEDANCE OVER MANY DECADES OF FREQUENCY HTTPWWWANALOGCOMANALOGDIALOGUE 4HIS PROCESS SHOULD BE REPEATED FOR THE NEXT HIGHER VALUE CAPACITOR ! GOOD PLACE TO START IS WITH M& FOR THE SMALLEST VALUE AND A M&OR LARGERELECTROLYTIC WITH LOW %32 FOR THE NEXT CAPACITOR 4HE M& IN THE CASE SIZE OFFERS LOW SERIES INDUCTANCE AND EXCELLENT HIGH FREQUENCY PERFORMANCE K K P& )-0%$!.#% 6 P& K 2AIL TO RAIL !N ALTERNATE CONlGURATION USES ONE OR MORE BYPASS CAPACITORS TIED BETWEEN THE POSITIVE AND NEGATIVE SUPPLY RAILS OF THE OP AMP 4HIS METHOD IS TYPICALLY USED WHEN IT IS DIFlCULT TO GET ALL FOUR CAPACITORS IN THE CIRCUIT ! DRAWBACK TO THIS APPROACH IS THAT THE CAPACITOR CASE SIZE CAN BECOME LARGER BECAUSE THE VOLTAGE ACROSS THE CAPACITOR IS DOUBLE THAT OF THE SINGLE SUPPLY BYPASSING METHOD 4HE HIGHER VOLTAGE REQUIRES A HIGHER BREAKDOWN RATING WHICH TRANSLATES INTO A LARGER CASE SIZE 4HIS OPTION CAN HOWEVER OFFER IMPROVEMENTS TO BOTH 032 AND DISTORTION PERFORMANCE M& M& M& &2%15%.#9 -(Z K K &IGURE #APACITOR IMPEDANCE VS FREQUENCY 3INCE EACH CIRCUIT AND LAYOUT IS DIFFERENT THE CONlGURATION NUMBER AND VALUES OF THE CAPACITORS ARE DETERMINED BY THE ACTUAL CIRCUIT REQUIREMENTS 3TARTING DIRECTLY AT THE OP AMPS POWER SUPPLY PINS THE CAPACITOR WITH THE LOWEST VALUE AND SMALLEST PHYSICAL SIZE SHOULD BE PLACED ON THE SAME SIDE OF THE BOARD AS THE OP AMPAND AS CLOSE TO THE AMPLIlER AS POSSIBLE 4HE GROUND SIDE OF THE CAPACITOR SHOULD BE CONNECTED INTO THE GROUND PLANE WITH MINIMAL LEAD OR TRACE LENGTH 4HIS GROUND CONNECTION SHOULD BE AS CLOSE AS POSSIBLE TO THE AMPLIlERS LOAD TO MINIMIZE DISTURBANCES BETWEEN THE RAILS AND GROUND &IGURE ILLUSTRATES THIS TECHNIQUE 63 0ARASITICS 0ARASITICS ARE THOSE NASTY LITTLE GREMLINS THAT CREEP INTO YOUR 0#" QUITE LITERALLY AND WREAK HAVOC WITHIN YOUR CIRCUIT 4HEY ARE THE HIDDEN STRAY CAPACITORS AND INDUCTORS THAT INlLTRATE HIGH SPEED CIRCUITS 4HEY INCLUDE INDUCTORS FORMED BY PACKAGE LEADS AND EXCESS TRACE LENGTHS PAD TO GROUND PAD TO POWER PLANE AND PAD TO TRACE CAPACITORS INTERACTIONS WITH VIAS AND MANY MORE POSSIBILITIES &IGURE A IS A TYPICAL SCHEMATIC OF A NONINVERTING OP AMP )F PARASITIC ELEMENTS WERE TO BE TAKEN INTO ACCOUNT HOWEVER THE SAME CIRCUIT WOULD LOOK LIKE &IGURE B "90!33 #!0!#)4/23 ,/!$ n63 )N HIGH SPEED CIRCUITS IT DOESNT TAKE MUCH TO INmUENCE CIRCUIT PERFORMANCE 3OMETIMES JUST A FEW TENTHS OF A PICOFARAD IS ENOUGH #ASE IN POINT IF ONLY P& OF ADDITIONAL STRAY PARASITIC CAPACITANCE IS PRESENT AT THE INVERTING INPUT IT CAN CAUSE ALMOST D" OF PEAKING IN THE FREQUENCY DOMAIN &IGURE )F ENOUGH CAPACITANCE IS PRESENT IT CAN CAUSE INSTABILITY AND OSCILLATIONS "90!33 #!0!#)4/23 &IGURE 0ARALLEL CAPACITOR RAILS TO GROUND BYPASSING 0!$ 6 0!$ 2& 0!$ 6 2& 6)! 0!$ 2' 42!#% 2' 6) !6 2&2' 42!#% 0!$ 2, 6) 0!$ 0!$ 42!#% 0!$ 6/ 0!$ 0!$ n6 6)! 2, 0!$ 0!$ n6 A B &IGURE 4YPICAL OP AMP CIRCUIT AS DESIGNED A AND WITH PARASITICS B !NALOG $IALOGUE 3EPTEMBER P& 6/,4!'% 6 '!). D" P& &2%15%.#9 -(Z 4)-% NS &IGURE !DDITIONAL PEAKING CAUSED BY PARASITIC CAPACITANCE &IGURE 0ULSE RESPONSE WITHAND WITHOUTGROUND PLANE ! FEW BASIC FORMULAS FOR CALCULATING THE SIZE OF THOSE GREMLINS CAN COME IN HANDY WHEN SEEKING THE SOURCES OF THE PROBLEMATIC PARASITICS %QUATION IS THE FORMULA FOR A PARALLEL PLATE CAPACITOR SEE &IGURE 6IAS ARE ANOTHER SOURCE OF PARASITICS THEY CAN INTRODUCE BOTH INDUCTANCE AND CAPACITANCE %QUATION IS THE FORMULA FOR PARASITIC INDUCTANCE SEE &IGURE K! # P& D ¨ 4 , 4 ©LN ª D # IS THE CAPACITANCE ! IS THE AREA OF THE PLATE IN CM K IS THE RELATIVE DIELECTRIC CONSTANT OF BOARD MATERIAL AND D IS THE DISTANCE BETWEEN THE PLATES IN CENTIMETERS · ¸N( ¹ 4 IS THE THICKNESS OF THE BOARD AND D IS THE DIAMETER OF THE VIA IN CENTIMETERS '2/5.$ 0,!.% $ D $ ! D &IGURE #APACITANCE BETWEEN TWO PLATES 3TRIP INDUCTANCE IS ANOTHER PARASITIC TO BE CONSIDERED RESULTING FROM EXCESSIVE TRACE LENGTH AND LACK OF GROUND PLANE %QUATION SHOWS THE FORMULA FOR TRACE INDUCTANCE 3EE &IGURE ¨ , )NDUCTANCE , ©LN ©ª 7 ( ¥7 ( ´ ¦ µ § , ¶ · ¸M( ¸¹ 7 IS THE TRACE WIDTH , IS THE TRACE LENGTH AND ( IS THE THICKNESS OF THE TRACE !LL DIMENSIONS ARE IN MILLIMETERS , ( 4 D $ $ &IGURE 6IA DIMENSIONS 7 %QUATION SHOWS HOW TO CALCULATE THE PARASITIC CAPACITANCE OF A VIA SEE &IGURE E R4$ P& # $ $ &IGURE )NDUCTANCE OF A TRACE LENGTH 4HE OSCILLATION IN &IGURE SHOWS THE EFFECT OF A CM TRACE LENGTH AT THE NONINVERTING INPUT OF A HIGH SPEED OP AMP 4HE EQUIVALENT STRAY INDUCTANCE IS N( NANOHENRY ENOUGH TO CAUSE A SUSTAINED LOW LEVEL OSCILLATION THAT PERSISTS THROUGHOUT THE PERIOD OF THE TRANSIENT RESPONSE 4HE PICTURE ALSO SHOWS HOW USING A GROUND PLANE MITIGATES THE EFFECTS OF STRAY INDUCTANCE !NALOG $IALOGUE 3EPTEMBER dR IS THE RELATIVE PERMEABILITY OF THE BOARD MATERIAL 4 IS THE THICKNESS OF THE BOARD $ IS THE DIAMETER OF THE PAD SURROUNDING THE VIA $ IS THE DIAMETER OF THE CLEARANCE HOLE IN THE GROUND PLANE !LL DIMENSIONS ARE IN CENTIMETERS ! SINGLE VIA IN A CM THICK BOARD CAN ADD N( OF INDUCTANCE AND P& OF CAPACITANCE THIS IS WHY WHEN LAYING OUT BOARDS A CONSTANT VIGIL MUST BE KEPT TO MINIMIZE THE INlLTRATION OF PARASITES ! GROUND PLANE ACTS AS A COMMON REFERENCE VOLTAGE PROVIDES SHIELDING ENABLES HEAT DISSIPATION AND REDUCES STRAY INDUCTANCE BUT IT ALSO INCREASES PARASITIC CAPACITANCE 7HILE THERE ARE MANY ADVANTAGES TO USING A GROUND PLANE CARE MUST BE TAKEN WHEN IMPLEMENTING IT BECAUSE THERE ARE LIMITATIONS TO WHAT IT CAN AND CANNOT DO )DEALLY ONE LAYER OF THE 0#" SHOULD BE DEDICATED TO SERVE AS THE GROUND PLANE "EST RESULTS WILL OCCUR WHEN THE ENTIRE PLANE IS UNBROKEN 2ESIST THE TEMPTATION TO REMOVE AREAS OF THE GROUND PLANE FOR ROUTING OTHER SIGNALS ON THIS DEDICATED LAYER 4HE GROUND PLANE REDUCES TRACE INDUCTANCE BY MAGNETIC lELD CANCELLATION BETWEEN THE CONDUCTOR AND THE GROUND PLANE 7HEN AREAS OF THE GROUND PLANE ARE REMOVED UNEXPECTED PARASITIC INDUCTANCE CAN BE INTRODUCED INTO THE TRACES ABOVE OR BELOW THE GROUND PLANE PACKAGE TYPE PRESENTS ITS OWN SET OF CHALLENGES &OCUSING ON A CLOSE EXAMINATION OF THE FEEDBACK PATH SUGGESTS THAT THERE ARE MULTIPLE OPTIONS FOR ROUTING THE FEEDBACK +EEPING TRACE LENGTHS SHORT IS PARAMOUNT 0ARASITIC INDUCTANCE IN THE FEEDBACK CAN CAUSE RINGING AND OVERSHOOT )N &IGURES A AND B THE FEEDBACK PATH IS ROUTED AROUND THE AMPLIlER &IGURE C SHOWS AN ALTERNATIVE APPROACHROUTING THE FEEDBACK PATH UNDER THE 3/)# PACKAGEWHICH MINIMIZES THE FEEDBACK PATH LENGTH %ACH OPTION HAS SUBTLE DIFFERENCES 4HE lRST OPTION CAN LEAD TO EXCESS TRACE LENGTH WITH INCREASED SERIES INDUCTANCE 4HE SECOND OPTION USES VIAS WHICH CAN INTRODUCE PARASITIC CAPACITANCE AND INDUCTANCE 4HE INmUENCE AND IMPLICATIONS OF THESE PARASITICS MUST BE TAKEN INTO CONSIDERATION WHEN LAYING OUT THE BOARD 4HE 3/4 LAYOUT IS ALMOST IDEAL MINIMAL FEEDBACK TRACE LENGTH AND USE OF VIAS THE LOAD AND BYPASS CAPACITORS ARE RETURNED WITH SHORT PATHS TO THE SAME GROUND CONNECTION AND THE POSITIVE RAIL CAPACITORS NOT SHOWN IN &IGURE B ARE LOCATED DIRECTLY UNDER THE NEGATIVE RAIL CAPACITORS ON THE BOTTOM OF THE BOARD 63 2& "ECAUSE GROUND PLANES TYPICALLY HAVE LARGE SURFACE AND CROSS SECTIONAL AREAS THE RESISTANCE IN THE GROUND PLANE IS KEPT TO A MINIMUM !T LOW FREQUENCIES CURRENT WILL TAKE THE PATH OF LEAST RESISTANCE BUT AT HIGH FREQUENCIES CURRENT FOLLOWS THE PATH OF LEAST IMPEDANCE .EVERTHELESS THERE ARE EXCEPTIONS AND SOMETIMES LESS GROUND PLANE IS BETTER (IGH SPEED OP AMPS WILL PERFORM BETTER IF THE GROUND PLANE IS REMOVED FROM UNDER THE INPUT AND OUTPUT PADS 4HE STRAY CAPACITANCE INTRODUCED BY THE GROUND PLANE AT THE INPUT ADDED TO THE OP AMPS INPUT CAPACITANCE LOWERS THE PHASE MARGIN AND CAN CAUSE INSTABILITY !S SEEN IN THE PARASITICS DISCUSSION P& OF CAPACITANCE AT AN OP AMPS INPUT CAN CAUSE SIGNIlCANT PEAKING #APACITIVE LOADING AT THE OUTPUTINCLUDING STRAYSCREATES A POLE IN THE FEEDBACK LOOP 4HIS CAN REDUCE PHASE MARGIN AND COULD CAUSE THE CIRCUIT TO BECOME UNSTABLE !NALOG AND DIGITAL CIRCUITRY INCLUDING GROUNDS AND GROUND PLANES SHOULD BE KEPT SEPARATE WHEN POSSIBLE &AST RISING EDGES CREATE CURRENT SPIKES mOWING IN THE GROUND PLANE 4HESE FAST CURRENT SPIKES CREATE NOISE THAT CAN CORRUPT ANALOG PERFORMANCE !NALOG AND DIGITAL GROUNDS AND SUPPLIES SHOULD BE TIED AT ONE COMMON GROUND POINT TO MINIMIZE CIRCULATING DIGITAL AND ANALOG GROUND CURRENTS AND NOISE $)3!",% 6/54 6). /04)/.!, #!0!#)4/2 #%2!-)# "90!33 #%2!-)# "90!33 n63 %,%#42/,94)# "90!33 A 6/54 2& 2, n63 6 6/54 ). n). 63 "90!33 #!03 !2% /. "/44/- /& "/!2$ 7)4( '2/5.$ 2%452.3 )--%$)!4%,9 5.$%2 2, 2' 6). 63 B %,%#42/,94)# "90!33 F (Z ,ESS SUSCEPTIBLE PLATING METALS CAN BE HELPFUL IN REDUCING SKIN EFFECT 0ACKAGING /P AMPS ARE TYPICALLY OFFERED IN A VARIETY OF PACKAGES 4HE PACKAGE CHOSEN CAN AFFECT AN AMPLIlERS HIGH FREQUENCY PERFORMANCE 4HE MAIN INmUENCES ARE PARASITICS MENTIONED EARLIER AND SIGNAL ROUTING (ERE WE WILL FOCUS ON ROUTING INPUTS OUTPUTS AND POWER TO THE AMPLIlER &IGURE ILLUSTRATES THE LAYOUT DIFFERENCES BETWEEN AN OP AMP IN AN 3/)# PACKAGE A AND ONE IN AN 3/4 PACKAGE B %ACH #%2!-)# "90!33 2' !T HIGH FREQUENCIES A PHENOMENON CALLED SKIN EFFECT MUST BE CONSIDERED 3KIN EFFECT CAUSES CURRENTS TO mOW IN THE OUTER SURFACES OF A CONDUCTORIN EFFECT MAKING THE CONDUCTOR NARROWER THUS INCREASING THE RESISTANCE FROM ITS DC VALUE 7HILE SKIN EFFECT IS BEYOND THE SCOPE OF THIS ARTICLE A GOOD APPROXIMATION FOR THE SKIN DEPTH IN COPPER IN CENTIMETERS IS 3KIN $EPTH %,%#42/,94)# "90!33 #%2!-)# "90!33 4HERE IS MUCH MORE TO DISCUSS THAN CAN BE COVERED HERE BUT WELL HIGHLIGHT SOME OF THE KEY FEATURES AND ENCOURAGE THE READER TO PURSUE THE SUBJECT IN GREATER DETAIL ! LIST OF REFERENCES APPEARS AT THE END OF THIS ARTICLE %,%#42/,94)# "90!33 'ROUND 0LANE $)3!",% #%2!-)# "90!33 2' 2& 6). /04)/.!, #!0!#)4/2 #%2!-)# "90!33 6/54 #%2!-)# "90!33 n63 %,%#42/,94)# "90!33 C &IGURE ,AYOUT DIFFERENCES FOR AN OP AMP CIRCUIT A 3/)# PACKAGE B 3/4 AND C 3/)# WITH 2& UNDERNEATH BOARD !NALOG $IALOGUE 3EPTEMBER DISABLE 1 AD8099 8 +VS 7 VOUT –IN 3 6 CC +IN 4 5 –VS FEEDBACK 2 n n (!2-/.)# $)34/24)/. D"C ,OW DISTORTION AMPLIlER PINOUT ! NEW LOW DISTORTION PINOUT AVAILABLE IN SOME !NALOG $EVICES OP AMPS THE !$ FOR EXAMPLE HELPS ELIMINATE BOTH OF THE PREVIOUSLY MENTIONED PROBLEMS AND IT IMPROVES PERFORMANCE IN TWO OTHER IMPORTANT AREAS AS WELL 4HE ,&#30S LOW DISTORTION PINOUT AS SHOWN IN &IGURE TAKES THE TRADITIONAL OP AMP PINOUT ROTATES IT COUNTER CLOCKWISE BY ONE PIN AND ADDS A SECOND OUTPUT PIN THAT SERVES AS A DEDICATED FEEDBACK PIN ' 6/54 6 P P 63 6 2, 6 n n n n #30 n &IGURE /P AMP WITH LOW DISTORTION PINOUT 4HE LOW DISTORTION PINOUT PERMITS A CLOSE CONNECTION BETWEEN THE OUTPUT THE DEDICATED FEEDBACK PIN AND THE INVERTING INPUT AS SHOWN IN &IGURE 4HIS GREATLY SIMPLIlES AND STREAMLINES THE LAYOUT 63 3/)# n 3/,)$ ,).%33%#/.$ (!2-/.)# $/44%$ ,).%34()2$ (!2-/.)# &2%15%.#9 -(Z &IGURE !$ DISTORTION COMPARISONTHE SAME OP AMP IN 3/)# AND ,&#30 PACKAGES !T PRESENT THREE !NALOG $EVICES HIGH SPEED OP AMPS ARE AVAILABLE WITH THE NEW LOW DISTORTION PINOUT !$ !$ AND !$ %,%#42/,94)# "90!33 2OUTING AND 3HIELDING ! WIDE VARIETY OF ANALOG AND DIGITAL SIGNALS WITH HIGH AND LOW VOLTAGES AND CURRENTS RANGING FROM DC TO '(Z EXISTS ON CIRCUIT BOARDS +EEPING SIGNALS FROM INTERFERING WITH ONE ANOTHER CAN BE DIFlCULT #%2!-)# "90!33 $)3!",% 6/ 2' 2, 2& #%2!-)# "90!33 6). n63 %,%#42/,94)# "90!33 &IGURE 0#" LAYOUT FOR !$ LOW DISTORTION OP AMP !NOTHER BENElT IS DECREASED SECOND HARMONIC DISTORTION /NE CAUSE OF SECOND HARMONIC DISTORTION IN CONVENTIONAL OP AMP PIN CONlGURATIONS IS THE COUPLING BETWEEN THE NONINVERTING INPUT AND THE NEGATIVE SUPPLY PIN 4HE LOW DISTORTION PINOUT FOR THE ,&#30 PACKAGE ELIMINATES THIS COUPLING AND GREATLY REDUCES SECOND HARMONIC DISTORTION IN SOME CASES THE REDUCTION CAN BE AS MUCH AS D" &IGURE SHOWS THE DIFFERENCE IN DISTORTION PERFORMANCE BETWEEN THE !$ 3/)# AND THE ,&#30 PACKAGE 4HIS PACKAGE HAS YET ANOTHER ADVANTAGEIN POWER DISSIPATION 4HE ,&#30 PROVIDES AN EXPOSED PADDLE WHICH LOWERS THE THERMAL RESISTANCE OF THE PACKAGE AND CAN IMPROVE U*! BY APPROXIMATELY 7ITH ITS LOWER THERMAL RESISTANCE THE DEVICE RUNS COOLER WHICH TRANSLATES INTO HIGHER RELIABILITY !NALOG $IALOGUE 3EPTEMBER 2ECALLING THE ADVICE TO h4RUST .O /NE v IT IS CRITICAL TO THINK AHEAD AND COME UP WITH A PLAN FOR HOW THE SIGNALS WILL BE PROCESSED ON THE BOARD )T IS IMPORTANT TO NOTE WHICH SIGNALS ARE SENSITIVE AND TO DETERMINE WHAT STEPS MUST BE TAKEN TO MAINTAIN THEIR INTEGRITY 'ROUND PLANES PROVIDE A COMMON REFERENCE POINT FOR ELECTRICAL SIGNALS AND THEY CAN ALSO BE USED FOR SHIELDING 7HEN SIGNAL ISOLATION IS REQUIRED THE lRST STEP SHOULD BE TO PROVIDE PHYSICAL DISTANCE BETWEEN THE SIGNAL TRACES (ERE ARE SOME GOOD PRACTICES TO OBSERVE s -INIMIZING LONG PARALLEL RUNS AND CLOSE PROXIMITY OF SIGNAL TRACES ON THE SAME BOARD WILL REDUCE INDUCTIVE COUPLING s -INIMIZING LONG TRACES ON ADJACENT LAYERS WILL PREVENT CAPACITIVE COUPLING s 3IGNAL TRACES REQUIRING HIGH ISOLATION SHOULD BE ROUTED ON SEPARATE LAYERS ANDIF THEY CANNOT BE TOTALLY DISTANCED SHOULD RUN ORTHOGONALLY TO ONE ANOTHER WITH GROUND PLANE IN BETWEEN /RTHOGONAL ROUTING WILL MINIMIZE CAPACITIVE COUPLING AND THE GROUND WILL FORM AN ELECTRICAL SHIELD 4HIS TECHNIQUE IS EXPLOITED IN THE FORMATION OF CONTROLLED IMPEDANCE LINES (IGH FREQUENCY 2& SIGNALS ARE TYPICALLY RUN ON CONTROLLED IMPEDANCE LINES 4HAT IS THE TRACE MAINTAINS A CHARACTERISTIC IMPEDANCE SUCH AS OHMS TYPICAL IN 2& APPLICATIONS 4WO COMMON TYPES OF CONTROLLED IMPEDANCE LINES MICROSTRIP AND STRIPLINE CAN BOTH YIELD SIMILAR RESULTS BUT WITH DIFFERENT IMPLEMENTATIONS ! MICROSTRIP CONTROLLED IMPEDANCE LINE SHOWN IN &IGURE CAN BE RUN ON EITHER SIDE OF A BOARD IT USES THE GROUND PLANE IMMEDIATELY BENEATH IT AS A REFERENCE PLANE '5!2$ 2).' 7 '5!2$ 2).' 42!#% 4 ).6%24).' $)%,%#42)# ./.).6%24).' A ( VOUT '2/5.$ 0,!.% AD8067 +V VOUT –V AD8067 +V –V &IGURE ! MICROSTRIP TRANSMISSION LINE +IN –IN +IN –IN %QUATION CAN BE USED TO CALCULATE THE CHARACTERISTIC IMPEDANCE FOR AN &2 BOARD : INVERTING ¨ ( · LN © ¸ ©ª 7 4 ¸¹ ER ( IS THE DISTANCE IN FROM THE GROUND PLANE TO THE SIGNAL TRACE 7 IS THE TRACE WIDTH 4 IS THE TRACE THICKNESS ALL DIMENSIONS ARE IN MILS INCHES n dR IS THE DIELECTRIC CONSTANT OF THE 0#" MATERIAL 3TRIPLINE CONTROLLED IMPEDANCE LINES SEE &IGURE USE TWO LAYERS OF GROUND PLANE WITH SIGNAL TRACE SANDWICHED BETWEEN THEM 4HIS APPROACH USES MORE TRACES REQUIRES MORE BOARD LAYERS IS SENSITIVE TO DIELECTRIC THICKNESS VARIATIONS AND COSTS MORESO IT IS TYPICALLY USED ONLY IN DEMANDING APPLICATIONS $)%,%#42)# ( 7 '2/5.$ 0/7%2 0,!.%3 4 %-"%$$%$ 42!#% " ( 4HE CHARACTERISTIC IMPEDANCE DESIGN EQUATION FOR STRIPLINE IS SHOWN IN EQUATION ¨ " LN © E R ©ª 7 4 · ¸ ¸¹ 'UARD RINGS OR hGUARDING v IS ANOTHER COMMON TYPE OF SHIELDING USED WITH OP AMPS IT IS USED TO PREVENT STRAY CURRENTS FROM ENTERING SENSITIVE NODES 4HE PRINCIPLE IS STRAIGHTFORWARDCOMPLETELY SURROUND THE SENSITIVE NODE WITH A GUARD CONDUCTOR THAT IS KEPT AT OR DRIVEN TO AT LOW IMPEDANCE THE SAME POTENTIAL AS THE SENSITIVE NODE AND THUS SINKS STRAY CURRENTS AWAY FROM THE SENSITIVE NODE &IGURE A SHOWS THE GUARD RING SCHEMATICS FOR INVERTING AND NONINVERTING OP AMP CONlGURATIONS &IGURE B SHOWS A TYPICAL IMPLEMENTATION OF BOTH GUARD RINGS FOR A 3/4 PACKAGE &IGURE 'UARD RINGS A )NVERTING AND NONINVERTING OPERATION B 3/4 PACKAGE 4HERE ARE MANY OTHER OPTIONS FOR SHIELDING AND ROUTING 4HE READER IS ENCOURAGED TO REVIEW THE REFERENCES BELOW FOR MORE INFORMATION ON THIS AND OTHER TOPICS MENTIONED ABOVE #/.#,53)/. )NTELLIGENT CIRCUIT BOARD LAYOUT IS IMPORTANT TO SUCCESSFUL OP AMP CIRCUIT DESIGN ESPECIALLY FOR HIGH SPEED CIRCUITS ! GOOD SCHEMATIC IS THE FOUNDATION FOR A GOOD LAYOUT AND CLOSE COORDINATION BETWEEN THE CIRCUIT DESIGNER AND THE LAYOUT DESIGNER IS ESSENTIAL ESPECIALLY IN REGARD TO THE LOCATION OF PARTS AND WIRING 4OPICS TO CONSIDER INCLUDE POWER SUPPLY BYPASSING MINIMIZING PARASITICS USE OF GROUND PLANES THE EFFECTS OF OP AMP PACKAGING AND METHODS OF ROUTING AND SHIELDING &/2 &524(%2 2%!$).' &IGURE 3TRIPLINE CONTROLLED IMPEDANCE LINE : 7 NONINVERTING B !RDIZZONI *OHN h+EEP (IGH 3PEED #IRCUIT "OARD ,AYOUT ON 4RACK v %% 4IMES -AY "ROKAW 0AUL h!N )# !MPLIFIER 5SERS 'UIDE TO $ECOUPLING 'ROUNDING AND -AKING 4HINGS 'O 2IGHT FOR A #HANGE v !NALOG $EVICES !PPLICATION .OTE !. "ROKAW 0AUL AND *EFF "ARROW h'ROUNDING FOR ,OW AND (IGH &REQUENCY #IRCUITS v !NALOG $EVICES !PPLICATION .OTE !. "UXTON *OE h#AREFUL $ESIGN 4AMES (IGH 3PEED /P !MPS v !NALOG $EVICES !PPLICATION .OTE !. $I3ANTO 'REG h0ROPER 0# "OARD ,AYOUT )MPROVES $YNAMIC 2ANGE v %$. .OVEMBER 'RANT $OUG AND 3COTT 7URCER h!VOIDING 0ASSIVE #OMPONENT 0ITFALLS v !NALOG $EVICES !PPLICATION .OTE !. *OHNSON (OWARD 7 AND -ARTIN 'RAHAM (IGH 3PEED $IGITAL $ESIGN A (ANDBOOK OF "LACK -AGIC 0RENTICE (ALL *UNG 7ALT ED /P !MP !PPLICATIONS (ANDBOOK %LSEVIER .EWNES 2%&%2%.#%3n6!,)$ !3 /& 3%04%-"%2 !$) WEBSITE WWWANALOGCOM 3EARCH !$ 'O !$) WEBSITE WWWANALOGCOM 3EARCH !$ 'O !$) WEBSITE WWWANALOGCOM 3EARCH !$ 'O HTTPWWWMICROWAVESCOMENCYCLOPEDIAMICROSTRIPCFM HTTPWWWMICROWAVESCOMENCYCLOPEDIASTRIPLINECFM !NALOG $IALOGUE 3EPTEMBER
