Vol. 36, No. 8
Journal of Semiconductors
August 2015
Design space of electrostatic chuck in etching chamber
Sun Yuchun(孙钰淳), Cheng Jia(程嘉), Lu Yijia(路益嘉), Hou Yuemin(侯悦民),
and Ji Linhong(季林红)Ž
State Key Laboratory of Tribology, Department of Mechanical Engineering, Tsinghua University, Beijing 100084, China
Abstract: One of the core semiconductor devices is the electrostatic chuck. It has been widely used in plasmabased and vacuum-based semiconductor processing. The electrostatic chuck plays an important role in adsorbing
and cooling/heating wafers, and has technical advantages on non-edge exclusion, high reliability, wafer planarity,
particles reduction and so on. This article extracts key design elements from the existing knowledge and techniques
of electrostatic chuck by the method proposed by Paul and Beitz, and establishes a design space systematically. The
design space is composed of working objects, working principles and working structures. The working objects involve electrostatic chuck components and materials, classifications, and relevant properties; the working principles
involve clamping force, residual force, and temperature control; the working structures describe how to compose an
electrostatic chuck and to fulfill the overall functions. The systematic design space exhibits the main issues during
electrostatic chuck design. The design space will facilitate and inspire designers to improve the design quality and
shorten the design time in the conceptual design.
Key words: design space; electrostatic chuck; clamping force; temperature control
DOI: 10.1088/1674-4926/36/8/084004
PACC: 7850G
1. Introduction
An electrostatic chuck (ESC) is one of the core components of many semiconductor devices and has been widely
utilized in plasma-based and vacuum-based semiconductor
processing, such as dry etching, plasma enhanced chemical
vapor deposition (PECVD), thermal chemical vapor deposition, physical vapor deposition (PVD), ion implantation, and
extreme ultraviolet lithography (EUVL). The ESC adsorbs
wafers by the electrostatic force on its own surface. According to application processes, it can be classified into two types,
of which one is for the etching process, etc., the other for the
EUVL process, etc. The ESC for the etching process has a surface with small mesas or several narrow grooves for fast gas
transportŒ1; 2 . The ESC for the EUVL process has a surface
with many static pins to weaken image placement errors due to
the distortion caused by the particles trapped between the reticle and the chuckŒ3; 4 . This article focuses only on the type for
the etching process.
Compared with a vacuum chuck’s incompatibility with the
vacuum environment and a mechanical chuck’s contaminations
to silicon wafers during the handling process, the ESC has technical advantages on non-edge exclusion, high reliability, wafer
temperature uniformity control, wafer planarity, particles reduction and yielding improvementŒ5; 6 .
1.1. Background
As a core element of semiconductor manufacturing equipment, the ESC plays a key role in wafer performances during
the etching process. Nevertheless, designers are still faced with
several problems in the design of ESCs, such as non-uniformity
of wafer temperature, chuck surface damage due to plasma erosion, poor process repeatability and low efficiency caused by
residual charges during de-chucking, film damage induced by
the chuck current, and wafer cracking during pin risingŒ7 . To
solve these problems, designers have to create new techniques.
Because the ESC is a complicated electromechanical system
with precise structures and complex principles, the design of
ESCs involves a wealth of knowledge regarding the thermal
field, electric field, plasma, structure and material science. In
the design process, the conflict of many parameters in multidisciplinary domains is unavoidable.
1.2. Motivation
So far, the systematic and comprehensive literature and research about ESC design have been seldom, possibly due to the
enormous information and complicated principles, as well as
confidentiality of the relevant enterprises. How to make ESCs
perform well and what to consider about in ESC design are
what designers are concerned with most. In this research, an
overview of the main existing ESC knowledge and techniques
is presented, and attempting to establish a systematic design
space by extracting the key design elements from the existing
ESC knowledge based on the theory of design space proposed
by Paul and Beitz. The design space aim is to assist designers
to understand what an ESC is and how to design it, inspire them
to innovate, and facilitate the ESC modeling. The design space
exhibits the main issues during ESC design, which can extend
designers’ thinking and understanding. It can also remind designers not to ignore any crucial factor.
* Project supported by the Ministry of Science and Technology of China (No. 2011ZX02403), and the National Natural Science Foundation
of China (No. 51175284).
Ž Corresponding author. Email: jilh@tsinghua.edu.cn
c 2015 Chinese Institute of Electronics
Received 29 January 2015, revised manuscript received 2 April 2015
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3. Working objects
3.1. Components and materials
A schematic graph of ESC components is presented in Figure 2. One of the main components of the ESC is the electrostatic electrode embedded in a dielectric/bulk layer (usually
ceramics, e.g. Al2 O3 , Ta2 O5 , AlN, SiO2 , TiO2 - and Cr2 O3 added alumina, polymer or composite materials). The dielectric
layer is the top surface of the ESC and contacts with the wafer.
The top surface is flat with grooves or mesas for transporting
heat-conductive gas everywhere quickly and uniformly, and
has pins lifting wafers up and down during clamping and declampingŒ1; 11 16 . Therefore, mesas, grooves and the roughness of the dielectric layer top surface build a gap between the
wafer and the ESC, which is filled with a heat-conductive gas,
mentioned above, usually heliumŒ11 . This gap is commonly
named the gas/interfacial layer. There is also a gas supply system, a cooling system, a chucking power source, a radio frequency (RF) source, a collar ring and a substrate, etc. All the
above assemble a whole ESC.
Figure 1. The constitution of ESC current design space.
3.2. Classifications
2. Definition of design space
The goal of this article is to build a design space for the integrated design and innovative design of ESCs. A design space
is understood as a universe of possible design choicesŒ8; 9 . Despite not being a space in the strict mathematical sense of a
vector space, it serves as an established analogy in many fields.
The most prevalent strategy to define a design space is to extract common design principles from a set of existing knowledge. In other words, a design space is treated as an information space which represents a description of a given object on
a much higher level of abstraction. In this article, the design
space is composed of working objects, working principles and
working structures.
Using the strategy above, the current design space of the
ESC is established as shown in Figure 1. Attributes are subdivided into working objects, working principles and working structures based on the decomposition of engineering designŒ10 . First, the working objects describe the intrinsic characters of the target. Second, working principles describe the
surface, force, motion, material and energy to enable the intended physical process to take place. A physical effect will
take place through or on the surface with the material under
force to enable motion. Finally, the working structure describes
the type, form, space requirement, dimension and how it works.
According to the specific design of ESCs, the working objects involve components and materials, classification and the
properties related to the ESC; the main working principles of
the ESC involve electrostatic and residual force, wafer temperature control, etc.; the ESC working structure combines the
principles above to fulfill the task function. A dielectric layer,
a conductive gas layer, an electrostatic electrode that creates
electrostatic force, a source and a bias power that determine
ion energy, a cooling system and a pin system are organically
assembled to embody working principles and implement the
functions.
According to the configuration of electrodes, the ESC can
be classified into the paired coplanar type (two D-shaped type),
the parallelly interdigitated type (comb type), the spirally interdigitated typeŒ17 , and many othersŒ18 .
According to the number of electrodes, ESCs can be classified into the monopolar, bipolar and multipolar type. Just as
its name implies, the monopolar type has only one electrode,
so at this time the wafer must be treated as the other electrode
of the capacitor. High-voltage is applied between the electrostatic electrode and the grounded plasma chamber wallŒ7 . A
current loop flows through the electrode, the wafer, plasma and
the grounded chamber wall in sequence. Only the electrostatic
clamping force depends on this current loop; in other words,
if there is no plasma, there will be no clamping force without
plasma. Nevertheless, it is notable that just this feeble current
may cause damage to the wafer. Except the grounded chamber wall as above, a grounded substrate is also feasible for the
same reasonŒ19 . The advantages of the monopolar type are that
the configuration is simple and the clamping force is higher
than that of the bipolar one since the effective area is larger
and the distribution of electric potential is homogeneousŒ19; 20 .
The disadvantage is that plasma is necessary during the clamping and de-clamping period respectively before and after the
etching process, because charging or discharging current has
to flow through the plasma. Thus it means a low throughput of
wafers. What is worse is that wafer-temperature controllability starts to deteriorate just after plasma generation, because at
this moment the conductive gas could not be applied yet on the
condition of no clamping forceŒ21; 22 .
The bipolar type ESC has two electrodes, and a high voltage is split between the two electrodesŒ7 ; it can clamp the wafer
without the need for plasma, since the current loop can flow
through these two electrodes instead of the plasma. So a clamping force can be exerted before the plasma is excited, which is
different from the sequence of the monopolar type. Furthermore, since in the clamping and declamping steps plasma is
not required, the throughput is higherŒ13 . As a result, gener-
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Figure 2. Schematic graph of ESC components.
ally the bipolar type is more common due to such defects of
the monopolar type.
According to the mechanism of clamping force, ESCs
are mainly classified into the Coulomb typeŒ20; 23 , and the
Johnsen-Rahbek (J-R) typeŒ14; 20 . Actually, both types combine the Coulomb force and J-R effectŒ14; 24 to some extent, the only difference is which one dominates the other.
Which one dominates is related to several factors, like the
volume resistivity of the dielectric material, clamping time,
temperature, and so forth. The Coulomb type usually uses an
insulating spacer layer (volume resistivity > 1014 cm)
between the electrostatic electrode and wafer, while the JR type uses a semi-conductive spacer layer ( D 109 –1013
cm)Œ7; 13; 14; 25 . The Coulomb force is generated due to the
polarized charges that are induced by the electric field between
the electrostatic electrode and waferŒ15 , as shown in Figure
3(a). The field strength of the Coulomb type is lower than that
of the J-R type because its dielectric thickness is thicker. The
leakage current is little because the resistance of the dielectric
layer is very high, so the voltage drop in the dielectric layer is
almost the same as the source voltageŒ19 . One of the advantages of this type is that residual clamping force can be eliminated relatively more easily after the applied voltage is cut off,
because the charges are just induced by the electric field.
If the resistivity of the dielectric layer is not high enough,
charges on the electrostatic electrode will transfer to the top
surface of the dielectric layer under the electric field as shown
in Figure 3(b). This charge migration and accumulation depend
on the dielectric’s volume resistivity; the lower the resistivity
is, the faster the charges will transfer. It is assumed that microscopic unevenness (roughness) exists on the surfaces. In Figure
3(b), the random contact points may cause local leakage paths.
Usually, the ratio of the contact area to the noncontact area is
very small. Electric charges migrate to and are stored in the
dielectric’s top surface, which generates a strong electric field
at noncontact areas. This is the J-R effect and the electrostatic
force generated in this way is called the J-R forceŒ13; 17; 24 .
The J-R ESC shows some superior performances compared to the Coulomb type. The superiority is embodied in the
stronger clamping force for a given clamping voltage (or lower
clamping voltage required for the given clamping force), and
relaxed material and machining criteria for dielectric manufacturing. A stronger clamping force could load higher back-
Figure 3. Schematic graph of E-chuck adsorbing principle. (a)
Coulomb type. (b) J-R typeŒ26 .
pressure, therefore, a higher heat-transfer capability can be
achieved. In view of these advantages, the J-R effect has become widespread in many applications in semiconductor production processes. However, the wafer held by the J-R force
may be harder to detach than by the Coulomb force after turning off the chuck voltage in the de-chucking operation, because
in case of the J-R type, the electrostatic charges remain for a
long time, worse still, sometimes they cause wafer crack problems during pins risingŒ7 .
3.3. Properties
The properties related to the ESC play an essential role in
the quality and yield of wafers, and can be divided into an objective level and a primary level. Just as its name implies, the
objective level should consist of properties which are processing quality indices that concern designers most: etching uniformity, etching rate, etching profile, production efficiency, temperature and pressure distribution on the wafer, plasma density
and energy, ion incident angle, wafer flatness, particle contam-
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ination, the lifetime and so on. Nevertheless, all of them depend
on the properties in the primary level, such as pressure and
thermal conductivity of cooling gas; flow rate and pressure of
process gas; the inner geometric structure of the chamberŒ27 ;
the layout of components like the ESC, RF power and frequencyŒ28; 29 ; electrostatic voltage and current; hardness and
roughness of the dielectric layer; conductivity and resistivity
of the dielectric layer; corrosion resistance of the ESC surface;
and size, type, material, structure of the ESC components.
4. Working principles
ESC working principles derive from the physical theory
and sometimes from experience. In the task of designing ESCs,
there are several key subfunctions to fulfill by three physical
processes: electrostatic force generation, residual force elimination, and temperature control. The ESC working principles
correspond to the physical processes.
4.1. Clamping force
According to References [5, 30–34], it is clear that the
clamping force is one of the most important factors concerning the effectiveness of ESCs. The clamping force is generally
affected by the following factors: external applied voltages of
the electrostatic electrode, properties of the dielectric layer, and
geometric structuresŒ35 . In what follows, two equations are established to calculate the clamping force for the Coulomb type
and the J-R type ESCs respectively.
4.1.1. Coulomb type
The Coulomb force between two parallel capacitors can be
calculated byŒ15
1
kU 2
F D "0 A
;
(1)
2
h
where A is the electrode area, "0 is free-space permittivity, k is
relative permittivity, U is the applied voltage, and h is the distance between the wafer’s bottom surface and the electrostatic
electrode’s top surface. This distance is always composed of
two parts, of which one is the dielectric layer with thickness
d and relative permittivity kd , the other is the gas layer with
thickness g and relative permittivity kg . This sandwich structure can be considered as two capacitors, connected serially.
Therefore, it can be revised as
2
kd kg U
1
F D "0 A
:
(2)
2
kg d C kd g
kg 1, and if in most cases of g d , so that Equation (2) still
can be approximately equal to
kd U 2
1
:
(3)
F D "0 A
2
d
It indicates that clamping force depends directly on dielectric material properties (kd / and layer thickness (d ). A thinner
dielectric layer can gain a higher clamping force, but on the
other hand it is easily deformed and torn by tension when the
wafer starts movingŒ24 , and is probably broken down by the
chuck current. Usually, a greater clamping force could be obtained with a ceramic film than a polymer oneŒ11 .
4.1.2. J-R type
J-R force can be calculated by the following equationŒ15 ,
1
F D "0 A0
2
kg U 0
g
2
;
(4)
where A0 is the effective area ( area A except the contact area);
kg is gas relative permittivity; g is the gap distance between the
dielectric’s top surface and wafer’s bottom surface; and U 0 is
effective clamping voltage. Effective area A0 , usually close to
A, is related to contact surface roughness and clamping force
condition. The gas layer thickness g is determined by the contact surface roughness and the clamping force condition too,
because the gap could be changed a bit by the elastic deformation of the rough surfaces, and increasing the clamping pressure though dielectric materials is always hardŒ14 . From Equation (4), it can be seen that the clamping force increases with a
square of the applied DC voltage. However, the clamping force
will not increase continuously by increasing the applied voltage. It will gradually saturate at a higher voltage as a result of
gas micro breakdown due to the surface roughness in the interfacial spaceŒ24 . U 0 is based on an equivalent resistor ratio
U0 D
RC
V;
RC C RV
(5)
where RV is the equivalent dielectric volume resistance and RC
is the equivalent contact resistance of contact portions. RV can
be determined from the dielectric volume resistivity, the area
A and thickness d , while RC is a function of surface roughness and pressure. The contact area is also a function of surface roughness and pressure. Generally speaking, the contact
area is much smaller than the electrode area, and RC is much
larger than RV in the case of the J-R type. So that U 0 U
and A0 A. Moreover, the resistivity of dielectric layer decreases with increasing applied voltage and temperature because of increasing leakage currentŒ14 . In the plasma environment, calculation of clamping force becomes more complicated and difficult. What cannot be ignored is that plasma
can change the effective voltage due to self-bias induced by
the plasma sheathŒ25 .
Although U 0 and A0 of J-R ESC are smaller than in classic
Coulomb ESC, the J-R force is larger than the Coulomb force
for a given applied voltage. Besides that, the J-R force is independent from dielectric properties like material, permittivity
and thickness, etc. This feature relaxes critical requirements of
ESC machining and dielectric materials, as well as the consideration of dielectric material breakdown and mechanical integrity issues.
Besides all the above factors of clamping force, ChoeŒ2
studied the behaviors of wafer taking RF electric field into considerations and provided a comprehensive equation of clamping force,
qE C FHe G FESC 6 0;
(6)
where qE represents the RF electric field force, E is always
changing following RF power; FHe is the force generated by
the pressure of the interface gas helium; G is gravity; and FESC
is the electrostatic force. In Equation (6), a positive sign means
the force is upwards.
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4.2. Residual force
In volume production, wafers have to be declamped speedily. However, in the declamping operation, withdrawal of DC
voltage leaves surface charges and yields residual force where
the magnitude is comparable to the original clamping force.
Hence wafers cannot be transported rapidly leading to low production efficiency. In addition, subsequent clamping force in
the next processing cycle is variable and not steady due to
residual charges.
Several methods can be adopted to eliminate the influence of residual force. Ceramic as the dielectric layer performs
much better than polymer. Taking PET as an example compared with ceramic, the electrostatic force is 1/10 smaller, and
the declamping time may last even 60 min, which is hundreds
of times longer. Usually, wafers held by the Coulomb force can
be easily detached after the chuck voltage is turned off by making the electrostatic electrode grounded for the monopolar type
or adding a resistance between two electrodes for the bipolar
type. However, as for the J-R type electrostatic residual charges
always endure and cause wafers to crack occasionally during
pin rising. The declamping time may last for 20 s as a result
that productivity is reduced to some extent. The root cause of
residual force is the charges left on the top surface of the dielectric layer. Surface charges can be removed or limited by
(1) exposing the chuck surface to brief low-power inert plasma
discharge; (2) alternating the polarity of applied voltage during
declamping for a few seconds; (3) applying AC voltage instead
of DC as the electrostatic force sourceŒ17 , however the electrostatic force for AC applied voltage is much lower than that for
equal DC voltageŒ11 ; (4) increasing roughness of the dielectric layer top surface (gap distance); and (5) reducing volume
resistivity of the dielectric layer.
4.3. Temperature control
There is a heat budget model to describe heat transmission
of the wafer on the ESC. When the heat budget comes to a
stable state, a heat balance composed of several main budgets
is described by a formula as shown in Equation (7). The heat
power input to the wafer is from plasma (Qplasma /. On the other
hand, the different heat released from the wafer are radiation
to the chamber walls and the chuck (Qrad /, conduction at the
contact parts of the chuck and wafer (Qcnt /, and heat transfer
through the interface gas helium trapped between the chuck
and the wafer (Qgas /, as shown in Figure 4. The heat budget
could be expressed by
Qplasma D Qrad C Qcnt C Qgas :
(7)
The heat transferred from the plasma to the wafer has a
great influence on wafer temperature uniformityŒ36 , which is
critical to etching rate and uniformity. The usage of a photoresist requires a wafer temperature low enough to prevent itself
from damage. Therefore, one kind of heat-conductive gas, usually inert gas such as helium or neon, is necessary as a transfer
medium between the wafer and the ESC. Otherwise wafer temperature would rise rapidly because of there being no way to
lose heat except through radiation in the almost vacuum environment. Gas is trapped in the narrow gap and mostly does
not flow away with the heat, except a little leakage through the
Figure 4. Heat budget model of ESC.
edge due to a seal effect by the close contact at the edge of
the chuck and the wafer. The leakage may displace etchant gas
and lead to etching non-uniformity to some extentŒ33 . Generally speaking, wafer temperature is mainly a function of input
power, chuck temperature and the heat transfer between the
wafer and chuckŒ34 .
Heat radiation between the wafer and chamber wall could
be ignored because the temperature of the wafer is not very
high in a stable status. It can be calculated by the following
formula,
4
4
Qrad D "A.Twafer
Twall
/;
(8)
where Twafer is the wafer temperature, Twall is the chamber wall
temperature, " is the wafer emissivity that is in the range [0, 1],
and D 5.68 10 8 W/m2 K4 is the Stephan-Boltzmann coefficient. Therefore, based on Equation (8), in the case when
Twafer is not very high (e.g. 200 ıC), the radiation is small
enough to ignore after calculating.
Heat transfer between the chuck and the wafer may be considered as the combination of contact point conduction, heat
convection by helium, and heat radiation between them. Nevertheless, heat radiation between the wafer and chuck could
likewise be ignored if accuracy is not very strict. Because at a
stable situation the temperature difference between the chuck
surface and wafer is small enough, the radiation heat exchange
is negligible compared to conduction through contact points or
backside helium. Heat convection belongs to the category of
heat convection between two parallel plates. However, if the
higher temperature plate is above, heat convection will not take
place based on the principle of heat transfer. In the etching process, heat is loaded from the plasma above the wafer, in other
words, the case is just like what is mentioned above. So helium
as a heat transfer medium only plays the role of heat conduction
here.
Heat transfer can be categorized according to backside
pressure as the following: the regime of continuum thermal
conduction, the regime of conduction of the temperature jump
(slip), the transition regime, and the regime of free molecule
heat conductionŒ31 . In the case of extreme low pressure and a
narrow gap, the heat conduction no longer follows continuum
gas behaviour where the thermal conductivity is independent of
pressure, but depends on the pressure of gas. At low pressures,
the heat transfer coefficient increases with pressure because
the free path for collisions is larger than the wafer–chuck dis-
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Figure 5. Four types of ESC with different structures.
tance. KlickŒ37 proposed a microscopic approach to describe
the whole pressure range, considering the basic features of gas
species, surface properties, the velocity and angular distribution of the atoms.
A dimensionless number named Knudsen number (Kn) is
introduced to describe the degree of rarefaction which is important in rarefied gas dynamicsŒ38 , expressed by the formula
below:
Kn D ;
(9)
l
where is the mean free path for helium, and l is characteristic dimension (the distance between two parallel planes, for
instance in this research between the wafer and chuck).
In case the Kn is very small, the number of collisions between the molecules is larger than the number of collisions between the molecules and the body. As a result, the general continuum concepts are applicable, thus the well-known NavierStokes equations and Fourier Heat Conduction Law are valid.
If the Kn is very high, the number of collisions between
the molecules and the wall is much larger than the number of
collisions between the molecules. This type of flow belongs to
the regime of free molecule.
The four regimes are just divided according to: the regime
of continuum thermal conduction where Kn < 0.01, the regime
of conduction of the temperature jump (slip) where 0.01 < Kn
< 0.1, the transition regime where 0.1 < Kn < 10, and the
regime of free molecule heat conduction where Kn > 10.
Through calculation the type of gas thermal conduction
between the chuck and wafer is in the regime of either free
molecule or transition. In these two regimes, l is very close to
or even smaller than , therefore, thermal conductivity changes
sensitively as l varies, which could be seen in Springer’s paperŒ38 , while in the other two regimes where l is much larger
than , l has little influence on thermal conductivity.
5. Working structures
5.1. Structure
Working structures describe the type, form, space requirement and dimension, etc. ESC working structure integrates all
elements and physical effects to fulfill the functions and requirements. The structure diagram of a bipolar type ESC is
shown in Figure 2. The elements work together to realize the
Figure 6. Timing settings of working signals of the monopolar type
ESC.
two most important functions: wafer clamping and temperature
controlling, meanwhile ensure the etching qualities, like etching uniformity. Figure 5 shows sketch graphs of four types of
ESC with different structures but the same functions derived
from real facilities of several companies. How these structures
work will be introduced as follows.
5.2. Process
ESC is located in the bottom of the chamber. Take a
monopolar ESC as an example, it can clamp and de-clamp a
wafer with plasma since net charge flow through the plasma is
necessary. Before etching process pins arise, after that a robot
hand submits a wafer into the chamber and positions it on the
pins. Then the wafer goes down with the pins, and contacts the
top surface of the ESC. Next, RF power turns on and runs at
low power state in case that wafer temperature rises fast, and
now plasma comes into being. After that, the chuck electrostatic electrode starts working to hold the wafer, and shortly
interface gas from the gas supply system begins filling the gap
between the wafer and the ESC. Then RF bias is opened to induce ions to bomb towards the wafer. RF power decides the
density of the plasma, while bias RF determines the energy of
ions. This is when the etching process really starts. After the
etching process, the RF bias, gas supply, the chucking power
and the RF power turn off in sequence opposite to the process
of turning on. The robot hand takes away the wafer risen by the
pins. The process above is illustrated in Figure 6. The cooling
plate is full of fluid to cool down the chuck. The collar ring is
used to protect the ESC surface from damage by plasma and
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help the wafer locate at the right position. This is how the ESC
structure works.
6. Conclusion
The design space of the ESC established in this article is
treated as an information space, which represents a description
of the ESC on a much higher level of abstraction. The design
space is composed of working objects, working principles and
working structure. The design space mostly involves all key
elements of the ESC techniques and knowledge mentioned in
articles and patents. Such a design space is usually used in the
conceptual design process, and to some degree, is a seed for
the embodiment design process of ESCs. Through the design
space of ESCs, designers can be inspired to know how to design
ESCs, and how to resolve problems in the design process of
ESCs. The design space can also facilitate the ESC modelling.
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