CMOS
Manufacturing
Process
Digital Integrated Circuits
Manufacturing Process
EE141
CMOS Process
Digital Integrated Circuits
Manufacturing Process
EE141
A Modern CMOS Process
gate-oxide
TiSi2
AlCu
SiO2
Tungsten
poly
p-well
n+
SiO2
n-well
p-epi
p+
p+
Dual -Well Trench -Isolated CMOS Process
Digital Integrated Circuits
Manufacturing Process
EE141
Circuit Under Design
VDD
VDD
M2
M4
Vout
Vin
M1
Vout2
M3
This two-inverter circuit (of Figure 3.25 in the text) will be
manufactured in a twin-well process.
Digital Integrated Circuits
Manufacturing Process
EE141
Circuit Layout
Digital Integrated Circuits
Manufacturing Process
EE141
The Manufacturing Process
For a great tour through the process and its different steps, check
http://www.fullman.com/semiconductors/semiconductors.html
For a complete walk-through of the process (64 steps), check the
Book web-page
http://bwrc.eecs.berkeley.edu/Classes/IcBook
Digital Integrated Circuits
Manufacturing Process
EE141
Photo-Lithographic Process
optical
mask
oxidation
photoresist
removal (ashing)
photoresist coating
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step
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spin, rinse, dry
Manufacturing Process
EE141
Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO2
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
Si-substrate
Hardened resist
SiO
2
(b) After oxidation and deposition
of negative photoresist
Si-substrate
UV-light
Patterned
optical mask
(e) After etching
Exposed resist
Si-substrate
(c) Stepper exposure
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SiO
2
Si-substrate
(f) Final result after removal of resist
Manufacturing Process
EE141
CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
Create contact and via windows
Deposit and pattern metal layers
Digital Integrated Circuits
Manufacturing Process
EE141
CMOS Process Walk-Through
p-epi
(a) Base material: p+ substrate
with p-epi layer
p+
SiN
34
p-epi
SiO
2
(b) After deposition of gate-oxide and
sacrificial nitride (acts as a
buffer layer)
p+
(c) After plasma etch of insulating
trenches using the inverse of
the active area mask
p+
Digital Integrated Circuits
Manufacturing Process
EE141
CMOS Process Walk-Through
SiO
2
(d) After trench filling, CMP
planarization, and removal of
sacrificial nitride
n
p
Digital Integrated Circuits
(e) After n-well and
VTp adjust implants
(f) After p-well and
VTn adjust implants
Manufacturing Process
EE141
CMOS Process Walk-Through
poly(silicon)
(g) After polysilicon deposition
and etch
n+
p+
(h) After n+ source/drain and
p+source/drain implants. These
steps also dope the polysilicon.
SiO2
(i) After deposition of SiO 2
insulator and contact hole etch.
Digital Integrated Circuits
Manufacturing Process
EE141
CMOS Process Walk-Through
Al
(j) After deposition and
patterning of first Al layer.
Al
SiO
2
(k) After deposition of SiO
insulator, etching of via’s, 2
deposition and patterning of
second layer of Al.
Digital Integrated Circuits
Manufacturing Process
EE141
Advanced Metalization
Digital Integrated Circuits
Manufacturing Process
EE141
Advanced Metalization
Digital Integrated Circuits
Manufacturing Process
EE141
Design Rules
Jan M. Rabaey
Digital Integrated Circuits
Manufacturing Process
EE141
3D Perspective
Polysilicon
Digital Integrated Circuits
Manufacturing Process
Aluminum
EE141
Design Rules
l
l
l
Interface between designer and process
engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
» scalable design rules: lambda parameter
» absolute dimensions (micron rules)
Digital Integrated Circuits
Manufacturing Process
EE141
CMOS Process Layers
Layer
Color
Well (p,n)
Yellow
Active Area (n+,p+)
Green
Select (p+,n+)
Green
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Contact To Poly
Black
Contact To Diffusion
Black
Via
Black
Digital Integrated Circuits
Manufacturing Process
Representation
EE141
Layers in 0.25 µm CMOS process
Digital Integrated Circuits
Manufacturing Process
EE141
Intra-Layer Design Rules
Same Potential
0
or
6
Well
Different Potential
2
9
Polysilicon
2
10
3
Active
Contact
or Via
Hole
3
2
3
Metal1
2
3
2
Select
4
Metal2
3
Digital Integrated Circuits
Manufacturing Process
EE141
Transistor
Transistor Layout
1
3
2
5
Digital Integrated Circuits
Manufacturing Process
EE141
Vias and Contacts
2
4
Via
1
1
5
Metal to
1
Active Contact
Metal to
Poly Contact
3
2
2
2
Digital Integrated Circuits
Manufacturing Process
EE141
Select Layer
2
Select
3
2
1
3
3
2
5
Well
Substrate
Digital Integrated Circuits
Manufacturing Process
EE141
CMOS Inverter Layout
In
GND
VD D
A
A’
Out
(a) Layout
A
A’
n
p-substrate
n+
p+
Field
Oxide
(b) Cross-Section along A-A’
Digital Integrated Circuits
Manufacturing Process
EE141
Layout Editor
Digital Integrated Circuits
Manufacturing Process
EE141
Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um.
Digital Integrated Circuits
Manufacturing Process
EE141
Sticks Diagram
V DD
3
Out
In
1
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
“compaction” program
GND
Stick diagram of inverter
Digital Integrated Circuits
Manufacturing Process
EE141