General bus operation Timing Diagrams BUS TIMING It is essential to understand system bus timing before choosing memory or I/O devices for interfacing to 8086 microprocessors. This section provides insight into operation of the bus signals and the basic read/write timing of the 8086. Cycles and States T- State: One subdivision of an operation performed in one clock period. A T-state lasts for one clock period. An instruction’s execution length is usually measured in a number of T-states. (clock cycles). Machine Cycle: The time required to complete one operation of accessing memory, I/O, or acknowledging an external request. Instruction Cycle: The time required to complete the execution of an instruction. 3 Timing in General 8086/8088 use memory and I/O in periods called bus cycles. Each cycle usually equals four system-clocking periods (T states). If the clock is operated at 5 MHz, one 8086/8088 bus cycle is complete in 800 ns. basic operating frequency for these processors Bus operation Basic Bus Operation- Read cycle If data are read from the memory the microprocessor: outputs the memory address on the address bus issues a read memory signal (RD) and accepts the data via the data bus See simplified timing for read cycle. Simplified 8086/8088 read bus cycle. Basic Bus Operation The three buses of 8086 function the same way as any other microprocessor. If data are written to memory the processor: outputs the memory address on the address bus outputs the data to be written on the data bus issues a write (WR) to memory IO/M = 1 for 8086 See simplified timing for write cycle. Simplified 8086/8088 write bus cycle. Simplified 8086/8088 Read/Write bus cycle. During the first clocking period in a bus cycle, called T1, many things happen: 1. The address of the memory or I/O location is sent out via the address bus and the address/data bus connections. 2. During T1, control signals are also generated and sent indicating whether the address bus contains a memory address or an I/O device (port) number 3. During T2, the processor issues the RD or WR signal, DEN, and in the case of a write, the data to be written appears on the data bus. The 8086 microprocessor shown with a demultiplexed address bus. TIMING DIAG – WRITE CYCLE memrd memwr control signals 8086 Simplified 8086/8088 Read/Write bus cycle. These events cause the memory or I/O device to begin to perform a read or a write. READY is sampled at the end of T2. If low at this time, T3 becomes a wait state (Tw) Wait state is also called idle state or inactive state Processor uses these clocks for internal housekeeping. This clocking period is provided to allow the memory time to access data If a read bus cycle, the data bus is sampled at the end of T3. The READY input is sampled at the end of T2 and again, if applicable, in the middle of Tw. Fig shows READY causing one wait state (Tw), with the required setup and hold times from the system clock. Setup time and Hold time Setup time: Setup time is defined as the minimum amount of time before the clock's active edge that the data must be stable for it to be latched correctly. In other words, each flip-flop (or any sequential element, in general) needs some time for the data to remain stable before the clock edge arrives, such that it can reliably capture the data. This duration is known as setup time. Hold time: Hold time is defined as the minimum amount of time after the clock's active edge during which data must be stable. This duration is known as hold time. Setup time and Hold time Figure 8086/8088 READY input timing. • If READY is logic 0 at the end of T2, • T3 is delayed and Tw inserted between T2 and T3. • READY is next sampled at the middle of Tw to determine if the next state is Tw or T3. READ CYCLE-MIN mode • The working of the minimum mode configuration system can be better described in terms of the timing diagrams rather than qualitatively describing the operations. • The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle. • The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also M / IO signal. • During the negative going edge of this signal, the valid address is latched on the local bus. READ CYCLE-MIN mode The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal indicates a memory or I/O operation. At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated for changing the direction of the bus. • The read (RD) control signal is also activated in T2. RD is somewhat delayed in T2 to provide time for floating). The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus. The addressed device will drive the READY line high. When the processor returns the read signal to high level, the addressed device will again tristate its bus drivers. TIMING DIAG - READ CYCLE Write cycle MIN mode • A write cycle also begins with the assertion of ALE and the • • • • • • • emission of the address. The M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processor sends the data to be written to the addressed location. The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating). The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write. The M/IO, RD and WR signals indicate the type of data Transfer i.e. Memory read or write or an input read or output write operation. Write cycle MIN mode TIMING DIAG – WRITE CYCLE T1 T2 T3 TW T4 CLK M/IO ALE ADDR/ DATA ADDR/ STATUS RD/INTA READY DT/R DEN MEMORY ACCESS TIME A15-A0 A19-A16 RESERVED FOR DATA VALID D15-D0 T2 T1 T3 TW CLK M/IO ALE ADDR/ DATA ADDR/ STATUS WR READY DT/R DEN A15-A0 A19-A16 DATA OUT (D15-D0) T4 Any Queries?? Thank you
