LDO Deisgn Santosh kumar Nov20 Design specifications: LDO with low output capacitor S.No Parameter Value units 1 LDO output 1.2+/-5% V 2 Output current 10 mA 3 No load current(pass gate) 33 uA 4 Reference output 0.7 V 5 Output capacitance Max:200 Min: 80 pF 4 Phase margin Min:35 Deg 5 Gain margin Min:-5 dB 6 PSR overshoot Max:0 dB Design: Error Amplifier 1. Error amplifier has with 8u A tail current with supply 1.5v and input common mode is 0.7v i.e from vref. Design: overall LDO with out compensation 1.Ldo consist of error amplifier, pass gate and resistive divider. 2. Both pass gate and resistive divider connected in feedback fashion 3. Sizes of resistor is determined from non π inverting amp Vout=vref(1+π 2) configuration 1 4. The resistor ratio will come from above π equation i.e π 2 1 5. Vout 1.2v and current at no load 30u A gives R1+R2, finally we get both R1 and R2 values 21k,15k 6. Size of pass gate is done at full load condition and with slow process corner at high temp(150 deg) Design: LDO with internally compensated 1. Ldo with source follower compensation to improve the stability of Ldo. 2. By the addition of extra source follower, it cancels right half plane zero (gm6/Cgd). 3. New pole locations are ππ1 = ππ2 = ππ§ = 1 πππππ π ∗ π ππ’π‘,πΈπ΄ ∗ π 1 + π 2 π ππππ πππ , πππ π ∗ πΆπΆ ππ,πππ π πΆππππ −ππ,ππΉ πΆπΆ Test bench: LDO with internally compensated DC and Stability analysis ADE XL setup ADE XL Setup Corner setup DC gain: No Load condition Phase: No Load condition Unity Gain Bandwidth: No Load condition Gain margin: No Load condition Phase margin: No Load condition Regulated output: No Load condition DC gain: Full Load condition Phase: Full Load condition Unity Gain Bandwidth: Full Load condition Gain margin: Full Load condition Phase margin: Full Load condition Regulated output: Full Load condition Test bench: LDO with internally compensated Transient Variations Regulator output: tr and tf =1us typ corners Regulator output: tr and tf =1us typ corners Regulator output: tr and tf =5us typical corners Regulator output: tr and tf =1us Regulator output: tr and tf =5us typ corners Regulator output: tr and tf =5us Test bench: LDO with internally compensated PSR LDO : power supply rejection at no load(rload=1M ohms) LDO : power supply rejection at full load(rload=120 ohms) Gain error and Settling time: model of LDO Gain error and Settling time: model of LDO Gain error and Settling time: model of LDO Gain error and Settling time: model of LDO Gain error and Settling time: model of LDO Gain error and Settling time: model of LDO Gain error and Settling time: model of LDO Gain error and Settling time: model of LDO Effect of finite risetime in single pole system Ideal 1. Time Constant T= RC=1k*1u=1m Sec Effect of finite risetime in single pole system Effect of finite risetime in single pole system Effect of finite risetime S.No Rise time(βtr) Input delay(ππππππ,πτ ) Output delay(πππππππ,πτ ) Delay=πππππππ,πτ-ππππππ,πτ units 1 1u 632.1n 1.001m 1m Sec 2 2u 1.264u 1.001m 1m Sec 3 4u 2.528u 1.002m 999.44u Sec 4 10u 6.321u 1.005m 998.8u Sec 5 50u 31.6u 1.026m 994.4u Sec 6 100u 63.21u 1.051m 987.8u Sec βtr ππππππ,πτ=0.632*βtr πππππππ,πτ=τππ πππ + π. πβtr Delay=~ τππ πππ - 0.132βtr Effect of finite risetime S.No Rise time(βtr) Theoretical calculation simulation unit s Input delay(ππππππ,πτ ) Output delay(πππππππ,πτ ) Delay=πππππππ,πτ -ππππππ,πτ Input delay(ππππππ,πτ Output delay(πππππππ,πτ ) Delay=πππππππ,πτ ππππππ,πτ 1 1m 632.1u 1.5m 868u 632.1u 1.519m 886.9u Sec 2 2m 1264u 2m 736u 1264u 2.158m 914u Sec 3 3m 1896u 2.5m 604u 1896u 2.837m 941.5u Note: Above equation is valid only when rise time< 1τ(for smaller time constants) It verified with other time constant circuits also Capacitor charging with current step βπππ’π‘ = πΌπ π‘ππ ∗ βπ‘ πΆππ’π‘ Calculation: Iavg= 0.5m A βπ‘=1u Sec Cout=200p F βπππ’π‘ =2.5 V Capacitor charging with current step Load transient analysis of LDO • Sudden rise current step of iLoad which creates voltage undershoot and overshoot at output voltage, it will be regulated after loop response time • The change in undershoot or overshoot approximately defined βπππ’π‘ = πΌππππππ£π πππ’π‘ 1 ( 2πππΊπΉ + πΆπ ππ πΌπ πππ€ ) πΌππππππ£π =0.5m A cout=200p UGF at no load=906K Hz Cgg=620f F Vg=145m V Islew=5.3m A =484.5m V Load transient analysis of LDO Load transient analysis of LDO • Change in output voltage βπππ’π‘ due sudden current step(βπΌππππ) The voltage scaled at the feedback network • βVf= π½ βπππ’π‘ ……………..(1) This change in voltage generated the current called as Ix • βπΌπ₯ = ππ1,2 βππ ……………(2) • The output voltage at error amplifier for that we need to find output impedance πππ’π‘ • Let unity gain frequency and dc gain is available so that we will get first pole location i.e • ππ1 = π΄π ππ π΄π => 1 π ππ’π‘,πΈπ΄ πΆππ’π‘,πΈπ΄ • πΆππ’π‘,πΈπ΄ = πΆπΆ π΄π£2 • π ππ’π‘,πΈπ΄ = (π΄π£2 =ππ,πππ π π ππ’π‘,πππ π ) 1 ππ1 ∗πΆππ’π‘,πΈπ΄ 1 Finally πππ’π‘ = π ππ’π‘,πΈπ΄ || ππΆππ’π‘ πΈπ΄ at 3 dB frequency Load transient analysis of LDO • Change in current at error amplifier provides the voltage at pass gate • ππ,πππ π = βπΌπ₯ ∗ πππ’π‘,πΈπ΄ Voltage change at gate of pass gate circuit creates current change in βπΌπππ π βπΌπππ π = ππ,πππ π ∗ ππ,πππ π The discharge current pass through the capacitor is βπΌπΏπππ − βπΌπππ π βπΌπππ π −βπΌπΏπππ ∗ βt βπππ’π‘ = πΆ ππ’π‘ Verifications: Current step βπΌππππ = 1π π΄ πππ π€ππ‘β βπ‘ = 1π’ ππ’π π‘π π‘βππ π πβππππ ππ βπππ’π‘ Load transient analysis of LDO Load transient analysis of LDO Load transient analysis of LDO Load transient analysis of LDO Low dropout regulator : Noise analysis Low dropout regulator : Detail Noise Contributions Noise contribution of Ldo elements Noise Contributed by Pass Gate 1.Major contribution of noise is differential pair (M1 and M2 ) 2. Pass gate noise was diminished by larger size 3. Input noise of second stage was attenuated by first stage differential pair Summary of LDO design S.No Parameter Value 1 Supply 1.5V 2 Technology 0.18u UMC CMOS 3 Output 1.2V 4 Gain@ No load Gain@ Full load 62dB 49.5dB 5 UGB@ No load UGB@ Full load 1.06M Hz 1.105M Hz 6 PM@ No load PM@ Full load 62 deg 102 deg 7 GM @ No load GM @ Full load 59dB 57dB 8 Quiescent current(iq) 93u A 9 1. 2. 3. 4. Error amplifier 10u A Bleeder current 35u A Voltage buffer compensation 5u A Pull down circuit 40u A PSR@ No load -57.4dB at DC(min) -69mdb at UGB(max) PSR@ Full load -45.36dB at DC(min) -60m dB max 10 Settling time(ts)| 98% 1.04u Sec 11 Load Transient (1m A/1u Sec) βπ1 =41m V (< 5% vout i.e 60m), βπ‘1 = 282.56π πππ 12 Input referred noise 61u V/ π»π§ compensation with simple miller compensation • Simple miller compensation: Frequency response : simulation Frequency response : simulation No Load PSR Simulation 1. A higher ROEA undoubtedly provides a better PSRR at low frequency. However, the PSRR in the moderate frequency range is degraded seriously. 2. AEA and RESR take a significant role on improving the PSRR. A larger AEA could gain a better PSRR at low to moderate frequency, while a smaller RESR could achieve PSRR enhancement at moderate to high frequency. 3. Finally, the worst PSRR happens at maximum IO. PSR: simulation No Load PSR: simulation No Load variation with Error amplifier gain PSR: simulation No Load variation with R ESR LDO with miller compensation : load transient Ldo with Ahuja compensation Improvement of frequency response: 1. Complex non-dominant poles with small damping factors are undesirable because those can cause loss in phase and/or gain margins, poor transient behavior and, in extreme cases 2. for large values of gm3 needs to be high and/or CC small. 3. The zero in the circuit is usually located just before the complex poles and the resulting magnitude curve shows pronounced peaking after the unity-gain crossover Frequency response of LDO: no load PM=90deg GM=28.13dB PSR response of LDO: no load Transient performance of LDO ahuja 14 bit accuracy: π‘1 1 πππΊπ΅ = π∗ln(2) here πππΊπ΅ = 2∗π∗π ππΊπ΅ Settling time= 1.96u sec (calculated) form simulation πππΊπ΅ = 790π π»π§ Ldo Ahuja compensation with gm boosting Loop1 Outer loop Loop2 Inner loop Frequency response of LDO: outer loop no load PM=90deg GM=28.13dB Frequency response of LDO: inner loop no load PM=90deg GM=28.13dB PSR response of LDO: no load Transient performance of LDO ahuja 14 bit accuracy: π‘1 1 πππΊπ΅ = π∗ln(2) here πππΊπ΅ = 2∗π∗π ππΊπ΅ Settling time= 1.23u sec (calculated) form simulation πππΊπ΅ = 1.25π π»π§ Comparison of LDO: Miller , Ahuja and Ahuja with gm boosting Parameter Miller Ahuja Ahuja with gm boosting Second pole 1.37 M Hz 7.1M Hz 41M Hz PSR @DC 55dB -46dB -32dB PSR@UGB -390m dB -18dB -18dB
