Chapter 5
ASIC
CONSTRUCTION
Floor planning
Definition: Floor planning is a mapping between the logical
description(the netlist) and the physical description(the floorplan)..
It is also the center of design operations for all types of ASIC.
Goals of floor planning:
 arrange the blocks on a chip,
 decide the location of the I/O pads,
 decide the location and number of the power pads,
 decide the type of power distribution, and
 decide the location and type of clock distribution.
Objectives of floor planning are:
 to minimize the chip area, and
 minimize delay.
Cont’s
 Floorplan is an essential step in electronic design automation.
 – It assigns exact locations for various circuit components within the
chip’s core area.
 – An inferior placement assignment will not only affect the chip’s
performance but might also make it non-manufacturable by
producing excessive wire length, which exceeds available routing
resources or critical delay constraint.
 A floorplan tool must perform the assignment while optimizing a
number of objectives to ensure that a circuit meets its performance
demands.
Floorplanning
Floorplanning methods
 Constraint Based.
 Linear Programming.
- Mixed Integer Linear Programming (MILP) complete.
 Rectangular Dualization Based.
 Hierarchical Tree Based.
 Simulated Annealing and Evolution Algorithms.
 Timing Driven.
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Physical Design Flow
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1.
2.
3.
4.
Because interconnect delay now dominates gate delay, the trend is to include
placement within a floor planning tool and use a separate router.
Design entry. The input is a logical description with no physical information.
Initial synthesis. The initial synthesis contains little or no information on any
interconnect loading. The output of the synthesis tool (typically an EDIF netlist)
is the input to the floor planner.
Initial floor plan . From the initial floor plan inter block capacitances are input to
the synthesis tool as load constraints and intra block capacitances are input as
wire-load tables
Synthesis with load constraints. At this point the synthesis tool is able to
resynthesize the logic based on estimates of the interconnect capacitance each
gate is driving. The synthesis tool produces a forward annotation file to constrain
path delays in the placement step.
Cont.s
5. Timing-driven placement. After placement using
constraints from the synthesis tool, the location of every
logic cell on the chip is fixed and accurate estimates of
interconnect delay can be passed back to the synthesis tool.
6. Synthesis with in-place optimization (IPO).The synthesis
tool changes the drive strength of gates based on the
accurate interconnect delay estimates from the floorplanner
withoutaltering the netlist structure.
7. Detailed placement. The placement information is ready
to be input to the routing step.
Placement Goals and Objectives
Goals:
Guarantee the router can complete the
routing step
Minimize all the critical net delays
 Make the chip as dense as possible
Objectives:
Minimize power dissipation
Minimize crosstalk between signals
Contd…
Types of routing
• Channel routing:
– channel may grow in one dimension to
accommodate wires;
– pins generally on only two sides.
• Switchbox routing:
– cannot grow in any dimension;
– pins are on all four sides, fixing dimensions of
the box.
Block placement
• Blocks have:
– area;
– aspect ratio.
• Blocks may be placed at different rotations
and reflections.
• Uniform size blocks are easier to
interchange.
Blocks and wiring
• Cannot ignore wiring during block
placement - large wiring areas may force
rearrangement of blocks.
• Wiring plan must consider area and delay
of critical signals.
• Blocks divide wiring area into routing
channels.
Key term
A microelectronic system (or system on a
chip) is the town and ASICs (or system
blocks) are the buildings.
System partitioning corresponds to town
planning.
 Floorplanning is the architect’s job.
 Placement is done by the builder.
Routing is done by the electrician.
Cont.…
System partitioning:
• Goal. Partition a system into a number of ASICs.
Objectives. Minimize the number of external connections between
the ASICs. Keep each ASIC smaller than a maximum size.
Floor planning:
Goal. Calculate the sizes of all the blocks and assign them locations.
Objective. Keep the highly connected blocks physically close to each
other.
Placement:
Goal. Assign the interconnect areas and the location of all the logic
cells within the flexible blocks.
Objectives. Minimize the ASIC area and the interconnect density.
Finally