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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004
Radio Frequency Digital-to-Analog Converter
Susan Luschas, Member, IEEE, Richard Schreier, Member, IEEE, and Hae-Seung Lee, Fellow, IEEE
Abstract—Dynamic performance of high-speed high-resolution
digital-to-analog converters (DACs) is limited by distortion at the
data switching instants. Inter-symbol interference (ISI), imperfect
timing synchronization, and clock jitter are all culprits. A DAC
output controlled by an oscillating waveform is proposed to mitigate the effects of switching distortion and clock jitter. This architecture has the additional benefit of mixing the DAC impulse
response energy to a higher frequency, allowing a high-frequency
image of the input to be used as the output. This has the potential for better noise performance and power and hardware savings
relative to a conventional DAC
mixer architecture. A narrowband sigma-delta
DAC with eight unit elements is chosen to
demonstrate the radio frequency digital-to-analog converter (RF
DAC) concept in a 1.8-V 0.18- m CMOS technology. Measured
single-tone SFDR is 75 dBc, SNR is 53 dB, and two-tone IMD3
is 70.8 dBc for a 17.5-MHz band centered at 942 MHz. SNR performance is shown to have the predicted dependence on the phase
alignment of the data clock and oscillating pulse.
(61)
Fig. 1. Conventional DAC impulse response with switching edge distortion.
+
Index Terms—Digital–analog conversion, mixing DAC, sigmadelta modulation.
Fig. 2. (a) Return to zero DAC. (b) dual-return to zero DAC [7]. (c) Pulse
shaped DAC output [9].
I. INTRODUCTION
W
IRELESS communications applications are challenging
the speed and frequency-domain performance of
modern data converters. High-speed accurate DACs require
fewer mixing and filtering stages before the antenna. The
frequency domain performance of conventional high-speed
high-resolution DACs is limited by distortion at the data
switching instants. This is indicated in the impulse response of
Fig. 1. Inter-symbol interference (ISI), imperfect timing synchronization, and clock jitter are the three main components of
this switching distortion [1]–[5]. When ISI is present, the DAC
output is dependent on the previous data, often in a nonlinear
way. This problem can be addressed by using a return-to-zero
(RZ) DAC output pulse, as shown in Fig. 2(a). This essentially nulls the sample-to-sample memory of the DAC, making
switching dynamics more linearly related to the input data.
However, for the same output energy as the conventional DAC
of Fig. 1, the amplitude of the pulse must be larger. These larger
steps in the DAC output increase the jitter sensitivity [6], [7].
Fig. 2(b) illustrates the dual RZ technique proposed in [7].
The outputs of two RZ DACs are summed to create a total
impulse response like a conventional DAC. The amplitude of
DAC1 and DAC2 is the same as the conventional DAC, which
Manuscript received December 19, 2003; revised February 28, 2004. This
work was supported by the Department of Defense, a Lucent GRPW Fellowship,
ABB Corporation, a National Semiconductor Fellowship, and MIT CICS.
S. Luschas is with Atheros Communications, Sunnyvale, CA 94085 USA
(e-mail: sdacy@alum.mit.edu).
R. Schreier is with Analog Devices Inc., Wilmington, MA 01887 USA.
H.-S. Lee is with the Massachusetts Institute of Technology, Cambridge, MA
02139 USA.
Digital Object Identifier 10.1109/JSSC.2004.829377
means no increased clock jitter sensitivity. The border between
the falling edge of DAC1 and the rising edge of DAC2 is tightly
controlled by the same clock edge, cancelling the effect of jitter
at this border. In summary, the dual RZ technique removes ISI
while maintaining the jitter sensitivity of a conventional DAC.
Imperfect timing synchronization among the elements of
the DAC is especially troublesome in a multibit DAC, where
glitches are created if the bits switch at different times. This
problem has been addressed in previous work by a combination
of a synchronization block in front of the switches and careful
layout to match path delays [3], [5]. The accuracy of this
method is limited by the matching achievable in the synchronization blocks and clock routing, and may become critical at
high output frequencies.
Sampling jitter also limits performance as output frequencies increase [6], [8]. Traditional approaches to mitigating the
DAC clock jitter problem have focused on either building a
high-power sampling clock with low jitter or using systems with
oversampling to reduce the in-band noise.
This work proposes the use of a DAC impulse response controlled by an oscillator at a harmonic of the DAC update rate.
This RF DAC architecture alleviates the ISI, timing synchronization, and sampling jitter problems. The RF DAC architecture is also shown to have the additional benefit of mixing the
DAC impulse response to higher frequencies, allowing the use
of an image of the input as the output of the DAC. Section II describes the RF DAC concept. Section III compares RF DAC to
that of a conventional DAC mixer architecture. The prototype
design is described in Section IV. Section V discusses experimental results, and conclusions are given in Section VI.
0018-9200/04$20.00 © 2004 IEEE
LUSCHAS et al.: RADIO FREQUENCY DIGITAL-TO-ANALOG CONVERTER
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Fig. 3. RF DAC concept of using multiple oscillatory pulses for every DAC
output code.
II. RF DAC CONCEPT
Zhang [9] recognized the problem of clock jitter in the
ADC and proposed
feedback DAC waveform of a CT
the use of a sine wave to generate a RZ DAC output pulse, as
illustrated in Fig. 2(c). The sinusoidal pulse and DAC sampling
clock are aligned so the DAC switches in the zero regions of
the output pulse, ensuring this RZ DAC behavior alleviates ISI.
If the sine wave is perfectly locked to the data clock, first and
second order clock jitter insensitivity are expected from the
waveform of Fig. 2(c) due to the zero value and zero slope of
the control waveform at the sampling instants.
The RF DAC concept builds on Zhang’s theoretical work
by proposing multiple oscillatory pulses per DAC output code
value as in Fig. 3(a). By using a harmonic of the DAC clock
, DAC switching
as the oscillatory waveform
can still occur in the zero regions of the oscillating waveform.
The ISI and clock jitter problems are reduced since the DAC
switches in the zero regions of the oscillating waveform as
Zhang proposed. The extra advantage of using multiple pulses
per period becomes clear when considering the impulse responses of Fig. 3 in the frequency domain, as shown in Fig. 4.
frequency domain reA conventional DAC has a
sponse which attenuates the higher order images of the input, as
in Fig. 4. Thus, the output frequency of a conventional DAC is
most often taken from within the first two Nyquist zones. The
oscillatory response of the RF DAC impulse responses creates
in the frequency
a high-energy, high-frequency lobe near
domain. This in effect accomplishes a mixing operation, mixing
the DAC impulse response to a higher frequency. Thus, RF DAC
can be thought of as a mixing DAC that combines a conventional
DAC mixer in one stage. Comparing the impulse response
magnitude of Fig. 3(a) to the conventional DAC impulse redB increase for the image near
.
sponse shows a
A high-frequency image of the input now has enough energy to
be used as the output of the DAC.
Figs. 3(b) and 4(b) demonstrate that the peak of the high-frequency energy lobe could easily be centered around any fre. Figs. 3(c) and 4(c) show a
quency simply by changing
waveform with no dc component and a wide bandwidth impulse
response. Note that the oscillatory waveform does not have to
be a perfect sinusoid to produce a high-frequency lobe. Any distortion in the waveform only affects the shape of the lobe (i.e.,
the in-band gain) and does not degrade either the SNR or SFDR
performance.
Fig. 4. Frequency domain impulse response for the waveforms of Fig. 3.
Fig. 5. Conventional transmitter architecture showing components that can be
replaced by RF DAC.
The concept of an RF DAC with an oscillating impulse response could be applied to Nyquist rate DACs,
DACs, feedADCs, binary DACs, multibit DACs, current
back DACs in
steering DACs, or resistor ladder DACs. Any oscillating DAC
can achieve a large high-frecontrol waveform with
quency lobe in the impulse response. The additional constraint
and switching in the zero regions of the control
of
waveform reduce ISI and the effects of clock jitter.
III. COMPARISON OF RF DAC TO CONVENTIONAL
DAC MIXER ARCHITECTURE
Fig. 5 shows a transmitter architecture for communications
applications. A baseband or low-IF DAC is employed with a
filter and a mixer to increase the frequency for RF transmit.
Some modern transmitter architectures include two IF frequencies and mixing stages with filters. This work proposes replacing
the DAC, filter, and mixer with RF DAC. Note that depending
on the frequency planning and implementation of RF DAC, an
RF filter may still be needed before the power amplifier. This
section is devoted to comparing the RF DAC approach to the
conventional transmitter architecture.
In the conventional DAC mixer architecture, DACs are nonreturn to zero (NRZ) as in Fig. 1, thereby making them sensitive
to ISI and DAC sampling clock jitter. Furthermore, the output
is also sensitive to noise in the chopping mixer local oscillator
(LO) sinusoid—either phase and amplitude noise if the LO is
small signal or jitter at the switching edges if it is a large signal.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004
The burden of noise and timing accuracy in the RF DAC is
placed on the oscillatory waveform. However, the accuracy requirements are no different than the phase and amplitude noise
requirements of the LO driving the mixers in Fig. 5. Sinusoidal
waveforms occupy a narrow bandwidth and thus, unlike the
square waves that typically clock DACs, they can be filtered
to reduce their wide-band noise. An analytical comparison
showing the potential improvement of this tradeoff between
sampling clock jitter and oscillator phase noise can be found in
[10].
Another advantage of the RF DAC over a DAC mixer approach is power, hardware and noise budget savings by eliminating the need for the mixers, filters and additional intermediate
frequencies in Fig. 5. Intermediate frequency stages typically require several voltage to current conversions. The RF DAC can
be thought of as combining the mixer and DAC in a single current-steering stage.
The additional hardware requirement of the RF DAC is some
type of phase locked loop to ensure that the DAC switches in
the zero or minimum regions of the oscillatory output. Even
if there is no phase-locked loop and the switching instants are
not aligned with the minimum of the oscillatory waveform, the
high-energy, high-frequency lobe is still created. However, the
DAC will be more sensitive to clock jitter and ISI, an effect
which will be demonstrated in Section V.
Fig. 6. One of eight current steering
0.18-m CMOS technology.
61 DAC elements implemented in 1.8-V
of the cascode headroom allows DACs to scale with technology
to reduced supply voltages.
Finally, a
DAC implementation means fewer, smaller
current source elements for the oscillator to drive, reducing the
oscillator power requirements. Note that this final advantage applies only to the RF DAC implementation.
architecture is that
The primary disadvantage of using a
the out-of-band quantization noise needs to be filtered. Communications applications as shown in Fig. 5 typically require
a filter anyway. The filter may have to be narrower than previously required, or extra bits added to the
DAC to widen the
bandwidth and relax constraints on the filter. Another possible
solution would be the use of a multistage (MASH) DAC architecture to cancel the out-of-band quantization noise.
IV. PROTOTYPE DESIGN
High-frequency communications applications guide the architecture selection for demonstration of the RF DAC concept.
A. Comparison of Nyquist-Rate and
Implementations
Although
DACs are currently neither deployed nor
heavily researched for high-speed applications, there are several reasons why they may be good candidates compared to
Nyquist-rate DACs. This section is devoted to clarifying the
DACs at high frequencies.
advantages of
The same in-band performance can be achieved in a
DAC
with fewer DAC elements since quantization-noise shaping is
employed. Fewer DAC elements means not only a reduction in
chip area, but also less clock and signal routing which reduces
mismatches between elements.
DACs can also
In addition to quantization noise shaping,
employ mismatch-shaping [11]. Mismatch shaping reduces
DAC element matching requirements so the current source
transistors can be smaller.
mismatch shaping has the additional benefit of shaping static timing differences and offsets
in the unit elements. Although previous work [12], [1] solves
this problem in Nyquist-rate DACs by careful layout, this may
become intractable as speeds increase.
DAC with fewer elements and reduced matching
A
requirements allows high-frequency layout techniques to be
employed. This coupled with reduced matching requirements
results in lower current source drain capacitance. This increases the high-frequency output impedance of the DAC,
eliminating the need for the traditional high-speed DAC
impedance-boosting cascode transistor [12], [13]. Elimination
B. System and Circuit Design
DAC is chosen
For the above reasons, a current-steering
to demonstrate the RF DAC concept. The design is targeted for
a half-GSM bandwidth of 17.5 MHz with a center frequency of
942.5 MHz, inband SNR of 60 dB and SFDR of 70 dBc. The
minimum number of RF DAC elements was chosen to meet
inband quantization noise requirements. Any extra elements
would mean a larger capacitance for the oscillatory control
DAC
waveform to drive. A nine-level (eight-unit element)
is built in a six-metal, 0.18- m CMOS technology with a 1.8-V
supply. With mismatch-shaping employed, only 1% element
matching is required to meet the noise specifications.
RF
One element of the current-steering, eight-element
DAC implemented in this work is shown in Fig. 6. The current
source M1 is driven by an off-chip oscillator to give the oscillatory output current waveform. The current sources are driven
from strong inversion into accumulation in an attempt to reduce
noise upconversion [14], [15]. The length of M1 was
their
chosen for better than 1% matching, and the width for a comgate
bined maximum current output of 20 mA with a peak
drive of 1 V. Switches M2 and M3 steer M1’s current depending
on the input data. These switches are designed to be in saturation to increase the output impedance. As the size of the switches
and
increase, but the capacitance
M2 and M3 increase,
at node N1 also increases. This tradeoff results in the existence
of optimal device sizes for M2 and M3 which maximize output
impedance.
Note that the traditional output impedance-boosting cascode
transistor at the drain of M1 is missing. This is possible due to
reduced capacitance at node N1 as well as a careful analysis of
LUSCHAS et al.: RADIO FREQUENCY DIGITAL-TO-ANALOG CONVERTER
1465
Fig. 7. Switch drivers for each unit element of the DAC. A dummy switch driver switches whenever the data does not. Also shown are the power and ground
plane divisions. Dummy Data allows the Vdd clk and Vdd swdr supply domains to see constant switching.
Fig. 8. Prototype system block diagram.
the output impedance requirements for frequency domain performance of a fully-differential DAC [13]. Elimination of the
cascode transistor will increase coupling of the data switching
instants to node N1. However, if the data switches as planned
when M1 is off, this coupling should not affect the output current.
The switch drivers shown in Fig. 7 receive the digital data and
drive M2 and M3 of Fig. 6. The dummy switch driver switches
whenever the data does not. This constant switching is an attempt to reduce data dependent coupling to the DAC by ensuring
that the Vdd clk and Vdd swdr power/ground planes see constant switching [1].
Conventional switch driver designs have a high crossing
point, so M2 and M3 are never simultaneously in the off state
and the voltage at node N1 in Fig. 6 is held constant [3], [5].
This work strives to minimize the total switching time to ensure
that all switching transients fit into the zero regions of the tail
current source. Thus, the switching point is at midscale, as
illustrated in Fig. 7. Conventional high-speed DAC designs also
use a reduced swing at the output of the switch drivers [3] to
minimize charge injection of the digital control signals to the
output. However, this technique reduces the switching speed of
the waveform, so a full swing switch driver output is used in
this design.
Fig. 8 shows a block diagram of the complete prototype
quantization noise shaping and mismatch
test system.
shaping are performed offline. The input data is parallelized by
a factor of four so that 32 full-swing data lines enter the chip
at 128.5 MHz. An on-chip multiplexer serializes the data to
eight lines at 514 MHz. For an output frequency of 942.5 MHz,
the oscillator frequency is chosen at 1.028 GHz and the digital
. The oscillating
input is centered around 85.6 MHz
waveform and clock are locked off-chip so the phase between
them could be adjusted to maximize testing flexibility.
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Fig. 9.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 9, SEPTEMBER 2004
Single tone output spectrum.
Fig. 11.
In-band spectrum for dual-tone inputs with f = 514 MHz, f
=
1:028 GHz.
Fig. 10. Spectrum of 942-MHz single-tone DAC output. (a) With constant
output waveform. (b) With oscillating waveform.
V. EXPERIMENTAL RESULTS
Fig. 9 compares the single-tone output spectrum for RF DAC
and a conventional DAC. The conventional DAC is configured
by setting
to a dc bias voltage instead of an oscillatory
waveform. The amplitude envelopes follow the DAC impulse
response as expected from Fig. 4(a). Similar output amplitudes
of RF DAC and the conventional DAC are observed near dc. RF
DAC shows increased output power at
MHz
due to the high-frequency, high-energy lobe. Clock feedthrough
at the input data rate of 514 MHz is observed. The other
out-of-band spurs are even harmonics due to mismatches in the
fully differential outputs at high frequencies.
Fig. 10 zooms in on the in-band part of Fig. 9. RF DAC shows
an 18.8-dB amplitude improvement over the conventional DAC.
This is slightly larger than expected in Fig. 4(a) since the ratio
of the output current amplitudes was not exactly equal to 2 as
in Fig. 3(a). SNR is also improved from 40 dB in the conventional DAC to 53 dB for RF DAC. This is due primarily to
the small amplitude in the conventional DAC output and the
noise floor being limited by other sources of thermal noise in
the system. In-band single-tone SFDR is 75 dBc for RF DAC
and 60 dBc for the conventional DAC.
Fig. 11 shows an in-band plot of a two-tone output. IMD3
is 70.8 dBc and IMD5 is 69 dBc for the 17.5-MHz band
centered at 942 MHz.
Fig. 12. SNR as a function of the phase between the data switching edge (f )
and the zero region of the current waveform. The curves shown are for increasing
values of gate bias voltage.
Fig. 12 plots SNR as a function of the relative phase between
the data switching instants
and the zero regions of the tail
current waveform. As expected, SNR degrades as the data shifts
from switching at the minimum of the oscillatory waveform to
the maximum. SNR degradation due to both clock jitter and ISI
is proportional to the height of the current output waveform at
the switching instant. Some of the SNR degradation is also due
to amplitude loss when the data switches at the peak of the current waveform. Therefore, the SNR degradation traces the sinusoidal output current waveform shape. Several curves are shown
for increasing values of gate bias voltage. For low dc values of
gate drive, the zero region is increased, giving more margin between the phase of the oscillator and data clock for best case
SNR. For the largest gate bias voltage, the current waveform
does not return completely to zero and the best-case SNR is near
48 dB. Note that the output current looks more like a distorted
pulse than a sinusoid.
Table I summarizes the performance of this RF DAC. With
the exception of in-band SNR, design targets are met. SNR is
limited by coupling of the full-swing input data onto M1 of
Fig. 6. Any noise coupled to M1 is mixed with the input data.
If the frequency of the noise is not a multiple of
in a
LUSCHAS et al.: RADIO FREQUENCY DIGITAL-TO-ANALOG CONVERTER
TABLE I
RF DAC PERFORMANCE SUMMARY
implementation, out-of-band quantization noise will be aliased
back in-band. Recommended measures to deal with this include
LVDS inputs, increased well and substrate contacts near the current source transistors, and a fully differential current source so
disturbances become common mode.
VI. CONCLUSION
The RF DAC concept of using an oscillator at a multiple of
the data clock frequency to control the DAC output waveform
has been introduced. This technique mixes the DAC impulse
response, creating a high-frequency, high-energy lobe near
. Boosted amplitude allows an image of the input to
be used as the output of the DAC. The differences between the
RF DAC approach and the traditional DAC mixer architecture
have been discussed. The use of
DACs for high-frequency
applications has been highlighted. A prototype demonstrated in
0.18- m CMOS technology achieves 75-dBc SFDR, 53-dB
SNR, and 70.8-dBc two-tone IMD3 for a 17.5-MHz band
centered at 942 MHz. Degradation of SNR when the data
switches in the peaks of the oscillatory waveform has been
shown, demonstrating the noise advantages of switching the
data in the zero regions of the oscillating waveform.
ACKNOWLEDGMENT
The technical advice of S. Decker, R. Kranz, J. Lloyd,
D. Mercer, J. Munson, B. Schafferer, B. Schofield, and
L. Singer of Analog Devices is gratefully recognized.
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[10] S. Luschas and H. S. Lee, “High speed sigma delta modulators with
reduced timing jitter sensitivity,” IEEE Trans. Circuits Syst. II, vol. 49,
pp. 712–720, Nov. 2002.
[11] T. Shui, R. Schreier, and F. Hudson, “Mismatch-shaping for a currentmode multi-bit delta-sigma DAC,” IEEE J. Solid-State Circuits, vol. 34,
pp. 331–338, Mar. 1999.
[12] A. Van den Bosch, M. Steyaert, and W. Sansen, “SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters,” in Proc. IEEE Int. Conf. Electronics, Circuits, and Systems
(ICECS), Sept. 1999, pp. 1193–1196.
[13] S. Luschas and H.-S. Lee, “Output impedance requirements for DAC’s,”
in Proc. Int. Symp. Circuits and Systems, vol. 1, May 2003, pp. 25–28.
[14] E. Klumperink et al., “Reducing MOSFET 1=f noise and power consumption by switched biasing,” IEEE J. Solid-State Circuits, vol. 35,
pp. 994–1001, July 2000.
[15] I. Bloom and Y. Nemirovsky, “1=f noise reduction of metal-oxide-semiconductor transistors by cycling from inversion to accumulation,” Appl.
Phys. Lett., vol. 58, no. 15, pp. 1664–1666, Apr. 15, 1991.
Susan Luschas (M’03) received the B.S., M.Eng.,
and Ph.D. degrees in electrical engineering from the
Massachusetts Institute of Technology, Cambridge,
in 1997, 1998, and 2003, respectively.
During the summer and fall of 1997, she was with
Lucent Technologies, Holmdel, NJ, working on the
design of A/D converters for CMOS imagers. During
the summer of 1999, she worked at Analog Devices,
Wilmington, MA, designing CMOS mixers and
LNAs. She was involved in the design of high-speed
A/D input stages at National Semiconductor Corporation, Munich, Germany, during the summer of 2000. She is currently pursuing
her interest in analog and RF circuits and systems at Atheros Communications,
Sunnyvale, CA.
Richard Schreier (M’91) received the B.A.Sc, M.S.,
and Ph.D. degrees from the University of Toronto,
Toronto, ON, Canada, in 1983, 1985, and 1991, respectively.
From 1985 to 1987, he worked for Bell-Northern
Research, Ottawa, ON, Canada, and from 1991 to
1997, he was an Assistant/Associate Professor at
Oregon State University, Corvallis. Since 1997,
he has been working for Analog Devices, Inc.,
Wilmington, MA. He is the author of the freeware
Delta-Sigma Toolbox for MATLAB and is co-editor
(with S. R. Norsworthy and G.C. Temes) of an IEEE Press book on delta-sigma
modulation.
REFERENCES
[1] W. Schofield, D. Mercer, and L. St. Onge, “A 16 b 400 MS/s DAC with
80 dBc IMD to 300 MHz and
160 dBm/Hz noise power spectral
density,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2003, pp. 1–10.
[2] B. Schafferer and R. Adams, “A 3 V CMOS 400 mW 14 b 1.4 GS/s DAC
for multi-carrier applications,” in IEEE ISSCC Dig. Tech. Papers, Feb.
2004, pp. 360–361.
[3] A. Van den Bosch et al., “A 10-bit 1-G sample/s nyquist current-steering
CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp.
315–324, Mar. 2001.
[4] J. Wikner and N. Tan, “Modeling of CMOS digital-to-analog converters
for telecommunication,” IEEE Transactions on Circuits and Systems,
vol. 46, no. 5, May 1999.
[5] D. Mercer, “A 16-b D/A converter with increased spurious free dynamic
range,” IEEE J. Solid State Circuits, vol. 29, pp. 1180–1185, Oct. 1994.
[6] H. Tao, L. Toth, and J. Khoury, “Analysis of timing jitter in bandpass
sigma-delta modulators,” IEEE Trans. Circuits Syst. II, vol. 46, pp.
991–1001, Aug. 1999.
[7] R. Adams et al., “A 113 dB SNR oversampling DAC with segmented
noise-shaped scrambling,” in IEEE ISSCC Dig. Tech. Papers, Feb. 1998,
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[8] ADC and OEIC Survey, R. Walden. (1999, July). [Online]. Available:
http://www.hrl.com/TECHLABS/micro/ADC/adc.html
[9] B. Zhang, “Delta-sigma modulators employing continuous-time circuits
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0
Hae-Seung Lee (M’85–SM’92–F’96) received the
B.S. and the M.S. degrees in electronic engineering
from Seoul National University, Seoul, Korea, in
1978 and 1980, respectively, and the Ph.D. degree
in electrical engineering from the University of
California, Berkeley, in 1984, where he developed
self-calibration techniques for A/D converters.
In 1980, he was a Member of Technical Staff in
the Department of Mechanical Engineering, Korean
Institute of Science and Technology, Seoul, where he
was involved in the development of alternative energy sources. Since 1984, he has been with the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, where he is now a Professor. Since 1985, he has acted as a Consultant to
Analog Devices, Inc., Wilmington, MA. His research interests are in the areas of
analog integrated circuits with emphasis on analog-to-digital converters, operational amplifiers, and microsensor interface circuits. He has authored or coauthored 75 journal and conference papers.
Prof. Lee was a recipient of the 1988 Presidential Young Investigators’ Award.
He has served on a number of technical program committees for various IEEE
conferences, including the Intenational Electron Devices Meeting, the International Solid-State Circuits Conference, the Custom Integrated Circuits Conference, and the IEEE Symposium on VLSI Circuits. From 1992 to 1994, he was
an associate editor for the IEEE JOURNAL OF SOLID-STATE CIRCUITS.