Systems
8-16,
N o . 5 ,
S h o p
Microprocessor & its
Buses
Internal Architecture
O
Architecture
Bus interface unit & Execution unit
Processor Model
Stack Memory
Instruction Cycle
Modes of Operation
H-o
from memory
Operation of the CPU
a
sequential
manner
(performed
in
Executes the instruction by carrying out these
actions (Performed in the Instruction decoder)
Decodes the instruction into'a series of simple
Fetches the instruction
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Microprocessor & Microcontroller R I5
E&.
Microprocessor & Its Architecturre
Sth
Microprocessor
A t the heart of microprocessor based system is the
microprocessor integrated circuit. The
microprocessor some time referred as CPU.
a
T h e microprocessor conrol memóry & I/O devices
series of connection called buses.
through
actions in
the logic control unit)
(ALU)
which
executes
Main part of CPU
Arithmetic-logic unit
instructions.
the
and sequences
Logic control unit which interprets
instructions and generates the bus control signals.
Special purpose registers such as program counter
or
(PC) that holds the address of the next instruction
data item to be fetched from memory.
General purpose registers which are used for
as
temporary storage of binary data- such
accumulator A, status register, etc.
Buses
A bus is a common group of wires that
interconnect in a computer systemn.
Buses of the system
Data Bus
Address Bus
Control Bus
BBoqk-5,
5,
Keboar
Printer
of Computer System
DRAM
Data Bus
ROM
Diagram
MRIK
RTR
Microprucessor
Block
S t a t i o n p r y & C o m p U t e rS ø r t e
Al-Myshtnq P h o t o s t a t
No.
an
8-bit data bus
80386 32-bit internal and external data buses
external data bus
80386SX 32-bit internal data bus, 16-bit
8-bit microprocessor has
The width of the data bus determines how
much data the processor can read or write in
one memory or VO cycle
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Address Bus
Control Bus
intendsto
*******
VO Write
1/O Read
When Memory Read or VO Read are active, data is inputto the
processor
When Memory Write or I/O Write are active, data is output from
the processor.
control bus signals are defined from the processor's point of
The
view.
*****************
-****
**e************
Bus Intertace Unit (SIU)
nstctin Oueue
GeteralK
6us Conlrol
AJdress
Register
nsn.ction Pontar
Segmeni
Processor Model
Control and address lines are output lines only but the data bus is
bidirectional
Service
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Bi»ck-5,
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5,
No.
S h o p
Gerera
Registsr
ALI
Oprand Register
L
unlt (EU)L
Execution
Gulshan-eqyál,Ph:4984001
Stationaryå
Read
Write
How can we tell the address is a memory address oran /O port
address
device
-**-*-
***
Memory
Memory
The address called
bus is used totheidentify the memory location or 1/0
communicate
(also
port)
processor
with
2 0 bits for the 8086 and 8088
3 2 bits for the 80386/80486 and the Pentium
36 bits for the Pentium II and III
The total number of memory locations addressable by a given
CPU is always equal to 2^x where x is the number of address
bits, regardless of the data bus.
or
8086 has a 20-bit address bus and therefore addresses all
combinations of addresses from all Os to all 1s. This
20 addresses or 1M (1 Meg) addresses
corresponds to 2
memory locations.
Pentium: 4Gbyte main memory
**** *
***:****
Internal Architecture of 8086/88
-**
*
*****
3
Bus Interface Unit (BIU)
such
as instruction
address any
one
and data
(1,048,576)
address generation
of the 220
bus for 8088 (8086).
queuing
instruction fetching, reading/writing
Perform bus operation such asinputting/outputting
data for I/O
of data operand for memory,
other functions
peripherals.
Perform
can
bi-directional data
address bus!
(16-bit)
acquisitions.
8-bit
ytes.
20-bit
adder, bus control logic,
instruction pointer,
Contain segment register,and
an instruction queue.
jump instruction,
the
flushed out (known as branch
around reduces the efficiency of the
a
not in
Use instruction queue to implement a pipelined architecture
for 8088 (8086) and
(prefetch up to 4 (6) bytes of instruction code
then store and access the codes in FIFO order).
Pipelined Architecture
should
is
a wait mode
Three conditions that will cause the EU to enter
location
w h e n the instnuction requires access to a memory
the queue
when
queue
jumping
time for
the BIU
the queue
bits
8 bits for 8088, BIU data bus width 16
of slow instructions
much
the instruction to bebeexecuted
too
instruction
penalty
program)
vs. 8088
during the execution
8086
data bus width
BIU
for 8086
more
30% slower than 8086
8088 instruction queue is four bytes instead of six
8 0 8 8 is found to be
WHY
Long instructions provide
Execution Unit (EU)
instruction.
Responsible for decoding and executing
instruction
from
a
time, decodes them,
flags
and control flags and
AH AX ALAccumulaor
Base Inde
BX TL|
DI
CI.
Daa
Ccunt
E
ICHC
SP.*
Fiags
struc
t u n Poantcr
Soune Index
Destination Indet
SLCk PUUntecr
Base Pointer
DH
DL
S
Data
Code
Extra
Stack
the
operand
instruction queue
to
generates
output end of the
status and control flags.
Contains: arithmetic logic unit (ALU),
and temporary-operand register.
general purpose registers,
the
instruction at
and data from general-purpose register
EU access
these
may test the status
During execution, EU
based on the results of execution.
update
to
pertorm
address if necessary, passes them BIU and request
the operation
read/write cycle to memory or VO, and performs
specified by the instruction on operand.
I t reads one
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No.
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EBX
EAX
Processor Model
-bit
EDI
EBP
ESP
EDX
ECX
registers
AH AX AL
1ncs
1ab! 16-bit
8-bit
32-bit
Censions
ESI
EIP
only
FFLAGS
sO38-Pentiun l
are
l6-bit
registers
General Data Registers
AX, BX, CX, DX
The l6-bit registers in this set may be splitinto two.
instructions
AX (accumulator) stores the result of many arithmetic and logic
BX (Base) stores the base (oftset) address data in memory and the base
address of a table of data referenced by the translate (XLAT) instruction.
C X stores the count for certain instructions (e g. Counter in the LOOP
instruction, the shift count for shit instructions)
it selects
64KB in the 8086-80286 and 4
a descriptor.
to
string
instructions to hold
the CS except tihis segment holds the stack.
B-16
6,
No.
8tatloay
S h o p
Pointer and Index
Registers
This set of registers usually store offset addresses of memory. IP
usually stores theoffset address of the next instruction in memory,
store the offset address of data in
memory.
SP, BP, DI and SI usually
S P , BP, DI and SI may also be used for general purposes.
in the
indirect destination address
addressing an array ofdata
SP (Stack Pointer) is used inthe PUSH and POP instructions for
operations on a LlFO (Last-ln, First-Out) stack
B P (Base Pointer) is oten used in
stack memory.
DI
(Destination Index) usually stores the
of data trom an instructioon.
(Source Index) is used when indirectly addressing source data in
be
modified with
CALL & JUMP instructions.
of next instruction to be executed in
Instruction Pointer
certain string instructions.
SI
can
16-bits (IP) in real mode and 32-bits in protected mode.
It
I t Points to the location
current code segment.
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DX holds the most significant part of the result of a l6-bit multiplication.
most
the
significant part of a dividend before division and VO port number
tor a var:able I/O instruction
Segment Registers
C S (Code Segment):
protected mode,
I n real mode, this specities the start ofa 64KB memory segment.
In
The
code segment is limited
GB in the 386 and above.
to
some
Similar to the CS except this segment holds data
DS (Data Segment)
destination data.
ES (Extra Segment):
Data segment used by
Simlar
S S (Stack Segment):
S
9
FLAGS can be set to
the occurrence of an
set to
zero on
power up.
when certain events
The other 7 bits are
4 3210
event.)
one
.Flags Register
(ie they flag
of the 16 bits in
occur
unused.
are
test the
0, S, Z, P and C flags.
15 14 13 12 11 10 9 8 7 65
A l l bits
instructions
-
in
certain string manipulation
Control Flags
(direction flag)
Conditional jump
D
-
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Conditional Flags
C (carry flag) set to 1 when the result of an addition has a carry out
(C.g. subtraction)
of the most significant byte. Other instructions can also affect C
number of ones; otherwise it is set to
zero
P (parity flag) - set to 1 if the low order byte of the result contains
an even
A
(auxiliary carry flag) set to one if there is a carry out of bit 3
during an addition or a borrow by bit 3 during subtraction.
Z (zero flag) set to 1 ifthe result is zero; Z is otherwise zero.
positive
-
set if a result is out of range (e.g. iwhen
numbers and the result appears negative)
(overflow flag)
Instruction Set
RISC (Reduced Instruction
Set Comp ers)
number of very fast executing instructions
CISC (Complex Instruction Set Computers),
family has more than 3000 instructions
adding
A small
e.g., 80x86
The list of all recognizable instructions by the instruction
decoder is called the instruction set
two
O
S(sign
flag) equal to the most significant bit ofthe result (i.e. set
to I if the result is negative)
Gulsyan-e-NGbal,
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R i A 5 ,
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determines whether amaskable interrupt is
D determines whether the string is processed frominstructions,
the lowest
address (D=0) or the highest address (D=1).
I (interrupt flag)
recognized by the microprocessor. If I=1, a maskable interrupt
is possible, otherwise the interrupt is ignored.
T (trap flag) - if T=l, a trap (eg for single stepping through a
is executed after every instruction.
program)
A
Origin and Definition of a Segment
segment is an area of memory that includes up to 64 Kbytes
64Kbytes
16
address lines
and begins on an address divisible by 16 (such an address ends
with an hex digit Oh)
8085 could address
I n the 8085, 64 K is for code. data, and stack
I n the 8086/88, 64 K is assigned to each category
Code segment
Data segment
Extra Segment
Stack Segment
Logical and Physical Addresses
Addresses within a segment can range from address 0 to address
FFFFh. This corresponds to the 64Kbyte length of the segment
15
ENT REISTEB
A n address within a segment is called an ofset or logical address
Ex. Logical address 0005h in the code segment actually corresponds
to B3FFOh +5 B3FFSh.
19.
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Example
physical
=
eddress
83DAE
FFFF = SFA1P
logical Aadress
nen
SD270
SFAIF
83DAE
7FA20
Segment Registers
aainerd Ds
S:wunet SS)
the
If OS=7FA2H and tha offset is 438E
a) Calculale
7FA20 438E
bi calculaie the lower range
7FA20+0oc0 =7FA2a
She: tho
7FA20
ci Calculatethe uppor lange of thes a seyusnt
d
TFAZ38E
FFE
If CS
=
Example
and IP
24F6h
634Ah, show
The logical address
The offset address
The physical address
and calculate
The lower range
The upper range
F F ed
Son-plpelined arehitecture
Feich
TNne
Nonpipelined vs pipelined architecture
F
FerchExecine| FerchExecne
FTF
EU
Wait
ndd
Pipelined architecture
F
Segment
Alternata
SI, Di address
EX. adcress
SP,BP
Offset
16 bit Segment Register Assignments
Default
none
CS,ES, SS
CS. ES,SS
None
The Stack
Segment
Cs
Reference
Type of
Memory
Instructlon Fetch
SS
Operatlons
ES
Stack
Strlng
Destinatlon
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The stack is used for temporary storage of information such as data
or addresses; for instance when a call is executed the 8088
automatically pushes the current value of CS and IP onto the stack.
Other registers can also be pushed
Near the end of the subroutine, pop instructions can be used to pop
values back from the stack into the corresponding registers
MS
SS:00CI
S$ SP
SS:FTTh
Given
SS
PUSH AX instruction?
Example for PUSH
010Sh
SP = 0008h
AX = 1234h
of the
ABOS= 01050 + FFFEh = 1 104h
What is the outcome
1056h.
0Gh
of Segmented
Memory
001
ATOS = 01050 +0008h 1058h
Decrement the SP by 2 and write AX into the word location
o1057
O1056h
SP
Advantages
be
loaded
and
run
sets of data. This is done
can
One program can work on several different
by reloading register DS to a new value.
Programs that reference logical addresses
anywhere in the memory: relocatable
Segmented memory introduces extra complexity in both hardware in
a
new
segment.
8086 but the softvare
in that programs are
registers.
software
can be
run on
must switoh to
in
that memory addresses require two
complexity
also require
Timited to the segment size
They
greater than 64 KB
complex as it
needed is more
Programs
Protection among segments is provided.
following
Example for PODP
What is the outcome of the
POP AX
n
POP BXX
if originally 1058h contained AABBh?
Read into the specified register from the stack and increment the
stack pointer for each POP
operation
= 000Ah
A X = 1234h SP = 0008h
A t the first POP
B X = AABBh SP
At the second POP
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to the program written for the
physical devices and circuitry of the
Important Terminologies
the
referred
Hardware is
is
computers.
Software
computer.
Firmware is the term given to programs stored in
ROMs or in other devices which
permanently keep
their stored information.
Instruction Set
The list of all recognizable instructions by the
struction decoder is called the instruction set
CISC (Complex Instruction Set Computers), e.g.,
80x86 family has more than 3000 instructions
executing instructions
RISC (Reduced Instruction Set Computers)- A
small number of very fast
Embedded Systems
toys, garage door openers, answering machines,
microprocessor to do one task and one task onlyy
An embedded system uses a microcontroller or a
Example:
B.16,
5,
Microcontrollers
A microcontroller has a CPU
in addition to a fixed amount
of RAM, ROM, I/0 ports on
one single chip; this makes
them ideal for applications in
critical
5030 Up
"
FaH_
623
Gnor
CM4
vdac Care
SHs
NL:3r
i
A Typical PC Motherboard
which cost and space are
A-MshtaqPhotnstat
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Computer8fArk-5,
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Ph:sA001
S h o p
No.
Statighary
every mouse, there is a microcontroller that performs
ABS, keyless entry, etc.
Inside
the task of finding the mouse position and sends it to the
PC.
Although microcontrollers are the preferred choice for
embedded systems, there are times that the microcontroller is
inadequate for the task
Intel, Motorola, AMD, Cyrix have also targeted the embedded
market with their general purpose microprocessors
For example, Power PC microprocessors (IBM Motorola
joint ventiure) are used in PCs and routers/switches today
Gulh Jhop tlNoon.5ary e
shan-eJoh P
4801
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Execution of a Three-Instruction program
T o understand the basic idea of how the parts of
microcomputer function together.
Program specification
1. Input a value from a key board connected to the port at
address 05H.
2. Add 7 to the value read in.
3. Output the result to a display connected to the port at
address 02H,
Input a value from port 05
Program
Add 7 to the value.
Output the result to port 02.
Memory
Contents
Binary
(Hex)
Contents
Operation
Program loaded in Memory
Address
11100100
04H
05H
E4H
07H
Add
Port 05HH
Input from
00000101
07H
00100H
00101H
00000100
00000111
00102H
00103H
Output tu
Port 02H
E6H
02H
11100110
00000001
00104H
00105H
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rie-5,
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Computer
8-15,
5,
Assembly
Instructions
Machine
04
E4
02
07
05
Code
E6
program
ADD 07H
IN 05H
OUT 02H
Modes of Operation
registers
with each segment limited to 64KB
Two new features are available to the
in the
new
and
programmer
addressing mechanism
Addition of two new segments F and G
Access to the 32 bit
Protected Mode
Each memory
Difference is
programs
segment may range from a singie byte to 4GB
feature is the ability to assign a
privilege
le vel
level carnot
(programs). Tasks of
final protected
A
mode
to individual tasks
access
lower privilege
programs or data vith a higher privilege leve
scheme, the operating system car run multip'e
Using this
ear
protection levels
The
address space is limited to 1MB using address lines A0-19, the
high address lines are inactive
The segmented memory addressing mechanism of the 8086 is retained
Real Mode
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