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Embedded Controller Design, W00
Problem Solutions
4
Solutions to Chapter 3 Problems
For the following problems, refer to the loading example and Figure 3-15.
1. A) If a 10K pull-up resistor is used, how many additional LSTTL loads can be connected?
B) How many CMOS loads could be added?
When the LSTTL driver's output is 0:
The output is assumed to be at 0.4 volts. This is max V(ol), and represents a noise margin of
0.4 volts from V(il) max of the CMOS and LSTTL loads. The CMOS gate input is sourcing
a negligible amount of leakage current--less than 1 uA. The LSTTL gate input is sourcing as
much as 360 uA (I(il) max) to the LSTTL output.
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The voltage across the 10k resistor is 4.6 volts (Vcc - V(ol) max).
Therefore the current sunk by the LSTTL output is
(4.6/10k) + 360 uA = 820 uA.
The LSTTL output is specified to sink at least 3.2 mA and maintain V(ol) max, so it can sink
an additional 3.2 - .820 = 2.38 mA.
Since each additional LSTTL input would source 360 uA, the 2.38-mA excess sink capability
of the LSTTL input represents 2.38/0.36 = 6 additional inputs.
When the LSTTL driver's output is 1:
The output is assumed to be at 3.4 volts; the min V(ih) for the CMOS device (3.0v), plus the
same 0.4 volt noise margin that applies to the TTL signals. This represents a voltage drop of
1.6 volts across the 10k resistor. By Ohm's law, that's a current flow of 160 uA. The CMOS
gate input is sinking a negligible amount of leakage current--less than 1 uA.
The LSTTL gate input is sinking 60 uA of the 160 available.
The excess source capability is 160 - 60 = 100 uA.
Th
Since each additional LSTTL input would require 60 uA, the circuit can support only one
more LSTTL input, which is more restrictive than the logic 0 case above.
Bottom Line: Only one more LSTTL input can be connected.
2. What could be done to increase the number of LSTTL loads?
Increase the available source current from the pull-up resistor by lowering the resistor's
value. For every 60 uA of additional current provided, an additional LSTTL load can be
driven high. The upper limit is then defined by the output driver's output low sink current
limit and the number of loads that must be pulled low.
(Chapter 3 Problem Solutions, continued)
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Embedded Controller Design, W00
Problem Solutions
5
For the following problem, refer to the timing example and Figure 3-15.
3. Using the same D flip-flop specified in the example, how fast could it be clocked if the /Q
output was directly connected to the D input? (Eliminating the gate from the circuit.)
There is no gate delay in the feedback network without the NAND gate. There is no
propagation delay between /Q and D, so the /Q input will fall TPCKQ (15 nS) after the falling
edge of the clock. The D input must remain low for at least TSU (10 nS) before the next
falling edge of the clock. Therefore, the period from one falling edge to the next must be >=
15 + 10 = 25 nS.
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The maximum clocking rate is 1/25 nS = 40 MHz. Note that this is lower than the flip-flop's
maximum clock rate spec.
4. Under what conditions would the addition of a pull-up or pull-down resistor increase the
fanout of a logic output?
If the pull-up (source) and pull-down (sink) capabilities of a circuit are not symmetrical, and
one of them is the limiting factor in the fanout, it is possible to add a resistor to provide
additional sink current (R to ground) or source current (R to +supply) as in the solution to
problem 2 above. This comes at the expense of the other specs, since the additional current
due flowing in the resistor must also be handled by the driving device when it's in the other
logic state.
5. What, if anything, can be done to increase fanout when it is limited by AC (capacitive)
loading?
There are several options:
Th
a) Use multiple buffers to split up the loads so that each output carries only a fraction of the
total load.
b) Change to a different output logic device or family with higher CL capacity.
c) Connect multiple outputs from the same IC only in parallel. (They must be from the
same IC in order to guarantee that they will switch at the same time. Otherwise the
outputs would be in contention for the propagation time difference from different
devices.)
d) Derate the signal timing specs in proportion to the excess CL since the heavier capacitive
loading will degrade the rise and fall time of the signal. The derating is calculated using
the available current and the excess capacitance to determine the rate of change of
voltage (slew rate) that will extend the rise and fall time for the overloaded signal. The
limit to this approach is usually due to the stress on the output when large peak currents
flow into the large load capacitance through the output, heating the device and potentially
damaging it.
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Embedded Controller Design, W00
Problem Solutions
6
6. For a 32 bit CMOS 5 volt microprocessor that has a 32 bit address bus and a separate 32 bit
data bus, and the processor has a 1 nS rise time and 0.5 nH of ground inductance on a board
made from glass epoxy material. The processor has output high and low voltages of 4.5 and
0.5 volts respectively and drives a capacitance of 100 pF on the address and data buses. How
long can the printed circuit traces be before they must be considered as transmission lines?
For determining when the trace should be treated as a transmission line, the effective
physical length of the pulse edge (l) should be between 4 and 6 times the length of the
longest PCB trace. The rise time length in inches is defined as:
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l = Tr / D where
l = length of rising or falling edge in inches (in)
Tr = rise time in picoseconds (pS)
D = delay in picoseconds per inch (pS/in), nominally 100 to 200 pS per inch in standard PCBs
The relevant parameters here are the rise time and delay, so the worst case length of the 1 nS
(=1000 pS) pulse edge is when the D is at its maximum value of 200 pS/inch:
l = Tr/D = 1000 pS / (200 pS/in) = 5 inches
The trace will behave as a transmission line when it is between1/6th and 1/4th of that
length or greater. In this case the PCB traces less than about one inch in length do
not have to be treated as a transmission line.
7. For the same processor and conditions described in problem 6, what is the worst case ground
bounce voltage that can be expected?
The magnitude of the ground bounce in this case will be:
V = L * C * (Voh-Vol) / (Tr )2 = 0.5 nH * 100 pF * (4.5 - 0.5) / (1)2 = 200 mV or 0.2 V
Assuming a trace length of one inch or less, the 1-2 pF per inch of trace capacitance is
insignificant compared to the 100 pF of load capacitance.
Th
With 32 address and 32 data lines being discharged through a single ground pin, the worst
case is when both busses cange from all ones to all zeros or vice versa. In that case the total
ground bounce on a single ground pin could result in 64 * 0.2 volts or 12.8 Volts!
This example underscores the reason why many chips must have multiple short ground leads
to keep the ground bounce within the noise margin of the logic levels.
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