KAUSHIK ROY
Edward G. Tiedemann, Jr., Distingushied Professor
Director, Center for Brain Inspired Computing (c-BRIC)
Electrical and Computer Engineering, Purdue University
West Lafayette, Indiana 47907, USA.
ADDRESS:
Office:
School of Electrical & Computer Engineering
Purdue University
West Lafayette, IN 47907-1285
765-494-2361 (off); 765-494-3371 (fax)
e-mail: kaushik@ecn.purdue.edu
URL: http://engineering.purdue.edu/NRL/index.html
RESEARCH INTERESTS:
Brain/Bio Inspired Computing, AI circuits and architecture, Low-power electronics, process variations and robust design
Neuro-mimetic devices, Spintronics, Device/Circuit/Architecture Co-design
EDUCATION:
Ph.D. (Jun. 1990)
B.Tech. (May 1983)
Electrical & Computer Engineering, University of Illinois at Urbana-Champaign
Thesis: Timing Verification and Synthesis of Robust Delay Fault Testable Circuits
Advisor: Prof. Jacob Abraham
Electronics & Electrical Engineering, Indian Institute of Technology, Kharagpur
WORK EXPERIENCE:
May 2013 – present
Jan. 2005 – May 2013
Aug. 2001 – 2005
Jul. 1997 – 2001
Sep. 1999 – Dec. 1999
Jul. 1999 – Aug. 1999
Aug. 1993 – Jun. 1997
Sep. 1997 – Dec. 1997
Jun. 1996 – Jul. 1996
Aug. 1990 – Aug. 1993
Spring 1993
1992 – 1993
1985 – 1990
Edward G. Tiedemann Distingushed Professor
Purdue University
Roscoe H. George Professor of ECE
Purdue University
Professor, School of Electrical & Computer Engineering
Purdue University
Associate Professor, School of Electrical & Computer Engineering
Purdue University
Visiting Faculty, EECS, University of California – Berkeley
Visiting Faculty, Intel Corporation, Portland, Oregon
Assistant Professor, School of Electrical & Computer Engineering
Purdue University
Visiting faculty at Intel Corporation, Portland, Oregon
Visiting faculty at Intel Corporation, Santa Clara, California
Member of Technical Staff in Semiconductor Process and Design Center
Texas Instruments, Dallas
Worked on Field Programmable Gate Arrays and on low-power electronics
Adjunct Faculty, University of Texas at Dallas
Taught Fault-Tolerant Computing
SRC (Semiconductor Research Corporation) Mentor
Responsibilities included monitoring research on VLSI testing at the University
of Texas at Austin and the University of Illinois at Urbana-Champaign.
University of Illinois, Graduate Research Assistant
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Feb . 1989 – May 1989
May 1988 - Aug. 1988
Summer Intern, Texas Instruments, Dallas
Summer Intern, Texas Instruments, Dallas
AWARDS AND HONORS:
ˆ Fellow, IEEE, since 2001.
ˆ Humboldt Research Award for Senior Scientists, 2010.
ˆ Semiconductor Research Corporation (SRC) Aristotle Award, 2015.
ˆ IEEE Charles Desoer Award from Circuits and Systems, 2011.
ˆ Distinguished Alumnus Award, Indian Institute of Technology, Kharagpur, 2011.
ˆ Fulbright-Nehru Distinguished Chair for India, 2013.
ˆ Vannevar Bush Faculty Fellow (Department of Defense), 2014-2019.
ˆ Semiconductor Research Corporation (SRC) Technical Excellence Award, 2005.
ˆ Arden Bement Research Award in 2020, most prestigious award given by the university in pure and
applied science and engineering
ˆ Purdue College of Engineering Research Excellence Award, 2008.
ˆ M.K. Gandhi Distinguished Visiting Faculty, Indian Institute of Technology. Mumbai, Jan. 2010.
ˆ Motorola Research Visionary Board Member, 2002.
ˆ Purdue University Faculty Scholar 1998.
ˆ Roscoe H. George Professor of ECE.
ˆ NSF CAREER development award, 1995.
ˆ IBM Faculty Partnership Award, 2001.
ˆ ATT/Lucent Foundation award, 1997.
ˆ IEEE Outstanding Young Author Award for paper titled, ”Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities Through Domain Wall Motion in
Ferromagnets”. Authors: A. Sengupta and K. Roy.
ˆ 2015 IEEE Circuits and Systems Society Transactions on Very Large Scale Integration Systems Best
Paper Award for your paper, ”Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based
SRAM Design”.
ˆ 2012 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) Best
Paper Award for paper titled, ”TapeCache: High Density, Energy Efficient Cache Based on Domain
Wall Memory,” August 2012.
ˆ 2013 IEEE Transactions on VLSI Systems Best Paper Award for paper titled, ”Design Paradigm
for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective.”
ˆ 2006 IEEE Transactions on VLSI Systems Best Paper Award for paper titled, A Process-Tolerant
Cache Architecture for Improved Yield in Nanoscale Technologies,” Jan. 2005.
ˆ 2006 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) Best
Paper Award for paper titled, Analysis of Super Cut-off Transistors for Ultralow Power Digital
Logic Circuits
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ˆ Low Power Design Contest Award (with C. Kim and J. Kim) for “A Low-Power Embedded SRAM
Cache with PVT-Aware Leakage Reduction and Improved Stability” in ISLPED 2005.
ˆ 2005 IEEE Circuits and Systems Society Outstanding Young Author Award (Chris Kim) for paper
titled, “Ultra-Low Power DLMS Adaptive Filter for Hearing Aid Applications” in IEEE Trans. on
VLSI Systems.
ˆ “A Novel Low-Power Scan Design Technique Using Supply Gating,” Best paper award, IEEE International Conference on Computer Design, 2004.
ˆ “Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Current,” Best
paper award, 4th IEEE Latin American Test Workshop, 2003.
ˆ “Circuit-Compatible Modeling of Carbon Nanotube FETs in the Ballistic Limit of Performance,”
Best Student Paper Award, IEEE NANO 2003.
ˆ ”On Effective IDDQ Testing of Low-Voltage CMOS Circuits Using Leakage Control Techniques,”
Best paper award, IEEE International Sympoisum on Quality of IC Design, 2000.
ˆ Technical Advisory Board, Zenasis Technologies.
ˆ ”Intrinsic leakage in low-power deep sub micron CMOS ICs,” Honorable Mention Paper Award,
International Test Conference, 1997.
ˆ Recipient of National Scholarship (Government of India) 1977-78.
ˆ Merit Scholarship (Indian Institute of Technology) 1979-83.
RESEARCH GRANTS AND CONTRACTS:
ˆ IBM Corporation (Single Investigator), “Research on Synthesis for Low Power CMOS Logic,”
$100,000, (December 1993 – November 1995), Award No. 6712385.
ˆ Advanced Research Projects Agency (Single Investigator), “Power Estimation and Synthesis for
Low Power,” $347,245, 03/21/95 – 07/20/98, Award No. F33615-95-C-1625.
ˆ National Science Foundation (CAREER Development Award), “Integrated Framework for Test Synthesis, Power Optimization, and Reliable Design of VLSI Circuits,” $90,000, 06/01/95 – 05/31/98,
Award No. 9501869-MIP.
ˆ National Science Foundation (Single Investigator), “Architectural Transformations to Achieve Low
Power Consumption in VLSI Circuits,” $10,000, 06/01/95 – 05/31/98, Award No. 9501869-MIP.
ˆ National Research Council (Senior Investigator), “Efficient Use of Narrowband Radio Channels for
Mobile Digital Communications,” PI: Michael Fitz, 1994.
ˆ Equipment grant from Intel, $10,154, October 1996, PI: KaushiK. Roy
ˆ FPGA Equipment Grant to Support EE559 and Computer Engineering Research Activities, Texas
Instruments Inc., Equipment worth $33,000, 1994.
ˆ LSI Logic, ASIX VLSI tester, KaushiK. Roy, worth $250,000, January 1996.
ˆ Intel Corporation (Single Investigator) “Differential Current Switch Logic,” Intel Corporation,
$66,000, 11/01/95 – 10/31/97, Award No. 6712575.
ˆ Intel Corporation (Single Investigator) “Multiple Threshold Voltage and Dynamic Threshold Voltage Design Techniques for in Deep Sub-Micron Bulk and SOI Technology,” $ 70,000 for 1 year
starting Dec. 1997.
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ˆ Intel Corporation (Single Investigator) “Multiple Threshold Voltage and Dynamic Threshold Voltage Design Techniques for in Deep Sub-Micron Bulk and SOI Technology,”– equipment worth $
13,768 for the project, Feb. 1998.
ˆ National Science Foundation (Single Investigator), “Ultra Low Energy Computing using Adiabatic
Switching Principle,” $45,146, 1996-1997, Award No. 9633516-MIP.
ˆ Advanced Research Projects Agency (Single Investigator), “Data Path Synthesis for Low-Power
Using Dual-Gated SOI Transistors,” $161,764, 06/01/96 – 05/31/99, Award No. DAAH04-96-10222.
ˆ IBM Corporation (Single Investigator), “Datapath Synthesis for Ultra-low Energy Portable Applications,” $ 50,000, 1996-1998.
ˆ Rockwell Corporation (Single Investigator), “Low-Power Electronics for Portable Computing and
Wireless Communications,” $50,000, 10/02/96-10/01/98.
ˆ AT&T/Lucent Technologies Special Purpose Grants in Science & Engineering (Single Investigator),
“Low-Power Design Techniques for Portable Computing and Wireless Communications,” $26,872,
1996-1998.
ˆ Office of Naval Research (Single Investigator), “Low Power Electronics for Portable Computing and
Wireless Communications,” $86,534, Award No. N00014-97-1-0324, 1997.
ˆ Lucent Technologies (Single Investigator), “Low-Power BIST,” $30,000 for one year, starting Dec.
1997.
ˆ Purdue Research Foundation (Single Investigator), “Power Dissipation and Performance Driven
Logic Optimization,” $30,600, 1994-1997.
ˆ Semiconductor Research Corporation (Single Investigator), “Ultra Low Power Digital Logic Design,” $440,000, Award No. 98-HJ-638 4 years staring September 1998.
ˆ Intel Corporation (Single Investigator) “Multiple Threshold Voltage and Dynamic Threshold Voltage Design Techniques for in Deep Sub-Micron Bulk and SOI Technology (renewal),” $332,014,
starting Dec. 1998 for three years.
ˆ National Science Foundation (Single Investigator), “Subthreshold Digital Logic,” $50,000, Award
No. CCR-9901152.
ˆ Semiconductor Research Corporation, Co-PI with Professor Cheng-Kok Koh, “On-Chip RLC Interconnect Synthesis,” $384,000, Award No. 99-TJ-689, July 1 1999 – June 30 2002.
ˆ Semiconductor Research Corporation, “Integrated Circuit Architecture Approach to Low-Power
Memory Hierarchy Design,” PI – KaushiK. Roy, Co-PI: Vijakumar and Babak Falsafi, $300,000 for
three years starting Feb. 2000.
ˆ Intel Corp., “SOI Circuit Design,” (Single Investigator), $210,000 for three years starting May 2000.
ˆ Intel Corp., “CAD for SOI Circuits,” (Single Investigator), $25,000 for one year starting May 2000.
ˆ Intel Corp., “Noise-Aware Floorplanning and Global Routing,” (Co-PI’s: C-K. Koh and K. Roy),
$165,000 for three year starting August 2000.
ˆ Semiconductor Research Corporation, “Low Power VLSI Signal Processing,“ (Single Investigator),
$35,690, 08/01/00 to 07/31/01, Award No. 6741608.
ˆ Agilent Technologies, “Leakage Power Management in Ultra High Performance Design,” (Single
Investigator), $60,000 for one year starting Dec. 2000.
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ˆ Gigascale Silicon Research Center (Uiversity of California – Berkeley) – DARPA/SRC Center,
“Design and Test of High-Speed Scaled CMOS Circuits,” $410,000 12/98 – 12/2003.
ˆ IBM Faculty Partnership Award, $80,000, 2001.
ˆ DARPA, “Mission Specific Processing,” $884,927 for three years starting June 2001.
ˆ DARPA, “Leakage Power Management in High Performance Systems,” PI: KaushiK. Roy, Co-PI:
T. Vijaykumar, $507,000 for 2.5 years starting April 2002.
ˆ National Science Foundation, “Novel testing of CMOS Circuits Using Wavelet Transforms,“ PI: K.
Roy, $160,000 for 4 years starting September 2002.
ˆ NASA Nanoelectronic Center at Purdue (URETI), Director: S. Datta, Co-PI: KaushiK. Roy,
$100,000/year + academic year support, 5 years starting December, 2002.
ˆ National Science Foundation Center for Nano Computing, Director: M. Lundstrom, Co-PI: KaushiK.
Roy, $75,000/year + academic year support, 5 years starting January 2003.
ˆ DARPA, ”Modulated Load Harmonic Reradiation for Low-Power Communication from Large Collections of Sensors,” PI: M. R. Bell, co-PIs: C. A. Bouman, J. V. Krogmeier, C. P. Rosenberg,,
K. Roy, N. Shroff, K. Webb, August 1, 2002 - July 31,2004, Contract No. MDA 972-02-1-0032,
$450,000.
ˆ Semiconductor Research Corporation, “Robust Circuits for Scaled CMOS Technologies,” PI: K.
Roy, $560,000 for period April, 2003 through December, 2007.
ˆ MARCO Center (Giga Scale Silicon System Research, University of California), “Design and Test
of Sacled CMOS Circuits,” Co-PI: KaushiK. Roy $450,000 for three years starting August 2003.
ˆ Semiconductor Research Corporation, “Tera-Scale Integration Using Carbon Nanotube Transistors,“ PI: K. Roy, Co-PI: M. Lundstrom, $40,000 for 1 year starting February, 2003.
ˆ Semiconductor Research Corporation, “System-On-Chip for Power-Aware Wireless Communications,” PI: K. Roy, $300,000 for three years starting October, 2003.
ˆ Intel Corporation, “Nano-Circuit Simulation Laboratory,” PI: K. Roy, $130,000 (October 2003).
ˆ Intel Corporation/Semiconductor Research Corporation, “Designing with Unreliable Components,”
PI: K. Roy, $60,000 for a year starting August 2004.
ˆ Motorola/Semiconductor Research Corporation, “Compact Models to Evaluate Asymmetric Double
Gate Devices,” PI: K. Roy, $25,000 for a year starting August 2004.
ˆ National Science Foundation/ Semiconductor Research Corporation, “Integrated Framework for
Reliability and Process Variation Aware Design Methodology for VLSI Circuits,” PI: M. Alam,
Co-PI: K. Roy, $470,000 for three years starting September 2004.
ˆ Gigascale Silicon Research Center (Uiversity of California – Berkeley) – MARCO Center, “Error
Resilient CMOS Circuits,” $600,000 12/2005 – 12/2009.
ˆ C2S2 (Circuits and Systems Research Center, Carnegie Mellon University), a MARCO Center,
Double-Gate MOSFET Devices and Circuits, $300,000 08/2006 08/2009.
ˆ Intel Corporation, Integrated Design and Test of Scaled CMOS Circuits, PI: Kaushik Roy, $45,000
gift, September 2006.
ˆ Texas Instruments, Ultralow Power Digital Circuits, PI: Kaushik Roy, $50,000 gift, December 2006.
ˆ Semiconductor Research Corporation, ”An Integrated BIST, Diagnosis, Self-Repair and Adaptive
Design Methodology for Highly Reliable Nano-Scale Systems,” PI: K. Roy, Start date Oct 1 2007,
$330,000 for 3 years.
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ˆ DARPA, ”Ultra-Low-Power and Low-Cost Systems Using Optimized Poly-Si Thin- Film-Transistors,”
PI: K. Roy, $200,000 for two years, 2007.
ˆ Semiconductor Research Corporation, Ultralow Power System Design Using Subthreshold Operations, PI: K. Roy, $180,000 for 3 years starting August 2007.
ˆ National Science Foundation, PI: K. Roy, co-PI: M. Thottethodi, $361,264 for 3 years starting Oct.
1, 2007. Award number CCF-0702612
ˆ Boeing, Process Adaptive Sub-Threshold Logic and Memory, PI: K. Roy, $108,000, 01/01//2008
12/22/2008.
ˆ Intel Corporation, ”Hybrid III-V/Si Devices for Enhanced Performance,” PI: K. Roy, $35,000,
December 2008.
ˆ Intel Corporation, ”High-Speed Nano-devices Simulation Cluster,” $85,000 of computers, December
2008.
ˆ NASA SBIR with RNET technologies, ”Phase I: Radiation Mitigation Methods for Reprogrammable
FPGA, Contract Number: NNX09CF29P,” K. Roy’s share: $33,000 for a year, starting February
2009.
ˆ DARPA SBIR with RNET technologies, ”Phase I: Innovative Approaches to Low Power, SubThreshold Electronic Circuits,” K. Roy’s share: $33,000 for a year, starting March 2009.
ˆ Cyberonics, Inc., PI: P. Irazoqui, Co-PIs: K. Roy, and J. Rickus, ”Core Technology Development
Plan for Seizure Detection and Mitigationfor Cyberonics Next-Generation Devices,” $ 1,200,000,
12/1/09-11/30/12.
ˆ NASA SBIR with RNET technologies, ”Phase II: Radiation Mitigation Methods for Reprogrammable
FPGA,” K. Roy’s share: $200,000 for 2 years, starting April 2010.
ˆ DARPA SBIR with RNET technologies, ”Phase I: Ultra Low Power-Rad-Hard SRAM” K. Roy’s
share: $33,000 for a year, starting April 2010.
ˆ National Science Foundation, PI: B. Jung, Co-PI: K. Roy and S. Bhunia (Case Western University)
”SHF: Medium: Collaborative Research: System Level Self Correction Using On-Chip Micro Sensor
Network and Autonomous Feedback Control,” $ 900,000, three years, starting July 2010.
ˆ Qualcomm Inc., PI: K. Roy, ”STT-MRAM Research Engagement,” $70,000, Project Period: 06/15/1006/14/11.
ˆ Qualcomm Inc., PI: K. Roy, ”STT-MRAM Research Engagement,” $55,000, gift money, 06/2010.
ˆ National Science Foundation, PI: K. Roy, Co-PI: B. Jung, ”SHF:Small: Standardized On-line Test
and Verification Architecture Using TFTs on Glass and Inductive Wireless Links,” $ 450,000, three
years, starting July 2010.
ˆ National Science Foundation, PI: A. Raghunathan, Co-PI: K. Roy, ”CSR: Small: Scalable Effort
Design: Exploiting Algorithmic Resilience for Energy Efficiency,” $ 500,000, three years, starting
July 2010.
ˆ Intel Corporation, PI: K. Roy, Co-PI: M. Lundstrom, A. Raghunathan, C. Kim, and S. Datta,
”Post-CMOS Devices and Architecture,” $ 300,000 (gift) for a year starting November 2010.
ˆ Intel Corporation, PI: K. Roy, Co-PI: M. Lundstrom, A. Raghunathan, ”Post-CMOS Devices and
Architecture,” $ 180,000 (gift) for a year starting November 2011 for one year.
ˆ Index Center/ Nano Research Initiative, PI: J. Appenzeller, Co-PI: S. Datta, K. Roy, Z. Chen, P.
Ye, ”All Spin Logic,” $ 450,000/ year for two years, starting January 2011.
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ˆ Boeing (and Dpeartment of Defense), PI: K. Roy, ”Modeling and Impact of TDDB on Mixed-Signal
Circuits,” $103,835/ year, November 2011 – December 2012.
ˆ Semiconductor Research Corporation, PI: K. Roy, ”Low-Power Reliable STT-MRAMs: MTJStacks,
Bit-Cells, and Architecture,” $300,000 for three years starting January 2012.
ˆ Intel Corporation, PI: K. Roy, Co-PI: M. Lundstrom, A. Raghunathan, ”Post-CMOS Devices and
Architecture,” $ 180,000 (gift) for a year starting October 2012 for one year.
ˆ Semiconductor Research Corporation, PI: K. Roy, ”Ultra Low Power Neuromophic/Non-Boolean
Computing with Spin Devices,” August 2013 – August 2016, $240,000.
ˆ DARPA, PI: K. Roy from Purdue side. Prime contract with USC, ”EMbedded POWER Optimized
Systems Using Near and Super-threshold Computing Fabric (EMPOWER),” DARPA Perfect program, $1,224,059 (Phase I, II, III), K. Roy share, 11/1/12-4/30/18.
ˆ Focused Center Research Proposal (DARPA/SRC/MARCO), Center for Spintronic Materials, Interfaces and Novel Architectures (C-SPIN), K. Roy, Thrust leader for Spin-Circuits and Architecture, $800,000 for 5 years, starting January 2013.
ˆ DARPA UPSIDE Program, PI: K. Roy, Prime contract with Hughes Research Laboratory, ”Revolutionary Analog-based Probabilistic Inference Devices for Unconventional Processing of Signals
for Intelligent Data Exploitation (RAPID-UPSIDE),” $1,500,000 for 3.5 years, starting April 2013.
ˆ Boeing (IRIS III DARPA program), PI: K. Roy; ”TDDB and NBTI Modeling for Scaled CMOS
Devices”, $250,000, August 2016 – March 2018.
ˆ National Science Foundation, PI: K. Roy, ”SHF:SMALL: Deep Spiking Neural Networks: Algorithms, Architecture, and Devices,” $500,000, July 2016 – July 2019.
ˆ National Science Foundation, Co-PI: K. Roy, PI: A. Raghunathan, ”CSR: Small: Quality Programmable Processing Platforms for Approximate Computing,” $482,682, August 2014 – August
2017.
ˆ Vannevar Bush Fellow (Office of Naval Research), PI: K. Roy, ”Neuromorphic Computing with
Spin-Torque Devices,” $2,697,773; for 5 years, starting October 2014.
ˆ Multi University Research Initiative (MURI via the Office of Naval Research), PI: K. Roy, ”Phase
Change Materials for Photonics”, Lead University of Pennsylvania, $850,000; for 5 years staring
August 2017.
ˆ SRC/DARPA Joint University Microelectronics Program (JUMP) Center for Brain Inspired Computing; Director and PI: Kaushik Roy; $32,000,000 for 5 years starting January 1, 2018.
ˆ Army Research Office, PI: K. Roy, ”Self-aware Cognitive Services for Distributed Coalition Environments,” $ 281,927, 1/15/2018 – 1/14/2020.
ˆ Hewlett-Packard Enterprise, PI: K. Roy, ”Training in the PUMA Architecture,” $60,000, 09/01/2018
– 08/31/2019.
ˆ Sandia National Laboratory, PI: K. Roy, ”Neural-Inspired Approaches and Implementations for
Automatic Target Recognition,” $280,000, 11/2018 – 11/2021.
ˆ Semiconductor Research Corporation, PI: A. Raychowdhury, Co-PI: K. Roy; ”EXPERT: ExplainableAI through Efficient Hardware Design in Emerging Technologies,” $375,000, 01/2020 – 12/2022.
ˆ National Science Foundation, PI: S. Gupta, Co-PI: K. Roy, ”FET: Small: Ferroelectric Transistor
based Spiking Neural Networks with Adaptive Learning for Edge AI: from Devices to Algorithms,”
$499,998, 06/03/2020 – 06/02/2023.
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PROFESSIONAL SOCIETY ACTIVITIES:
ˆ Guest Editor, IEEE Design and Test of Computers, special issue on Low-Power VLSI Design,
Winter 1994.
ˆ Guest Editor, IEEE Transactions on VLSI Systems, special issue on Low-Power Design, June 2000.
ˆ Guest Editor, IEE Proceedings: Computers and Digital Techniques, Special issue on “Low-power
systems-on-chip,” July 2002.
ˆ Guest Editor, IEEE Transactions on Circuits and Systems, Special issue on “Nano-electronic circuits and systems,” November 2007.
ˆ Guest Editor, IEEE Journal of Emerging and Selected Topics in Circuits and Systems, Special issue
on ”Advances in Design of Energy-Efficient Circuits and Systems,” June 2011.
ˆ Guest Editor, IEEE Sensors Journal, Special issue on ”Low Energy Systems”, to appear in summer
2011.
ˆ Guest Editor, IEEE Journal on Emerging and Selected Topics in Circuits, Special issue on ”Special
Issue on Computing in Emerging Technologies,” late 2015.
ˆ Editor, IEEE Transactions on Electron Devices, 2011 – 2014.
ˆ Associate Editor, IEEE Transactions on Circuits and Systems – I, August 1997- July 1999.
ˆ Associate Editor, IEEE Transactions on VLSI Systems, 1999 – 2001.
ˆ Associate Editor, IEEE Design and Test of Computers, 1995 – present.
ˆ Associate Editor, IEEE Signal Processing Letters, 2002 – 2003.
ˆ Associate Editor, IEEE Transactions on Circuits and Systems I, 2006 present.
ˆ Executive Committee Member Design Community Chair, IEEE/ACM Design Automation Conference, 2006-2008.
ˆ Executive Committee Member – IEEE/ACM International Symposium on Low Power Electronics
and Design, 2006-present.
ˆ Technical Program Chair, ACM/IEEE International Symposium on Low Power Electronics and
Design, August 2004.
ˆ Technical Program Chair, International Symposium on On-line Testing, 2005.
ˆ General Chair, ACM/IEEE International Symposium on Low Power Electronics and Design, August 2005.
ˆ Technical Program Chair, IEEE VLSI Design Conference, January 2005.
ˆ Program Chair, IEEE Great Lakes Symposium on VLSI, March 2000.
ˆ General Chair, IEEE Great Lakes Symposium on VLSI, March 2001.
ˆ IEEE Students Counselor, Purdue University, 1995 – 1997.
ˆ Publicity Chair, 12th IEEE VLSI Test Symposium, 1994.
ˆ Finance Chair, 13th IEEE VLSI Test Symposium, 1995.
ˆ Finance Chair, 14th IEEE VLSI Test Symposium, 1996.
ˆ Steering/Advisory Committee, IEEE 1st International Symp. on Quality of Electronic Design,
2000, 2001, 2002 & 2003.
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ˆ Program Committee Member, IEEE International Conference on Computer Design, 1995-1996.
ˆ Program Committee Member, IEEE VLSI Test Symposium, 1994-1997, 2004, 2005.
ˆ Program Committee Member, IEEE VLSI Conference, 1997-1999, 2001-2005.
ˆ Program Committee Member, IEEE Great Lakes Symp. on VLSI, 1999, 2000, 2001, 2002, 2003.
ˆ Program Committee Member, ACM/IEEE International Conference on Computer-Aided Design,
ICCAD, 1997, 1998, & 1999.
ˆ Program Committee Member, ACM International Conference on Low Power Electronics and Design, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005.
ˆ Program Committee Member, 1999 Power and Timing Optimization Workshop (PATMOS).
ˆ Program Committee Member, 1999 Microelectronic Education Conference, Arlington, VA.
ˆ Program Committee Member, IEEE International Symposium On-line Testing, 2000 – present.
ˆ Program Committee, 2000 Workshop on “Compilers and Operating Systems for Low Power,“ held
in conjunction with International Conference on Parallel Architectures and Compilation Techniques,
2000.
ˆ Program Committee, 2001 IEEE Computer Society International Conference on Microelectronic
Systems Education.
ˆ Program Committee, DATE (Design and Test in Europe) 2001, 2002, 2003, 2004, 2005.
ˆ Program Committee, International Symposium on Circuits and Systems, 2002, 2003.
ˆ Program Committee, ACM/IEEE Design Automation Conference, 2002, 2003, 2004.
ˆ Program Committee, IEEE VLSI Circuit Symposium, 2003, 2004, 2005.
ˆ Program Committee, SPIE’s First International Symposium on Microtechnologies for the New Millennium 2003, 2005, Maspalomas, Gran Canaria, Spain.
ˆ Member of IEEE, ACM, and Phi Kappa Phi
INVITED LECTURES AND TUTORIALS AND PLENARY/KEYNOTES:
Keynotes/Plenary/Forum Talks
ˆ “Low Power IC Design,” Keynote Talk, Low Power VLSI kick-off meeting for German NSF, Nov.
5, 1999.
ˆ “Deep-Submicron Leakage: Future Trends and Possible Solutions,” Keynote talk, Low Leakage
Conference, Texas Instruments, October 24, 2001.
ˆ “Design and Test Considerations for Scaled Technologies,” Keynote talk, IEEE Latin American Test
Workshop, 2004.
ˆ ”Integration of Design and Test in the Nano-Scale Era: Wishful Thinking or Reality?” Keynote
Talk , IEEE Latin American Test Workshop, March 2009.
ˆ ”Technology Scaling and Challenges for Ultralow Voltage Design,” Invited Presentation at 2009
International Solid State Circuits Conference (ISSCC), Low Voltage Forum, February 8, 2009, San
Francisco, California.
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ˆ ”Ultra-Dynamic Voltage Scaling: Power Dissipation, Error Resiliency, and Yield”, Keynote talk,
ST Microelectronics Conference, Noida, India, February 3, 2010.
ˆ ”Emerging Technologies: Prospects and Perspective,” Keynote talk, 2011 IEEE VLSI Conference,
Chennai, India, January 2011.
ˆ ”Computing with Spin as a State Variable,” International Symposium on Integrated Circuits (Singapore, December, 2011)
ˆ ”Spin as State Variable for Computation: Prospects and Perspectives,” ACM/IEEE International
Conference on Low Power Electronics and Design,” August 1, 2012.
ˆ ”Spin as State Variable for Computation: Prospects and Perspective,” International Conference on
Emerging Electronics, December 15-17, 2012, Mumbai, India.
ˆ ”Approximate Computing for Energy-efficient Error-resilient Multimedia Systems,” IEEE Design
and Diagnostic of Electronic Circuits and Systems (DDECS), April 2013.
ˆ ”Approximate Computing for Energy-efficient Error-resilient Multimedia Systems,” IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechlogy Systems, October 2, 2013.
ˆ ”Beyond Charge Based Computing,” IEEE Asia and South Pacific Design Automation Conference
(ASP-DAC), January 2014.
ˆ ”Beyond Charge Based Computing,” SLIP (System Level Interconnect Prediction), June 2016,
Austin, Texas.
ˆ ”Approximate Computing for Energy-efficient Error-resilient Multimedia Systems,” Embedded Systems Week, Pittsburgh, Oct. 2-7, 2016.
ˆ ”Brain-Inspired Computing Enabled By Spin Devices: Prospects and Perspectives,” IEEE/ACM
Workshop on Variability Modeling and Characterization, Austin, Nov. 10, 2016.
ˆ ”Approximate Computing for Energy-Effcient Multi-media Systems,” 2017 IEEE International
Workshop on Signal Processing Systems, October 3-5, Lorient, France.
ˆ ”Re-engineering Computing with Neuro-Inspired Learning,” 32nd International Conference on VLSI
Design, New Delhi, India, January 9, 2019.
ˆ ”Re-engineering computing with neuro-inspired learning: devices, circuits, and systems,” Keynote
Talk at IEEE AI Circuits and Systems (AICAS), Hsinchu, Taiwan, March 18, 2019.
ˆ ”Neural Computing: Algorithms, Approximation, and Devices,” Fourth Approximate Computing
Workshop, Florence, Italy, March 2019.
ˆ ”Cognitive Computing: Design, Verification and Security Challenges,” Invited Talk at European
Test Symposium, Baden, Germany, May 28, 2019.
ˆ ”Stochastic & Neuromorphic Computing with Magnetic Tunnel Junctions: Prospects and Perspectives,” 15th IEEE / ACM International Symposium on Nanoscale Architectures, Qingdao, China,
July 2019.
ˆ ”Re-engineering computing for Spike based Learning; Algorithms, Circuits, and Devices,” 2019
IEEE Albany Nanotechnology Symposium (ANS): Materials and Processing Innovation for Future
AI Applications, November 12, 2019.
ˆ ”Re-engineering computing for Spike based Learning; Algorithms, Circuits, and Devices,” International Conference on Electronics, Information, and Communication (ICEIC), January 21, 2020.
ˆ ”Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems,” International Symposium on Quality of Electronic Design (ISQED), March 2020.
10
ˆ ”Resistive Crossbars As Matrix-Vector Multiplication Engine For Machine Learning Applications:
Opportunities And Challenges,” 3rd IEEE International Symposium on Integrated Circuits and
Systems, August 2020.
ˆ ”In-Memory Computing based Machine Learning Accelerators: Opportunities and Challenges,”
2021 NSF Workshop on Processing-In-Memory Technology (PIMT), September 2020.
ˆ ”Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems,” 26th
Asia and South Pacific Design Automation Conference (ASP-DAC) , January 2021.
Invited Talks and Invited Tutorials
ˆ Invited to present lecture on “Power Analysis and Design at System Level: Notebook Computers”
and “Software Power Optimization,” at the NATO Advanced Studies Institute on “Low Power
Design in Deep Submicron Electronics,” (Lucca, Italy), August 20-30 1996.
ˆ “Channel Architecture Synthesis for Row-Based FPGAs,” in Advanced Routing of Electronic Modules, University of Maryland, CALCE Electronic Packaging Research Center, Sept. 1995.
ˆ “Low-Power Electronics,” Georgia Institute of Technology, April 1995.
ˆ “Power Estimation and Synthesis for Low-Power,” Computer Science Colloquium at Purdue University, March 1994.
ˆ One day tutorial on “Low-Power IC Design,” ACM Design Automation Conference (Anaheim, California), June 1997, with Dr. Brock Barton (TI) and Prof. Sayfe Kiaei (Oregon State University).
ˆ Educational session on “Low-Power IC Design,” IEEE Custom Integrated Circuits Conference
(Santa Clara, California), May 1997.
ˆ Invited to be a panel member to discuss “Future Needs and Directions in CAD,” at the IEEE Intl.
Symp. on Circuits and Systems (Atlanta, Georgia), May 15, 1996.
ˆ Invited to be a panel member to discuss “Low Voltage Design,” IEEE International Conference on
Computer Design (ICCD) (Austin, Texas), October 7-9, 1996.
ˆ One day tutorial on “Architecture and CAD Issues in FPGA’s,” International Conference on VLSI
Design (New Delhi, India), January 1995, with Mahesh Mehendale (Texas Instruments).
ˆ One day tutorial on “Low Power VLSI Design,” International Conference on VLSI Design (Bangalore, India), January 1996, with Rabindra K. Roy (NEC Research).
ˆ Tutorial on “Low-Power Design,” European Design and Test Conference (Paris, France), March
1996.
ˆ Tutorial on “Low-Power Design,” IEEE International Symposium on Circuits and Systems (Atlanta,
Georgia), May 1996, with Rabindra K. Roy (NEC Research).
ˆ Tutorial on “Low-Power Design,” IEEE ASIC Conference (Rochester, New York), September 23,
1996, with Rabindra K. Roy (NEC Research).
ˆ Tutorial on “Low-Power Design,” IEEE Intl. Conf. on Computer Design, (Austin, Texas), October
1996, with Rabindra K. Roy (NEC Research).
ˆ “Design of Low-Power High-Performance Circuits,” 1996 Annual Workshop on VLSI Clearwater,
Florida.
ˆ Tutorial on “Low-Power Design,” IEEE Intl. Conf. on Electronics, Circuits, and Systems (Rhodes,
Greece), October 13-16, 1996.
11
ˆ Tutorial on “Design of Low-Power Digital and Analog Systems,” IEEE VLSI Conference (Hyderabad, India), Jan. 1997, with R. Harjani (University of Minnesota) and R. Roy (NEC Research).
ˆ Tutorial on “Low Power Design of Digital CMOS LSI,” 1997 Asia & South Pacific Design Automation Conference - ASP-DAC (Chiba, Japan), Jan. 28, 1997.
ˆ Invited to present a one day course on “Low Power Design,” at Ecole Poly de Montreal (Montreal,
Canada), February 14, 1997.
ˆ Invited to present a one day course on “Low Power Design,” at Kodak, (Rochester, New York),
February 7, 1997.
ˆ Visiting faculty, Sep. 1997, Lulea University of Technology, Sweden.
ˆ Tutorial on “Low Power IC Design,” 7th International Symposium on IC Technology, Systems &
Applications (Singapore, Sep. 1997).
ˆ “Design of Low-Power Circuits,” Ericsson, Lund, Sweden, Sept. 19, 1997.
ˆ Tutorial on “Low Power IC Design,” 5th Internal Conference on VLSI and CAD (Seoul, Korea,
Oct. 1997)
ˆ “Programmable DSP,” IEEE VLSI Conference, Chennai, India, Jan. 1998.
ˆ “Low-Power VLSI: Design, Technology, and CAD,” 1998 Asia & South Pacific Design Automation
Conference - ASP-DAC, (Yokohama, Japan, Feb. 1998).
ˆ “Low-Power Circuit Techniques,” Invited tutorial at IEEE Custom Integrated Circuits Conference,
May 1998.
ˆ “Low-Power System Design,” IEEE VLSI Design, Goa, India, with A. Raghunathan (NEC) and S.
Dey (University of California, San Diego).
ˆ “VLSI Signal Processing using FPGA’s,” IEEE VLSI Design, Goa, India, with Sudip Nag (Xilinx
Corporation).
ˆ “Design and Optimization for Low-Leakage with Multiple Threshold CMOS,” Invited talk at International Workshop on Power and Timing Modeling, Optimization and Simulation, Lyngby, Denmark, October 7, 1998.
ˆ “Low Energy Computing for Portable and Wireless Applications,” Invited Talk at NORCHIP Conference & Ericsson, Lund, Sweden, Nov. 10, 1998.
ˆ “Low Power IC Design,” Two day short course at Lund University, Lund, Sweden, Nov. 11-12,
1998.
ˆ “Low Power CMOS Digital Design,” 8th International Symposium on Integrated Circuits, Devices,
and Systems, Sep. 1999, Singapore.
ˆ “Low Power VLSI Signal Processing,” Computer Science Department, University of Hamburg,
Germany, Nov. 6, 1999.
ˆ “Low Power VLSI Signal Processing,“ IEEE VLSI Conference, Jan. 2000, Calcutta, India.
ˆ “Low Voltage CMOS,“ invited talk at IBM T. J. Watson Research.
ˆ “System Level Low-Power Design,” IEEE/ACM Design Automation Conference, tutorial presentation, June 2000.
ˆ “Low Voltage CMOS Design,” IEEE International Symposium on Circuits and Systems, tutorial
presentation, May 6, 2001, Sydney.
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ˆ “Low Power Design Techniques,” ACM Design Automation Summer School, short course, May 21,
2001, Hyanisport.
ˆ “Low Voltage CMOS Design,” International Symposium on Integrated Circuits, Devices, and Systems, invited tutorial, September 5, 2001, Singapore.
ˆ “Design and Test of Low Voltage CMOS Circuits,” IEEE International Test Conference, full day
tutorial, Baltimore, October 28, 2001.
ˆ “Low Voltage CMOS Design and Test,” Design and Test in Europe, Tutorial presentation, Munich,
March 2002.
ˆ “Leakage Tolerant CMOS Design,” IEEE Custom Integrated Circuits Conference, Invited tutorial
presentation, Orlando, May 2002.
ˆ “Leakage Tolerant CMOS Design,” VLSI Circuits Symposium, Tutorial presentation, June 2002.
ˆ “ Low-Power Design,“ Invited short course presentation in ACM organized short course in Latin
America, November 2002, Porto Alegre, Brazil.
ˆ “Low-Power CMOS Design,“ IEEE VLSI Design Conference, Tuorial Presentation, January 2003.
ˆ “Leakage Tolerant Design,” IEEE International Symposium on Circuits and Systems, Tutorial Presentation, May 2003.
ˆ “Design of Scaled CMOS Circuits for Low-Leakage,” IEEE Custom Integrated Circuits Conference,
San Jose, September 2003.
ˆ “Design of Scaled CMOS Circuits for Low-Leakage,” IEEE SOC Conference, Portland, September
2003.
ˆ “Design of Nano-scale CMOS Circuits,” Full day tutorial, ISIC-2004, September, 2004.
ˆ “Design of Nano-scale CMOS Circuits,” Short course in Brazil (Porto de Gahlinas), Sponsored by
the Brazilian National Science Foundation (cNPQ), Catholic University, Porto Allegre, 2004.
ˆ “Design Considerations for the Nano-Scale Regime: Device, Circuit, Architecture Perspective,”
ECE Colloqium, University of Minnesota, February 2005.
ˆ “Design Considerations for the Nano-Scale Regime: Device, Circuit, Architecture Perspective,” invited lecture in Austin Conference on Energy Efficient Design (ACEED), sposored by IBM, February
2005.
ˆ “Design Considerations for the Nano-Scale Regime: Device, Circuit, Architecture Perspective,” half
day workshop on Circuits and Systems, University of California - Irvine, April 2005.
ˆ ”Low-Power System Design,” nVidia, February 2006.
ˆ ”Low-Power Design of Scaled CMOS Circuits,” ECE, Distinguished lecture at the University of
Maryland, 2006.
ˆ ”Low-Power Design of Scaled CMOS Circuits,” ECE, Distinguished lecture at the University of
Southern California, 2006.
ˆ ”Low-Power Design of Scaled CMOS Circuits,” ECE, Distinguished lecture at UT-Austin, 2006.
ˆ ”Low-Leakage Electronic System Design,” 7-day short course at Texas Instruments, Bangalore.
ˆ ”Design of Nano-Scale CMOS: From devices to Circuits,” Invited lecture at Intel, Haifa, July 2006.
ˆ ”Design of Nano-Scale CMOS: From devices to Circuits,” Invited lecture at the PowerWall Forum,
Intel, Hillsboro, August 2006.
13
ˆ ”Process Tolerant Design of Nano-scale CMOS Circuits,” Invited lecture, ECE, Carnegie Mellon
University, October 2006.
ˆ ”Process Variation Tolerant System design”, Invited lecture at Intel PowerWall Forum, 2007.
ˆ ”Low-Power Process-Tolerant System design in the Nano-Scale Era,” IBM TJ Watson Experts
Workshop, November 2007.
ˆ ”Low-Power design under Parameter Variations,” International Symposium on Low Power Electronics and Design,”Embedded Tutorial, August, 2008, Bangalore, India.
ˆ ”Low-Power and variation Tolerant Electronics,” Kenote Presentation, 6th IEEE East-West Design
and Test Symposium (EWDTS), October 2009, Lviv, Ukraine.
ˆ ”Ultra Low Voltage CMOS,” Invited Presentation, 2008 VLSI SoC Conference, October 2009,
Rhodes, Greece.
ˆ ”Device/Circuit Interactions at the 22nm Technology Node,” Tutorial Presentation at 2008 IEEE
Electron Devices Meeting (IEDM), December 2008, San Francisco, California.
ˆ ”Process Variations & Process -Adaptive Design for the Nano-meter Regime,” 2009 Asia & South
Pacific Design Automation Conference Design Forum, January 2009.
ˆ ”‘Robust SRAMs in sub-45nm Technology,” ISQED Tutorial, March 2009.
ˆ ”Process Adaptive Design,” & ”‘Ultralow Power Design,” University of Catalunya – Barcelona,
Inivited lectures and interactions, June 2009.
ˆ ”Low-Power SOC Design: State of the Art and Directions,” Tutorial Presentation, ACM Design
Automation Conference, July 27, 2009.
ˆ ”Design of CMOS Circuits in the Nano-scale Regime,” IEEE TTTC organized Summer school
presentation, Florianapolis, Brazil, May 7-9, 2010.
ˆ ”New Design Paradigms for Low-Power Systems,” SRC/ATIC/NSF Forum on Minimum Energy
Electronic Systems (MEES 2020), Invited presentation, May 23-24, 2010.
ˆ ”Integrated Systems with Heterogeneous Devices,” 3D System Integration Workshop, Georgia Tech.,
Atlanta, Invited presentation, June 14, 2010.
ˆ ”Towards Zero Test Cost,” Intel Forum on Test and Verification of IC’s, Invited Talk, Santa Clara,
California, November 2010.
ˆ ”Error Resilient System Design,” Tutorial Talk at the 2011 IEEE VLSI Conference, Chennai, India,
January 2011.
ˆ ”Brain-Inspired Computing with Spin-Torque Devices,” Nano Saclay Nanoelectronic Workshop,
Paris, December 10-13, 2013.
ˆ ”Spin Transfer Torque Devices for Boolean and Non-Boolean Computing,” invited talk at IEEE
S3S Conference, San Francisco, October 8 2014.
ˆ ”Spin as State Variable for Computation: Prospects and Perspectives” ECE Colloquium speaker,
Cornell University, November 3, 2014.
ˆ ”Computing with Spintronics: From Devices to Architecture,” tutorial presentation at the IEEE
VLSI Conference, Bangalore, India, January 2015.
ˆ ”Efficient Neural Computing using Cellular Array of Magneto-Metallic Neurons, ITRS Emerging
Research Device (ERD) Meeting: Bridging the Research Gap between Emerging Architectures and
Devices, February 26-27, 2015, Stanford University, California.
14
ˆ ”Efficient Neural Computing using Cellular Array of Magneto-Metallic Neurons and Synapses,”
invited presentation at The 2nd International Symposium on Brainware LSI, March 2-3, 2015,
Tohoku University, Japan.
ˆ ”Sub-10nm Technology Nodes: Design and Test Challenges,” invited presentation at IEEE Latin
American Test Symposium, Puerto Vallarta, Mexico, March 2015.
ˆ ”Spin as State Variable for Computation: Prospects and Perspectives”, Invited lecture atSamsung
MRAM Forum, Seoul, Korea, October 26, 2016.
ˆ ”EMERGING ARCHITECTURES: WHICH ONE WOULD YOU BET ON?” Design automation
Conference, Panelist, June 2017.
ˆ ”Re-Engineering Computing For Next Generation Autonomous Intelligent Systems,” Invited Presentation at Design Automation Conference, June 2017.
ˆ ”Re-Engineering Computing For Next Generation Autonomous Intelligent Systems,” Invited Talk
at the Winter Course on Computational Brain Research at IIT Madras, Chennai, India, January 7,
2019.
ˆ ”Energy-Effciency Through Spiking neural Networks,” Invited Talk at the Winter Course on Computational Brain Research at IIT Madras, Chennai, India, January 6, 2020.
OTHER ACTIVITIES:
ˆ IEEE Students Advisor, Purdue University, 1995 – 1997.
ˆ Organized the IEEE student paper contest for undergraduates, April 1995 (sponsored by Sprint).
ˆ Organized the IEEE student paper contest for undergraduates, April 1996 (sponsored by Sprint).
ˆ Organized the IEEE student paper contest for undergraduates, April 1997 (sponsored by Sprint).
ˆ Vice-General Chair, Purdue University ECE Industrial Affiliates Workshop, 1998.
ˆ General Chair, Purdue University ECE Industrial Affiliates Workshop, 1999.
ADMINISTRATIVE SERVICES TO UNIVERSITY:
ˆ VLSI and Circuit Design area chair, 1994 – 2001; 2007-present.
ˆ Graduate Admissions Committee, 1998 and 1999.
ˆ Computer Engineering area committee, member, 1993-present.
ˆ Computer Engineering Chaired Professor Search Committee, 1996.
ˆ QE (Qualifying Exam.) Committee, 1996-1997.
ˆ IEEE Student Branch Advisor, 1995 – 1997.
ˆ Faculty grievances committee member, 1995 & 1996.
ˆ Dean’s Research Advisory Committee, 1997.
ˆ Awards Committee, 2002-2003.
ˆ Space Management Comittee, 2003.
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TEACHING EXPERIENCE:
1. Taught the following courses at Purdue University:
ˆ MOS VLSI Design (EE559)
ˆ VLSI Testing and Verification (EE695K)
ˆ Computer Architecture (EE 565)
2. Developed VLSI Testing and Verification course (EE695K) for the first time. Now it has a permanent number EE 688.
3. Developed an Advanced VLSI course (EE695KR) with Professor Koh. Course was taught in Spring
2000.
4. Taught the following course at University of Texas at Dallas (Adjunct Faculty):
ˆ Fault-Tolerant Computing (Spring ’93)
GRADUATE STUDENT SUPERVISION:
Ph.D. Theses Supervised:
1. Tan-Li Chou, Accurate Power Estimation of CMOS Digital Circuits And Its Applications to LowPower Digital Logic Synthesis, Sep. 1996. TSMC (Taiwan Semiconductor Manufacturing Corporation), Hsinchu, Taiwan.
2. Yibin Ye, Design and Synthesis of Adiabatic Switching Circuits, Aug. 1997. Intel Corp., Hillsboro,
Oregon.
3. Chuan-Yu Wang, Estimation of Maximum Power for CMOS Digital Circuits, Aug. 1997. Synopsys
Corp., Mountain View, California.
4. Mark Johnson, Design Optimizations to Facilitate Rduction of Supply Voltage and Threshold Voltage in CMOS Logic, Jun. 1998. Lab Manager for Digital and Systems Laboratories at Purdue
University, Indiana.
5. Khurram Muhammad, Algorithmic and Architectural Techniques for Low Power Digital Signal Processing, Mar. 1999. Texas Instruments, Dallas.
6. Zhanping Chen, Accurate Power Estimation in Low Voltage CMOS with Application to Circuit
Design and Testing, Mar. 1999. Intel Corp., Hillsboro, Oregon.
7. Dinesh Somasekhar, Power and Dynamic Noise Consideration in High Performance CMOS VLSI,
Jul. 1999. Intel Corp., Hillsboro, Oregon.
8. Xiaodong Zhang, Low Power BIST, Oct. 1999. Synopsys, Mountain View, California.
9. Ali Keshavarzi, Testing Solutions for Intrinsically Leaky CMOS Integrated Circuits, Aug. 2000.
Consultant and Ajunct faculty at Stanford University.
10. Liqiong Wei, Design and Optimization of Multiple Threshold CMOS for Low Power and High Performance Applications, Nov. 1999. Intel Corp., Hillsboro, Oregon.
11. Hendrawan Soeleman, Ultra Low Power Digital Sub-threshold Logic, August 2000. Sun Microsystems, Mountain View, California.
16
12. Rongtian Zhang, Low-Power High-Performance SOI Circuit Design, July 2001. Qualcomm, San
Diego, California.
13. Shiyou Zhao, Power Supply Noise Analysis for Deep Submicron VLSI Circuits, August 2001. Micron, Idaho. Co-advisor: C. Koh.
14. Yonghee Im, Design of Robust CMOS Circuits for Scaled Technologies, December 2002. Samsung,
Korea.
15. Lih-Yih Chiou, Synthesis of Application-Specific Multi-Mode Systems for Low-Power Applications,
May 2003. Assistant Professor,National Cheng Kung University, Tainan, Taiwan.
16. Naran Sirisantana, High-Performance Low-Power CMOS Circuits Using Multiple Channel Length
and Multiple Oxide Thickness , December 2003. Intel Corporation.
17. Seung-Hoon Choi, Analysis and Design of CMOS VLSI Considering Uncertainties in Circuit Parameters, December 2003. Intel Corporation.
18. Jae-Joon Kim, Circuit Design for Silicon-On-Insulator (SOI) CMOS Technologies, May 2004. Professor at Pohang University of Science and Technology (POSTECH), Pohang, Korea
19. Cassondra Crotty Neau, Exploring Device and Circuit Architecture for Scaled Technologies, August
2004.
20. Chris Hyung-Il Kim, Design of High Performance, Low Power VLSI Circuits for Scaled Technologies, August 2004. Professor, University of Minnesota, Minneapolis.
21. Hai Li, Low Power Design Techniques at Architectural Level, August 200., Professor, Duke University, Durham, North Carolina.
22. Woopyo Jeong, Robust and Higly Efficient Datapath Design in Scaled CMOS Technologies, December 2005. SK Hynix, Korea.
23. Dongku Kang, Low-Power and Layout-Aware Data-Path Synthesis for Nanometer Technologies,
December 2005. Samsung, Korea.
24. Hunsoo Choo, Low Power Methodology for Digital Signal Processing and Multimedia Applications,
May 2005. Samsung, Texas.
25. Yongtao Wang, Algorithm and Architectural Low-Power Techniques for Digital Signal Processing
and Wireless Communication Applications, August 2005. Texas Instruments, Dallas, Texas.
26. Yiran Chen, Design Techniques for Power-Efficiency and Robustness in Scaled High-Performance
Systems, August 2005. Professor, Duke University. Co-advisor: C. Koh
27. Hamid Mahmoodi, Low Power, Robust, and High Performance Circuit Design in Nano-Scale CMOS
August 2005. Professor, San Francisco State University, San Francisco, California.
28. Swarup Bhunia, Power and Yield-Aware Design and Test of Nano-Scale CMOS Circuits, August
2005. Endowed Chair Professor, University of Florida, Gainesville, Florida.
29. Amit Agarwal, Process Variation Aware High Performance and Low Power VLSI System Design
in Nano-Scale Regime, September 2005. Circuits Research Laboratory, Intel, Hillsboro, Oregon.
30. Mark M Budnik, A Distributed Power delivery and Decoupling Network Minimizing Ohmic Loss
and Supply Voltage Variation in Silicon Nanoscale Technologies, May 2006. Professor, Valparaiso
University, Valpariso, Indiana.
31. Jongsun Park, Low Complexity Digital Signal Processing System Design Techniques, September
2005. Professor, Korea University.
17
32. Hari Ananthanarayanan, Technology and Circuit Design in Nanoscale Single- and Multiple-Gate
Silicon CMOS, September 2006. Qualcomm, San Diego.
33. Saibal Mukhopadhyay, Design Methodologies for Memories in Scaled Technologies, August 2006.
Professor, ECE, Georgia Institute of Technology starting September 2007.
34. Animesh Datta, Process-Tolerant CMOS Circuit and System Design, January 2007. Qualcomm,
San Diego.
35. Qikai Chen, Low Power and Robust Memory Design: Device, Circuit, and Microarchitecture Perspective, May 2007. Apple, Santa Clara.
36. Tamer Cakici, Exploiting Independent Gate Technology in Multiple-Gate Silicon CMOS Circuit
Design, May 2007. Texas Instruments, Dallas.
37. Aditya Bansal, Modeling and Optimization of Multiple-Gate FETs for Low-Power and Robust Circuit Design, August 2007. IBM TJ Watson Research, Yorktown Heights, New York.
38. Arijit Raychowdhury, Design of High Performance and Low Power Digital Circuits with Carbon
Nanotube Based FETs, September 2007, Professor, Georgia Institute of Technology, Atlanta, Georgia. Choras Foundation Doctoral Dissertation Award.
39. Kunhyuk Kang, Analysis and Design of Nano-Scale VLSI Circuits Considering The Spatial and
Temporal Reliability Degradation, October 2007. Qualcomm, San Diego, California.
40. Myeong-Eun Hwang, Ultralow Power and Process Variation Tolerant VLSI Circuit Design in Nanoscale Technologies, December 2007. Intel Corporation, Hillsboro, Oregon.
41. Swaroop Ghosh, Voltage-Scalable Adaptive System Design for Low Power and Error Resilience in
Nanometer Technologies,, August 2008. Associate Professor, Pennsylvania State University.
42. Nilanjan Banerjee, Architecture-Circuit Co-Design for Low-Power and Error-Resilience in the Nanometer Regime, August 2008. Qualcomm, San Diego, California.
43. Mesut Meterelliyoz, December 2008, Intel, Hillsboro, Oregon.
44. Jung-Hwan Choi, Thermal Modeling, analysis, and Management Techniques for Nano Scale VLSI
Circuits, March 2009. Samsung Corporation, Seoul, Korea.
45. Jaydeep Kulkarni, Low Voltage Robust Memory Circuit Design, May 2009. Assistant Professor,
University of Texas at Austin. Doctoral Dissertation Award.
46. Patrick Ndai, Architecture-Aware Circuit Design for Process Tolerance and Resilience, July 2009.
Texas Instruments, Dallas, Texas.
47. Jing Li, Robust and Energy-Efficient Heterogeneous System Design in Emerging Technologies, July
2009. Assistant Professor, University of Wisconsin, Madison, Wisconsin.
48. Ik-Joon Chang, Aggressive Voltage Scaling in Digital Circuits, October 2009. Assistant Professor,
Kyunghee University, Seoul, Korea.
49. Ashish Goel, Low-Power, Process and Error Tolerant Circuit Design for Nanometer Technologies,
June 2010. Broadcom.
50. Georgios Karakonstantis, Cross Layer Design Methodologies for Energy Efficient and Variation
Tolerant Circuits and Systems, December 2010. Assistant Professor, Queen’s University, Belfast,
United Kingdom.
51. Debabrata Mohapatra, Approximate Computing: Enabling Voltage Overscaling in Multi-media Applications, April 2011. Intel Corporation, Santa Clara.
18
52. Niladri Mojumder, Design of Hybrid Spintronic Devices at Scaled Technologies for Non-Volatile
Memory Applications, September 2011. Qualcomm, san Diego, California.
53. Charles Augustine, Spintronic Memory and Logic: From Atoms to Systems, October 2011. Intel
Corporation, Hillsboro, Oregon.
54. Sang Phill Park, On-Chip Memory Design in Scaled Technologies, October 2011. Amazon, Seattle,
Washington.
55. George Panagopoulos, On Variability and Reliability of CMOS and SPIN based Devices, August
2012. Intel Corporation, Munich, Germany.
56. Sumeet Gupta, Technology-Circuit Co-design and Analysis of Nano-scale Multi-Gate FETs for
Memory Applications, October 2012. Assistant Professor, Purdue University, West Lafayette, Indiana.
57. Lu Chao, Efficient Design of Micro-Scale Energy Harvesting Systems, December 2012. Assistant
Professor, Southern Illinois University, Carbondale, Illinois. co-advisor: V. Raghunathan.
58. Sooyoun Kim, Characterization and Modeling of Variability and Reliability in CMOS/Poly-Si Technology, May 2013. Assistant Professor, Dongguk University, Korea.
59. Dongsoo Lee, Memory Design for Robust and Energy-Efficient Computing Systems, June 2013.
IBM TJ Watson, Yorktown Heights, New York.
60. William Paul Griffin, Variation-Derived Chip Security and Accelerated Simulation of Variations,
August 2013. Intel Corporation, Hillsboro, Oregon.
61. Mrigank Sharad, Energy Efficient Hybrid Computing Systems using Spin Devices, July 2014. Assistant Professor, Indian Institute of Technology, Kharagpur.
62. Chih-Hsiang (Sam) Ho, On Variability and reliability of Poly-Silicon Thin Film Transistors, July
2014. Qualcomm, Boston, Massachussetts.
63. Sri Harsha Choday, Thin-Film Thermoelectric Devices for On-Chip Cooling and Energy Harvesting,
July 2014. Intel Corporation, Santa Clara, California.
64. Xuanyao Fong, Design of Robust Spin-transfer Torque Magnetic Random Access Memories for Ultralow Power High Performance On-chip Cache Applications, September 2014. Assistant Professor,
National University of Singapore, Singapore.
65. Himanshu Markendeya, Algorithm-Circuit Co-design for Detecting Symptomatic Patterns in Biological Signals, December 2014. Intel Corporation, Chandler, Arizona.
66. Elif Selin Mungan, From Process to Circuits: New Perspectives on Solar Cell Design, March 2015.
Intel Corporation, California.
67. Konwoo Kwon, Nonvolatile Cache and Flip-Flop Design for Low Standby Leakage SOC, May 2015.
Hongik University, Korea.
68. Yusung Kim, Design Of Nonvolatile On-Chip Memory Using Spin Torque Devices, July 2015. Intel
Corporation, Portland Oregon.
69. Deliang Fan, Boolean and Brain-Inspired Computing Using Spin-Transfer Torque Devices, July
2015. Assistant Professor, Arizona State University, Tempe, Arizona.
70. Woo-suhl Cho, ”Device-Circuit Analysis of Sub-10nm Double-Gate FinFETs for Energy Efficiency,”
May 2016. Apple Computers, California.
71. Karthik Yogendra, ”Coupled Spin Torque Nan-Oscillators for Efficient Non-Boolean Computation,”
May 2016. IBM Watson, New York.
19
72. Arun Akkala, ”Asymmetric Underlap Optimization of Sub-10nm FinFETs for Realizing EnergyEfficient Logic and Robust Memories,” May 2016. Global Foundries, New York.
73. Zoha Pajouhi, ”Exploring Spin Transfer Torque Devices and Memristors for Logic and Memory
Applications,” May 2016. Intel Corporation, Portland, Oregon.
74. Yeongkyo Seo, ”Spin Transfer Torque Devices for On-Chip Memory and Their Applications to
Low-Standby Power Systems,” August 2016. Assistant Professor, Inha University, Incheon, South
Korea..
75. Mohammad Khaled Hassan, ”Statistical Modeling and Simulation of Variability and Reliability of
CMOS Technology,” December 2016. Global Foundries, New York.
76. Zubair Azim, ”Spin-Transfer Torque based Interconnects,” Februaray 2018. Intel Corporation,
Santa Clara, California.
77. Ankit Sharma, ”Sub-10nm Transistors for Low-Power Computing: Tunnel FETs and Negative
Capacitance FETs,” March 2018. Micron Corporation, Boise, Idaho.
78. Yong Shim, ”Stochastic Algorithms for Optimization: Devices, Circuits, and Architecture,” August
2018. Intel Corporation, Hillsboro, Oregon.
79. Abhronil Sengupta, ”Efficient Neuromorphic Computing Enabled by Spin-Transfer Torque: Devices,
Circuits, and Systems,” August 2018. Assistant Professor, Pennsylvania State University, University
Park, Pennsylvania.
80. Akhilesh Jaiswal, ”Exploiting Voltage Driven Switching of Ferromagnets for Novel Spin Based
Devices and Circuits,” May 2018. Global Foundries, New York.
81. Syed Shakib Sarwar, ”Exploration of Energy Efficient Hardware and Algorithms for Deep Learning,”
May 2018. Facebook, Redmond, Washington.
82. Parami Wijesinghe, ”Neuro-inspired Computing Enhanced by Scalable Algorithms and Physics of
Emerging Nanoscale Resistive Devices,” May 2018. Intel Corp., Hillsboro, Oregon.
83. Priyadarshini Panda, ”Learning and Design Methodologies for Efficient and Robust Neural Networks”, May 2018, Assistant Professor at Yale University, Connecticut.
84. Ahmed Reza, ”Modeling and Simulation of Topological Insulators, Topological Sem–metals and
Ferrimagnets for Time and Energy Efficicient Switching of Magnetic Tunnel Junction,” May, 2019,
Intel Corporation.
85. Gopalkrishnan Srinivasan, ”Training Spiking Neural Networks for Energy-Efficient Neuromorphic
Computing,” December 2019, MediaTek.
86. Mei-Chin Chen, ”Spintronic Devices and Its Applications,” May 2020, Micron.
87. Minsuk Koo, ”Energy-Efficient neuromorphic Computing: Circuits, Interconnects, and Architecture,” May 2020, Assistant Professor at Incheon National University, South Korea.
88. Maryam Parsa, ”Bayesian based Multi-objective Hyperparameter Optimization for Accurate, Fast,
and Efficient Neuromorphic System Design,” August 2020, Oak-Ridge National Laboratory.
89. Aayush Ankit, ”Hardware-Software Co-design for Efficient Machine Learning using In-Memory
Computing,” December 2020, Microsoft Research.
90. Robert Andrawis, ”Multiferroic Devices: Modeling, Analysis, and Applications,” December 2020,
Samsung.
Ph.D. Theses Currently Supervising:
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91. Indranil Chakraborty
92. Deboleena Roy
93. Amogh Agrawal
94. Nitin Rathi
95. Bing Han
96. Chamika Liyanagendra
97. Jason Allred
98. Sourav Sanyal
99. Tanvi Sharma
100. Saima Sharmin
101. Chankyu Lee
102. Isha Garg
103. Gobinda Saha
104. Mustafa Ali
105. Sayeed Chowdhury
106. Shubham Negi
107. Utkarsh Saxena
108. Eunseon Yu
109. Efsthatia Soufleri
110. Timur Ibrayev
111. Wachirawit Ponghiran
112. Yinghan Long
113. Srihari Shridharan
114. Sangamesh Kogde
115. Adarsh Kosta
116. Sai Aparna Aketi
117. Rayane Chatrieux
118. Deepika Sharma
119. Deepak Ravikumar
120. Chun Tao
121. Kang He
122. Amitangshu Mukherkee
123. Manish Nagaraj
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124. Marco Paul Enrique Apolinario Lainez
MS Theses Supervised:
125. Priya Patil, Low Power Driven Logic Synthesis, Feb. 1996. Currently at Intel Corp., California.
126. Hendrawan Soeleman, Power Estimation of Static CMOS Combinational Digital Logic Circuits,
Aug. 1996.
127. M. Lundberg, “Fast Power Estimation Methods with Application to Adaptive Channel Equalization,” Lulea University of Technology, Lulea, Sweden. Ericsson MD110 User Group Award for the
Best MS thesis in Telecommunications area in Sweden.
128. N. Sankarayya, Computational Optimizations for Low-Power Digital Signal Processing, Dec. 1997.
129. Naran Sirisantana, High-Performance Low-Power CMOS Circuits Using Multiple Channel Length
and Multiple Oxide Thickness, Jan. 2000.
130. Jong-Sun Park, High-Performance FIR Filter Implementation Based on Sharing Multiplication,
June 2000.
131. Cassondra Crotty, Low Complexity Finite Impulse Response Digital Filter Design Using Factorization of Perturbed Coefficients, June 2000.
132. Hunsoo Choo, Decision Feedback Equalizer with Computation Sharing Multiplication Using Redundant Number Scheme, December 2000.
133. Amit Agarwal, Design of Leakage Tolerant Caches for Scaled Technologies,, January 2002.
134. Hiroaki Suzuki, Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders,
December 2003.
135. Debjyoti Ghosh, Low-Complexity Power-Efficient BIST, December 2003, Analog Devices.
136. Aditya Bansal, Optimization and Characterization of Sub-50nm Gate Length Asymmetric Halo
MOSFETs, December 2003.
137. Cheng-Yi Chen, Efficient Communication Channel Utilization for Mapping FFT onto Mesh Array
and Torus Array, May 2004, Socle Technology Corp, TW.
138. Rouzbeh Jazayeri, An Efficient Low Power and High Performance Multiplier for Digital Filtering,
May 2004, Intel.
139. Mathew Cooke, Energy-Recovery Clocking Scheme and Circuit Elements, December 2004, AMD.
140. James Gallagher, Low Power Design using Dual-Vt for Nanometer-Scale CMOS, May 2005, Intel.
141. Arjun Guha, Design of Robust SRAM Cells, May 2006, Micron.
142. Pooja Batra, Logic Families for Ultralow-Power Process Tolerant Digital Subthreshold Design,
February 2007, Sun Microsystems.
143. Saakshi Gangwal, Optimization of Surface Orientation for Robust, High-Performance and LowPower FinFET SRAM, May 2007, Intel Corporation, Austin.
144. Dheepa Lekshmanan, Device Circuit Co-design for Robust and High Performance FinFET Logic
and SRAMs, May 2007, Texas Instruments, Dallas.
145. Vinita Soman, Cell Based Library Design Methodology for Improved performance and Variation
Tolerance in Subthreshold Circuits, Intel Corp., Hillsboro, Oregon.
22
146. Sumeet Gupta, Modeling and Analysis of Digital Computation in Ultra-Subthreshold Regime: Approaching CMOS Limits, currently enrolled in the PhD program in my group.
147. Niladri Mojumder, Self-Repairing SRAM using On-Chip Detection and Compensation, enrolled in
PhD program in my group.
148. Christine Placek, Voltage Over-Scaling in Unbalanced Pipelines with Adaptive Clocking, Intel Corporation, Hillsboro, Oregon.
149. Jolene Singh, Deeply Scaled FinFETs, Intel Corporation, Hillsboro, Oregon.
150. Aparajita Banerjee, A Framework for Optimal Design of Low-PowerFIR Filters, Intel Corporation.
MS Theses Currently Being Supervised:
Visiting Scholar and Post-doctoral Researcher:
151. Magnus Lundberg, Sweden.
152. Alexandro Adario, PhD student from Brazil.
153. Mikael Kerttu, Lulea University, Sweden.
154. Dr. Bipul Paul, Post-doctoral researcher, PhD from Indian Institute of Science, India.
155. Dr. Keejong Kim, Post-doctoral researcher from Samsung, currently in Broadcom.
156. Prof. Meng-Huseh Chiang, National Ilan University, Taiwan
157. Prof. Il-Sup Chung, Korea
158. Dr. Mohsen Radfar, Australia
159. Dr. Cheng Wang (current)
ACTIVITIES AS A REFEREE:
1992 - present
1988 - present
National Science Foundation
IEEE Transactions on Computer-Aided-Design, IEEE Transactions on
Circuits and Systems, IEEE Transactions on VLSI Systems, IEEE Transactions on
Electron Devices, IEEE/ACM Design Automation Conference, International
Test Conference, International Conference on Computer-Aided-Design, IEEE VLSI
Test Symposium, etc.
23
LIST OF PUBLICATIONS
BOOKS
1. K. Roy and S. Prasad, Low-Power CMOS VLSI Circuit Design, John Wiley & Sons, Inc., ISBN
0-471-11488-X, 2000, 359 pages.
2. K-S. Yeo and K. Roy, Low-Voltage Low-Power VLSI Subsystems, McGraw-Hill 2004, ISBN: 0-07143786-X, 294 pages.
CHAPTERS IN BOOKS
3. K. Roy, “Segmented Channel Routing,” book chapter in Advanced Routing of Electronic Modules,
ed. M. Pecht, CRC Press, 1995, pp. 207-235.
4. M. Levitt and K. Roy, “Testing of BiCMOS Logic,” book chapter in BiCMOS Technology and
Applications, Kluwer Academic Publishers, ed. A. Alvarez, 1993, pp. 271-294.
5. K. Roy and S. Prasad, “Power Dissipation Driven FPGA Place and Route under Delay Constraints,”
in Field Programmable Logic – Architectures, Synthesis, and Applications, Springer-Verlag, 1994,
pp. 57-65.
6. K. Roy and S. Nag, “On Channel Architecture and Routability for FPGA’s under Faulty Conditions,” in Field Programmable Logic – Architectures, Synthesis, and Applications, Springer-Verlag,
1994, pp. 361-372.
7. K. Roy, R. Roy, and T.-L. Chou, “Design of Low Power Digital Systems,” in Emerging Technologies,
ed. W. Liu and R. Cavin, IEEE, May 1996, pp. 137-204.
8. K. Roy, “Power Analysis and Design at System Level: Notebook Computers,” in , Kluwer Academic
Press, Low Power Design in Deep Submicron Electronics, October 1996, ed. J. Mermet and W.
Nebel, pp. 419-431.
9. K. Roy and M. Johnson, “Software Power Optimization,” in Low Power Design in Deep Submicron
Electronics, Kluwer Academic Press, October 1996, ed. J. Mermet and W. Nebel, pp. 433-459.
10. T.-L. Chou and K. Roy, “Logic Synthesis,” in Encyclopedia of Electronics, John Wiley & Sons,
March 1999, ISBN 0471139467.
11. H. Soeleman and K. Roy, “Accurate Power Estimation of Combinational Digital Circuits,” in The
Computer Engineering Handbook, edited by V. Oklobdzija, CRC Press, 2002, ISBN: 0-8493-0885-2.
12. A. Agarwal and K. Roy, “Exploring High Bandwidth Pipelined Cache Architecture for Scaled
Technology,” in Embedded Software for SoC, Edited by A. A. Jerraya, S. Yoo, N. Wehn, D. Verkest
(editors), Kluwer Academic Publishers, June 2003.
13. A. Agarwal, C. H. Kim, and K. Roy, “Circuit Techniques for Leakage Reduction,” in Low Power
Electronics Design, Edited by C. Piguet, CRC press, 2004, pp. 13.1-13.15, ISBN: 0-8493-1941-2.
14. A. Raychowdhury and K. Roy, “Nanometer Scale Technologies: Device Considerations,” in Nano,
Quantum, and Molecular Computing: Implications to High Level Design and Validation, Kluwer
Academic Press, pp. 5-29, June 2004, ISBN: 1-4020-8067-0.
15. A. Keshavarzi and K. Roy, “Impact of Leakage Power and Variation on Testing,” in Leakage in
Nanometer CMOS Technologies, Springer, 2006, ISBN: 0-387-25737-3.
16. K. Roy and S. Bhunia, ” Low Power Design Techniques and Test and Test Implications,” Chapter
in Power Aware Testing and Test Strategies for Low Power Devices, Springer, ISBN: 978-1-44190927-5.
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17. J. Kulkarni and K. Roy, ”Tecnology/Circuit Co-Design for III-V FETs,” Chapter in Fundamentals
of III-V Semiconductor MOSFETs, Springer, ISBN: 978-1-4419-1546-7, pp. 423-441.
18. G. Karakonstantis and K. Roy, ”Low-Power and Variation-Tolerant Application-Specific System
Design,” Chapter in Low-Power Variation-Tolerant Design in Nanometer Silicon, Springer, ISBN:
978-1-4419-7417-4, pp. 249-292.
19. M. Sharad and K. Roy, ”Cross-Hierarchy Design Exploration for Implantable Electronics,” Chapter
in Implantable Bioelectronics, Wiley-VCH, Edited by E. Katz, ISBN: 978-3-527-33525-1, pp. 65-84.
20. X. Fong, S. Choday, and K. Roy, ”Design and Optimization of Spin-Transfer Torque MRAMs,”
Chapter in More than Moore Technologies for Next Generation Computer Design, Springer Science+Business Media New York, .
21. S. Gupta and K. Roy, ”Low Power Robust FinFET-based SRAM Design in Scaled Technologie,”,
in Circuit Design for Reliability, Springer. 2015.
22. X. Fong and K. Roy, ”On-chip Non-volatile STT-MRAM for Zero-stanby Power,” in Enabling
Internet of Things from integrated circuits to integrated systems, Ed. M. Aliot, Springer, 2017.
ISBN: 978-3-319-51480-2.
23. A. Sengupta, A. Ankit, and K. Roy, ”Efficient Neuromorphic Systems and Emergin Technologies: Prospects and Perspectives,” in Emerging Technology and Architecture for Big-data Analytics,
Springer, 2017, ISBN: 978-3-319-54839-5.
ARTICLES IN JOURNALS
24. P. Banerjee, J. Rahmeh, C. Stunkel, S. Nair, K. Roy, V. Balasubramanian, and J. Abraham,
“Algorithm Based Fault Tolerance on Hypercube,” IEEE Transactions on Computers, August,
1990, pp. 1132-1145.
25. K. Roy and J. Abraham, “The Use of RTL Descriptions in Accurate Timing Verification and Test
Generation,” IEEE Journal of Solid State Circuits, September, 1991, pp. 1230-1239.
26. K. Roy, “A Bounded Search Algorithm for Segmented Channel Routing for FPGAs and Associated
Channel Architecture Issues,” IEEE Transactions on Computer-Aided-Design of Integrated Circuits,
November, 1993, pp. 1695-1705.
27. K. Roy and S. Prasad, “Circuit Activity Based Logic Synthesis for for Low Power Reliable Operations,” IEEE Transactions on VLSI Systems, December, 1993, pp. 503-513.
28. M. Levitt, K. Roy, and J. Abraham, “BiCMOS Logic Testing,” IEEE Transactions on VLSI Systems, June 1994, pp. 241-248.
29. K. Roy and S. Nag, “Automatic Synthesis of FPGA Channel Architecture for Performance and
Routability,” IEEE Transactions on VLSI Systems, December 1994, pp. 508-511.
30. K. Roy and S. Prasad, “Logic Synthesis for Reliability – An Early Start to Controlling Electromigration and Hot Carrier Effects,” IEEE Transactions on Reliability, June, 1995, pp. 251-255.
31. K. Roy and S. Nag, “On Routability for FPGA’s under Faulty Conditions,” IEEE Transactions on
Computers, November 1995, pp. 1296-1305.
32. K. Kornegay and K. Roy, “Structured Test Methodology and Test Economics for Multichip Modules,” IEEE Transactions on Components, Hybrids, Manufacturing Technology – Advanced Packaging, February 1996, pp. 195-202.
33. S. Prasad and K. Roy, “Transistor Reordering for Power Minimization under Delay Constraint,”
ACM Transactions on Design Automation of Electronic Systems, Vol. 1, No. 2, April 1996, pp.
280-300.
25
34. D. Somasekhar and K. Roy, “Differential Current Switch Logic: A Low-Power DCVS Logic Family,”
IEEE Journal of Solid-State Circuits, July 1996, pp. 981-991.
35. T.-L. Chou and K. Roy, “Accurate Power Estimation of CMOS Sequential Circuits,” IEEE Transactions on VLSI Systems, September 1996, pp. 369-380.
36. Y. Ye and K. Roy, “Energy Recovery Circuits Using Reversible and Partially Reversible Logic,”
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, September
1996, pp. 769-778.
37. T.-L. Chou and K. Roy, “Estimation of Activity for Static and Domino CMOS Circuits Considering
Signal Correlations and Simultaneous Switching,” IEEE Transactions on Computer-Aided Design
of Integrated Circuits, October 1996, pp. 1257-1265.
38. N. Sankarayya, K. Roy, and D. Bhattacharya, “Algorithms for Low Power High Speed FIR Filter
Realization Using Differential Coefficients,” IEEE Transactions on Circuits and Systems: Analog
and Digital Signal Processing, June 1997, pp. 488-497.
39. M. Johnson and K. Roy, “Datapath Scheduling with Multiple Supply Voltages and Voltage Converters,” ACM Transactions on Design Automation of Electronic Systems, July 1997.
40. T.-L. Chou and K. Roy, “Statistical Estimation of CMOS Circuit Activity under Probabilistic
Delays,” IEICE (Japan) Transactions on Fundamentals of Electronics, Communications and Computer Sciences, special issue on VLSI Design and CAD Algorithms, October 1997, pp. 1915-1923.
41. Y. Ye and K. Roy, “An XOR-Based Decomposition Diagram and Its Application in Synthesis of
AND-XOR Network,” IEICE (Japan) Transactions on Fundamentals of Electronics, Communications and Computer Sciences, special issue on VLSI Design and CAD Algorithms, October 1997,
pp. 1742-1748.
42. S. Nag and K. Roy, “Performance and Wireability Driven Layout for Row-Based FPGAs,” Journal
of VLSI Design, Vol. 7, No. 4, 1998, pp. 353-364.
43. K. Roy, “Power Dissipation Driven FPGA Place and Route Under Timing Constraints,” IEEE
Transactions on Circuits and Systems I: Fundamental Theory and Applications, May 1999, Vol. 46,
No. 4, pp. 634-637.
44. T.-L. Chou and K. Roy, “Power Estimation Under Uncertain Delays,” Integrated Computer-Aided
Engineering, Wiley-Intersciece, pp. 107-116, vol. 5, no. 2, 1998.
45. C.-Y. Wang and K. Roy, “Maximum Power Estimation for CMOS Circuits Using Deterministic and
Statistical Techniques,” IEEE Transactions on VLSI Systems, March 1998, pp. 134-140.
46. Z. Chen, K. Roy, and T.-L. Chou, “Efficient Statistical Approach to Estimate Power Considering
Uncertain Properties of Primary Inputs,” IEEE Transactions on VLSI Systems, pp. 484-492,
September 1998.
47. D. Somasekhar and K. Roy, “LVDCSL: A High-Performance Low-Power Logic Using High Fan-in
Gates,” IEEE Transactions on VLSI Systems, Special issue on low-power design, December 1998,
pp. 573-577.
48. L. Wei, Z. Chen, K. Roy, M. Johnson, Y. Ye, and V. De, “Design and Optimization of Dual
Threshold Circuits for Low-Voltage Low-Power Applications,” IEEE Transactions on VLSI Systems, Special issue on low-power electronics and design, March 1999, pp. 16-24.
49. C. Wang and K. Roy, “An Activity-Driven Encoding Scheme for Power Optimization in Microprogrammed Control Unit,” IEEE Transactions on VLSI Systems, March 1999, pp. 130-134.
50. M. Johnson, D. Somasekhar, and K. Roy, “Models and Algorithms for Bounds on Leakage in CMOS
Circuits,” IEEE Transactions on Computer-Aided Design of IC’s, June 1999, pp. 714-725.
26
51. H. Soeleman, K. Roy, and T.-L. Chou, “Estimating Circuit Activity in Combinational CMOS
Digital Circuits,” IEEE Design and Test of Computers, April-June 2000, pp. 112-119.
52. C-Y. Wang and K. Roy, “Maximization of Power Dissipation in Large CMOS Circuits Considering
Spurious Transitions,”IEEE Transactions on Circuits and Systems - I, April 2000, pp. 483-490.
53. Z. Chen, K. Roy, and E. Chong,”Estimation of Power Dissipation Using a Novel Power Macromodeling Technique,” IEEE Transactions on Computer-Aided-Design, November 2000, pp. 1363-1369.
54. X. Zhang, K. Roy, and S. Bhawmik, ‘Low Power Weighted Random Pattern Testing,” IEEE Transactions on Computer-Aided-Design, November 2000, pp. 1389-1398.
55. K. Muhammad and K. Roy, “Fault Detection and Location Using IDD Waveform Analysis,” IEEE
Design and Test, January-February 2001, pp. 42-49.
56. A. Keshavarzi, K. Roy, and C. Hawkins, “Intrinsic Leakage in Deep Submicron IC’s – Measurement
Based Test and Power Solutions,” IEEE Transactions on VLSI Systems, December 2000, pp. 717723.
57. Y. Ye and K. Roy, “QSERL: Quasi-Static Energy Recovery Logic,” IEEE Journal of Solid-State
Circuits, February, 2001 pp. 239-249.
58. L.-Y. Chiou, K. Muhammad, and K. Roy, “Signal Strength based Switching Activity Modeling and
Estimation for DSP Applications,” Journal of VLSI Design, Special issue on low power design, Vol.
12, No. 2, pp.233-243, 2001
59. S.-H. Yang, M. Powell, B. Falsafi, K. Roy, and T. Vijaykumar, “An Energy-Efficient High Performance Deep-Submicron Instruction Cache,” IEEE Transactions on VLSI Systems, Special issue on
low-power design, February 2001, pp. 77-89.
60. H. Soeleman, K. Roy, and B. Paul, “Robust Sub-Threshold Logic for Ultra-Low Power Operation,”
IEEE Transactions on VLSI Systems, Special issue on low-power design, February 2001, pp. 90-99.
61. R. Zhang, K. Roy, C.-K. Koh, and D. Janes, “Stochastic Interconnect Modeling, Power Trends, and
Performance Characterization of 3-Dimensional Circuits,” IEEE Transactions on Electron Devices,
April 2001, pp. 638-652.
62. Z. Chen, L. Wei, and K. Roy, “On Effective IDDQ Testing of Low Voltage CMOS Circuits Using
Leakage Control Techniques,“ IEEE Transactions on VLSI Systems, October 2001, pp. 718-725.
63. M. Lundberg, K. Muhammad, K. Roy, and S. Wilson, “A Novel Approach to High Level Switching
Activity Modeling with Applications to DSP System Synthesis,” IEEE Transactions on Signal
Processing, December 2001.
64. S. Zhao, C.-K. Koh, and K. Roy, “Decoupling Capacitance Allocation and Its Application to Power
Supply Noise Aware Floorplanning,” IEEE Transactions on Computer-Aided Design of IC’s, January 2002, pp. 81-92.
65. K. Muhammad and K. Roy, “A Graph Theoretic Approach for Synthesizing Very Low-Complexity
High-Speed Digital Filters,” IEEE Transactions on Computer-Aided Design of IC’s, February 2002,
pp. 204-216.
66. M. Johnson, D. Somasekhar, L. Chiou, and K. Roy, “Leakage Control With Efficient Use of Transistor Stacks in Single Threshold CMOS,“ IEEE Transactions on VLSI Systems, February 2002,
pp. 1-5.
67. Z. Chen, L. Wei, A. Keshavarzi, and K. Roy, “IDDQ Testing for Deep Sub-Micron IC’s: Challenges
& Solutions,” IEEE Design & Test, March-April 2002, pp. 24-33.
27
68. R. Zhang and K. Roy, “Low-Power High-Performance Double-Gate Fully Depleted SOI Circuit
Design,” IEEE Transactions on Electron Devices, May 2002, pp. 852-862.
69. Y. Im and K. Roy, “O2 ABA: A Novel High-Performance Predictable Circuit Architecture for the
Deep Sub-micron Era,” IEEE Transactions on VLSI Systems, June 2002, pp. 221-229.
70. K. Muhammad and K. Roy, “Reduced Computational Redundancy Implementation of DSP Algorithms Using Computation Sharing Vector Scaling,”IEEE Transactions on VLSI Systems, June
2002, pp. 292-300.
71. L. Wei, R. Zhang, K. Roy, Z. Chen, and D. Janes, “Vertically Integrated SOI Circuits for LowPower and High-Performance Applications,” IEEE Transactions on VLSI Systems, June 2002, pp.
351-362.
72. R. Zhang, K. Roy, C. Koh, and D. Janes, “Exploring SOI Device Structures and Interconnect
Architectures for Low-Power High-Performance Circuits,” IEE Proceedings: Computers and Digital
Techniques, Vol. 149, Issue 04, July 2002, pp. 137-145.
73. A. Solomatnikov, D. Somasekhar, N. Sirisantana, and K. Roy, “Skewed CMOS: Noise Tolerant
High Performance and Low Power Static Circuit Family,” IEEE Transactions on VLSI Systems,
pp. 469-476, August 2002.
74. A. Keshavarzi, K. Roy, J. Tschantz, S. Narendra, A. Daasch, C. Hawkins, and V. De, “Impact of
Leakage and Process Variation on Current-Based Testing for Future Scaled CMOS Circuits,” IEEE
Design and Test, September-October 2002, pp. 36-43.
75. S. Choi, D. Somasekhar, and K. Roy, “Dynamic Noise Model and Its Application to High Speed
Circuit Design,” Microelectronics Journal, 33, 2002, 835-846.
76. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage Current in Deep-Sub-micron
CMOS Circuits,” Journal of Circuits, Systems, and Computers, Vol. 11, No. 6, pp. 575-600,
December 2002.
77. H. Choo, K. Muhammad, and K. Roy, “Two’s Complement Computation Sharing Multiplier and
Its Application to Adaptive Filter Design,” IEEE Transactions on Signal Processing, pp. 458-469.
February, 2003.
78. A. Agarwal, H. Li, and K. Roy, “DRG Cache: A Data Retention Gated Ground Cache for Low
Power Applications,” IEEE Journal of Solid-State Circuits, pp. 319-328, February 2003.
79. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicron CMOS Circuits,” IEEE Proceedings, pp. 305-327,
February 2003.
80. J. Park, K. Muhammad, and K. Roy, “High Performance FIR Filter Design Based on Sharing
Multiplication,” IEEE Transactions on VLSI Systems, April 2003, pp. 244-253.
81. S. Mukhopadhyay, C. Neau, T. Cakici, A. Agarwal, C.Kim, and K. Roy, “Gate Leakage Reduction
for Scaled Devices Using Transistor Stacking,“ IEEE Transactions on VLSI Design, August 2003,
pp. 716-730.
82. A. Keshavarzi, K. Roy, C. Hawkins, and V. De, “Multiple-Parameter CMOS IC Testing with
Increased Sensitivity for IDDQ,” IEEE Transactions on VLSI Systems, October 2003, pp. 863-870.
83. G. Zhong, C.-K. Koh, and K. Roy, “On-Chip Interconnect Modeling by Wire Duplication,” IEEE
Transactions on CAD of Integrated Circuits, November 2003, pp. 1521-1532.
84. C. H. Kim, H. Soeleman, and K. Roy, “Ultra-Low Power DLMS Adaptive Filter for Hearing Aid
Applications,” IEEE Transactions on VLSI Systems, pp. 1058-1067, December 2003. 2005 IEEE
Circuits and Systems Society Outstanding Young Author Award.
28
85. N. Sirisantana and K. Roy, “High-Performance and Low-Power CMOS Circuits Using Multiple
Channel Length and Multiple Oxide Thickness,” IEEE Design and Test, pp. 56-63, Jan-Feb 2004.
86. J. Park, W. Jeong, H. Mahmoodi-Meimand, Y. Wang, H. Choo, and K. Roy, “Computation Sharing
Programmable FIR Filter for High Performance and Low Power Applications,” IEEE Journal of
Solid-State Circuits, pp. 348-357, February 2004.
87. H. Mahmoodi-Meimand and K. Roy, “Diode-Footed Domino: A Leakage-Tolerant High Fan-in
Dynamic Circuit Design Style,” IEEE Transaction on Circuits and Systems: I, pp. 495-503, March
2004.
88. H. Li, S. Bhunia, Y. Chen, K. Roy, and T. Vijaykumar, “DCG: Deterministic Clock Gating for
Low-Power Microprocessor Design,” IEEE Transactions on VLSI Systems, pp. 245-254, March
2004.
89. H. Choo, K. Muhammad, and K. Roy, “Complexity Reduction of Digital Filters using Shift Inclusive
Differential Coefficients,” IEEE Transactions on Signal Processing, June 2004, pp. 1760-1772.
90. J. Kim and K. Roy, “Double-Gate MOSFET Subthreshold Circuit for Ultralow Power Applications,”
IEEE Transactions on Electron Devices, pp. 1468-1474 September 2004.
91. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “A Circuit-Compatible Model of Ballistic Carbon
Nanotube Field-Effect Transistor,” IEEE Transactions on Computer-Aided Design of Integrated
Circuits, October 2004, pp. 1411-1420.
92. N. Sirisantana, B. Paul, and K. Roy, “Enhancing yield at the end of the technology roadmap,”
IEEE Design and Test, Nov.-Dec. 2004, pp. 563-571.
93. A. Agarwal, B. Paul, H. Mohammadi, A. Datta, and K. Roy, “A Process Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies,” IEEE Transactions on VLSI Systems, January
2005, pp. 27-38. 2005 IEEE Circuits and Systems Society VLSI Transactions Best Paper
Award.
94. Y. Chen, K. Roy, and C.-K. Koh, “Current Demand Balancing: A Technique for Minimization of
Current Surge in High Performance Clock-Gated Processors,” IEEE Transactions on VLSI Systems,
January 2005, pp. 75-85.
95. B. Paul, A. Raychowdhury, and K. Roy, “Device Optimization for Digital Subthreshold Logic
Operation,” IEEE Transactions on Electron Devices, February 2005, pp. 237-247.
96. A. Bansal, B. Paul, and K. Roy, “Modeling and Optimization of Fringe Capacitance of Nanoscale
DGMOS Devices,” IEEE Transactions on Electron Devices, February 2005, pp. 256-262.
97. W. Jeong and K. Roy, “High-Performance Low-Power Dual Transition Preferentially Sized (DTPS)
Logic,” IEEE Journal of Solid-State Circuits, February 2005, pp. 480-484.
98. S. Bhunia and K. Roy, “Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of
Dynamic Supply Current,” Journal of Electronic Testing: Theory and Applications, 21, 2005, pp.
147-159.
99. C. H. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, “A Forward Body-Biased Low-Leakage SRAM
Cache: Device, Circuit, and Architecture Considerations,” IEEE Transactions on VLSI systems,
March 2005, pp. 348-357.
100. L. Chiou, S. Bhunia, and K. Roy, “Synthesis of Application-Specific Highly-Efficient Multi-Mode
Cores for Embedded Systems,” ACM Transactions on Embedded Computing Systems, February
2005, Volume 4, Issue 1, pp. 168-188.
101. S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, and K. Roy, “Low-Power Scan Design
Using First Level Supply Gating,” IEEE Transactions on VLSI Systems, March 2005, pp. 384-395.
29
102. A. Raychowdhury and K. Roy, “Carbon Nanotube Based Voltage-Mode Multiple-Valued Logic
Design,“ IEEE Transactions on Nanotechnology, March 2005, pp. 168-179.
103. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, “Accurate Estimation of Total Leakage in
Nanometer Scale Bulk CMOS Circuits Based on Device Geometry and Doping Profile,” IEEE
Transactions on CAD of Integrated Circuits, March 2005, pp. 363-381.
104. A. Bansal and K. Roy, “Asymmetric Halo CMOSFET to Reduce Static Power Dissipation with
Improved Performance,” IEEE Transactions on Electron Devices, March 2005, pp. 397-405.
105. A. Cao, N. Sirisantana, C.-K. Koh, and K. Roy, “Synthesis of Skewed Logic Circuits,”ACM Transactions on Design Automation of Electronic Systems, Volume 10 , Issue 2, April 2005, pp. 205-228.
106. S. Bhunia and K. Roy, “A Novel Wavelet Transform Based Transient Current Analysis for Fault
Detection and Localization,” IEEE Transactions on VLSI Systems, April 2005, pp. 503-507.
107. A. Agarwal, S. Mukhopadhyay, C.H. Kim, A. Raychowdhury, and K. Roy, “Leakage Power Analysis and Reduction: Models, Estimation and Tools,” IEE Proceedings – Computers and Digital
Techniques, May 2005, pp. 353-368.
108. S. Bhunia, A. Datta, N. Banerjee, and K. Roy, “GAARP: A Power-Aware GALS Architecture for
Real-Time Algorithm-Specific Tasks,” IEEE Transactions on Computer, special issue on low-power
design, June 2005, pp. 752-766.
109. M. Hwang, A. Raychowdhury, and K. Roy, “Energy Recovery Techniques to Reduce On-Chip Power
Density in Molecular Nano-Technologies,” IEEE Transactions on Circuits and Systems, August
2005, pp. 1580-1589.
110. B. Paul, K. Kang, H. Kufluoglu, A. Alam, and K. Roy, “Impact of NBTI on the Temporal Performance Degradation of Digital Circuits,” IEEE Electron Device Letters, August 2005, pp. 560-562.
111. A. Agarwal, B. Paul, S. Mukhopadhyay, and K. Roy, “Process Variation in Embedded Memories: Failure Analysis and Variation Aware Architecture,” IEEE Journal of Solid-State Circuits,
September 2005, pp. 1804-1814.
112. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “Estimation of Delay Variations due To RandomDopant Fluctuations in Nanoscale CMOS Circuits,” IEEE Journal of Solid-State Circuits, September 2005, pp. 1787-1796.
113. Y. Wang and K. Roy, “CSDC: A New Complexity Reduction Technique for Multiplierless Implementation of Digital FIR Filters,” IEEE Transactions on Circuits and Systems I, September 2005,
pp. 1845-1853.
114. A. Raychowdhury, B. Paul, S. Bhunia, and K. Roy, “Computing with Subthreshold Leakage: Device/Circuit/Architecture Co-Design for Ultralow-Power Subthreshold Operation,” IEEE Transactions on VLSI Systems, November 2005, pp. 1213-1224.
115. Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, “Efficient Testing of SRAM with Optimized March
Sequences and a Novel DFT Technique for Emerging Failures due to Process Variations,” IEEE
Transactions on VLSI Systems, November 2005, pp. 1286-1295.
116. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Modeling of Failure Probability and Statistical
Design of SRAM Array for Yield Enhancement in Nano-Scaled Technologies,” IEEE Transactions
on Computer-Aided Design of Integrated Circuits, December 2005, pp. 1859-1880.
117. A. Raychowdhury and K. Roy, “Modeling of Metallic Carbon Nanotube Interconnects for Circuit
Simulation and a Comparison with Cu Interconnects for Scaled Technologies,” IEEE Transactions
on Computer-Aided Design of IC’s, January 2006, pp. 58-65.
30
118. C. H. Kim, J. Kim, I. Chang, and K. Roy, “PVT-Aware Leakage Reduction for On-Die Caches with
Improved Read Stability,” IEEE Journal of Solid-State Circuits, January 2006, pp. 170-177.
119. H. Ananthan and K. Roy, “Technology and Circuit Design Considerations in Width-Quantized
Quasi-Planar Double-Gate SRAM,” IEEE Transactions on Electron Devices, February 2006, pp
242-250.
120. B. Paul, A. Agarwal, and K. Roy, “Low-Power Design Techniques for Scaled Technologies,” Integration, the VLSI Journal, 39, 2006, pp. 64-89.
121. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “A Novel High-Performance and Robust Sense Amplifier Using Independent Gate Control in Sub-50nm Double-Gate MOSFET,” IEEE Transactions
on VLSI Systems, February 2006, pp. 183-192.
122. D. Kang, H. Choo, K. Muhammad, and K. Roy, “Layout-Driven Architecture Synthesis for HighSpeed Digital Filters,” IEEE Transactions on VLSI Systems, February 2006, pp. 203-207.
123. S. Mukhopadhyay, K. Kim, X. Wang, D. Frank, P. Oldiges, C.-T. Chuang, and K. Roy, “Optimal
Ultra-Thin Body FD/SOI Device Structure Using Thin-BOX for Sub-50nm SRAM Design,” IEEE
Electron Device Letters, Volume 27, Issue 4, April 2006 Page(s):284 - 287.
124. J. Kim and K. Roy, “A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-onInsulator CMOS Technologies,” IEEE Transactions on VLSI Systems, May 2006, pp. 549-552.
125. C.H. Kim, K. Roy, S. Hsu, R. Krishnamurthy, and S. Borkar, ”A Process variation Compensating
Technique With an On-Die Leakage Current Sensor for Nanometer Scale Dynamic Circuits,” IEEE
Journal of Solid-State Circuits, June 2006, pp. 646-649.
126. J. Park, K. Muhammad, and K. Roy, “Efficient Modeling of 1/f α Noise using Multi-Rate Process,”
IEEE Transactions on Computer-Aided Design of IC’s, July 2006, pp. 1247-1256.
127. S. Mukhopadhyay, S. Bhunia, and K. Roy, “Modeling and Analysis of Loading Effect on Leakage of Nano-Scale Bulk CMOS Logic Circuits,” IEEE Transactions on Computer-Aided Design of
Integrated Circuits, August 2006, pp. 1486-1495.
128. N. Banerjee, A Raychowdhury, K. Roy, S. Bhunia, and H. Mahmoodi, ”Novel Low-Overhead
Operand Isolation Techniques for Low-Power Datapath Synthesis,” IEEE Transactions on VLSI
Systems, September 2006, pp. 1034-1039.
129. S. Mukhopadhyay, K. Kim, C.-T. Chuang, and K. Roy, “Modeling and Analysis of Total Leakage
Currents in Nano-scale Double Gate Devices and Circuits,” IEEE Transactions on Computer-Aided
Design of Integrated Circuits, October 2006, pp. 2052-2061.
130. A. Raychowdhury, A. Keshavarzi, J. Kurtin, V. De, and K. Roy, ”Carbon Nanotube Field Effect
Transistors for High Performance Digital Circuits: DC Analysis and Modeling toward Optimum
Transistor Structure,” IEEE Transactions on Electron Devices, November 2006, pp. 2711-2716.
131. A. Keshavarzi, A. Raychowdhury, J. Kurtin, K. Roy, and V. De ”Carbon Nanotube Field Effect
Transistors for High Performance Digital Circuits: Transient Analysis, Parasitics, and Scalability,”
IEEE Transactions on Electron Devices, November 2006, pp. 2718-2726.
132. K. Kang, B. Paul, and K. Roy, ”Statistical Timing Analysis using Levelized Covariance Propagation
Considering Systematic and Random Variations of Process Parameters,” ACM Transactions on
Design Automation of Electronic Systems, vol. 11, no. 4, October 2006, pp. 848-879.
133. A. Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy, “Modeling of Pipeline Delay and Statistical
Design of Pipeline under Process Variations,” IEEE Transactions on Computer-Aided Design of
Integrated Circuits, November 2006, pp. 2427-2436.
31
134. M. Budnik and K. Roy, ”A Power Delivery and Decoupling Network Minimizing Ohmic Loss and
Supply Voltage Variation in Silicon Nanoscale Technologies,” IEEE Transactions on VLSI Systems,
December 2006, pp. 1336-1346.
135. A. Bansal, B. Paul, and K. Roy, “An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping,” IEEE Transactions on Computer-Aided Design of Integrated Circuits,
December 2006, pp. 2765-2774.
136. S. Bhunia, S. Ghosh, A. Raychowdhury, and K. Roy, ”A Novel Delay Fault Testing Methodology
Using Low-Overhead Built-In Delay Sensor,” IEEE Transactions on Computer-Aided design of
Electronic Circuits, December 2006, pp. 2934-2943.
137. H. Suzuki, C. H. Kim, and K. Roy, ”Fast Tag Comparators Using Diode Partitioned Domino for
64-Bit Microprocessors,” IEEE Transactions on Circuits and Systems – I, February 2007, pp. 322328.
138. B. Paul, K. Kang, H. Kufluoglu, M. Alam, and K. Roy, “Negative Bias Temperature Instability:
Estimation and Design for Improved Reliability of Nanoscale Circuits,” IEEE Transactions on
Computer-Aided Design of Integrated Circuits, April 2007, pp. 743-751.
139. A. Bansal, S. Mukhopadhyay, and K. Roy, ”Device-Optimization Technique for Robust and LowPower FinFET SRAM Design in NanoScale Era,” IEEE Transactions on Electron Devices, June
2007, pp. 1409-1419.
140. A. Agarwal, K. Kang, S. Bhunia, J. Gallagher, and K. Roy, ”Device-Aware Yield-Centric Dual
Vt Design Under Parameter Variations in Nanoscale Technologies,” IEEE Transactions on VLSI
Systems, June 2007, pp. 660-671.
141. S. Mukhopadhyay, K. Kim, H. Mahmoodi-Meimand, and K. Roy, ”Design of a Process Variation
Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS,” IEEE Journal of
Solid-State Circuits, June 2007, pp. 1370-1382.
142. A. Bansal and K. Roy, ”Analytical Sub-Threshold Potential Distribution Model for Gate Underlap
Double-Gate MOS Transistors,” IEEE Transactions on Electron Devices, July 2007, pp. 1793-1798.
143. S. Ghosh, S. Bhunia, and K. Roy, ”Low-Power and Testable Circuit Synthesis Using Shannon
Decomposition Based Structural Transformation,” ACM Transactions on Design Automation of
Electronic Systems, Volume 12 , Issue 4, September 2007.
144. K. Kang, H. Kufluoglu, K. Roy, and M. Alam, ”Impact of Negative-Bias temperature Instability
in Nanoscale SRAM Array,” IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, October 2007, pp. 1770-1781.
145. J. Kulkarni, K. Kim, and K. Roy, ”A 160 mV, Fully Differential, Robust, Schmitt Trigger Based
Sub-threshold SRAM,” IEEE Journal of Solid State Circuits, October 2007, pp. 2303-2313.
146. S. Ghosh, S. Bhunia, and K. Roy, ”CRISTA: A New Paradigm for Low-power, Variation-Tolerant
and Adaptive Circuit Synthesis Using Critical Path Isolation,” IEEE Transactions on ComputerAided Design of ICs, November 2007, pp. 1947-1956.
147. A. Datta, A. Goel, T. Cakici, H. Mahmoodi, D. Lekshmanan, and K, Roy, ”Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices,” IEEE Transactions on
Computer-Aided Design of Electronic Circuits, November 2007, pp. 1957-1966.
148. J. Choi, A. Bansal, M. Meterelliyoz, J. Murthy, and K. Roy, ”Self-consistent Approach for Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits,” IEEE
Transactions on Computer-Aided Design of ICs, November 2007, pp. 2059-2068.
149. J. Li, A. Bansal, and K. Roy, ”Poly-Si Thin Film Transistors: An Efficient and Low Cost Option
for Digital Operation,” IEEE Transactions on Electron Devices, November 2007, pp. 2918-2929.
32
150. A. Raychowdhury and K. Roy, ”Carbon Nanotube Electronics: Design of High-Performance and
Low-Power Digital Circuits,” IEEE Transactions on Circuits and Systems I – special issue on
Nano-electronic circuits and Nano-architectures, November 2007, pp. 2391-2401.
151. T. Cakici and K. Roy, ”Analysis of Options in Double Gate MOS Technology: A Circuit Perspective,” IEEE Transactions on Electron Devices, December 2007, pp. 3361-3368.
152. N. Banerjee and K. Roy, ”Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal Processing,” Journal of Low-Power Electronics, American Scientific Publishers, Volume 3, Number 3, December 2007 , pp. 254-270(17).
153. S. Mukhopadhyay, H. Mahoodi-Meimand, and K. Roy, ”Reduction of Parametric Failures in sub100nm SRAM using Body Biasing,” IEEE Transactions on Computer-Aided Design of ICs, Januanry 2008, pp. 174-183.
154. K. Kim, H. Mahmoodi-Meimand, and K. Roy, ”A Low-Power SRAM Using Bit-Line ChargeRecycling,” IEEE Journal of Solid-State Circuits, February 2008, pp. 446-459.
155. B. Paul and K. Roy, ”‘Oxide Thickness Optimization for Digital Subthreshold Operations,”’ IEEE
Transactions on Electron Devices, February, 2008, pp. 685-689.
156. A. Coker, V. Taylor, D. Bhaduri, S. Shukla, A. Raychowdhury, and K. Roy, ”‘Multijunction FaultTolerance Architecture for nanoscale Crossbar Memories,”’ IEEE Transactions on Nanotechnology,
March 2008, pp. 202-208.
157. Q. Chen, N. Mojumder, and K. Roy, ”Modeling and Analysis of Asymmetric Source/Drain Extension CMOS Transistors for Nano-Scale Technologies,” IEEE Transactions on Electron Devices,
April 2008, pp. 1005-1012.
158. A. Bansal, J. Kim, K. Kim, S. Mukhopadhyay, C. Chuang, and K. Roy, ”‘Optimal Dual-VT Design
in Sub-100nm PD/SOI and Double-Gate Technologies,”’ IEEE Transactions on Electron Devices,
May 2008, pp. 1161-1169.
159. S. Bhunia, H. Mahmoodi, A. Raychowdhury, and K. Roy, ”‘Arbitrary Two-Pattern Delay Testing Technique Using a Low-Overhead Supply Gating Technique,”’ Journal of Electronic Testing,
Springer-Verlag, June 25, 2008.
160. P. Ndai, S. Bhunia, a. Agarwal, and K. Roy, ”‘Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput,”’ IEEE Transactions on Computers, July 2008, pp.
940-951.
161. A. Datta, S. Bhunia, H. Choi, S. Mukhopadhyay, and K. Roy, ”‘Profit Aware Circuit Design Under
Process Variation Considering Speed Binning,”’ IEEE Transactions on VLSI Systems, July 2008,
pp. 806-815.
162. Q. Cao, H. Kim, N. Pimparkar, J. Kulkarni, C. Wang, M. Shim, K. Roy, M. Alam, and J. Rogers,
”‘Medium-scale Carbon Nanotube Thin-Film Circuits on Flexible Plastic Substrates,”’ Nature, July
2008, vol 454, pp. 495-499.
163. J. Li, S. Ghosh, A. Bansal, and K. Roy, ”An Alternate Paradigm for Low-Power, Low-Cost, Testable
Hybrid Systems using Scaled LTPS TFTs,” ACM Journal on Emerging Technologies in Computing,
Vol. 4, No. 3, August 2008.
164. S. Mukhopadhyay, K. Kim, K. Jenkins, C.-T. Chuang, and K. Roy, ”‘An On-chip Test Structure
and Digital Measurement method for Statistical Characterization of Local Random Variability in
Process,”’ IEEE Journal of Solid-State Circuits, September 2008, pp. 1951-1963.
165. J. Kulkarni, J. Kim, and K. Roy, ”Technology Circuit Co-Design for Ultra Fast InSb Quantum Well
Transistors,” IEEE Transactions on Electron Devices, October 2008, pp. 2537-2545.
33
166. J. Li, K. Kang, and K. Roy, ”Variation Estimation and Compensation Technique in Scaled LTPS
TFT Circuits for Low-Power Low-Cost Applications,” IEEE Transactions on Computer-Aided Design of ICs, Vol. 28, No. 1, January 2009.
167. J. Choi, N. Banerjee, and K. Roy, ”‘Variation-Aware Low-Power Synthesis Methodology for FixedPoint FIR Filters,”’ IEEE Transactions on Computer-Aided Design of IC’s, January 2009, pp.
87-97.
168. H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy, ”Ultra Low-Power Clocking Scheme
Using Energy recovery and Clock Gating,” IEEE Transactions on VLSI Systems, January 2009,
pp. 33-44.
169. I. Chang, J. Kim, S. Park, and K. Roy, ”A 32kb 10T Sub-Threshold SRAM Array with BitInterleaving and Differential Read Scheme in 90nm CMOS,” IEEE Journal of Solid-State Circuits,
February 2009, pp. 650-658.
170. A. Raychowdhury, V. De, J. Kurtin, S. Borkar, K. Roy, and A. Keshavarzi, ”‘Variation Tolerance in
a Multichannel Carbon-Nanotube Transistor for High-Speed Digital Circuits,”’ IEEE Transactions
on Electron Devices, March 2009, pp. 383-392.
171. S. f, A. Raychowdhury, and K. Roy, ”Compact Models Considering Incomplete Voltage Swing in
Complementary Metal Oxide Semiconductor Circuits at Ultralow Voltages: A Circuit Perspective
on Limits of Switching Energy,”’ Journal of Applied Physics (JAP, 105, 094901, 2009.
172. N. Banerjee, G. Karakonstantis, J.H. Choi, C Chakrabarti and K. Roy, Design Methodology for Low
Power Dissipation and Parametric Robustness through Output Quality Modulation: Application to
Color Interpolation Filtering, IEEE Transactions on Computer-Aided Design of IC’s, August 2009,
pp. 1127-1137.
173. N. Mojumder and K. Roy, ”Band-to-Band Tunneling Ballistic Nanowire FET: Circuit-Compatible
Device Modeling and Design of Ultra-Low Power Digital Circuits and Memories,” IEEE Transactions on Electron Devices, October 2009, pp. 2193-2201.
174. S. Raghunathan, S. Gupta, M. Ward, R. Worth, K. Roy and P. Irazoqui, The Design and Hardware Implementation of a Low-power Real-time Seizure Detection Algorithm, Journal of Neural
Engineering, 6 (2009) 056005.
175. S. Park, K. Kang, and K. Roy, ”Reliability Implications of Bias-temperature Instability in Digital
Circuits,” IEEE Design and Test of Computers, pp. 8-17, November-December 2009.
176. Y. Chen, H. Li, K. Roy, and C. Koh, ”Gated Decap: Gate Leakage Control of On-Chip Decoupling
Capacitors in Scaled Technologies,” IEEE Transactions on VLSI Systems, pp. 1749-1752, December
2009.
177. J. Li, P. Ndai, A. Goel, S. Salahuddin, and K. Roy, ”Design Paradigm for Robust Spin-Torque
Transfer Magnetic RAM (STT MRAM) from Circuit /Architecture Perspective,” IEEE Transactions on VLSI Systems, 2009, Digital Object Identifier: 10.1109/TVLSI.2009.2027907. 2013 IEEE
Transactions on VLSI Best paper Award.
178. N. Banerjee, G. Karakonstantis, and K. Roy, ”Process-Variation Resilient Voltage-Scalable Discrete
Cosine Transform Architecture for Robust Low-Power Computing,” IEEE Transactions on VLSI
Systems, 2009, Digital Object Identifier: 10.1109/TVLSI.2009.2025279.
179. S. Ghosh, D. Mohapatra, G. Karakonstantis, and K. Roy, ”Voltage Scalable High-Speed Robust
Hybrid Arithmetic Units Using Adaptive Clocking,” IEEE Transactions on VLSI Systems, 2009,
Digital Object Identifier: 10.1109/TVLSI.2009.2022531.
180. M. Hwang, S. Jung, and K. Roy, ”‘Slope Interconnect Effort: Gate-Interconnect Interdependent Delay,”’ IEEE Transactions on Circuits and Systems – I, 2009, Digital Object Identifier:
10.1109/TCSI.2008.2006217.
34
181. N. Mojumder, S. Mukhopadhyay, J. Kim, C. Chuang, and K. Roy, ”Self-Repairing SRAM using
On-Chip Detection and Compensation,” IEEE Transactions on VLSI Systems, January 2010, pp.
75-84 .
182. P. Ndai, N. Rafique, M. Thottethodi, S. Bhunia, S. Ghosh, and K. Roy, ”Trifecta: A Nonspeculative Scheme to Exploit Common Data-Dependent Subcritical Paths,” IEEE Transactions on VLSI
Systems, January 2010, pp.53-67.
183. M. Meterelliyoz, J. Kulkarni, and K. Roy, ”Analysis of SRAM and eDRAM Cache Memories Under
Spatial Temperature Variations,” IEEE Transactions on Computer-Aided Design of IC’s, January
2010, pp. 2-13.
184. K. Kang, S. Park, K. Kim, and K. Roy, ”On-Chip Variability Sensor Using Phase-Locked Loop
for Detecting and Correcting Parametric Timing Failures,” IEEE Transactions on VLSI Systems,
February 2010, pp.270-280.
185. M. Hwang and K. Roy, ”ABRM: Adaptive β-Ratio Modulation for process-Tolerant Ultradynamic
Voltage Scaling,” IEEE Transactions on VLSI Systems, February 2010, pp. 281-290.
186. I. Chang, J. Kim, S. Park, and K. Roy, ”Exploring Asynchronous Design Techniques for ProcessTolerant and Energy-Efficient Subthreshold Operation,” IEEE Journal of Solid State Circuits,
February 2010, pp. 401-410.
187. S. Gupta, A. Raychowdhury, and K. Roy, ”Digital Computation in Subthreshold Region for UltralowPower Operation: A device-Circuit-Architecture Codesign Perspective,” Proceedings of IEEE, February 2010, pp. 160-190. Invited Paper.
188. S. Choi, K. Kang, F. Dartu, and K. Roy, ”Timed Input Pattern Generation for Accurate Delay
Calculation under Multiple Input Switching,” IEEE Transactions on Computer-Aided Design of
IC’s, March 2010, pp. 497-501.
189. P. Ndai, A. Goel, and K. Roy, ”A Scalable Circuit-Architecture Co-design to Improve Memory Yield
for High-Performance Processors,” IEEE Transactions on VLSI Systems, Digital Object Identifier:
10.1109/TVLSI.2009.2022628, pp. 109-1218, August 2010.
190. M. Meterelliyoz, P. Song, F. Stellari, J. Kulkarni, and K. Roy, ”Characterization of Random Process
Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor,” IEEE
Trans. on Circuits and Systems 57-I(8): 1838-1847, 2010.
191. S. Ghosh, D. Mohapatra, G. Karakonstantis, and K. Roy, ”Voltage Scalable High-Speed Robust
Hybrid Arithmetic Units Using Adaptive Clocking,” IEEE Transactions on VLSI, pp. 1301-1309,
September 2010.
192. G. Karakonstantis, N. Banerjee, and K. Roy, ”Process-Variation Resilient & Voltage-Scalable DCT
Architecture for Robust Low-Power Computing,” IEEE Transactions on VLSI Systems, pp. 14611470, October 2010.
193. Y. Chen, H. Li, C.-K. Chen, K. Roy, J. Li and G. Sun, Variable-Latency Adder (VL-Adder): New
Arithmetic Circuit Design Practice for Low Power and NBTI Tolerance,IEEE Transactions on Very
Large Scale Integration (TVLSI) Systems, vol. 18, no. 11, October 2010, pp. 1621-1624.
194. S. Ghosh and K. Roy, ”Parameter Variation Tolerance and Error Resiliency: New Design Paradigm
for the Nano-Scale Era,” Proceedings of IEEE, pp. 1716-1751, October 2010.
195. I. Chang, J. Park, K. Kang, and K. Roy, ”’Fast and Accurate Estimation of SRAM Read and Hold
Failure Probability using Critical Point Sampling,” IET Circuits, devices & Systems, 2010, Volume
4, Issue 6, pp. 469-478.
35
196. S. Raghunathan, S. Gupta, H. Markendeya, K. Roy, and P. Irazoqui,” A Hardware-Algorithm codesign Approach to Optimize Seizure Detection Algorithms for Implantable Applications, Journal
of Neuroscience Methods, Vol. 193, Issue 1 Oct 2010, pp. 106-117.
197. Y. Chen, H. Li, C. Koh, G. Sun, J. Li, and K. Roy, ”Variable-Latency Adder (VL-Adder) Designs for
Low Power and NBTI Tolerance,” IEEE Transactions on VLSI Systems, pp. 1621-1624, November
2010.
198. N. Mojumder, C. Augustine, D. Nikonov, and K. Roy, ”Electronic Transport and Effect of Quantum
Confinement in Dual Barrier Resonant Tunneling Spin-Torque-Transfer Magnetic Tunnel Junctions,
Journal of Applied Physics (JAP), November 2010.
199. I. Chang, D. Mohapatra, and K. Roy, ”Priority-Based 6T/8T Hybrid SRAM Architecture for
Aggressive Voltage Scaling in Video Application,” IEEE Transactions on Circuits and Systems for
Video Technology, pp. 101-112, February 2011.
200. G. Panagopolous and K. Roy, ”A Physics-Based Three-Dimensional Analytical Model for RDF
Induced Threshold Voltage Variations,” IEEE Transactions on Electron Devices, February 2011,
pp. 392-403 .
201. A. Goel, S. Gupta, and K. Roy, ”Asymmetric Drain Spacer Extension (ADSE) FinFETs for LowPower and Robust SRAMs,” IEEE Transactions on Electron Devices, February 2011, pp. 296-309.
202. G. Karakonstantis, A. Chatterjee, and K. Roy, ”Containing the nanometer Pandora-Box: Design
Techniques for Variation Aware Low Power Systems,” IEEE Journal on Emerging and Selected
Topics in Circuits and Systems, Invited paper, pp. 19-29, March 2011.
203. S. Raghunathan, S. Gupta, H. Markendeya, P. Iraqozui, and K. Roy, ”Ultra Low-Power Algorithm Design for Implantable Devices: Application to Epilepsy Prostheses,” Journal of Low Power
Electronics and Applications, ISSN 2079-9268, April 2011.
204. N. Mojumder, S. Gupta, H. Choday, D. Nikonov, and K. Roy, ”A Three Terminal Dual Pillar
Spin-Transfer Torque (STT) MRAM for High Performance, Robust Memory Applications,” IEEE
Transactions on Electron Devices, pp. 1508-1516, May 2011.
205. S. Kim, S. Baytok, and K. Roy, ”Thin Box Poly-Si Thin-Film Transistors for CMOS-compatible
Analog Operations,” IEEE Transactions on Electron Devices, pp. 1687-1698, June 2011.
206. C. Augustine, X. Fong, B. Behin-Aein, K. Roy, Ultra-low Power Nano-magnet Based Computing:
A System-Level Perspective, IEEE Transactions on Nanotechnology, July 2011, pp. 778-788.
207. I. Chang, J. Kim, K. Kim, and K. Roy, ”Robust Level Converter for Sub-Threshold/Super-Threshold
Operation:100 mV to 2.5 V,” IEEE Transactions on VLSI Systems, August 2011, pp. 1429-1437.
208. S. Raghunathan, S. Gupta, H. Markandeya, P. Irazoqui and K. Roy, ”Ultra Low-Power Algorithm
Design for Implantable Devices: Application to Epilepsy Prostheses,” Journal of Low Power Electronics and Applications, 2011, 1(1), MDPI Publishing, Basel, Switzerland, pp. 175-203.
209. S. Ghosh and K. Roy, ”Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel
Prefix Adders Using Selective Redundancy and Adaptive Clocking,” IEEE Transactions on VLSI
Systems, August 2011, pp. 1504-1507.
210. G. Panagopolous and K. Roy, ”A Three-Dimensional Physical Model for Vth Variations Considering
the Combined Effect of NBTI and RDF,” IEEE Transactions on Electron Devices, August 2011,
pp. 2337-2346.
211. J. Kulkarni, A. Goel, P. Ndai, and K. Roy, ”A Read-Disturb-Free, Differential Sensing, 1R/1W
Port 8T SRAM Array,” IEEE Transactions on VLSI Systems, September 2011, pp. 17-27-17-30.
36
212. C. Lu, V. Raghunathan, and K. Roy, ”Efficient Design of Micro-scale Energy Harvesting Systems,”
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Sepetember 2011, pp.
254-266. (Invited Paper).
213. S. Gupta, S. Park, and K. Roy, ”Tri-Mode Independent Gate (TMIG) FinFETs for Dynamic Voltage/Frequency Scalable 6T SRAMs,” IEEE Transactions on Electron Devices, November 2011, pp.
3837 - 3846.
214. F. Moradi, S. Gupta, G. Panagopoulos, D. Wesland, H. Mahmoodi, and K. Roy, ”Asymmetrically Doped FinFETs for Low-Power Robust SRAMs,” IEEE Transactions on Electron Devices,
December 2011, pp. 4241 - 4249.
215. C. Augustine, A. Raychowdhury, D. Somasekhar, J. Tschanz, V. De and K. Roy, Design Space
Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and
Disturbances, IEEE Transactions on Electron Devices (TED), December, 2011.
216. C. Augustine, N. N. Mojumder, X. Fong, H. Choday, S. P. Park and K. Roy, Spin-Transfer Torque
MRAMs for Low Power Memories: Prospects and Perspective, IEEE Sensors Journal, April 2012,
pp. 756-766.
217. S.P. Park, D. Lee, and K. Roy, ”Soft Error Resilient FPGAs using Built-in 2D Hamming Product
Code,” IEEE Transactions on Very Large Scale Integration Systems, Issue 2, 2012, pp. 248 - 256.
218. J. Kulkarni and K. Roy, ”Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM
Design,” IEEE Transactions on VLSI Systems, Issue 2, 2012, pp. 319 - 332.
219. D. Lee and K. Roy, ”Viterbi-Based Efficient Test Data Compression,” IEEE Transactions on
Computer-Aided Design of IC’s, April 2012, pp. 610-619.
220. W. Griffin, A. Raghunathan, and K. Roy, ””CLIP: Circuit Level IC Protection through Direct
Injection of Process Variations,” IEEE Transactions on VLSI Systems, May 2012, pp. 791-804.
221. N. Mojumder, D. Abraham, K. Roy, and D. Worledge, ”Magnonic spin-transfer Torque MRAM
with Low Power, High Speed, and Error-free switching,” IEEE Transactions on Magnetics, June
2012, pp. 2016-2025.
222. M. Sharad, S. K. Gupta, S. Raghunathan, P. Irazoqui, K. Roy, ” Low-Power Architecture for
Epileptic Seizure Detection Based on Reduced Complexity DWT” , ACM Journal on Emerging
Technologies in Computing Systems, Vol 8, No. 2, June 2012, pp. 10-1-10-14.
223. M. Sharad, C. Augustine, G. Panagopoulos, and K. Roy, ”Spin-Based Neuron Model with Domain
Wall Magnets as Synapse,” IEEE Transactions on Nanotechnology, July 2012, pp. 843-853.
224. S. Kim, W. Lok, B. Jung, and K. Roy, ”High-Frequency Modeling of Poly-Si Thin Film Transistors
for Low-Cost RF Applications,” IEEE Transactions on Electron Devices, September 2012, pp.
2296-2301.
225. C.-H. Ho, G. Panagopoulos, and K. Roy, ”A Physical Model for Grain Boundary Induced Threshold
Voltage Variation in Poly-silicon Thin-Film Transistors,” IEEE Transactions on Electron Devices,
Sepetember 2012, pp. 2396-2402.
226. S. Gupta, G. Panagopoulos, and K. Roy, ”NBTI in n-type SOI Access FinFETs in SRAMs and its
Impact on Cell Stability and Performance,” IEEE Transactions on Electron Devices, October 2012,
pp. 2603-2609.
227. N. Mojumder and K. Roy, ”Proposal for Switching Current Reduction Using Reference Layer
With Tilted Magnetic Anisotropy in Magnetic Tunnel Junctions for Spin-Transfer Torque (STT)
MRAM,” IEEE Transactions on Electron Devices, November 2012, pp. 3054-3060.
37
228. S. Gupta, J. Kulkarni, S. Datta, and K. Roy, ”Heterojunction Intra-Band Tunnel (HIBT) FETs for
Low Voltage SRAMs,” IEEE Transactions on Electron Devices, December 2012, pp. 3533 - 3542.
229. N. Mojumder, K. Roy, and D. Abraham, ”Thermoelectric Spin-Transfer Torque MRAM with Fast
Bidirectional Writing Using Magnonic Current,” IEEE Transactions on Magnetics, January 2013,
pp. 483-488. (Cover Story)
230. V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy, ”Low-Power Digital Signal Processing
using Approximate Adders,” IEEE Transactions on Computer-Aided Design of IC’s, January 2013,
pp. 124 - 137.
231. X. Fong, S.H. Choday, and K. Roy, ”Bit-Cell Level Optimization for Non-volatile Memories Using
Magnetic Tunnel Junctions and Spin-Transfer Torque Switching,” IEEE Transactions on Nanotechnology, January 2013, pp. 172-181.
232. C. Ho, G. Panagopoulos, and K. Roy, ”A Self-Consistent Electro-Thermal Model for Analyzing
NBTI Effect in P-Type Poly-Si Thin-Film Transistors,” IEEE Transactions on Electron Devices,
January 2013, pp. 288 - 294.
233. K. Roy, B. Jung, D. Peroulis, and A. Raghunathan, ”Integrated Systems In The More-Than-Moore
Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components,” IEEE Design and Test, 2013, Digital Object Identifier: 10.1109/MDT.2011.49.
234. X. Fong and K. Roy, ”Complimentary Polarizers STT-MRAM (CPSTT) for On-Chip Caches,”
IEEE Electron Device Letters, February 2013, pp. 232 - 234.
235. N. Mojumder, X. Fong, C. Augustine, S. Gupta, S.C. Choday, and K. Roy, ”Dual Pillar SpinTransfer Torque MRAMs for Low Power Applications,” Journal on Emerging Technologies in Computing Systems (JETC), May 2013, pp. 14-1:14-17.
236. S.H. Choday and K. Roy, ”Sensitivity Analysis and Optimization of Thin-Film Thermoelectric
Coolers,” Journal of Applied Physics (JAP), June 2013.
237. M. Sharad and K. Roy, ”Spintronic Switches for Ultralow Energy On-Chip and Inter-Chip Current
Mode Interconnects,” IEEE Electron Device Letters (EDL), August 2013, 1068-1070.
238. G. Panagopoulos, C. Augustine, and K. Roy, ”Physics-based SPICE-compatible Compact Model
for Simulating Hybrid MTJ/CMOS Circuits,” IEEE Transactions on Electron Devices, September
2013, pp. 2808 - 2814.
239. D. Lee and K. Roy, ”An Area Efficient ROM-Embedded SRAM Cache,” IEEE Transactions on
VLSI Systems, September 2013, 1583 - 1595.
240. D. Lee, X. Fong, and K. Roy, ”R-MRAM: A ROM-Embedded STT MRAM Cache,” IEEE Electron
Device Letter (EDL), October 2013, pp. 1256-1258.
241. M. Sharad, K. Yogendra, and K. Roy, ”Dual Pillar Spin Torque Nano-oscillator,” Applied Physics
Letters (APL), 103, 152403 (2013).
242. M. Sharad, D. Fan, and K. Roy, ”Spin-neurons: A Possible Path to Energy-efficient Neuromorphic
Computers,” JOURNAL OF APPLIED PHYSICS, 114, 234906 (2013).
243. Y. Kim, S.H. Choday, and K. Roy, ”DSH-MRAM: Differential Spin Hall MRAM for On-chip Memories,” IEEE Electron Device Letter (EDL), October 2013, pp. 1259-1261.
244. S.Narasimhan, D. Du, R. Chakraborty, S. Paul, F. Wolff, C. Papachristou, K. Roy, and S. Bhunia,
”Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis,” IEEE Transactions
on Computers, November 2013, pp. 2183-2195.
38
245. S. Gupta and K. Roy, ”Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs,”
IEEE Design and Test, November-December 2013, pp. 18-28.
246. S.H. Choday, M. Lundstrom, and K. Roy, ”Prospects of Thin-film Thermoelectric Devices for HotSpot Cooling and On-chip Energy Harvesting,” IEEE Transactions on Components, Packaging and
Manufacturing Technology, December 2013, pp. 2059-2067.
247. S. Kim, C. Ho, and K. Roy, ”Statistical SBD Modeling and Characterization and Its Impact on
SRAM Cells,” IEEE Transactions on Electron Devices, January 2014, pp. 54-59.
248. C. Ho, C. Lu, and K. Roy, ”An Enhanced Voltage Programming Pixel Circuit for Compensating GBInduced Variations in Poly-Si TFTs for AMOLED Displays,” IEEE Journal of Display Technology,
January 2014, pp. 345-351.
249. M. Sharad, D. Fan, K. Aitken, and K. Roy, ” Energy-Efficient Non-Boolean Computing with Spin
Neurons and Resistive Memory,” IEEE Transactions on Nanotechnology, January 2014, pp. 23-34.
250. X. Fong, Y. Kim, S.H. Choday, and K. Roy, ”Failure Mitigation Techniques for 1T-1MTJ SpinTransfer Torque MRAM Bit-cells,” IEEE Transactions on VLSI Systems, February 2014, pp. 384395.
251. K. Kwon, Y. Kim, H. Choday, X. Fong, S. Park, and K. Roy, ”SHE-NVFF: Spin Hall Effect based
Nonvolatile Flip Flop for Power Gating Architecture,” IEEE Electron Device Letters (EDL), April
2014, pp. 488-490.
252. D. Fan, M. Sharad, and K. Roy, ”Design and Synthesis of Ultra Low Energy Spin-Memristor
Threshold Logic,” IEEE Transactions on Nanotechnology, May 2014, pp. 574-583.
253. M. K. Hassan, C.-H. Ho, and K. Roy, Stochastic Modeling of Positive Bais Temperature Instability
in High-k Metal Gate nMOSFETs, IEEE Trans. Electron Devices, July 2014, pp. 2243-2249.
254. D. Lee and K. Roy, Energy-Delay Optimization of STT MRAM Write Operation Under Process
Variations, IEEE Transactions on Nanotechnology, July 2014, pp. 714-723.
255. C. Ho, K. Hassan, S. Kim, and K. Roy, , ”Analysis of Stability Degradation of SRAMs Using a
Physics-based PBTI Model,” IEEE Electron Device Letters, September 2014, pp. 951-953.
256. V. Chippa, D. Mohapatra, K. Roy, S. Chakradhar, and A. Raghunathan, ”Scalable Effort Hardware
Design,” IEEE Transactions on VLSI Systems, September 2014, pp. 2004-2016.
257. R. Venkatesan, V. Chippa, K. Roy, and A. Raghunathan, ”Domain-Specific Many-core Computing
using Spin-based Memory,” IEEE Transactions on Nanotechnology, September 2014, pp. 881-894.
258. S.H. Choday, S. Gupta, and K. Roy, ”Write-Optimized STT-MRAM Bit-cells Using Asymmetrically
Doped Transistors,” IEEE Electron Device Letters, October 2014, pp 1100-1102.
259. Z. Azim, X. Fong, T. Ostler, R. Chantrell, and K. Roy, ”Laser Induced Magnetization Reversal for
Detection in Optical Interconnects,” IEEE Electron Device Letters, October 2014, pp. 1317-1319.
260. X. Fong, R. Vankatesan, A. Raghunathan, and K. Roy, ”Non-volatile Complementary Polarizer
Spin-Transfer Torque (CPSTT) On-chip Caches: A Device/Circuit/Systems Perspective,” IEEE
Transactions on Magnetics, October 2014, p. 3400611.
261. M. Sharad and K. Roy, ”Spintronic Sswitches for Ultra Low Energy Global Interconnects,” Journal
of Applied Physics, 2014, Vol. 115, Issue 17, Page(s): 17C737 - 17C737-3
262. A. Sharma, A. Akkala, and K. Roy, ”GaSb-InAs n-TFET with Doped Source Underlap Exhibiting
Low Sub-threshold Swing at Sub-10nm Gate-Lengths” IEEE Electron Device Letters, December
2014, pp. 1221-1223.
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263. F. Botman, D. Bol, J. Legut, and K. Roy, ”Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits,” IEEE Transactions
on VLSI Systems, December 2014, pp. 2561-2570.
264. W. Cho, S. Gupta, and K. Roy, ”Device-Circuit Analysis of Double-Gate MOSFETs and SchottkyBarrier FETs: A Comparison Study for Sub-10nm Technologies,” IEEE Transactions on Electron
Devices, December 2014, pp. 4025-4031.
265. S. Kim, and K. Roy, ”A Low-Cost Low-Noise Amplifier in Poly-Si TFT Technology,” IEEE Journal
of Display Technology, Vol. 10, No. 12, December 2014.
266. G. Panagopoulos, C. Ho, S. Kim, and K. Roy, ”Physics-Based Compact Modeling of Successive
Breakdown in Ultrathin Oxides,” IEEE Transaction on Nanotechnology, January 2015, pp. 7-10.
267. H. Markandeya, P.Irazoqui, and K. Roy, ”Low-Energy Two-StageAlgorithm for High Efficacy
Epileptic Seizure Detection,” IEEE Transaction on VLSI Systems, January 2015, pp.208-212.
268. Y. Seo, X. Fong, and K. Roy, ”Domain Wall Coupling based STT-MRAM for On-Chip Cache
Applications,” IEEE Transactions on Electron Devices, February 2015, pp. 5-16.
269. Y. Kim, X. Fong, K. Kwon, M. Chen, and K. Roy, ”Multi-level Spin-Orbit Torque MRAMs”, IEEE
Transactions on Electron Devices, February 2015, pp. 561-567.
270. Y. Kim, X. Fong, and K. Roy, ”Spin-Orbit-Torque Based Spin-Dice: A True Random Number
Generator,” IEEE Magnetics Letters, 6, 1-4, 2015.
271. A. Sengupta, Z. Azim, X. Fong, and K. Roy, ”Spin-orbit Torque Induced Spike-Timing Dependent
Plasticity,” Applied Physics Letters, March 2015.
272. K. Roy, D. Fan, X. Fong, Y. Kim, M. Sharad, M. Paul, S. Chatterjee, S. Bhunia, S. Mukhopadhyay, ”Exploring Spin Transfer Torque Devices for Unconventional Computing,” IEEE Journal of
Emerging and Selected Topics in Circuits and Systems (JETCAS), invited paper, March 2015.
273. A. Sengupta, Z. Azim, X. Fong, and K. Roy, ”Spin Orbit Torque Based Electronic Neuron,” Applied
Physics Letters, April 2015.
274. Y. Seo, K. Kwon, and K. Roy, ”Spin Hall MRAMs with Dual Read/Write Ports for On-chip Caches,”
IEEE Magnetics Letters, Vol 6, April 2015.
275. W. Cho and K. Roy, ”The Effects of Direct Source-to-Drain Tunneling and Variation in Body
Thickness on (100) and (110) Sub-10nm Double-Gate Transistors”, IEEE Electron Device Letters,
May 2015, pp. 427-429.
276. X. Fong, R. Venkatesan, D. Lee, A. Raghunathan, and K. Roy, ”Embedding Read-Only Memory in
Spin-Transfer Torque MRAM Based On-chip Caches,” IEEE Transactions on VLSI Systems, June
2015.
277. L. Zhang, X. Fong, C. Chang, Z. Kong, and K. Roy, ”Optimizing emerging Nonvolatile Memories
for dual-Mode Applications: Data Storage and Key Generator”, IEEE Transactions on ComputerAided Design of Integrated Circuits, July 2015, pp. 1176-1187.
278. M. Sharad, D. Fan, and K. Roy, ” Energy-Efficient and Robust Associative Computing with
Injection-Locked Dual Pillar Spin-Torque Oscillators,” IEEE Transactions on Magnetics, July 2015,
3400609.
279. R. Venkatesan, M. Sharad, K. Roy, and A. Raghunathan, ”Dense, Energy-efficient All-Spin Cache
Hierarchy using Shift based Writes and Multi-Level Storage,” ACM Journal of Emerging Technologies, July 2015, Vol. 12, Issue 1, Article 4.
40
280. L. Zhang, X. Fong, C. Chang, Z. Kong, and K. Roy, ”Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function with Mult-Response Bits,” IEEE Transactions on
Information Forensics and Security, August 2015, pp. 1630-1642.
281. Z. Pajouhi, S. Venkatramani, K. Yogendra, A. Raghunathan, and K. Roy, ”Exploring Spin-TransferTorque Devices for Logic Applications,” IEEE Transactions on Computer Aided Design of IC’s,
September 2015, pp. 1441-1454.
282. K. Yogendra, D. Fan, and K. Roy, ”Coupled Spin Torque Nano Oscillators for Low Power Neural
Computation,” IEEE Transactions on Magnetics, October 2015, pp. 4003909.
283. M. Chen, Y. Kim, K. Yogendra, and K. Roy, ”Domino-Style SpinOrbit Torque-Based Spin Logic,”
IEEE Magnetics Letters, Vol. 6, 2015.
284. D. Fan, S. Maji, K. Yogendra, M. Sharad, and K. Roy, ,”Injection Locked, Spin Hall Induced
Coupled-Oscillators for Energy Efficient Associative Computing”, IEEE Transactions on Nanotechnology, November 2015, pp. 1083-1093.
285. K. Kwon, X. Fong, P. Wajesinghe, P. Panda, and K. Roy, ,”High-Density and Robust STT-MRAM
Array Through Device/Circuit/Architecture Interactions”, IEEE Transactions on Nanotechnology,
November 2015, pp. 1024-1034.
286. D. Fan, Y. Shim, A. Raghunathan, and K. Roy, ””STT-SNN: A Spin-Transfer-Torque Based SoftLimiting Non-Linear Neuron for Low-Power Artificial Neural Networks,” IEEE Transactions on
Nanotechnology, November 2015, pp. 1013-1023.
287. X. Fong, Y. Kim, K. Yogendra, D. Fan, A. Sengupta, A. Raghunathan, and K. Roy, ”SpinTransfer Torque Devices for Logic and Memory: Prospects and Perspectives,” IEEE Transactions
on Computer-Aiided Design of Integrated Circuits, January 2016, pp. 1-22, Keynote Paper.
288. J. Kwon, S. Goolaup, G. Lim, I. Kerk, C. Chang, K. Roy, and W. Lew, ”Low Field Domain Wall
Dynamics in Artificial Spin-Ice Basis Basis Structure,” Journal of Applied Physics 118.
289. Z. Azim, A. Sengupta, S. Sarwar, and K. Roy, ”Spin-Torque Sensors for Energy Efficient High
Speed Long Interconnects,” IEEE Transactions on Electron Devices, February 2016, pp. 800-808.
290. A. Sengupta and K. Roy, ”Short-Term Plasticity and Long-Term Potentiation in Magnetic Tunnel
Junctions: Towards Volatile Synapses”, Physical Review Applied, Vol. 5, Iss. 2, pp. 024012, 2016.
291. A. Akkala, R. Venkatesan, A. Raghunathan, and K. Roy, ”Asymmetric Underlapped Sub-10-nm
n-FinFETs for High-Speed and Low-Leakage 6T SRAMs,” IEEE Transactions on Electron Devices,
March 2016, pp. 1034-1040.
292. A. Reza, Z. Azim, X. Fong, and K. Roy, ”Modeling and Evaluation of Topological Insulator/Ferromagnet
Heterostructure Based Memory,” IEEE Transactions on Electron Devices, March 2016, pp. 13591367.
293. E. Mungan, C. Lu, C. Ho, and K. Roy, ”Effects of Deposition Process on Poly-Si Microscale Energy
Harvesting System: A Simulation Study,” IEEE Transactions on Electron Devices, April 2016, pp.
1650-1657.
294. Y. Seo, X. Fong, and K. Roy, ”High Performance and Energy-Efficient On-Chip Cache using Dual
Port SOT-MRAM”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, April
2016, pp. 1-12.
295. K. Yogendra, D. Fan, B. Jung, and K. Roy, ”Magnetic Pattern Recognition using Injection Locked
Spin Torque Nano-Oscillators,” IEEE Transactions on Electron Devices, April 2016, pp. 1674-1680.
41
296. R. Venkatesan, V. Kozhikkottu, M. Sharad, C. Augustine, A. Raychowdhury, K. Roy, and A.
Raghunathan, ”Cache Design with Domain Wall Memory,” IEEE Transactions on Computers,
April 2016, pp. 1010-1024.
297. K. Roy, B. Jung, D. Peroulis, and A. Raghunathan, ”Integrated Systems in the More-Than-Moore
Era: Designing Low-Cost Energy Efficient Systems Using Heterogeneous Components,” IEEE Design and Test, May/June 2016, pp. 56-65.
298. A. Jaiswal, X. Fong, and K. Roy, ”Comprehensive Scaling Analysis of Current Induced Switching in
Magnetic Memories based on In-plane and Perpendicular Anisotropies,” IEEE Journal on Emerging
and Selected Topics in Circuits and Systems, June 2016, pp. 120-123.
299. C. Ho, S. Kim, G. Panagopoulos, and K. Roy, ”Statistical TDDB Degradation in Memory Circuits:
Bit-Cells to Arrays,” IEEE Transactions on Electron Devices, June 2016, pp. 2384-2390.
300. A. Sharma, A. Akkala, J. Kulkarni, and K. Roy, ”Source-Underlapped GaSb-InAs TFETs with
Application to Gain Cell Embedded DRAMs,” IEEE Transactions on Electron Devices, June 2016,
pp. 2563-2569.
301. A. Sharma, A. Reza, and K. Roy, ” Proposal of an Intrinsic-Source Broken-Gap Tunnel FET to
Reduce Band Tail Effects on Subthreshold Swing: A Simulation Study,” IEEE Transactions on
Electron Devices, June 2016, pp. 2597-2602.
302. X. Fong, Y. Kim, R. Venkatesan, S. Choday, A. Raghunathan, and K. Roy, ”Spin-Transfer Torque
Memories: Devices, Circuits, and Systems,” Proceedings of IEEE, July 2016, pp. 1449-1488.
303. W. Cho and K. Roy, ”Device-Circuit Cosimulation for Energy Efficiency in Sub-10-nm Gate Length
Logic and Memory,” IEEE Transactions on Electron Devices, July 2016, pp. 2879-2886.
304. A. Sengupta, M. Parsa, B. Han, and K. Roy, ”Probabilistic Deep Spiking Neural Systems Enabled
by Magnetic Tunnel Junctions,” IEEE Transactions on Electron Devices, July 2016, pp. 2963-2970.
305. G. Srinivasan, A. Sengupta, and K. Roy, ”Magnetic Tunnel Junction Based Long-Term Short-Term
Stochastic Synapse for a Spiking Neural Network with On-Chip STDP Learning,” Scientific Reports,
July 2016.
306. A. Sengupta, P. Panda, P. Wijesinghe, Y. Kim, and K. Roy, ”Magnetic Tunnel Junction Mimics
Stochastic Cortical Spiking Neurons,” Scientific Reports, July 2016.
307. H. Markendeya and K. Roy, ”, ”Low-power System for Detection of Symptomatic Patterns in Audio
Biological Signals,” IEEE Transactions on VLSI Systems, August 2016, pp. 2679-2688.
308. Y. Seo, K. Kwon, and K. Royt, ”Area-Efficient SOT-MRAM with Schottky Diode,” IEEE Electron
Device Letters, August 2016, pp. 982-984.
309. D. Fan, M. Sharad, A. Sengupta, and K. Roy, ”Hierarchical Temporal Memory Based on Spin
Neurons and Resistive Memory for Energy-Efficient Brain Inspired Computing,” IEEE Transactions
on Neural Networks, September 2016, pp. 1907-1919.
310. S. Sharmin, A. Jaiswal, and K. Roy, ”Modeling and Design Space Exploration of Bit-Cells Based on
Voltage-Assisted Switching of Magnetic Tunnel Junctions,” IEEE Transactions on Electron Devices,
September 2016, pp. 3493-3500.
311. Y. Seo, K. Kwon, X. Fong, and K. Roy, ”High Performance and Energy-Efficient On-Chip Cache
Using Dual Port (1R/1W) Spin Orbit Torque MRAM,” IEEE Journal on Emerging and Selected
Topics in Circuits and Systems, September 2016, pp. 293-304.
312. Z. Azim, A. Sharma, and K. Roy, Buffered Spin-Torque Sensors for Minimizing Delay and Energy
Consumption in Global Interconnects,” IEEE Magnetics Letters, DOI: 10.1109/LMAG.2016.2620427,
October 2016.
42
313. A. Sengupta, Y. Shim, and K. Roy, ”Proposal for an All-Spin Artificial Neural Network: Emulating Neural and Synaptic Functionalities through Domain Wall Motion in Ferromagnets,” IEEE
Transactions on Biomedical Circuits and Systems, December 2016, pp. 1151-1160.
314. A. Sengupta and K. Roy, ”A Vision for All-Spin Neural Networks: A Device to Systems Perspective,” IEEE Transaction on Circuits and Systems I, December 2016, pp. 2267-2277.
315. A. Sengupta, A. Banerjee, and K. Roy, ”Hybrid Spintronic-CMOS Spiking Neural Network with
On-chip Learning: Devices, Circuits, and Systems,” Physical Review Applied 6, 064003, December
2016.
316. A. Jaiswal and K. Roy, ”MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin
Logic,” Scientific Reports, January 2017.
317. Z. Azim, M. Chen, and K. Roy, ”Skyrmion Sensor based Low Power Global Interconnects,” IEEE
Transactions on Magnetics, Paper 1500106, January 2017.
318. M. Radfar, K. Yogendra, and K. Roy, ”Stochastic Quantization using Magnetic Tunnel Junction
Devices: A Simulation Study,” IEEE Transactions on Magnetics, paper 4400206, March 2017.
319. A. Jaiswal, S. Roy, G. Srinivasan, and K. Roy, ”Proposal for a Leaky-Integrate-Fire Spiking Neuron
based on Magneto-Electric Switching of Ferro-magnets,” IEEE Transactions on Electron Devices,
April 2017, pp. 1818-1824.
320. Y. Seo, X. Fong, and K. Roy, ”Fast and Disturb-Free Nonvolatile Flip-Flop using Complementary
Polarizer MTJ,” IEEE Transactions on VLSI Systems, April 2017, pp. 1573-1577.
321. P. Panda, A. Sengupta, and K. Roy, ”Energy-efficient and Improved Image Recognition with Conditional Deep Learning,” ACM Journal on Emerging Technologies in Computing Systems (JETC) Special Issue on Hardware and Algorithms for Learning On-a-chip and Special Issue on Alternative
Computing Systems, Volume 13, Issue 3, May 2017.
322. A. Reza, K. Hassan, and K. Roy, ”Bttiker Probe Based Modeling of TDDB: Application to Dielectric Breakdown in MTJs and MOS Devices,” IEEE Transactions on Electron Devices, DOI:
10.1109/TED.2017.2715164, August 2017, pp. 3337-3346.
323. Y. Shim, A. Jaiswal, and K. Roy, ”Ising Computation based Combinatorial Optimization using
Spin-Jall Effect (SHE) Induced Stochastic Magnetization Reversal,” Journal of Applied Physics,
121, 193902, published online May, 2017.
324. J. Kwon, S. Goolaup, F. Tan, C. Chang, K. Roy and W. Lew, ”Cyclic Resistance Change in
Perpendicularly Magnetized Co/Ni Nanowire Induced by Alternating Current Pulse Injection,”
Current Applied Physics, 17 (1), 98-102.
325. P. Panda, S. Venkatramani, A. Sengupta, A. Raghunathan, and K. Roy, ”Energy Efficient Object
Detection using Semantic Decomposition,” IEEE Transactions on VLSI Systems, DOI: 10.1109/TVLSI.2017.2707077,
September 2017.
326. P. Panda, A. Ankit, P. Wijesinghe, and K. Roy, ”FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition,” IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, to appear.
327. A. Sharma and K. Roy, ”Design Space Exploration of Hysteresis-Free HfZrOx-based Negative Capacitance FETs,” IEEE Electron Device Letters, DOI: 10.1109/LED.2017.2714659, August 2017,
1165-1167.
328. K. Yogendra, C. Liyanagendra, D. Fan, Y. Shim, and K. Roy, ”Coupled Spin-Torque NanoOscillator-Based Computation: A Simulation Study,” ACM Journal on Emerging Technologies in
Computing Systems (JETC), Volume 13 Issue 4, August 2017, Article No. 56
43
329. Fan Zuo, Priyadarshini Panda, Michele Kotiuga, Jiarui Li, Min Gu Kang, Claudio Mazzoli, Hua
Zhou, Andi Barbour, Stuart Wilkins, Badri Narayanan, Mathew Cherukara, Zhen Zhang, Subramanian KRS Sankaranarayanan, Riccardo Comin, Karin M Rabe, Kaushik Roy, Shriram Ramanathan,
”Habituation Based Synaptic Plasticity and Organismic Learning in a Quantum Perovskite,” Nature
Communications, June 2017.
330. S. Sharmin, Y. Shim, and K. Roy, ”Magnetoelectric Oxide based Stochastic Spin Device towards Solving Combinatorial Optimization Problems,” Scientific Reports 7, Article number: 11276,
September 2017.
331. A. Sengupta, C. Liyanagendra, B. Jung, and K. Roy, ”Magnetic Tunnel Junction as an On-Chip
Temperature Sensor,” Scientific Reports 7, Article number: 11764, September 2017.
332. Y. Shim, S. Chen, A. Sengupta, and K. Roy, ”Stochastic Spin-Orbit Torque Devices as Elements
for Bayesian Inference,” Scientific Reports, Article number: 14101, October 2017.
333. A. Jaiswal, A. Agrawal, and K. Roy, ”Robust and Cascadable Non-volatile Magneto-Electric Majority Logic,” IEEE Transactions on Electron Devices, December 2017, pp. 5209 - 5216.
334. C. Liyanagendra, A. Sengupta, A. Jaiswal, and K. Roy, ”Stochastic Spiking Neural Networks Enabled by Magnetic Tunnel Junctions: From Nontelegraphic to Telegraphic Switching Regimes,”
Phys. Rev. Applied 8, 064017, December 2017.
335. P. Panda and K. Roy, ”Learning to Generate Sequences with Combination of Hebbian and nonHebbian Plasticity in Recurrent Spiking Neural Networks,” Frontiers in Neuroscience, December
2017, Article 693.
336. A. Raha, A. Jaiswal, S. Sarwar, H. Jayakumar, V. Raghunathan, and K. Roy, ”Designing EnergyEfficient Intermittently Powered Systems using Spin Hall Effect based Non-Volatile SRAM,” IEEE
Transactions on VLSI Systems, February 2018, pp. 294-307.
337. A. Sengupta and K. Roy, ”Neuromorphic Computing Enabled by Physics of Electron Spins: Prospects
and Perspectives,” Applied Physics Express, Volume 11, Number 3, Februray 2018.
338. S. Jain, A. Ranjan, K. Roy, and A. Raghunathan, ”Computing in Memory with Spin-Transfer
Torque Magnetic RAM,” IEEE Transactions on VLSI Systems, March 2018, pp. 470-483.
339. A. Sharma and K. Roy, ””1T Non-Volatile Memory Design Using Sub-10nm Ferroelectric FETs,”
IEEE Electron Device Letters, March 2018, 359-362.
340. P. Panda, J. Allred, S. Ramanathan, and K. Roy, ”ASP: Learning to Forget with Adative Adaptive
Synaptic Plasticity in Spiking Neural Networks,” IEEE Journal on Emerging and Selected Topics
in Circuits and Systems, March 2018, pp. 51-64.
341. Y. Shim, A. Sengupta, and K. Roy, ”Biased Random-Walk Using Stochastic Switching of Nanomagnets: Application to SAT Solver,” IEEE Transactions on Electron Devices, April 2018, pp.
1617-1624.
342. A. Jaiswal, A. Agrawal, and K. Roy, ”In-situ, In-Memory Stateful Vector Logic Operations based
on Voltage Controlled Magnetic Anisotropy,” Scientific Reports 8 Article 5738, April 2018.
343. A. Jaiswal, R. Andrawis, and K. Roy, ”Proposal for an Area-Efficient Non-volatile Flip-Flop based
on Spin Hall Effect,” IEEE Magnetics Letters, April 2018.
344. Z. Azim, A. Jaiswal, I. Chakraborty, and K. Roy, ”Capacitively Driven Global Interconnect with
Magnetoelectric Switching Based Receiver for Higher Energy Efficiency,” IEEE Magnetic Letters,
April 2018.
44
345. C. Lee, G. Srinivasan, P. Panda, and K. Roy, ”Deep Spiking Convolutional Neural Network Trained
with Unsupervised Spike Timing Dependent Plasticity,” IEEE Transactions on Cognitive and Developmental Systems, May 2018.
346. R. Andrawis, A. Jaiswal, and K. Roy, ”Design and Comparative Analysis of Spintronic Memories
based on Current and Voltage driven Switching,” IEEE Transactions on Electron Devices, pp.
2682-2693, July 2018.
347. Y. Seo and K. Rpy, High Density SOT-MRAM based on Shared Bit-line Structure,” IEEE Transactions on VLSI Systems, pp. 1600-1603, August 2018.
348. M.-C. Chen, A. Sengupta, and K. Roy, ”Magnetic Skyrmion as a Spintronic Deep Learning Spiking
Neuron Processor,” IEEE Transactions on Magnetics, Article Number 15000207, August 2018.
349. C. Lee, P. Panda, G. Srinivasan, and K. Roy, ”Training Deep Spiking Convolutional Neural Networks with STDP-based Unsupervised Pre-training followed by Supervised Fine-tuning,” Frontiers
in Neuroscience, August 2018.
350. B. Han and K. Roy, ”DeltaFrame-BP: An Algorithm using Frame Difference for Deep Convolutional Neural Network Training and Inference on Video Data,” IEEE Transactions on Multi-Scale
Computing Systems, pp. 624 - 634, August 2018.
351. Z. Pajouhi and K. Roy, ”Image Edge Detection based on Swarm Intelligence using Memristive Networks,” IEEE Transactions on Computer-Aided Design of ICs, 2017, DOI: 10.1109/TCAD.2017.2775227,
September 2018, pp. 1174-1787.
352. I. Chakraborty, D. Roy, and K. Roy, ”Technology Aware Training in Memristive Neuromorphic Systems for non-ideal Synaptic Crossbars,” IEEE Transactions on Emerging Topics in Computational
Intelligence, pp. 335-344, October 2018.
353. N. Rathi and K. Roy, ”STDP Based Unsupervised Multimodal Learning with Cross-modal Processing in Spiking Neural Networks,” IEEE Transactions on Emerging Topics in Computational
Intelligence, October 2018.
354. P. Wejisinghe, A. Sengupta, A. Ankit, and K. Roy, ”An All-Memristor Deep Spiking Neural Computing System: A Step Towards Realizing Low-Power Stochastic Brain,” IEEE Transactions on
Emerging Topics in Computational Intelligence, pp. 345 - 358, October 2018. item T. Ostler, Z.
Azim, C. Xu, and K. Roy, ”Optical Receiver with Helicity Dependent Magnetization Reversal,”
IEEE Transactions on Magnetics, Paper 4400206, November 2018.
355. K. Roy, A. Sengupta, and Y. Shim, ”Perspective: Stochastic Magnetic Devices for Cognitive Computing,” Journal of Applied Physics, Volume 123, Issue 21, 2018. I. Chakraborty, A. Agrawal, and
K. Roy. ”Design of a low-voltage analog-to-digital converter using voltage-controlled stochastic
switching of low barrier nanomagnets.” IEEE Magnetics Letters 9 (2018): 1-5.
356. B. Han, A. Ankit, A. Sengupta, and K. Roy, Cross-Layer Design Exploration for Energy-Quality
Tradeoffs in Spiking and Non-Spiking Deep Artificial Neural Networks, IEEE Trans. On Multi-Scale
Computing, 2017, DOI: 10.1109/TMSCS.2017.2737625.
357. A. Sengupta and K. Roy, ”Encoding Neural and Synaptic Functionalities in Electron Spin: A Pathway to Efficient Neuromorphic Computing,” Applied Physics Reviews 4, 041105 (2017); https://doi.org/10.1063/1.5012
358. D Patra, A. Reza, M. Hassan, M. Katoozi, E. Cannon, K. Roy, and Y. Cao, ”Adaptive Accelerated
Aging for 28nm HKMG Technology,” Microelectronics Reliability 80, pp. 149-154.
359. I. Chakraborty, G. Das, and K. Roy, ”Toward Fast Neural Computing using All-Photonic Spiking
Neurons,” Scientific Reports 8, Article number: 12980, 2018.
45
360. S. Sarwar, G. Srinivasan, B. Han, P. Wejisinghe, A. Jaiswal, P. Panda, A. Raghunathan, and K.
Roy, ”Energy Efficient Neural Computing: A Study of Cross-Layer Approximations,” IEEE Journal
on Emerging and Selected Topics in Circuits and Systems, pp. 796-809, December 2018.
361. A. Agrawal, A. Jaiswal, C. Lee and K. Roy, ”X-SRAM: Enabling In-Memory Boolean Computations
in CMOS Static Random Access Memories,” IEEE Transactions on Circuits and Systems I: Regular
Papers, vol. 65, no. 12, pp. 4219-4232, Dec. 2018.
362. G. Srinivasan, P. Panda, and K. Roy, ”STDP-based Unsupervised Feature Learning using Convolutionover-time in Spiking Networks for Energy-Efficient Neuromorphic Computing,” ACM Journal on
Emerging Technologies in Computing Systems, Article No. 44, December 2018.
363. I. Chakraborty, G. Saha, and K. Roy, ”Photonic In-memory Computing Primitive for Spiking Neural
Networks using Phase-change Materials,” Physical Review Applied, January 2019.
364. A. Agrawal and K. Roy, Mimicking Leaky-Integrate-Fire Spiking neuron Using Automotion of
Domain Walls for Energy-Efficient Brain-Inspired Computing, IEEE Transactions on Magnetics,
Article number: 1400107, January 2019.
365. A. Reza and K. Roy, ”Effect of Dzyaloshinskii-Moriya Interaction at Ferrimagnet and Heavy Metal
Interface,” IEEE Transactions on Electron Devices, pp. 1598-1603, March 2019.
366. Andrawis, Robert, and Kaushik Roy. ”Nonequilibrium Greens Function and First-Principles Approach to Modeling of Multiferroic Tunnel Junctions.” Physical Review Applied 12, no. 1 (2019):
014003.
367. A. Sengupta, Y. Ye, R. Wang, C. Liu, and K. Roy, Going Deeper in Spiking Neural Networks: VGG
and Residual Architectures, Frontiers in Neuroscience – Neuromorphic Engineering, 07 March 2019
— https://doi.org/10.3389/fnins.2019.00095.
368. N. Rathi, P. Panda, and K. Roy, ”STDP Based Pruning of Connections and Weight Quantization in
Spiking Neural Networks for Energy-Efficient Recognition,” IEEE Transaction on Computer-Aided
Design of Integrated Circuits, pp. 668-677, April 2019.
369. P. Wijesinghe, G. Srinivasan, P. Panda, and K. Roy, ”Analysis of Liquid Ensembles for Enhancing
the Performance and Accuracy of Liquid State Machines,” Frontiers in Neuroscience-Neuromorphic
Engineering, May 2019.
370. P. Panda and K. Roy, ”Discretization based Solutions for Secure Machine Learning against Adversarial Attacks,” IEEE Access, Digital Object Identifier: 10.1109/ACCESS.2019.291946, pp. 70157
- 70168, May 2019.
371. D. Roy, P. Panda, and K. Roy, ”Synthesizing Images from Spatio-Temporal Representations using
Spike-based Backpropagation,” Frontiers in Neuroscience-Neuromorphic Engineering, https://doi.org/10.3389/fnins.2
June 2019.
372. B Chatterjee, P Panda, S Maity, A Biswas, K Roy, S Sen, ”Exploiting Inherent Error Resiliency
of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons,”
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1365-1377, June 2019.
373. R. Andrawis and K. Roy, ”Nonequilibrium Green’s Function and First-principles Approach to
Modeling of Multiferroic Tunnel Junctions,” Physical Review Applied, 12, 014003, July 2019.
374. M-C Chen, A. Ranjan, A. Raghunathan, and K. Roy, ” Cache Memory Design with magnetic
Skyrmions in a Long Nanotrack,” IEEE Transactions on Magnetics, Paper 1500309, August 2019.
A. Agrawal, A. Ankit and K. Roy, ”SPARE: Spiking Neural Network Acceleration Using ROMEmbedded RAMs as In-Memory-Computation Primitives,” in IEEE Transactions on Computers,
vol. 68, no. 8, pp. 1190-1200, 1 Aug. 2019.
46
375. A. Ankit, M. Koo, S. Sen, and K. Roy, ”Powerline Communication for Enhanced Connectivity in
Neuromorphic Systems,” IEEE Transactions on VLSI Systems, pp. 1897 - 1906, August 2019.
376. A. Agrawal, A. Jaiswal, D. Roy, B. Han, G. Srinivasan, A. Ankit, and K. Roy, ”Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays,” IEEE Transactions
on Circuits and Systems – I, pp. 3064 - 3076, August 2019.
377. M. Ali, R. Andrawis, and K. Roy, ”Dynamic Read Current Sensing with Amplified Bit-line Voltage
for STT-MRAMs,” IEEE Transactions on Circuits and Systems – II, May 2019.
378. A. Reza and K. Roy, ”Fast Switching in CoTb Based Ferrimagnetic Tunnel Junction,” Journal of
Applied Phyics, 126, 023901, 2019.
379. Hai-Tian Zhang, Fan Zuo, Feiran Li, Henry Chan, Qiuyu Wu, Zhan Zhang, Badri Narayanan,
Koushik Ramadoss, Indranil Chakraborty, Gobinda Saha, Ganesh Kamath, Kaushik Roy, Hua
Zhou, Alexander A Chubykin, Subramanian KRS Sankaranarayanan, Jong Hyun Choi, Shriram
Ramanathan, ”Perovskite Nickelates as Bio-electronic Interfaces,” Nature Communications, —
https://doi.org/10.1038/s41467-019-09660-6, 2019.
380. I. Chakraborty, A. Jaiswal, A. Saha, S. Gupta, K. Roy, ”Pathways to Efficient Neuromorphic
Computing with Non-Volatile Technologies,” Applied Physics Review, July 2019.
381. Y. Long, G. Srinivasan, P. Panda, and K. Roy, ”Structured Learning for Action Recognition in
Videos,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, August 2019,
pp. 475-484.
382. W. Ponghiran, G. Srinivasan, and K. Roy, Reinforcement Learning with Low-Complexity Liquid
State Machines, Frontiers in Neuroscience, August 2019.
383. M. Ali, R. Andrawis, and K. Roy, ”Dynamic Read Current Sensing with Amplified Bit-line Voltage
for STT-MRAMs,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2019.
384. D. Roy, P. Panda, and K. Roy, ”Tree-CNN: A hierarchical Deep Convolutional Neural Network for
incremental learning,” Neural Networks, September 2019, DOI: 10.1016/j.neunet.2019.09.010.
385. A. Jaiswal, I. Chakraborty, A. Agrawal, and K. Roy, ”8T SRAM Cell as a Multi-bit Dot Product
Engine for Beyond von-Neumann Computing,” IEEE Transactions on VLSI Systems, 2019.
386. P. Panda, I. Chakraborty, K. Roy, ”Discretization Based Solutions for Secure Machine Learning
Against Adversarial Attacks,” IEEE Access, May 2019, pp. 70157-70168.
387. K. Roy, A.Jaiswal, and P. Panda, ”Towards Spike-based Machine Intelligence with Neuromorphic
Computing,” Nature, November 27, 2019, pp. 607-617.
388. Shubham Jain, Aayush Ankit, Indranil Chakraborty, Tayfun Gokmen, Malte J. Rasch, Wilfried
Haensch, Kaushik Roy, Anand Raghunathan, Neural Network Accelerator Design with Resistive
Crossbars: Opportunities and Challenges, IBM Journal of Research and Development, 10:1-10:13,
Nov/Dec. 2019.
389. I. Garg, P. Panda, K. Roy, ”A Low Effort Approach to Structured CNN Design Using PCA,” IEEE
ACCESS, December 2019, pp. 1347 - 1360.
390. I. Chakraborty, A. Agrawal, A. Jaiswal, G. Srinivasan, K. Roy, ”In-Situ Unsupervised Learning
using Stochastic Switching in Magneto-Electric Magnetic Tunnel Junctions,” Philosophical Transactions of the Royal Society A, December 2019.
391. I. Chakraborty, D. Roy, I. Garg, A. Ankit, and K. Roy, ”Constructing Energy-efficnet Mixedprecision Neural Networks through Principle Component Analysis for Edge Intelligence,” Nature:
Machine Intelligence, January 2020, pp. 43-55.
47
392. M. Ali, A. Jaiswal, and K. Roy, ”In-Memory Low-Cost Bit-Serial Addition Using Commodity
DRAM Technology,” IEEE Transactions on Circuits and Systems I: Regular Papers, January 2020,
pp. 155-165.
393. J. Allred and K. Roy, ”Controlled Forgetting: Targeted Stimulation and Dopaminergic Plasticity
Modulation for Unsupervised Lifelong Learning in Spiking Neural Networks,” Frontiers in Neuroscience, January 28, 2020, https://doi.org/10.3389/fnins.2020.00007.
394. Hai-Tian Zhang, Priyadarshini Panda, Jerome Lin, Yoav Kalcheim, Kai Wang, John W. Freeland, Dillon D. Fong, Shashank Priya, Ivan K. Schuller, Subramanian K. R. S. Sankaranarayanan,
Kaushik Roy, and Shriram Ramanathan, ”Organismic materials for beyond von Neumann machines,” Appled Physics Reviews, January 2020.
395. I. Chakraborty, A. Jaiswal, A. Saha, S. Gupta, and K. Roy, ”Pathways to Efficient Neuromorphic
Computing with Non-Volatile Memory Technologies,” March 2020, Applied Physics Reviews, Vol.7,
Issue 2.
396. Hai-Tian Zhang, Tae Joon Park, Ivan A. Zaluzhnyy, Qi Wang, Shakti Nagnath Wadekar, Sukriti
Manna, Robert Andrawis, Peter O. Sprau, Yifei Sun, Zhen Zhang, Chengzi Huang, Hua Zhou, Zhan
Zhang, Badri Narayanan, Gopalakrishnan Srinivasan, Nelson Hua, Evgeny Nazaretski, Xiaojing
Huang, Hanfei Yan, Mingyuan Ge, Yong S. Chu, Mathew J. Cherukara,, Martin V. Holt, Muthu
Krishnamurthy, Oleg Shpyrko, Subramanian K.R.S. Sankaranarayanan, Alex Frano, Kaushik Roy,
and Shriram Ramanathan, ”Perovskite Neural Trees,” Nature Communications, May 7, 2020.
397. A. Agrawal, I. Chakraborty, D. Roy, U. Saxena, S. Sharmin, Y. Shim, G. Srinivasan, C. Liyanagendra, A. Sengupta, and K. Roy, ”Revisiting Stochastic Computing in the Era of Nano-scale
Non-volatile Technologies,” IEEE Transactions on VLSI Systems, to appear, Keynote paper.
398. R. Andrawis and K. Roy, ”Antiferroelectric Tunnel Junctions as Energy-Efficient Coupled Oscillators: Modeling, Analysis, and Application to Solving Combinatorial Optimization Problems,”
IEEE Transactions on Electron Devices, Issue 7, Vol. 67, 2020, pp. 2974-2980.
399. S. Jain, I. Sengupta, K. Roy, and A. Raghunathan, ”RxNN: A framework for evaluating deep neural
networks on resistive crossbars,” IEEE Transactions on Computer-Aided Design of ICs, 2020.
400. Aayush Ankit, Izzat El Hajj, Sapan Agarwal, Matthew Marinella, Martin Foltin, John-Paul Strachan, Dejan S Milojicic, Wen-Mei W Hwu, Kaushik Roy, ”PANTHER: A programmable architecture
for neural network training harnessing energy-efficient ReRAM,” IEEE Transactions on Computer,
2020.
401. Mustafa Ali, Akhilesh Jaiswal, Sangamesh Kodge, Amogh Agrawal, Indranil Chakraborty, Kaushik
Roy, ”IMAC: In-Memory Multi-Bit Multiplication and Accumulation in 6T SRAM Array,” IEEE
Transactions on Circuits and Systems I: Regular Papers, 2020.
402. M. Parsa, J. Mitchell, C. Schuman, R. Patton, T. Potok, and K. Roy, ”Bayesian Multi-Objective
Hyperparameter Optimization for Accurate, Fast, and Efficient Neural Network Accelerator Design,” Frontiers in Neuroscience, 14, 667, 2020.
403. P. Panda, S. Aketi, and K. Roy, ”Towards Scalable, Efficient and Accurate Deep Spiking Neural
Networks with Backward Residual Connections, Stochastic Softmax and Hybridization, Frontiers
in Neuroscience, 2020.
404. P. Wijesinghe, C. Liyanagendra, and K. Roy, ”Biologically Plausible Class Discrimination Based
Recurrent Neural Network Training for Motor Pattern Generation, Frontiers in Neuroscience, 2020.
405. M. Koo, G. Srinivasan, and K. Roy, ”sBSNN: Stochastic-Bits Enabled Binary Spiking Neural Network With On-Chip Learning for Energy Efficient Neuromorphic Computing at the Edge,” IEEE
Transactions on Circuits and Systems I: Regular Papers, 2020.
48
406. A. Agrawal, A. Jaiswal, P. Panda, and K. Roy, ”Neural Computing with Magnetoelectric DomainWall based Neuro-Synaptic Devices,” IEEE Transactions on Magnetics, 2020, Digital Object Identifier: 10.1109/TMAG.2020.3010712.
407. A. Jaiswal, A. Agrawal, M. Ali, S. Sharmin, and K. Roy,”i-SRAM: Interleaved Wordlines for Vector
Boolean Operations Using SRAMs,” IEEE Transactions on Circuits and Systems–I: Regular Papers,
Digital Object Identifier: 10.1109/TCSI.2020.3005783
408. A. Aketi, S. Roy, A. Raghunathan, and K. Roy, ”Gradual Channel Pruning while Training suing
Feature Relevance Scores for Convolutional Neural Networks,” IEEE ACCESS, Sepetember 2020.
409. Robert Andrawis, Kaushik Roy, ”A new oscillator coupling function for improving the solution of
graph coloring problem,” Physica D: Nonlinear Phenomena, November 2020.
410. Indranil Chakraborty, Mustafa Ali, Aayush Ankit, Shubham Jain, Sourjya Roy, Shrihari Sridharan,
Amogh Agrawal, Anand Raghunathan, Kaushik Roy, ”Resistive Crossbars as Approximate Hardware Building Blocks for Machine Learning: Opportunities and Challenges,” Proceedings of IEEE,
December 2020, pp. 2276 - 2310.
411. Aayush Ankit, Indranil Chakraborty, Amogh Agrawal, Mustafa Ali, Kaushik Roy, ”Circuits and
Architectures for In-Memory Computing-Based Machine Learning Accelerators,” IEEE Micro, NovDec 2020, pp 8-22.
412. Akhilesh Jaiswal, Robert Andrawis, Amogh Agrawal, Kaushik Roy, ”Functional Read Enabling InMemory Computations in 1Transistor1Resistor Memory Arrays,” IEEE Transactions on Circuits
and Systems II: Express Briefs, December 2020, pp. 3347 - 3351.
413. Amogh Agrawal, Indranil Chakraborty, Deboleena Roy, Utkarsh Saxena, Saima Sharmin, Minsuk
Koo, Yong Shim, Gopalakrishnan Srinivasan, Chamika Liyanagedera, Abhronil Sengupta, Kaushik
Roy, ”Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies,” IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, December 2020, pp. 2481 - 2494.
Keynote paper.
414. A. Agrawal, D. Roy, U. Saxena, and K. Roy, ”Embracing Stochasticity to Enable Neuromorphic
Computing at the Edge,” IEEE Design and Test, to appear.
GUEST EDITOR’S INTRODUCTION
415. K. Roy and A. Chatterjee, ”Guest editors introduction: Low-Power VLSI Design,” IEEE Design
and Test of Computers, December 1994, pp. 6-7.
416. K. Roy and D. T. Lee, “Guest editors introduction: Low-Power Electronics and Design,” IEEE
Transactions on VLSI Systems, June 2000, pp. 233-234.
417. B. Al-Hashimi, E. Macii, and K. Roy, “Low-Power Systems-on-Chip,” IEE Proceedings: Computers
and Digital Techniques, July 2002, pp. 135-136.
418. K. Roy, “Guest Editorial: Low-Power Design,” Integration, the VLSI Journal, 39, 2006, pp. 63.
419. C. Lau, A. Orailoglu, and K. Roy, ”Guest Editorial: Spacial Issue on Nano-electronic Circuits and
Nano-architectures,” IEEE Transactions on Circuits and Systems I, November 2007, pp. 2342-2344.
420. E. Macii, V. Narayanan, and K. Roy, ”Advances in Design of Energy-Efficient Circuits and Systems
(First Issue),” IEEE Journal of Emerging and Selected Topics in Circuits and Systems, June 2011,
pp. 73-75.
421. E. Macii, V. Narayanan, and K. Roy, ”Advances in Design of Energy-Efficient Circuits and Systems
(Second Issue Issue),” IEEE Journal of Emerging and Selected Topics in Circuits and Systems,
September 2011, pp. 205-207.
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422. Mukhopadhyay, S., Bhunia, S., Hunter, H. C., and Roy, K., Guest Editorial Computing in Emerging
Technologies (First Issue); JETCAS Dec. 2014, pp. 377-379
423. S. Mukhopadhyay, S. Bhunia, H. Hunter, and K. Roy, ”Guest Editorial: Special Issue on Computing in Emerging Technologies (Second Issue)”, IEEE Journal of Emerging and Selected Topics in
Circuits and Systems (JETCAS), 2015.
424. C. Campagnoni, J. Kang, Y. Shi, P. Du, T. Ki, C. Mouli, J. Yang and K. Roy, ”Special Issue on
Memory Devices andTechnologies for the Next Decade, IEEE Transactions on Electron Devices,
April 2020.
CONFERENCE PROCEEDINGS
425. M. Ilyas and K. Roy, “Multi-Level Flow Control in Computer Networks,” Eastern Simulation
Conference, 1986, pp. 127-132.
426. P. Banerjee, J. Rahmeh, C. Stunkel, S. Nair, K. Roy, J. Abraham,“An Evaluation of System-Level
Fault Tolerance on the Intel Hypercube Multiprocessor,” IEEE International Symposium on FaultTolerant Computing, 1988, pp. 362-367.
427. K. Roy and J.A. Abraham,“A Novel Approach to Accurate Timing Verification Using RTL Descriptions,” IEEE/ACM Design Automation Conference, 1989, 638-641.
428. K. Roy, J.A. Abraham, K. De, and S. Lusky, “Synthesis of Delay Fault Testable Combinational
Logic,” IEEE International Conference on Computer Aided Design, 1989, pp. 418-421.
429. K. Roy and J.A. Abraham, “High Level Test Generation Using Data Flow Descriptions,” European
Design Automation Conference, 1990, pp. 480-484.
430. K. Roy, A. Chatterjee and J. Abraham, “Issues in Logic Synthesis for Delay and Bridging Faults,”
IEEE International Symposium on Circuits and Systems, May 1990, pp. 3101-3104.
431. M. Levitt, K. Roy and J. Abraham, “BiCMOS Fault Models: Is Stuck-At Adequate?” IEEE
International Conference on Computer Design, 1990, pp. 294-297.
432. K. Roy, M. Levitt and J. Abraham, “Test Considerations for BiCMOS Logic Families,” IEEE
Custom Integrated Circuits Conference, 1991, pp. 17.2.1-17.2.4.
433. K. Roy, M. Levitt and J. Abraham, “The Effect of Multiple Charge-Discharge Paths on Testing of
BiCMOS Logic Circuits,” European Conference on Design Automation, 1992, pp. 549-553.
434. K. Roy and S. Prasad, “SYCLOP: Synthesis of CMOS Logic for Low Power Applications,” IEEE
International Conference on Computer Design, 1992, pp. 464-467.
435. K. Roy and M. Mehendale, “Optimization of Channel Segmentation for Channeled Architecture
FPGAs,” IEEE Custom Integrated Circuits Conference, 1992, pp. 4.4.1-4.4.4.
436. C. Shaw, M. Mehendale, K. Roy et. al., “An FPGA Architecture Evaluation Framework,” FPGA-92
Workshop, Berkeley, California, February 1992, pp. 15-20.
437. S. Prasad and K. Roy, “Circuit Activity Driven Multilevel Logic Optimization for Low Power
Reliable Operation,” European Conference on Design Automation, 1993, 368-372.
438. M. Mehendale and K. Roy, “Estimating Area Efficiency of Antifuse based Channeled FPGA Architectures,” IEEE International Conference on VLSI Design, January 1993, pp. 100-103.
439. K. Roy, “On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs,” IEEE International
Symposium on Circuits and Systems, May 1993, pp. 1623-1626.
440. S. Nag and K. Roy, “Iterative Wireability and Performance Improvement for FPGAs,” ACM/IEEE
Design Automation Conference, 1993, pp. 321-325.
50
441. K. Roy, S. Nag, and S. Dutta, “Channel Architecture Optimization for Performance and Routability
of Row-Based FPGAs,” IEEE International Conference on Computer Design, 1993, pp. 220-223.
442. S. Datta, S. Nag, and K. Roy, “ASAP: A Transistor Sizing Tool for Speed, Area, and Power
Optimization of Static CMOS Circuits,” International Symposium on Circuits and Systems, 1994,
pp. 61-64.
443. S. Prasad and K. Roy, “Circuit Optimization for Minimization of Power Consumption Under Delay
Constraints,” International Workshop on Low Power Design, April 1994, pp. 15-20.
444. K. Roy and S. Prasad, “Power Dissipation Driven FPGA Place and Route under Delay Constraints,”
FPL-94 and in Lecture Notes in Computer Science, Springer-Verlag, 1994, pp. 57-65.
445. K. Roy and S. Nag, “On Channel Architecture and Routability for FPGA’s under Faulty Conditions,” FPL-94 and in Lecture Notes in Computer Science, Springer-Verlag, 1994, pp. 361-372.
446. K. Roy and S. Prasad, “Logic Synthesis for Reliability – An Early Start to Controlling Electromigration and Hot Carrier Effects,” IEEE/ACM European Design Automation Conference, September
1994, pp. 136-141.
447. T-L. Chou, K. Roy, and S. Prasad, “Estimation of Circuit Activity Considering Signal Correlations and Simultaneous Switching,” IEEE International Conference on Computer-Aided Design,
November 1994, pp. 300-303.
448. S. Prasad and K. Roy, “Circuit Optimization for Minimization of Power Consumption under Delay
Constraints,” IEEE International Conference on VLSI Design, January 1995, pp. 305-309.
449. K. Roy, R. Roy, and A. Chatterjee, “Stress Testing of Combinational VLSI Circuits using Existing
Test Sets,” IEEE International Symposium on VLSI Technology, Systems, and Applications, May
1995, pp. 93-98.
450. T.-L. Chou and K. Roy, “Accurate Estimation of Power Dissipation in CMOS Sequential Circuits,”
IEEE International ASIC Conference, Austin, Texas, September 1995, pp. 285-288.
451. C.-Y. Wang and K. Roy, “Control Unit Synthesis Targeting Low-Power Processors,” IEEE International Conference on Computer Design, Austin, Texas, October 1995, pp. 454-459.
452. T.-L. Chou and K. Roy, “Estimation of Sequential Circuit Activity Considering Spatial and Temporal Correlations,” IEEE International Conference on Computer Design, Austin, Texas, October
1995, pp. 577-582.
453. K. Kornegay and K. Roy, “Integrated Test Solutions and Test Economics for MCMs,” IEEE International Test Conference, 1995, pp. 193-201.
454. Y. Ye and K. Roy, “Low Power Circuit Design using Adiabatic Switching Principle,” IEEE Midwest
Symposium on Circuits and Systems, 1995, pp. 1189-1193.
455. D. Somasekhar and K. Roy, “Differential Current Switch Logic: A Low Power DCVS Logic Family,”
21st European Solid-State Circuits Conference, September 1995, pp. 182-185.
456. K. Kornegay and K. Roy, “A Programmable 1149.N Test Interface for MCM Testing,” IEEE/ISHM
MCM Test Workshop, 1995.
457. D. Somasekhar, Y. Ye, and K. Roy, “An Energy Recovery Static RAM Memory Core,” IEEE
Symposium on Low Power Electronics, October 1995, pp. 62-63.
458. T.-L. Chou and K. Roy, “Statistical Estimation of Sequential Circuit Activity,” IEEE/ACM International Conference on Computer-Aided Design, November 1995, pp. 34-37.
459. C.-Y. Wang and K. Roy, “Maximum Power Estimation for CMOS Circuits Using Deterministic and
Statistical Approaches,” IEEE VLSI Design Conference, January 1996, pp. 364-369.
51
460. C.-Y. Wang, T.-L. Chou, and K. Roy, “Maximum Power Estimation for CMOS Circuits Under
Arbitrary Delay Model,” IEEE International Symposium on Circuits and Systems, May 1996.
461. C.-Y. Wang, K. Roy, and T.-L. Chou, “Maximum Power Estimation for Sequential Circuits Using
a Test Generation Based Technique,” IEEE Custom Integrated Circuits Conference, May 1996, pp.
229-232.
462. K. Muhammad, K. Letaief, and K. Roy, “Efficient Simulation of Coded DS/CDMA Over Wireless
Personal Communication Channels,” 1996 IEEE International Conference on Universal Personal
Communications, October 1996, pp. 240-244.
463. M. Johnson and K. Roy, “Optimal Selection of Supply Voltages and Level Conversions During Datapath Scheduling Under Resource Constraints,” IEEE Intl. Conf. on Computer Design, October
1996, pp. 72-77.
464. N. Sankarayya, K. Roy, and D. Bhattacharya, “Algorithms for Low Power FIR Filter Realization
using Differential Coefficients,” IEEE VLSI Design Conference, January 1997, pp. 174-178.
465. P. Patil, T.-L. Chou, K. Roy, and R. Roy, “Low-Power Driven Logic Synthesis Using Accurate
Power Estimation Technique,” IEEE VLSI Design Conference, January 1997, pp. 179-183.
466. T.-L. Chou and K. Roy, “Statistical Estimation of Combinational and Sequential CMOS Digital Circuit Activity Considering Uncertainty of Gate Delays,” 1997 Asia & South Pacific Design
Automation Conference - ASP-DAC, January 1997, pp. 95-100.
467. Y. Ye and K. Roy, “Efficient Synthesis of AND/XOR Networks,” 1997 Asia & South Pacific Design
Automation Conference - ASP-DAC, January 1997, pp. 539-544.
468. K. Roy and R. Roy, “Low-Power Design: Estimation and Synthesis Techniques,“ tutorial presentation at the 1997 Asia & South Pacific Design Automation Conference - ASP-DAC, January 1997.
469. Z. Chen, K. Roy, and T.-L. Chou, “Sensitivity of Power Dissipation to Uncertainties in Primary
Input Specification,” IEEE Custom Integrated Circuits Conference, 1997, pp. 487-490.
470. Y. Ye and K. Roy, “A Graph-based Synthesis Algorithm for Multi-Level AND/XOR Networks,”
ACM/IEEE Design Automation Conference, 1997, pp. 107-112.
471. M. Johnson and K. Roy, “Scheduling and Optimal Voltage Selection for Low Power Multi-Voltage
DSP Datapaths,” IEEE International Symposium on Circuits and Systems, Hongkong, May 1997,
invited paper.
472. K. Muhammad and K. Roy, “Low Power Digital Filters Based on Constrained Least Squares Solution,” 31st Asilomar Conference on Signals, Systems, and Computers, 1997, invited paper.
473. Y. Ye and K. Roy, “Reversible and Quasi Static Adiabatic Design,” European Conference on Circuit
Theory and Design, 1997, invited paper, pp. 912-917.
474. K. Muhammed and K. Roy, “On Power Reduction of FIR Digital Filters Using Constrained Least
Square Solutions,” IEEE International Conference on Computer Design, 1997, pp. 196-201.
475. C.-Y. Wang and K. Roy, “An ATG-Based Maximum Power Estimation Technique Considering
Spurious Transitions,” IEEE International Conference on Computer Design, 1997, pp. 746-751.
476. D. Somasekhar and K. Roy, “LVDCSL: Low Voltage Differential Current Switch Logic, A Robust
Low Power DCSL Family,” 1997 International Symposium on Low Power Electronics and Design,
pp. 18-23.
477. Y. Ye, K. Roy, and G. Stamoulis, “Quasi-Static Energy Recovery Logic and Supply Clock Generation Circuits,” 1997 International Symposium on Low Power Electronics and Design, pp. 96-99.
52
478. N. Kapadia, M. Lundstrom, J. Fortes, and K. Roy, “Network-Based Simulation Laboratories for
Microelectronics Systems Design and Education,” International Conference on Microelectronic Systems Education, Arlington, Virginia, July 21-23, 1997.
479. Z. Chen and K. Roy, “An Efficient Statistical Method to Estimate Average Power in Sequential
Circuits Considering Input Uncertainties,” IEEE International ASIC Conference, Portland, 1997,
pp. 189-193.
480. A. Keshavarzi, K. Roy, and C. Hawkins, “Intrinsic Leakage in Low Power Deep Submicron CMOS
IC’s,” IEEE International Test Conference, 1997, pp. 146-155. Best Paper Award.
481. C.-Y. Wang and K. Roy, “COSMOS: A Continuous Optimization Approach for Maximum Power
Estimation of CMOS Circuits,” ACM/IEEE International Conference on Computer-Aided Design,
Santa Clara, 1997, pp. 52-55.
482. Z. Chen, K. Roy, and T.-L. Chou, “Power Sensitivity – A New Method to Estimate Power Considering Uncertain Specifications of Primary Inputs,” ACM/IEEE International Conference on
Computer-Aided Design, Santa Clara, 1997, pp. 40-44.
483. N. Sankarayya, K. Roy, and D. Bhattacharya, “Optimizing Computations for Reducing Energy
Dissipation in Realization of High Speed LTI-FIR Systems,” ACM/IEEE International Conference
on Computer-Aided Design, Santa Clara, 1997, pp. 120-125.
484. Y. Ye, K. Roy, and R. Drechsler, “On Power Dissipation in AND-XOR Circuits,” Workshop on
Reed-Muller Circuits, Oxford, England, 1997, pp. 75-84.
485. L. Wei, Z. Chen, and K. Roy, “Double Gate Dynamic Threshold Voltage (DGDT) SOI MOSFETs
for Low Power High Performance Designs,” IEEE SOI Conference, 1997, pp. 82-83.
486. J. Anderson, S. Seth, and K. Roy, “A Coarse-Grained FPGA Architecture for High-Performance
FIR Filtering,” Sixth ACM International Symposium on Field Programmable Gate Arrays, Feb.
1998, Monterrey, CA, pp. 234-243.
487. H. Soeleman, D. Somasekhar, and K. Roy, “IDD Waveform Analysis for Testing of Domino and
Low Voltage Static CMOS Circuits,” IEEE Great Lakes Symp. on VLSI, Feb. 1998.
488. Z. Chen, K. Roy, and Y. Ye, “Estimation of Average Switching Power Under Accurate Modeling of
Signal Correlations,” IEEE Custom Integrated Circuits Conference, May 1998, pp. 507-510.
489. C. Hawkins, A. Keshavarzi, and K. Roy, “High Performance CMOS IC Challenges in IDDQ Testing,” IEEE European Test Workshop, May 27-29, Barcelona, 1998.
490. L. Wei, Z. Chen, and K. Roy, “Design and Optimization of Low Voltage High Performance Dual
Threshold CMOS Circuits,” IEEE/ACM Design Automation Conference, San Francisco, 1998, pp.
489-494.
491. Z. Chen and K. Roy, “A Novel Power Macromodeling Technique Based on Power Sensitivity,”
IEEE/ACM Design Automation Conference, San Francisco, June 1998, pp. 678-683.
492. Z. Chen, L. Wei, M. Johnson, and K. Roy, “Estimation of Standby Leakage Power in CMOS Circuits
Considering Accurate Modeling of Transistor Stacks,” Intl. Symp. on Low Power Electronics and
Design, Monterrey, CA, August 1998, pp. 239-244.
493. K. Roy, “Leakage Power Reduction in Low-Voltage CMOS Designs,” Invited paper, 5th IEEE
International Conference on Electronics, Circuits and Systems, September 7-10, 1998, pp. 2.1672.173.
494. L. Wei and K. Roy, “Multiple Vth CMOS for Leakage Control in Deep Submicron IC’s,“ Invited
paper, International Workshop on Power and Timing Modeling, Optimization and Simulation, Lyngby, Denmark, October 7, 1998, pp. 3-7. Keynote Talk.
53
495. K. Muhammad, E. Amyeen, K. Roy, and W. Fuchs, “IDD Waveform Analysis for Testing of Digital
CMOS Circuits,” 4th IEEE International On-Line Testing Workshop, July 6-8, Capri, Italy, 1998,
pp. 66-70.
496. Z. Chen, K. Roy, and E. Chong, “Estimation of Power Sensitivity for Sequential Circuits With
Application to Power Macromodeling,” IEEE/ACM International Conference on Computer-Aided
Design, Nov. 1998, pp. 468-472.
497. L. Wei, Z. Chen, and K. Roy, “Design and Optimization of Double-Gate Fully-Depleted SOI MOSFETs for Low Voltage Low Power CMOS Circuits,” IEEE International SOI Conference, 1998, pp.
69-70.
498. K. Muhammad, D. Somasekhar, and K. Roy, “Low Energy Computing for Portable and Wireless
Applications,” Invited paper, 1998 Norchip Conference, Lund, Sweden, Nov. 9-10, 1998, pp. 183190.
499. X. Zhang, K. Roy, and S. Bhawmik, “Low-Power BIST,” IEEE VLSI Conference, Jan. 1999, pp.
416-422.
500. K. Roy, L. Wei, and Z. Chen, “Multiple Vdd Multiple Vth CMOS (MVCMOS) for Low Power
Applications,” 1998 IEEE International Symposium on Circuits and Systems, May 1999, pp. 366370. Invited Paper
501. Y. Ye, K. Roy, and R. Drechsler, “Power Consumption in AND-XOR Based Circuits,” Asia &
South Pacific – Design Automation Conference, Jan. 1999, pp. 299-302.
502. M. Lundberg, K. Muhammad, K. Roy, and S. Wilson, “High Level Modeling of Switching Activity
With Application to Low-Power DSP System Synthesis,” International Conference on Acoustics,
Speech, and Signal Processing (ICASSP-99), March 1999.
503. M. Johnson, D. Somasekhar, and K. Roy, “Leakage Control with Efficient Use of Transistor Stacks
in Single Threshold CMOS,” 1999 Design Automation Conference, June 1999, pp. 442-445.
504. L. Wei, Z. Chen, K. Roy, Y. Ye, and V. De, “Mixed-Vth (MVT) CMOS Circuit Design Methodology
for Low Power Applications,” 1999 Design Automation Conference, June 1999, pp. 430-435.
505. X. Zhang and K. Roy, “Design and Synthesis of Programmable Low Power Weighted Random
Pattern Generator,” IEEE International On-Line Testing Workshop, July 1999, pp. 82-85.
506. H. Soeleman and K. Roy, “Ultra Low Power Digital Sub-Threshold Logic,” International Symp. on
Low-Power Electronics and Design, August 1999, pp. 94-96.
507. A. Keshavarzi, S. Narendra, C. Hawkins, K. Roy, S. Borkar, and V. De, “Optimum Reverse Body
Bias for Standby Power Reduction in Logic CMOS IC’s,” International Symp. on Low-Power
Electronics and Design, August 1999, pp. 252-254.
508. K. Muhammad, D. Somasekhar, and K. Roy, “Switching Characteristics of Generalized Array Multiplier Architectures and their Applications to Low Power Design,” IEEE International Conference
on Computer Design, Austin, TX, September 1999.
509. D. Somasekhar and K. Roy, “Split Gates: A Low Swing Technique for Reducing Power for High
Fanout Gates,” 25th European Solid State Circuits Conference, Duisburg, Germany, September
1999.
510. X. Zhang, W. Shan, and K. Roy, “Macromodel Based Maximum Power Estimation in CMOS
Digital Circuits,“ 9th International Workshop on Power and Timing Modeling, Optimization, and
Simulation, Kos Island, Greece, October 6-8, 1999, pp. 283-292.
54
511. K. Muhammad and K. Roy, “A Novel Design Methodology for High Performance and Low Power
Digital Filters,” International Conf. on Computer-Aided Design, San Jose, California, November
1999, pp. 80-83.
512. K. Muhammad and K. Roy, “A Graph Theoretic Approach for Design and Synthesis of LowComplexity Digital Filters,” International Symposium on System Level Synthesis, San Jose, California, November 1999, 94-99.
513. X. Zhang and K. Roy, “Design and Synthesis of Low Power Weighted Random Pattern Generator
Considering Peak Power Reduction,” 1999 International Symposium on Defect and Fault Tolerance
in VLSI Systems, October 1999, pp. 148-156.
514. A. Keshavarzi, C. Hawkins, K. Roy, and V. De, “Effectiveness of Reverse Body Bias for Low Power
CMOS Circuits,” 8th NASA Symposium on VLSI Design, 1999, pp. 2.3.1 - 2.3.9.
515. R. Zhang, K. Roy, and D. Janes, “Architecture and Performance of 3-Dimensional SOI Circuits,”
IEEE SOI Conference, October 1999, pp. 44-45.
516. S. Zhao and K. Roy, “Estimation of Worst Case Switching Noise on Power Supply Lines in DeepSubmicron CMOS Circuits,” International Conference on VLSI Design, Jan. 2000, pp. 168-173.
517. L. Wei, K. Roy, and V. De, “Low Voltage Low Power CMOS Design Techniques for Deep Submicron
IC’s,“ International VLSI Design, Jan. 2000, pp. 24-29. Invited Paper
518. Z. Chen, L. Wei, and K. Roy, “On Effective IDDQ Testing of Low-Voltage CMOS Circuits Using
Leakage Control Techniques,” IEEE International Symposium on Quality of IC Design, San Jose,
2000 pp. 181-188. Best Paper Award.
519. X. Zhang and K. Roy, “Low-Power BIST with Peak Power Vector Elimination,” International
Symposium on Quality of IC Design, 2000, pp. 425-432.
520. H. Soeleman and K. Roy, “Digital CMOS Logic Operation in the Sub-Threshold Region,“ IEEE
Great Lakes Symposium on VLSI, March 2000, pp. 107-112.
521. J. Park, H. Chooh, K. Muhammad, Y. Im, S. Choi, and K. Roy, “Non-Adaptive and Adaptive
Filter Implementation Based on Sharing Multiplication,“ International Conference on Acoustics,
Speech, and Signal Processing (ICASSP 2000), June 2000.
522. K. Muhammad and K. Roy, “Minimally Redundant Parallel Implementation Of Digital Filters and
Vector Scaling,“ International Conference on Acoustics, Speech, and Signal Processing (ICASSP
2000), June, 2000.
523. L. Wei, K. Roy, and C. Koh, “Power Minimization by Simultaneous Dual Vth Assignment and Gate
Sizing,“ IEEE Custom Integrated Circuits Conference, May 2000, pp. 413-416.
524. Y. Im and K. Roy, “A Novel High-Performance Predictable Circuit Architecture for the Deep Submicron Era,” IEEE Custom Integrated Circuits Conference, May 2000, pp. 503-506.
525. D. Somasekhar, S. Choi, K. Roy, Y. Ye, and V. De, “Dynamic Noise Immunity in Precharge Evaluate
Circuits,“ ACM/IEEE Design Automation Conf., 2000, pp. 243-246.
526. K.-T. Cheng, S. Dey, M. Rodgers, and K. Roy, “Test Challenges for Deep Submicron Technologies,”
ACM/IEEE Design Automation Conf., 2000, pp. 142-149. Invited Embedded Tutorial.
527. X. Zhang and K. Roy, “Power Reduction in Test-Per-Scan BIST,” IEEE International On-Line
Test Workshop, 2000, pp. 133-138.
528. H. Soeleman, K. Roy, and B. Paul, “Robust Ultra-Low Power Sub-threshold DTMOS Logic,” IEEE
International Symposium on Low-Power Electronics and Design, 2000, pp. 25-30.
55
529. M. Powell, S.-H. Yang, B. Falsafi, K. Roy, and T. Vijaykumar, “Gated-Vdd: A Circuit Technique
to Reduce Leakage in Deep Submicron Cache Memories,” IEEE International Symposium on LowPower Electronics and Design, 2000, pp. 90-95.
530. S. Zhao, K. Roy, and C. Koh, “Estimation of Inductive and Resistive Switching Noise on Power
Supply Network in Deep Sub-micron CMOS Circuits,” IEEE International Conference on Computer
Design, 2000, pp. 65-72.
531. N. Sirisantana, L. Wei, and K. Roy, “High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness,“ IEEE International Conference on Computer
Design, 2000, pp. 227-232.
532. A. Solomatnikov, D. Somasekhar, and K. Roy, “Skewed CMOS: Noise-Immune High-Performance
Low-Power Static Circuit Family,” European Solid-State Circuits Conference, pp 424-427, Sep.
2000.
533. A. Keshavarzi, K. Roy, M. Sachdev, C. Hawkins, K. Soumyanath, and V. De, “Multiple-Parameter
CMOS IC Testing with Increased Sensitivity for IDDQ ,” IEEE International Test Conference, 2000,
pp. 1051-1059.
534. R. Zhang, K. Roy, D. Janes, and C.-K. Koh, “Stochastic Interconnection Length and Delay Distribution of 3-Dimensional Circuits,” IEEE International Conference on Computer-Aided Design,
2000, pp. 208-213.
535. G. Zhong, C.-K. Koh, and K. Roy, “A Twisted-Bundle Layout Structure for Minimizing Inductive
Coupling Noise,“ IEEE International Conference on Computer-Aided Design, 2000, 406-411; also
appeared in Signal Integrity Effects in Custom IC and ASIC Design, edited by R. Singh, IEEE &
Wiley Interscience, 2002, ISBN 0-471-15042-8.
536. S. Zhao, K. Roy, and C.-K. Koh, “Frequency Domain Analysis of Switching Noise on Power Supply
Network,” IEEE International Conference on Computer-Aided Design, 2000, pp. 487-492.
537. H. Soeleman and K. Roy, “Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Logic,“
IEEE International Conference on VLSI Design, 2001, pp. 211-214.
538. S.-H. Yang, M. Powell, B. Falsafi, K. Roy, and T. Vijaykumar, “An Integrated Circuit/Architecture
Aproach to Reducing Leakage in Deep-Submicron High-Performance I-Caches,” High Performance
Computer Architecture Conference, Feb. 2001.
539. C. Crotty Neau, K. Muhammad, and K. Roy, “Low Complexity Design of FIR Filters Using Factorization of Perturbed Coefficients,” European Design and Test Conference, March 2001.
540. R. Zhang, K. Roy; C.-K. Koh, D.B, Janes, “Power Trends and Performance Characterization of 3Dimensional Integration for Future Technology Generations,” International Symposium on Qulaity
of IC Design, March 2001.
541. H. Choo, K. Muhammad, and K. Roy, “Decision Feedback Equalizer Based on Fast Sharing Multiplication,” IEEE International Conference on Acoustics, Speech, and Signal Processing(ICASSP
2001), May, 2001.
542. L-Y. Chiou, K. Muhammad, and K. Roy, “DSP Datapath Synthesis for Low-Power Applications,”
IEEE International Conference on Acoustics, Speech, and Signal Processing(ICASSP 2001), May,
2001.
543. S. Zhao, K. Roy, and C.-K. Koh, “Decoupling Capacitance Allocation for Power Supply Noise
Suppression,” Internation Symposium on Physical Design, April 2001.
544. R. Zhang, K. Roy, C.-K. Koh, and D. Janes, “Power Trends and Performance Characterization of
3-Dimensional Integration,” IEEE International Symposium on Circuits and Systems, May 2001.
56
545. R. Wang, K. Roy, and C.-K. Koh, “Short Circuit Power Analysis of an Inverter Driving and RLC
Load,” IEEE International Symposium on Circuits and Systems, May 2001.
546. S.-H. Choi, D. Somasekhar, and K. Roy, “Dynamic Noise Model and Its Application to High Speed
Circuit Design,” IEEE Mixed-Signal Test Workshop, Lake Lanier, Georgia, June 2001.
547. R. Zhang, K. Roy, D. Janes, and C. Koh, “Exploring SOI Device Structures and Interconnect
Architectures for 3-Dimensional Integration,“ ACM/IEEE Design Automation Conf., 2001, pp.
846-851.
548. H. Kim and K. Roy, “Ultra Low-Power DLMS Adaptive Filter For Hearing Aid Applications,”
ACM/IEEE International Symposium on Low Power Electronics and Design, August 2001, pp.
352-357.
549. R. Zhang, K. Roy, and D. Janes, “Double-Gate Fully-Depleted SOI Transistors for Nano-Technology
Regime,” ACM/IEEE International Symposium on Low Power Electronics and Design, August
2001, pp. 213-218.
550. N. Sirisantana, A. Caoa, S. Davidson, C. Koh, and K. Roy, “Selectively Clocked Skewed Logic
(SCSL): A Robust Low-Power Logic Style for High-Performance Applications,” ACM/IEEE International Symposium on Low Power Electronics and Design, August 2001, pp. 267-270.
551. W. Jeong, K. Roy, and C. Koh, “High-Performance Low-Power Carry Select Adder Using Dual
Transition Logic,” European Solid State Circuits Conference, September 2001.
552. J. Kim and K. Roy, “A Leakage Tolerant High Fan-in Dynamic Circuit Design Technique,” European
Solid State Circuits Conference, September 2001.
553. B. Paul, H. Soeleman, and K. Roy, “An 8X8 Sub-Threshold Digital CMOS Carry Save Array
Multiplier,” European Solid State Circuits Conference, September 2001.
554. B. Paul, S.-H. Choi, Y. Im, and K. Roy, “Design Verification and Robust Design Technique for
Cross-Talk Faults,” Asian Test Symposium, November 2001, pp. 449-454.
555. Y. Im and K. Roy, “CASh: A Novel “Clock As Shield” Design Methodology for Noise Immune
Precharge-Evaluate Logic,” IEEE International Conference on Computer-Aided Design, November
2001.
556. M. Powell, A. Agrawal, T. Vijaykumar, B. Falsafi, and K. Roy, “Reducing Set-Associative Cache
Energy via Selective Direct-Mapping and Way Prediction,” 34th International Symposium on Micro
Architecture (MICRO), December 2001.
557. S.-H. Choi, B. Paul, and K. Roy, “Dynamic Noise Analysis with Capacitive and Inductive Coupling in Precharge-Evaluate Circuits,“ Asia-South Pacific Design Automation Conference/ VLSI
Conference, 2002, pp. 65-70.
558. S. Zhao, K. Roy, and C.-K. Koh,, “Power Supply Noise Aware Floorplanning and Decoupling
Capacitance Placement,“ Asia-South Pacific Design Automation Conference/ VLSI Conference,
2002, pp. 489-495.
559. S. Choi and K. Roy, “Noise Analysis under Capacitive and Inductive Coupling for High Speed Circuits,” IEEE International Workshop on Electronic Design, Test, and Applications, Christchurch,
New Zealand, January 2002, pp. 365-369.
560. A. Caoa, C.-K. Koh, N. Sirisantana, and K. Roy, “Synthesis of Selectively Clocked Skewed Logic
Circuits,” International Symposium on Quality IC Design, March 2002.
561. Z. Chen, L. Wei, A. Keshavarzi, and K. Roy, “IDDQ Testing for Deep Submicron CMOS ICs:
Challenges and Solutions,” IEEE Latin America Test Workshop, February 2002.
57
562. S. Bhunia and K. Roy, “Fault Detection and Diagnosis Using Wavelet Based Transient Current
Analysis,” Design Automation and Test in Europe (DATE), March 2002, pp. 1118.
563. Y. Chen, V. Balakrishnan, C.-K. Koh, and K. Roy, “Model Reduction in Time Domain using
Laguerre Polynomials and Krylov Methods,” Design Automation and Test in Europe (DATE),
March 2002, pp. 931-935.
564. H.-Y. Kim and K. Roy, “Dynamic VT H Scaling for Active Leakage Management,” Design Automation and Test in Europe (DATE), March 2002, pp. 163-167.
565. S. Bhunia and K. Roy, “Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform,” IEEE VSLI Test Symposium, pp. 302 -307, April, 2002.
566. J. Kim, R. Joshi, C. Chuang, and K. Roy, “SOI-Optimized 64bit High-Speed CMOS Adder Design,”
IEEE VLSI Circuits Symposium, June 2002.
567. A. Agarwal, H. Hai, and K. Roy, “DRG-Cache: A Data Retention Gated-Ground Cache for Low
Power,” ACM/IEEE Design Automation Conference, June 2002, pp. 473-478.
568. S. Bhunia, K. Roy, and J. Segura, “A Novel Wavelet Transform Based Transient Current Analysis
for Fault Detection and Localization,” ACM/IEEE Design Automation Conference, June 2002, pp.
361-366.
569. S. Choi, F. Dartu, and K. Roy, “Timed Pattern Generation for Noise-on-Delay Calculation,”
ACM/IEEE Design Automation Conference, June 2002, pp. 870-873.
570. S. Kwon, J. Park, And K. Roy, “DCT Processor Architecture Based on Computation Sharing,”
IEEE International Conference on Circuits and Systems for Communications, June 2002, pp. 162165.
571. J. Park, W. Jeong, H. Choo, H. Mahmoodi-Meimand, Y. Wang and K. Roy, “High Performance and
Low Power FIR Filter Design Based on Sharing Multiplication,” ACM International Symposium
on Low Power Design, August 2002, pp. 295-300.
572. H. Kim and K. Roy, “Dynamic Vt SRAM’s for Low Leakage,” ACM International Symposium on
Low Power Design, August 2002, pp. 251-254.
573. H. Mahmoodi and K. Roy, “Self-Precharging Flip-Flop (SPFF): A New Level Converting Flip-Flop”,
European Solid-State Circuits Conference (ESSCIRC), September 2002, pp. 407-410.
574. T. Cakici and K. Roy, “Current Mirror Evaluation Logic: A New Circuit Style for High Fan-in
Dynamic Gates,” European Solid-State Circuits Conference (ESSCIRC), September 2002 pp. 395398.
575. J. Kim and K. Roy, “Sense-Amplifierless DCSL:A Circuit Style Tolerant to Folating Body Effects
in PD/SOI,” European Solid-State Circuits Conference (ESSCIRC), September 2002, pp. 271-274.
576. J. Kim and K. Roy, “SOI-Specific Tri-State Inverter and Its Application,” IEEE International SOI
Conference, pp. 145-146, 2002.
577. S. Bhunia, H. Li, and K. Roy, “A High Performance IDDQ Testable Cache for Scaled CMOS
Technologies,” IEEE Asian Test Symposium, pp. 157-162, November 2002.
578. G. Zhong, C-K. Koh, and K. Roy, “On-Chip Interconnect Modeling by Wire Duplication,” IEEE
International Conference on Computer-Aided Design, November 2002.
579. W. Jeong and K. Roy, “Robust High-Performance Low-Power Carry Select Adder,” IEEE AsiaSouth-Pacific Design Automation Conference, January 2003.
580. Y. Im and K. Roy, “LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity
of Domino Circuits,” IEEE International Symposium on VLSI, pp. 45-52, 2003.
58
581. S. Bhunia and K. Roy, “Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of
Dynamic Current,” 4th IEEE Latin American Test Workshop, pp. 183-187, February 2003. Best
Paper Award.
582. H. Li, S. Bhunia, Y. Chen, K. Roy, and T. Vijaykumar, “Deterministic Clock Gating for Microprocessor Power Reduction,” High Performance Computer Architecture Conference (HPCA), pp.
113-122, February 2003.
583. A. Agarwal, K. Roy, and T. Vijaykumar, “Exploring High Bandwidth Pipelined Cache Architecture
for Scaled Technology,” IEEE Design and Test in Europe (DATE), pp. 778-783, March 2003.
584. S. Choi and K. Roy, “A New Crosstalk Noise Model for DOMINO Logic Circuits,” IEEE Design
and Test in Europe (DATE), pp. 1112-1113, March 2003.
585. N. Sirisantana and K. Roy, “Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune
Operations in Scaled Technologies“, IEEE Design and Test in Europe (DATE), 1160-1161, March
2003.
586. H. Chooh, K. Muhammad, and K. Roy, “MRPF: An Architectural Transformation for Synthesis of
High-Performance and Low-Power Digital Filters,“ IEEE Design and Test in Europe (DATE), pp.
700-705, March 2003.
587. L. Chiou, S. Bhunia, and K. Roy, “Synthesis of Application-Specific Highly-Efficient Multi-Mode
Systems for Low-Power Applications,” IEEE Design and Test in Europe (DATE), pp. 96-101,
March 2003.
588. J. Abraham and K. Roy, “Test Considerations for Scaled CMOS Circuits,” European Test Symposium, 2003, Invited Paper.
589. K. Roy, T.M. Mak, and K.-T. Cheng, “Test Considerations for Nanometer Scale CMOS Circuits,”
IEEE VLSI Test Symposium, May 2003. Invited Paper.
590. Y. Im and K. Roy, “A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino
Circuits,” IEEE International Symposium on Circuits and Systems, May 2003.
591. K. Roy, “Leakage Control for Nanometer Scale Circuits,” SPIE International Symposium on Microtechnologies for the New Millennium 2003, pp. 135-146, May 2003.
592. S. Mukhopadhyay and K. Roy, “Accurate Modeling of Transistor Stacks to Effectively Reduce
Total Standby Leakage in Nano-Scale CMOS Circuits,” IEEE 2003 Symposium on VLSI Circuits,
pp. 53-56, June 2003.
593. C. H. Kim, K. Roy, S. Hsu, A. Alvandpour, R. Krishnamurthy, and S. Borkar, “A Process Variation Compensating Technique for Sub-90nm Dynamic Circuits,” IEEE 2003 Symposium on VLSI
Circuits, pp. 205-206, June 2003.
594. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, “Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling,”IEEE/ACM Design
Automation Conference, pp. 169-174, June 2003.
595. G. Zhong, C. Koh, V. Balakrishnan, and K. Roy, “An Adaptive Window-Based Suseptance Extraction and Its Efficient Implementation,” IEEE/ACM Design Automation Conference, pp. 728-731,
June 2003.
596. M. Cooke, H. Mahmoodi-Meimand, and K. Roy, “Energy Recovery Clocking Scheme andFlip-Flops
for Ultra Low Energy Applications,” IEEE International Symposium on Low-Power Electronics and
Design, pp. 54-59, August 2003.
59
597. C. Neau and K. Roy, “Optimal Body Bias Selection for Leakage Improvement and Process Compensation over Different Technology Generations,” IEEE International Symposium on Low-Power
Electronics and Design, pp. 116-121, August 2003.
598. C. H. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, “A Forward Body-Biased Low-Leakage SRAM
Cache: Device and Architecture Considerations,” IEEE International Symposium on Low-Power
Electronics and Design, pp. 6-9, August 2003.
599. A. Agarwal and K. Roy, “A Noise Tolerant Cache Design to Reduce Gate and Subthreshold Leakage
in the Nanometer Regime,” IEEE International Symposium on Low-Power Electronics and Design,
pp. 18-21, August 2003.
600. S. Mukhopadhyay and K. Roy, “Modeling and Estimation of Total Leakage Current in Nano-Scaled
CMOS Devices Considering the Effect of Process Variation,” IEEE International Symposium on
Low-Power Electronics and Design, pp. 172-175, August 2003.
601. Y. Chen, K. Roy, and C-K. Koh, “Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-Gated Microprocessor,” IEEE International
Symposium on Low-Power Electronics and Design, pp. 229-234, August 2003.
602. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “Circuit-Compatible Modeling of Carbon Nanotube FETs in the Ballistic Limit of Performance,” IEEE-Nano 2003, pp. 343-346, August 2003.
Best Student Paper Award.
603. A. Raychowdhury and K. Roy, “Performance Estimation in Molecular Crossbar Architecture Considering Capacitive and Inductive Coupling between Interconnects,” IEEE-Nano 2003, pp. 445-448,
August 2003.
604. J. Park, K. Muhammad, and K. Roy, “Efficient Generation of 1/f α Noise Using a Multirate Filter
Bank,” IEEE Custom Integrated Circuits Conference, pp. 707-710, September 2003.
605. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “Modeling of Ballistic Carbon Nanotube Field
Effect Transistors for Efficient Circuit Simulation,” IEEE International Conference on ComputerAided Design of IC’s, pp. 487-490, Nov. 2003.
606. D. Kang, M. Johnson, and K. Roy, “Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan,” IEEE International Conference on Computer Design, pp. 412-418, October 2003.
607. H. Suzuki, W. Jeong, and K. Roy, “Low Power Adder with Adaptive Supply Voltage,” IEEE
International Conference on Computer Design, pp. 103-106, 2003.
608. J. Kim and K. Roy, “Double Gate MOSFET Subthreshold Logic for Ultra-Low Power Applications”,
IEEE International SOI Conference, pp. 97-98, October 2003.
609. T. Cakici, A. Bansal, and K. Roy, “A Low Power Four Transistor Schmitt Trigger for Asymmetric
Double Gate Fully Depleted SOI Devices,” IEEE International SOI Conference, pp. 21-22, October
2003.
610. D. Ghosh, S. Bhunia, and K. Roy, “Multiple Scan Chain Design Technique for Power Reduction
During Test Application in BIST,” 18th International Symposium on Defect and Fault Tolerance
in VLSI Systems, pp. 191-198, 2003.
611. K. Roy, “Leakage Current in Scaled CMOS Circuits,” SPIE Conference on Microelectronics, Perth.
Invited Paper.
612. H. Li, C. Cher, T. Vijaykumar, and K. Roy, “VSV: L2-Miss-Driven Variable Supply Voltage Scaling
for Low-Power,” IEEE Micro, pp. 19-28, December 2003.
613. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “Modeling and Estimation of Leakage in Sub90nm Devices,” IEEE VLSI Conference, January 2004. Embedded Keynote Paper.
60
614. Y. Chen, K. Roy, and C.-K. Koh, “Priority Assignment Optimization for Minimization of of Current
Surge in High Performance Efficient Clock-Gated Microprocessor,” IEEE Asia and South Pacific
Design Automation Conference, January 2004.
615. W. Jeong, B. Paul, and K. Roy, “Adaptive Supply Voltage Technique for Low-Swing Interconnects,”
IEEE Asia and South Pacific Design Automation Conference, January 2004.
616. S. Bhunia, A. Raychowdhury, and K. Roy, “Frequency Specification Testing of Analog Filters Using
Wavelet Transform of Dynamic Supply Current,” IEEE Design and Test in Europe, February, 2004
& IEEE International Conference on Quality IC Design, pp. 389-394, March 2004.
617. D. Kang, M. Johnson, and K. Roy, “Simultaneous Multiple-Vdd Scheduling and Allocation for
Partioned Floorplan,” IEEE International Conference on Quality IC Design, pp. 98-103. March
2004.
618. H. Ananthan, A. Bansal, and K. Roy, “FinFET SRAM – Device and Circuit Design Considerations,”
IEEE International Conference on Quality IC Design, pp. 511-516, March 2004.
619. J. Park and K. Roy, “A Low Power Reconfigurable DCT Architecture to Trade-Off Image Quality
for Computational Complexity,” IEEE International Conference on Acoustics, Speech, and Signal
Processing(ICASSP 2004), May 2004.
620. Y. Wang, H. Mahmoodi-Meimand, L. Chiou, H. Choo, J. Park, W. Jeong, and K. Roy, “Hardware
Architecture and VLSI Implementation of Low-Power High-Performance Polyphase Channelizer
with Application to Sub-band Adaptive Filtering,” IEEE International Conference on Acoustics,
Speech, and Signal Processing(ICASSP 2004), May 2004.
621. M. Hwang, A. Raychowdhury, and K. Roy, “Effectiveness of Energy Recover Techniques in Reducing On-Chip Power Density in Molecular Nano-Technologies,” IEEE International Symposium on
Circuits and Systems, May 2003.
622. H. Mahmoodi-Meimand and K. Roy, “Dual-Edge Triggered Level Converting Flip-Flops,” IEEE
International Symposium on Circuits and Systems, May 2003.
623. H. Mahmoodi-Meimand and K. Roy, “Data-Retention Flip-Flops for Power-Down Applications,”
IEEE International Symposium on Circuits and Systems, May 2003.
624. A. Agarwal, K. Roy, S. Hsu, R. Krishnamurthy, and S. Borkar, “90nm 6.5GHz 128X64 4-Read 4Write Ported Parameter Variation Tolerant Register File,” IEEE 2004 Symposium on VLSI Circuits,
pp. 386-387, June 2004.
625. C. Kim, K. Roy, S. Hsu, R. Krishnamurthy, and S. Borkar, “An On-Die CMOS Leakage Sensor for
Measuring Process Variation in Sub-90nm Generation,” IEEE 2004 Symposium on VLSI Circuits,
pp. 250-251, June 2004.
626. S. Mukhopadhyay, H. Mahmoodi-Meimand, and K. Roy, “Modeling and Estimation of Failure
Probability due to Parameter Variations in Nano-Scaled SRAMs for Yield Enhancement,” IEEE
2004 Symposium on VLSI Circuits, pp. 64-67, June 2004.
627. C.-Y Chen, S. Kwon, and K. Roy, “Efficient Communication Channel Utilization for Mapping FFT
onto Mesh Array,” 2004 International Conference on Communication and Computing,, pp. 167-173,
June 2004.
628. S. Choi, B. Paul, And K. Roy, “Novel Sizing Algorithm for Yield Improvement under Process
Variation in Nanometer Technology,” IEEE/ACM Design Automation Conference, pp. 454-459,
June 2004.
629. A. Agarwal, C. H. Kim, S. Mukhopadyaya, and K. Roy, “Leakage in Nano-Scale Technologies:
Mechanisms, Impact, and Design Considerations,” IEEE/ACM Design Automation Conference,
pp. 6-11, June 2004, Invited Paper.
61
630. B. Paul and K. Roy, “Device Optimization for Digital Sub-threshold Operation,” IEEE Device
Research Conference, pp. 113-114, June 2004.
631. A. Raychowdhury and K. Roy, “Modeling and Analysis of Carbon Nanotube Interconnects for High
Speed VLSI Design,” Fourth IEEE Nano Conference, Munich, Aug. 2004.
632. A. Raychowdhury, J. Guo, K. Roy, and M. Lundstrom, “Choice of Flat-Band Voltage, VDD and
Diameter of Ambipolar Schottky-Barrier Carbon Nanotube Transistors in Digital Circuit Design,”
Fourth IEEE Nano Conference, Munich, Aug. 2004.
633. A. Agarwal, B. Paul, and K. Roy, “Process Variation in Nano-Scale Memories: Failure Analysis
and Process-Tolerant Architecture,” IEEE Custom Integrated Circuits Conference, October 2004.
634. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “Estimation of Delay Variations Due to RandomDopant Fluctuations in Nano-Scaled CMOS Circuits,“ IEEE Custom Integrated Circuits Conference, Oct. 2004
635. H. Choo, and K. Roy, “A Parametric Approach for Low Energy Wireless Data Communication,”
IEEE Workshop on Signal Processing Systems, 2004.
636. Y. Wang and K. Roy, “Reduced Complexity Spehere Decoding Via Detection Ordering for Linear
Multi-Input Multi-Output Channels,” IEEE Workshop on Signal Processing Systems, 2004.
637. D. Kang, H. Choo, and K. Roy, “Floorplan-Aware Low-Complexity Digital Filter Synthesis for
Low-Power and High-Speed” IEEE International Conference on Computer Design, pp. 354-357,
2004.
638. S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, and K. Roy, “A Novel Low-Power Scan
Design Technique Using Supply Gating,” IEEE International Conference on Computer Design, pp.
60-65, 2004, Best Paper Award.
639. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “High Performance and Low Power Domino Logic
Using Independent Gate Control in Double-Gate SOI MOSFETs,” IEEE International SOI Conference, pp. 67-68, Oct. 2004.
640. C. H. Kim, H. Ananthan, J. Kim, and K. Roy, “Effectiveness of Using Supply Voltage as Back-Gate
Bias in Ground Plane SOI MOSFETs,” IEEE International SOI Conference, pp. 69-70, Oct. 2004.
641. A. Bansal, B. Paul, and K. Roy, “Impact of Underlap on Gate Capacitance and Gate Tunneling
Current in 16nm DGMOS Devices,” IEEE International SOI Conference, pp. 94-95, Oct. 2004.
642. A. Raychowdhury and K. Roy, “Carbon Nanotubes as the Interconnects of the Future: A Circuit
Perspective,” Advanced Metallization Conference, pp. 277-283, October 2004, invited paper.
643. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Statistical Design and Optimization of SRAM
Cell for Yield Enhancement,” International Conference on Computer-Aided Design (ICCAD), pp.
10-13, Nov. 2004.
644. B.C. Paul, A. Raychowdhury, K. Roy, “Device Optimization for Ultra-Low Power Digital SubThreshold Operation”, IEEE International Symposium on Low-Power Electronics and Design, pp.
96-101, August 2004.
645. H. Ananthan, C. H. Kim, K. Roy, “Larger-than-Vdd forward body bias in sub-0.5V nanoscale
CMOS”, IEEE International Symposium on Low-Power Electronics and Design, pp. 8-13, August
2004.
646. A. Raychowdhury and K. Roy, “A Circuit Model for Carbon Nanotube Interconnects: Comparative Study with Cu Interconnects for Scaled Technologies,” IEEE International Conference on
Computer-Aided Design (ICCAD), pp. 237-240, San Jose, Nov. 2004.
62
647. A. Bansal and K. Roy, “Assymetric Halo CMOSFET to Reduce Static Power Dissipation with Improved Performance,” IEEE International Symposium on Circuits and Systems, May 2005. Invited
Paper.
648. C.H. Kim, J. Kim, I, Kim, and K. Roy, “A Process and Temperature Variation Aware Leakage
Reduction Technique with Improved Stability for On-Die Caches,” IEEE International Solid-State
Circuits Conference, pp. 482-483, February 2005.
649. D. Kang, Y. Chen, and K. Roy, “Power Supply Noise-Aware Scheduling and Allocation for DSP
Synthesis,” IEEE International Symposium on Quality Electronic Design, pp. 48-53, 2005.
650. A. Datta, S. Bhunia, N. Banerjee, and K. Roy, “A Power-Aware GALS Architecture for RealTime Algorithm-Specific Tasks,” IEEE International Symposium on Quality Electronic Design, pp.
358-363, 2005.
651. S. Bhunia, H. Mahmoodi, and K. Roy, “Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Patitioning,” IEEE International Symposium on Quality Electronic Design,
pp.453-458, 2005.
652. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Design of High Performance Sense Amplifier Using
Independent Gate Control in sub-50nm Double-Gate MOSFET,” IEEE International Symposium
on Quality Electronic Design, pp.490-495, 2005.
653. S. Mukhopadhyay, K. Kim, C. Chuang, and K. Roy, “Modeling and Analysis of Gate Leakage in
Ultra-Thin Oxide sub-50nm Double Gate Devices and Circuits,” IEEE International Symposium
on Quality Electronic Design, pp. 410-415, 2005.
654. K. Kim, C. Kim, and K. Roy, “TFT-LCD Application Specific Low-Power SRAM using ChargeRecycling Technique,” IEEE International Symposium on Quality Electronic Design, pp. 59-64,
2005.
655. S. Mukhopadhyay, S. Bhunia, and K. Roy, “Modeling and Analysis of Loading Effect in Leakage of
Nano-Scaled Bulk-CMOS Logic Circuits,” IEEE Design and Test in Europe (DATE), pp. 224-229,
2005.
656. K. Kang, B. Paul, and K. Roy, “Statistical Timing Analysis using Levelized Covariance Propagation,” IEEE Design and Test in Europe (DATE), pp. 764-769, 2005.
657. S. Bhunia, H. Mahmoodi, A. Raychowdhury, and K. Roy, “A Novel Low-Overhead Delay Testing
Technique for Arbitrary Two-Pattern Test Application,” IEEE Design and Test in Europe (DATE),
pp.1136-1141 , 2005.
658. A. Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy, “Statistical Modeling of Pipeline Delay and
Design of Pipeline Under Process Variation to Enhance Yield in Sub-100nm Technologies,” IEEE
Design and Test in Europe (DATE), pp. 926-931, 2005.
659. Y. Wang, K. Muhammad, and K. Roy, “Design of Sigma-Delta Modulators with Arbitrary Transfer
Functions,” International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2005.
660. H. Chooh and K. Roy, “Joint Control of Communications Subsystems for Low-Energy Image Transmission,” International Conference on Acoustics, Speech, and Signal Processing (ICASSP), 2005.
661. Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, “Modeling and Testing of SRAM for New Failure
Mechanisms due to Process Variations in Nan0scale CMOS,” IEEE VLSI Test Symposium, 2005.
662. A. Bansal and K. Roy, “Asymmetric Halo CMOSFET to Reduce Static Power with Improved
Performance,” IEEE International Symposium on Circuits and Systems, 2005.
663. Q. Chen, S. Mukhopadhyay, H. Mahmoodi and K. Roy, “Process Variation Tolerant Online Current
Monitor for Fault Immune Systems,” IEEE International Symposium on On-Line Testing, 2005.
63
664. A. Datta, S. Mukhopadhyay, S. Bhunia, and K. Roy, “Reliability Analysis and Yield Prediction
of High Performance Pipelined Circuit with respect to Delay Failures in sub-100nm Technology,”
IEEE International Symposium on On-Line Testing, 2005.
665. A. Raychowdhury, S. Ghosh, K. Roy, “A Novel On-chip Delay Measurement Hardware for Efficient
Speed-Binning,” IEEE International Symposium on On-Line Testing, 2005.
666. H. Ananthan and K. Roy, “Technology-Circuit Co-Design in Width-Quantized Quasi-Planar DoubleGate SRAM,” 2005 IEEE International Conference on Integrated Circuit and Technology, May 2005,
pp. 155-160.
667. C. Kim, K. Roy, S. Hsu, R. Krishnamurthy and S. Borkar, “ An On-Die Leakage Current Sensor
for Measuring Process Variation in Sub-90nm Generations,” 2005 IEEE International Conference
on Integrated Circuit and Technology, May 2005, pp. 221-222.
668. M. Alam, H. Kufluoglu, B. Paul, K. Kang, and K. Roy, “On Reliable Circuits and Systems: How
Reliability Considerations are Reshaping Oxide Scaling, Device Geometry, and VLSI Algorithm,”
2005 IEEE International Conference on Integrated Circuit and Technology, May 2005, pp. 117-122.
669. S. Bhunia, H. Mahmoodi, N. Banerjee, Q. Chen, and K. Roy, “A Novel Synthesis Approach for Active Leakage Power Reduction Using Supply Gating,” IEEE/ACM Design Automation Conference
(DAC), June 2005.
670. S. Mukhopadhyay, K. Kim, C.-T. Chuang, and K. Roy, “Modeling and Analysis of Total Leakage
Currents in Nanoscale Double Gate Devices and Circuits,” ACM/IEEE International Symposium
on Low-Power Electronics and Design, August 2005, pp. 8-13.
671. A. Agarwal, K. Kang, S. Bhunia, J. Gallagher, and K. Roy, “Effectiveness of Dual-Vt Designs
in Nano-Scale Technologies under Process Variations,” ACM/IEEE International Symposium on
Low-Power Electronics and Design, August 2005, pp. 14-19.
672. S. Hsu, A. Agarwal, K. Roy, R. Krishnamurthy, and S. Borkar, “An 8.3 GHz Dual Supply/Threshold
Optimized 32b Integer ALU-Register File Loop in 90nm CMOS,” ACM/IEEE International Symposium on Low-Power Electronics and Design, August 2005, pp. 103-106.
673. Y. Chen, H. Li, K. Roy, and C.-K. Koh, “Cascaded Carry-Select Adder (C 2 SA): A New Structure
for Low-Power CSA Design,” ACM/IEEE International Symposium on Low-Power Electronics and
Design, August 2005, pp. 115-118.
674. I. Chang, K. Kang, S. Mukhopadhyay, C. Kim, and K. Roy, “Fast and Accurate Estimation of NanoScaled SRAM Read Failure Probability using Critical Point Sampling,” IEEE Custom Integrated
Circuits Conference, Spetember 2005, pp. 439-452.
675. Y. Chen, H. Li, K. Roy, and C.-K. Koh, “Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies,” IEEE Custom Integrated Circuits Conference, Spetember
2005, pp. 775-778.
676. A. Bansal, S. Mukhopadhyay, and K. Roy, “Modeling and Optimization Approach to Robust and
Low-Power FinFET SRAM Design in NanoScale Era,” IEEE Custom Integrated Circuits Conference, Spetember 2005, pp. 835-838.
677. H. Ananthan, A. Bansal, and K. Roy, “Analysis of Drain-to-Body Band-To-Band Tunneling in
Double-Gate MOSFET,” IEEE SOI Conference, October 2005.
678. T. Cakici, H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “Independent Gate Skewed Logic in
Double-Gate SOI Technology,” IEEE SOI Conference, October 2005.
679. P. Ndai, A. Agarwal, Q. Chen, and K. Roy, “A Soft-Error Monitor Using Switching Current Detection,” IEEE International Conference on Computer Design (ICCD), October 2005.
64
680. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “A Feasibility Study of Subthreshold SRAM
Across Technology Generations,” IEEE International Conference on Computer Design (ICCD),
October 2005.
681. N. Banerjee, A. Raychowdhury, S. Bhunia, H. Mahmoodi, and K. Roy, “Novel Low-Overhead
Operand Isolation Techniques for Low-Power Datapath Synthesis,” IEEE International Conference
on Computer Design (ICCD), October 2005.
682. M. Meterelliyoz, H. Mahmoodi, and K. Roy, “A Leakage Control System for Thermal Stability
During Burn-In Test,” IEEE International Test Conference, November 2005.
683. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Reliable and Self-Repairing SRAM in Nano-Scale
Technologies using Leakage and Delay Monitoring,” IEEE International Test Conference, November
2005.
684. K. Roy, H. Mahmoodi, S. Mukhopadhyay, A. Bansal, H. Ananthan, and T. Cakici, “Double-Gate
SOI Devices for Low-Power and High-Performance Applications,” IEEE International Conference
on Computer-Aided Design (ICCAD), November 2005, Invited Paper.
685. A. Agarwal, K. Kang, and K. Roy, “Accurate Estimation and Modeling of Total Chip Leakage
Considering Inter- and Intra-Die Process Variations,” IEEE International Conference on ComputerAided Design (ICCAD), November 2005.
686. A. Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy, “A Statistical Approach to Area-Constrained
Yield Enhancement for Pipelined Circuits under Parameter Variations,” 14th Asian Test Symposium, December 2005.
687. S. Mukhopadhyay, A. Raychowdhury, H. Mahmoodi, and K. Roy, “Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-Scale SRAMs,”
14th Asian Test Symposium, December 2005.
688. S. Ghosh, S. Bhunia, and K. Roy, “Shannon Expansion Based Supply-Gated Logic for Improved
Power and Testability,” 14th Asian Test Symposium, December 2005.
689. A. Keshavarzi, A. Raychowdhury, J. Curtin, K. Roy, and V. De, Scalability of Carbon Nanotube
FET-based Circuits, Asian Solid-State Circuits Conference, 2005.
690. M. M. Budnik, K. Roy, “Implications of SiO2 Breakdown in an Integrated Nanoscale Power Supply”,
Proceedings of the 2005 International Semiconductor Device Research Symposium , pp. 268- 269,
December, 2005.
691. A. Datta, S. Bhunia, S Mukhopadhyay, J. Choi, and K. Roy, “Speed Binning Aware Design Methodology to Improve Profit under Parameter Variation”, Asia and South Pacific Design Automation
Conference (ASPDAC), January 2006, pp. 712 - 717.
692. H. Li, Y. Chen, K. Roy, and C.-K. Koh, “SAVS: A Self-Adaptive Variable Supply Voltage Technique
for Process-Tolerant and Power-Efficient Multi-Issue Superscalar Processor Design,” Asia and South
Pacific Design Automation Conference (ASPDAC), pp. 158-163, January 2006.
693. A. Goel, S. Bhunia, H. Mahmoodi, and K. Roy, “A Low-Overhead Design of Soft-Error-Tolerant
Scan Flip-Flop with Enhanced-Scan Capability,” Asia and South Pacific Design Automation Conference (ASPDAC), pp. 665-670, January 2006.
694. A. Bansal, M. Meterelliyoz, J. Choi, K. Roy, and J. Murthy, “Device/Circuit Co-Design for Effcient
Thermal Solutions for FinFET Technology,” Asia and South Pacific Design Automation Conference
(ASPDAC), Invited Paper, pp. 237-242, January 2006.
695. J. Park, J. H. Choi and K. Roy, “Dynamic Bit-Width Adaptation in DCT : Image Quality Versus
Computation Energy Trade-off”, IEEE Design and Test in Europe (DATE), March 2006.
65
696. Q. Chen, S. Mukhopadhyay, A. Bansal, and K. Roy, “Circuit-Aware Device Design Methodology
for Nanometer Technologies: A Case Study for Low Power SRAM Design”, IEEE Design and Test
in Europe (DATE), March 2006.
697. N. Banerjee, H. Mahmoodi, S. Bhunia, and K. Roy, “Low Power Synthesis of Dynamic Logic Circuits
using Fine-Grained Clock Gating”, IEEE Design and Test in Europe (DATE), March 2006.
698. A. Raychowdhury, B. Paul, S. Bhunia, and K. Roy, “Computing With Subthreshold Leakage: A
Comparative Study of Bulk and SOI Technologies”, IEEE Design and Test in Europe (DATE),
March 2006.
699. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam and K. Roy,“Temporal Performance Degradation
Under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits”, IEEE Design
and Test in Europe (DATE), March 2006.
700. M. M. Budnik, K. Roy, “Minimizing Ohmic Loss and Supply Voltage Variation Using a Novel
Distributed Power Supply Network”, IEEE Design and Test in Europe (DATE), March 2006.
701. M. M. Budnik, K.Roy, “Minimizing Ohmic Loss in Nanoscale Microprocessor IR Events”, IEEE
International Symposium on Quality Electronic Design (ISQED), March 2006.
702. Q. Chen, M. Meterelliyoz, and K. Roy, ”A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design,” IEEE International Symposium on Quality Electronic Design (ISQED)
2006, 243-248.
703. S. Mukhopadhyay, K. Kim, H. Mahmoodi, A. Datta, D. Park, and K. Roy, “Self-Repairing SRAM
for Reducing Parametric Failures in Nanoscaled Memory”, IEEE 2006 Symposium on VLSI Circuits,
June 2006.
704. M. M. Budnik, A. Raychowdhury, and K.Roy,“Power Delivery for Nanoscale Processors with Single
Wall Carbon Nanotube Interconnects”, IEEE Conference on Nanotechnology, 2006.
705. M. M. Budnik, A. Raychowdhury, A. Bansal, and K.Roy,“A High Density, Three-Dimensional,
Carbon Nanotube Capacitor Structure”, IEEE/ACM Design Automation Conference (DAC), July
2006.
706. H. Ananthan, and K. Roy, “A Fully Physical Model for Leakage Distribution under Process Variations in Nanoscale Double-Gate CMOS”, IEEE/ACM Design Automation Conference (DAC), July
2006.
707. S. Ghosh, S. Mukhopadhyay, and K.Roy, “Self-Calibration Technique for Reduction of Hold Failures
in Low-Power Nano-scaled SRAM”, IEEE/ACM Design Automation Conference (DAC), July 2006.
708. A. Raychowdhury, A. Keshavarzi, J. Kurtin, V. De, and K. Roy, Optimal Spacing of Carbon
Nanotubes in a CNFET Array for Highest Performance, IEEE Device Research Conference, 2006,
pp. 129-130.
709. J. Li, A. Bansal, and K. Roy, “Exploring Low Temperature Poly-Si for Low Cost and Low Power
Sub-micron Digital Operation”, IEEE Device Research Conference, 2006, pp. 61-62.
710. B. Paul, and K. Roy, “Optimizing Oxide Thickness for Digital Sub-threshold Operation”, IEEE
Device Research Conference, 2006, pp. 63-64.
711. S. Gangwal, S. Mukhopadhyay, and K. Roy, Optimization Of Surface Orientation For High-Performance,
Low-Power And Robust FinFET SRAM, IEEE Custom Integrated Circuits Conference, September
2006.
712. A. Raychowdhury, J. Kim, D. Peroulis and K. Roy, Integrated MEMS Switches for Leakage Control
of Battery Operated Systems, IEEE Custom Integrated Circuits Conference, September 2006.
66
713. S. Mukhopadhyay, A. Agarwal, Q. Chen and K. Roy, SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design, IEEE Custom Integrated
Circuits Conference, September 2006, Invited Paper.
714. A. Raychowdhury, X. Fong, Q. Chen, and K. Roy, Analysis of Super Cut-off Transistors for Ultralow
Power Digital Logic Circuits, ACM International Symposium on Low Power Electronics and Design,
2006. Best Paper Award.
715. I. Chang, J. Kim, and K. Roy, ,ACM International Symposium on Low Power Electronics and
Design, 2006.
716. T. Cakici, B. Jung, and K. Roy, High Q and High Tuning Range FinFET Varactors for Low-Cost
SoC Integration, IEEE SOI Conference, October 2006.
717. J. Choi, A. Bansal, M. Meterilliyoz, K. Roy, and J. Murthy, Leakage Power Dependent Temperature
Estimation to Predict Thermal Runaway in FinFET Circuits, IEEE International Conference on
Computer-Aided Design of ICs (ICCAD), 2006.
718. S. Ghosh, S. Bhunia, and K. Roy, A New Paradigm for Low-power, Variation-Tolerant and Adaptive
Circuit Synthesis Using Critical Path Isolation, IEEE International Conference on Computer-Aided
Design of ICs (ICCAD), 2006.
719. S. Mukhopadhyay, K. Kim, K. Jenkins, C.-T. Chuang, and K. Roy, ”Statistical Characterization
and On-Chip Measurement Methods for Local Random Variability Using Sense-Amplifier-Based
Test Structure,” 2007 International Solid-State Circuits Conference (ISSCC), February 2007.
720. T. Cakici, K. Kim, and K. Roy, FinFET Based SRAM Design For Low Standby Power Applications,
International Symposium on Quality of IC Design, March 2007.
721. J. Kulkarni and K. Roy, A High Performance, Scalable Multiplexed Keeper Technique, International
Symposium on Quality of IC Design, March 2007.
722. S. Ghosh, S. Bhunia, and K. Roy, Low-Overhead Circuit Synthesis for Temperature Adaptation
using Dynamic Voltage Scheduling, Design Automation and Test in Europe, April 2007.
723. N. Banerjee, G. Karakonstantis, and K. Roy, Process Variation Tolerant Low-Power DCT Architecture, Design Automation and Test in Europe, April 2007.
724. M. Hwang, T. Cakici, A. Raychowdhury, and K. Roy, Process Variation Tolerant Beta-ratio Modulation with Ultra Dynamic Voltage Scaling, Design Automation and Test in Europe, April 2007.
725. G. Karakonstantis and K. Roy, An Optimal Algorithm for Low Power Multiplierless FIR Filter
Design using Chebychev Criterion, International Conference on Acoustics, Speech, and Signal Processing (ICASSP-2007), 2007.
726. K. Kang, E. Islam, M. Alam, and K. Roy, Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement, ACM/IEEE Design Automation
Conference, June, 2007. Nominated for Best Paper Award.
727. K. Kang, K. Kim, and K. Roy, Variation Resilient Low-Power Circuit Design Methodology using OnChip Phase Locked Loop, ACM/IEEE Design Automation Conference, June, 2007. Nominated
for Best Paper Award
728. J. Li, K. Kang, A. Bansal, and K. Roy, High Performance and Low Power Electronics on Flexible
Substrate, ACM/IEEE Design Automation Conference, June, 2007.
729. A. Freuhling, D. Peroulis, and K. Roy, RF MEMS Switches for Leakage Control in Wireless Handheld Devices, 2007 IEEE APS International Symposium on Antennas and Propagation, Honolulu,
Hawaii, USA, June 10-15, 2007.
67
730. M. Hwang, K. Kim, A. Raychowdhury, and K. Roy, An 85mV 40nW Process Tolerant Subthreshold
8x8 FIR Filter in 130nm Technology, IEEE VLSI Circuit Symposium, June 2007.
731. D. Lakshmanan, A. Bansal, ”Body Thickness Optimization and Sensitivity Analysis for High Performance FinFETs,” Device Research Conference, 2007.
732. S. Ghosh, S. Bhunia, and K. Roy, ”A Fault Tolerant Technique for Improved Yield in Nanometer
Technologies by Adaptive Clock Stretching,” International On-Line Test Symposium, 2007.
733. M. Hwang and K. Roy, Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Model,
ACM/IEEE International Symposium on Low Power Electronics and Design, August 2007.
734. J. Kulkarni, K. Kim, and K. Roy, A 160 mV, Fully Differential, Robust Schmitt Trigger based
Sub-threshold SRAM,ACM/IEEE International Symposium on Low Power Electronics and Design,
August 2007.
735. D. Mohapatra, G. Karakonstantis, and K. Roy, Low-Power Process-Variation Tolerant Arithmetic
Units Using Input-Based Elastic Clocking, ACM/IEEE International Symposium on Low Power
Electronics and Design, August 2007.
736. N. Banerjee, G. Karakonstantis, and K. Roy, A Process Variation Aware Low Power Synthesis
Methodology for Fixed-point FIR filters, ACM/IEEE International Symposium on Low Power Electronics and Design, August 2007.
737. K. Kim, H. Mahmoodi, and K. Roy, A Low-Power SRAM using Bit-Line Charge-Recycling Technique, ACM/IEEE International Symposium on Low Power Electronics and Design, August 2007.
738. D. Lekshmanan, A. Bansal, and K. Roy, FinFET SRAM: Optimizing Silicon Fin Thickness and Fin
Ratio to Improve Stability at Iso Area, IEEE Custom Integrated Circuits Conference, 2007.
739. R. Rao, A. Bansal, J. Kim, K. Roy, and C.T. Chuang, Accurate Modeling and analysis of Currents
in Trapezoidal FinFET Devices, IEEE SOI Conference, October 2007.
740. K. Kang, S. Park, K. Roy, and A. Alam, Estimation of Statistical Variation in Temporal NBTI
Degradation and its Impact on Lifetime Circuit Performance, IEEE International Conference on
Computer-Aided Design (ICCAD), November 2007. Nominated for Best Paper Award
741. G. Karakonstantis, N. Banerjee, K. Roy, C. Chakrabarti, Design Methodology to trade off Power,
Output Quality and Error Resiliency: Application to Color Interpolation Filtering, IEEE International Conference on Computer-Aided Design (ICCAD), November 2007.
742. J. Choi, K. Roy, and J. Murthy, The Effect of Process Variation on Device Temperature on FinFET
Circuits, IEEE International Conference on Computer-Aided Design (ICCAD), November 2007.
743. S. Ghosh and K. Roy, Exploring High-Speed Low-Power Hybrid Arithmetic Units at Scaled Supply and Adaptive Clock-Stretching, IEEE Asia & South Pacific Design Automation Conference,
January 2008.
744. K. Kang, S. Park, S. Gangwal, and K. Roy, NBTI Induced Performance Degradation in Logic and
Memory Circuits: How Effectively Can We Approach a Reliability Solution? IEEE Asia & South
Pacific Design Automation Conference, January 2008.
745. N. Mojumder, S. Mukhopadhyay, J. Kim, C.-T. Chuang, and K. Roy, ”Design and Analysis of
a Self-Rapairing SRAM with On-Chip Monitor and Compensation Circuitry,”’ IEEE VLSI Test
Symposium, April 2008, pp. 101-106.
746. J. Kulkarni, M. Metterlliyoz, K. Roy, and J. Murthy, Nano-scaled SRAM Thermal Stability Analysis
Using Hierarchical Compact Thermal Models, Itherm 2008, Orlando, May 2008.
68
747. J. Li, C. Augustine, S. Salahuddin, and K. Roy, ”‘Modeling of Failure Probability and Statistical
Design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) Array for Yield
Enhancement,”’ ACM/IEEE Design Automation Conference, June 2008.
748. J. Kulkarni, K. Kim, S. Park, and K. Roy, ”‘Process Variation Tolerant SRAM Array for Ultra Low
Voltage Applications,”’ ACM/IEEE Design Automation Conference, June 2008.
749. K. Roy, J. Kulkarni, and M. Hwang, ”Process-Tolerant Ultralow Voltage Digital Subthreshold
Design,” Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008. IEEE Topical
Meeting on; Jan 2008. Invited Paper.
750. A. Raychowdhury, V. De, S. Borkar, K. Roy, and A. Keshavarzi, ”‘Theory of Multi-tube Carbon
Nanotube Transistors for High Speed Variation-Tolerant Circuits,”’ Device Research Conference,
2008.
751. J. Li, H. Liu, S. Salahauddin, and K. Roy, ”‘Variation-Tolerant Spin-Torque Transfer (STT) MRAM
Array for Yield Enhancement,”’ IEEE Custom Integrated Circuits Conference, September 2008.
752. M. Meterelliyoz, P. Song, F. Stellan, J. Kulkarni, and K. Roy, ”‘A High Sensitivity Process Variation Sensor Utilizing Sub-threshold Operation,”’ IEEE Custom Integrated Circuits Conference,
September 2008.
753. M. Hwang and K. Roy, ”A 135mV 0.13uW Process Tolerant 6T Subthreshold DTMOS SRAM in
90nm Technology,”’ IEEE Custom Integrated Circuits Conference, September 2008.
754. N. Banerjee, C. Augustine, and K. Roy, ”Fault-Tolerance with Graceful Degradation in Quality: A
Design Methodology and its Application to Digital Signal Processing Systems,” IEEE Defect and
Fault Tolerant Symposium, October 2008.
755. J. Li, P. Ndai, A. Goel, H. Liu, and K. Roy, ”An Alternate Design Paradigm for Robust Spin-Torque
Transfer Magnetic RAM (STT MRAM) from Circuit/Architecture Perspective,” IEEE Asia and
South Pacific Design Automation Conference, Jan. 2009.
756. M. Meterlliyoz and K. Roy, ”Design for Burn-In Test: A Technique for Burn-In Thermal Stability under Die-to-Die Parameter Variations,” IEEE Asia and South Pacific Design Automation
Conference, Jan. 2009.
757. C. Augustine, B. Behin-Aein, X. Fong, and K. Roy, ”A Design Methodology and Device/Circuit/Architecture
Compatible Simulation Framework for Low-Power Magnetic Quantum Cellular Automata Systems,”
IEEE Asia and South Pacific Design Automation Conference, Jan. 2009.
758. C. Augustine, A. Raychowdhury, Y. Gao, M. Lundstrom, and K. Roy, ”PETE: A device/circuit
analysis framework for evaluation and comparison of charge based emerging devices,” International
Conference on Quality of IC Design, March 2009.
759. S.Raghunathan, M.P. Ward, K. Roy and P.P. Irazoqui, A Low-power Implantable Event based
seizure detection algorithm, 4th International IEEE EMBS Conference on Neural Engineering,
March 2009, Antalya, Turkey.
760. A. Goel, S. Gupta, A. Bansal, M.-H. Chiang and K. Roy. ”Double-Gate MOSFETs with Asymmetric Drain Underlap: A device-circuit co-design and optimization perspective for SRAM”, Device
Research Conference, pp. 57-58, June 2009.
761. G. Panagopoulis and K. Roy, ”‘A Physics-Based 3-D Analytical Model for Threshold Voltage variations Considering RDF,” Device Research Conference, June 2009.
762. S. Raghunathan, S. Gupta, K. Roy and P. Irazoqui, Designing Epileptic Seizure Detection Algorithms Towards a Miniature Implantable Epilepsy Prosthesis, 4th International Workshop on
Seizure Prediction (IWSP), Kansas City, MO, June 2009.
69
763. S. Raghunathan, S. Gupta, K. Roy and P. Irazoqui, An Implantable Ultra-low Power Digital Circuit
Implementation of a Seizure Detection Algorithm, BMES 2009 Annual Fall Meeting, Pittsburg, PA,
USA, October 2009.
764. C. Augustine, B. Behin-Aein, and K. Roy, ”Nano-Magnet Based Ultra-Low Power Logic Design
Using Non-Majority Gates,” IEEE NANO, July 2009, Genoa, Italy.
765. K. Roy, J. Kulkarni, and S. Gupta, ”Device/Circuit Interactions at 22nm Technology Node,” invited presentation, ACM/IEEE Design Automation Conference, July 2009.
766. I. Chang, D. Mohapatra, and K. Roy, ”A Voltage-Scalable and Process Variation Resilient Hybrid
SRAM Architecture for MPEG-4 Video Processors,” ACM/IEEE Design Automation Conference,
pp. 670-675, July 2009.
767. D. Mohapatra, G. Karakonstantis, and K. Roy, ”Significance Driven Computation: A VoltageScalable Variation-Aware, Quality-Tuning Motion Estimator,” International Symposium on LowPower Electronics and Design (ISLPED), pp. 195-200, August 2009.
768. G. Karakonstantis, D. Mohapatra, K. Roy, System Level DSP Synthesis Using Voltage Overscaling,
Unequal Error Protection & Adaptive Quality Tuning, IEEE Signal and Information Processing
Systems (SIPS), pp.133-138, August 2009.
769. A. Goel, P. Ndai, J. Kulkarni and K. Roy,”REad/Access-Preferred (REAP) SRAM -ArchitectureAware Bit Cell Design for Improved Yield and Lower VMIN”, IEEE Custom Integrated Circuits
Conference, pp. 503-506, 2009.
770. S. Raghunathan, S. Gupta, H. Markandeya, K. Roy and P. Irazoqui, Co-design of Hardware and
Software to Optimize Seizure Prediction and Detection Algorithms Towards a Closed Loop Epilepsy
Prosthesis, Proceedings of the American Epilepsy Society (AES) Annual Meeting, Boston, USA,
December 4-9, 2009.
771. M. Meterelliyoz, A. Goel, J. Kulkarni and K. Roy, Accurate Characterization of Random Process
Variations using a Robust, Low Voltage, High Sensitivity Sensor featuring Replica Bias Circuit,
IEEE International Solid State Circuits Conference (ISSCC) 2010, pp. 186-187.
772. C. Lu, V. Raghunathan, and K. Roy, ”Micro-scale Energy Harvesting: A System Perspective, Asia
and South Pacific Design Automation Conference (ASPDAC), Taipei, Taiwan, pp. 89-94, 2010.
773. C. Lu, V. Raghunathan, and K. Roy, Efficient Power Conversion for Ultra Low Voltage Micro Scale
Energy Transducers, Design Automation and Test in Europe (DATE), pp. 1602-1607, 2010.
774. I. Vatajelu, G. Panagopoulos, K. Roy and J. Figueras, Parametric Failure Analysis of Embedded
SRAMs using Fast & Accurate Dynamic Analysis, European Test Symposium, Prague, May 2010.
775. C. Lu, V. Raghunathan, and K. Roy, Maximum Power Point Considerations for Micro-Scale Solar
Energy Harvesting Systems, IEEE International Symposium on Circuits and Systems (ISCAS),
invited paper, 2010.
776. V. Chippa, D. Mohapatra, A. Raghunathan, K. Roy, and S. Chakradhar, ”Scalable Effort Hardware
Design: Exploiting Algorithmic Resilience for Energy Efficiency,” IEEE/ACM Design Automation
Conference, Annaheim, California, June 2010.
777. N. Mojumder, S. Gupta, D. Nikonov, and K. Roy, ”Spin Torques Estimation and Magnetization
Dynamics in Dual Barrier Resonant Tunneling Penta-Layer Magnetic Tunnel Junctions,” 2010
Device Research Conference, pp. 93-94, June 21-23, 2010.
778. N. Mojumder, C. Augustine, and K. Roy, Self-Consistent Micro-Magnetic Simulation and Benchmarking of Different Spin-Torque Driven Magnetic Tunnel Junctions (MTJs), IEEE University
Government Industry Micro/Nano Symposium, Purdue University, West Lafayette, Indiana, pp.
95-100, June 28-July1 2010.
70
779. Y. Gao, C. Augustine, D. E. Nikonov, K. Roy and M. Lundstrom, Realistic Spin-FET Performance
Assessment for Reconfigurable Logic Circuits, IEEE VLSI Technology Symposium, 2010.
780. G. Karakonstantis, C. Augustine, K. Roy, ”A Self-Consistent Model to Estimate NBTI Degradation
and a On-Line Lifetime Enhancement Technique,” IEEE International On-Line Testing Symposium,
July 2010.
781. C. Augustine, X. Fong and K. Roy, Dual Ferroelectric Capacitor Architecture and its Application
to TAG RAM, ICICDT, 2010.
782. G. Karakonstantis, G. Panagopoulos, K. Roy, ”HERQULES: System Level Cross- Layer Design
Exploration for Efficient Energy-Quality Trade-offs,” IEEE International Symposium on Low Power
Design, August, 2010.
783. H. Markandeya, G. Karakonstantis, K. Roy, ”Low-Power Wavelet-Based Quasi- Averaging Algorithm and Architecture for Epileptic Seizure Detection,” IEEE International Symposium on Low
Power Design, August, 2010.
784. V. Gupta, G. Karakonstantis, D. Mohapatra, and K. Roy, VEDA: Variation-aware Energy-efficient
Discrete Wavelet Transform Architecture”, IEEE International Conference on Computer Design,
2010.
785. F. Moradi, C. Augustine, A. Goel, G. Karakonstantis, D. Wisland, H. Mahmoodi, K. Roy, ”DataDependent Sense-Amplifier Flip-Flop for Low Power Applications,” IEEE Custom Integrated Circuits Conference, October, 2010.
786. C. Augustine, A. Raychowdhury, D. Somsekhar, J. Tschanz, K. Roy, and Vivek De, Numerical
Analysis of Typical STT-MTJ Stacks for 1T-1R Memory Arrays, IEEE International Electron
Devices Meeting (IEDM), 2010.
787. C.-H. Ho, C. Lu, D. Mohapatra, and K. Roy, ”Variation-Tolerant and Self-Repair Design Methodology for Low Temperature Polycrystalline Silicon Liquid Crystal and Organic Light Emitting Diode
Displays,” IEEE/ACM Asia and Soth Pacific Design Automation Conference, Jan. 2011.
788. D. Mohapatra, V. Chippa, A. Raghunathan, and K. Roy, ”Design of Voltage-scalable Meta-functions
for Approximate Computing,” IEEE Design and Test in Europe (DATE) 2011, pp. 1-6.
789. M. Alam, K. Roy, and C. Augustine, ”Reliability- and Process-Variation Aware Design of Integrated
Circuits A Broader Perspective,” International Reliability Physics Symposium, May, 2011. Invited
Paper.
790. D. Lee, S.-P. Park, A. Goel, and K. Roy, ”Memory-based Embedded Digital ATE,” IEEE VLSI
Test Symposium, May 2011.
791. V. Chippa, A. Raghunathan, S. Chakradhar, and K. Roy, ”Dynamic Effort Scaling: Managing the
Quality-Efficiency Tradeoff,” ACM/IEEE Design Automation Conference, June, 2011.
792. G. Karakonstantis, N. Bellas, and K. Roy, ”Significance Driven Computation on Next-Generation
Unreliable Platforms,” ACM/IEEE Design Automation Conference, June, 2011.
793. E. Mungan and K. Roy, ””2D Modeling and Optimization of Excimer Laser Annealed Thin Film
Polysilicon Solar Cells,” 37th Photovoltaic Specialists Conference, June, 2011.
794. N. Majumder, Sumit Gupta, and K. Roy, ””Dual Pillar Spin Transfer Torque MRAM with Tilted
Magnetic Anisotropy for Fast & Error-free Switching,” Device Research Conference, June, 2011.
795. G. Panagopolous, C. Augustine, and K. Roy, ”Modeling of Dielectric Breakdown-Induced TimeDependent STT-MRAM Performance Degradation,” Device Research Conference, June, 2011.
71
796. B. Jung, K. Roy, S. Bhagavatula, and J. Lee, ”Self-Healing Design In Deep Scaled CMOS Technologies,” IEEE Midwest Symposium on Circuits and Systems, Seoul, Korea, August, 2010.
797. S.-P. Park, D. Lee, S. Kim, J. Kim, W. Griffin, and K. Roy, ”Column-Selection-Enabled 8T SRAM
Array with 1R/1W Multi-Port Operation for DVFS-Enabled Processors,” IEEE/ACM Symposium
on Low Power Electronics and Design, August, 2011.
798. V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy, ”IMPACT: IMPrecise adders for lowpower Approximate CompuTing,” IEEE/ACM Symposium on Low Power Electronics and Design,
August, 2011.
799. M. Sharad, S. K. Gupta, S. Raghunathan, P. Irazoqui, and K. Roy, ” Ultra Low Power, LPFOnly DWT Architecture for an Epileptic Seizure Prosthesis Implant, Subthreshold Microelectronics
Conference, MIT Lincoln Labs, 2011.
800. X. Fong, S. Gupta, N. Mojumder, H. Choday, and K. Roy, ”KNACK: A Hybrid Spin-Charge MixedMode Simulator for Evaluating Different Genres of STT-MRAMs,” IEEE International Conference
on Simulation of Semiconductor Processes and Devices (SISPAD 2011), Osaka, Japan, September
8-10, 2011.
801. R. Venkatesan, A. Agarwal, K. Roy, and A. Raghunathan, ”MACACO: Modeling and Analysis of
Circuits for Approximate Computing,” IEEE International Conference on Computer-Aided Design,
pp. 667-673, November 2011.
802. C. Augustine, A. Raychowdhury, B. Behin-Aein, J. Tschanz, V.K. De, and K. Roy, ”Numerical
Analysis of Domain Wall Propagation for Dense Memory Arrays,” IEEE Electron Devices Meeting
(IEDM), December 2011.
803. S. Gupta, S. Choday, and K. Roy, ”Exploration of Device-Circuit Interactions in FinFET-based
Memories for Sub-15nm Technologies Using a Mixed Mode Quantum Simulation Framework: Atoms
to Systems,” IEEE Electron Devices Meeting (IEDM), December 2011.
804. S. Gupta, S. Park, N. Mojumder, and K. Roy, ”Layout-aware Optimization of STT MRAMs,” IEEE
Design and Test in Europe (DATE), April 2012.
805. G. Panagopoulos, C. , and K. Roy, ”A Framework for Simulating Hybrid MTJ/CMOS circuits:
Atoms to System Approach,” IEEE Design and Test in Europe (DATE), April 2012, pp. 1443 1446.
806. S. Kim, W. Lok, S. Park, B. Jung, and K. Roy, ”Poly-Si Thin film Transistors: Opportunities for
Low-Cost RF Applications,” International Conference on IC Design and Technology, Austin, Texas,
April 2012.
807. M. Bubna, A. Goel, and K. Roy, ”HBIST: An Approach towards Zero External Test Cost,” IEEE
VLSI Test Symposium, April 2012.
808. C. Augustine, N. Mojumder, X. Fong, H. Choday, S. Park, and K. Roy, ”STT-MRAMs for future
universal memories: Perspective and Prospective,” 2012 28th International Conference on Microelectronics (MIEL), pp. 349 - 355, Nis, Serbia.
809. S. Park, S. Gupta, N. Mojumder, A. Raghunathan, and K. Roy, ”Future Cache Design using STT
MRAMs for Improved Energy Efficiency: Devices, Circuits, and Architecture,” ACM/IEEE Design
Automation Conference, June 2012.
810. M. Sharad, C. Augustine, G. Panagopoulos and K. Roy, Spin Based Neuron-Synapse Unit for
Ultra Low Power Programmable Computational Networks,IEEE International Joint Conference on
Neural Networks, 2012.
811. M. Sharad, C. Augustine, G. Panagopoulos, and K. Roy, ”Cognitive Computing with Spin-Based
Neural Networks,” ACM/IEEE Design Automation Conference, June 2012.
72
812. S. Venkataramani, A. Sabne, V. Kozhikkottu, K. Roy, and A. Raghunathan, ”SALSA: Systematic
Logic Synthesis of Approximate Circuits,” ACM/IEEE Design Automation Conference, June 2012.
813. M. Sharad G. Panagopoulos, C. Augustine, and K. Roy, ”NLSTT-MRAM: Robust Spin Transfer
Torque MRAM using Non-Local Spin Injection for Write,” Device Research Conference, June 2012.
814. G. Panagopoulos, C. Augustine, X. Fong, and K. Roy, ”Exploring Variability and Reliability of
Multi-Level STT-MRAM Cells,” Device Research Conference, June 2012.
815. S. Gupta, J. Kulkarni, S. Datta, and K. Roy, ”Dopant Straggle-free Hetreojunction Intra-band
Tunnel (HIBT) FETs with Low Drain-Induced Barrier Lowering/Thinning (DIBL/T) and Reduced
Variation in Off Current,” Device Research Conference, June 2012.
816. M. Sharad, G. Panagopoulos, and K. Roy, ”Spin-Neuron for Ultra Low Power Computational
Hardware,” Device Research Conference, June 2012, Invited Paper.
817. M. Sharad G. Panagopoulos, C. Augustine, and K. Roy, ”Ultra Low Energy Analog Image Processing Using Spin Based Neurons,” NANOARCH 8th ACM/IEEE International Symposium on
Nanoscale Architectures, July 2012, Amsterdam.
818. Y. Kim, S. Gupta, S. Park, G. Panagopoulos, and K. Roy, ”Write-Optimized Reliable Design of
STT MRAM,” ACM/IEEE International Symposium on Low Power Electronics and Design, JulyAugust, 2012, Best paper nomination.
819. D. Lee, S. Gupta, and K. Roy, ”High-Performance Low-Energy STT MRAM Based on Balanced
Write Scheme,” ACM/IEEE International Symposium on Low Power Electronics and Design, JulyAugust, 2012.
820. E. Mungan, L. Chao, V. Raghunathan, and K. Roy, ”Modeling, Design and Cross-Layer Optimization of Polysilicon Solar Cell Based Micro-scale Energy Harvesting System,” ACM/IEEE International Symposium on Low Power Electronics and Design, July-August, 2012.
821. R. Venkatesan, V. Kozhikkottu, C. Augustine, A. Raychowdhury, K. Roy, and A. Raghunathan,
”TapeCache: A High Density, Energy Efficient Cache Based on Domain Wall Memory,” ACM/IEEE
International Symposium on Low Power Electronics and Design, July-August, 2012, Best paper
award.
822. H. Markendeya, S. Raghunathan, P. Irazoqui, and K. Roy, ”A Low-power Near-threshold Epileptic
Seizure Detection Processor with Multiple Algorithm Programmability,” ACM/IEEE International
Symposium on Low Power Electronics and Design, July-August, 2012.
823. C.-H. Ho, G. Panagopoulos, and K. Roy, ”Physical Model to Predict Grain Boundary Induced Vth
Variation in Poly-Si TFTs,” International Conference on Simulation of Semiconductor Processes
and Devices (SISPAD), Sepetember 2012.
824. S. Gupta and K. Roy, ”Spacer Thickness Optimization for FinFET-based Logic and Memories: A
Device-Circuit Co-design Approach,” Electrochemical Society (ECS) Transactions, Hawaii, 50 (4),
2012, pp. 187-192.
825. M. Sharad, C. Augustine, and K. Roy, ”Boolean and Non-Boolean Computing with Spin Devices,”
International Electron Devices Meeting (IEDM), December 2012.
826. H. Choday, L. Chao, V. Raghunathan, and K. Roy, ”On–chip Energy Harvesting Using Thin-Film
Thermoelectric Materials,” Semi-Therm, March 2013.
827. M. Sharad, D. Fan, and K. Roy, ”Low Power and Compact Mixed-Mode Signal Processing Hardware
Using Spin-Neurons,” IEEE International Symposium on Quality of Electronic Design (ISQED),
March 2013.
73
828. M. Sharad, K. Yogendra, K. Kwon, and K. Roy, ”’Design Of Ultra High Density and Low Power
Computational Blocks Using Nano-Magnets,” IEEE International Symposium on Quality of Electronic Design (ISQED), March 2013.
829. R. Venkatesan, M. Sharad, K. Roy, A. Raghunathan, ”DWM-TAPESTRI - An Energy Efficient
Cache Design using Spin memory with Domain wall Shift based Writes”, IEEE Design and Test in
Europe (DATE), March 2013.
830. S. Venkataramani, K. Roy, and A. Raghunathan, ”Substitute-and-Simplify: A Unified Design
paradigm for Approximate and Quality Configurable Circuits,” IEEE Design and Test in Europe
(DATE), March 2013.
831. S.-Y. Kim, G. Panagopoulos, C.-H. Ho, M. Katoozi, E. Cannon, and K. Roy, ”A Compact SPICE
Model for Statistical Post-Breakdown Gate Current Increase Due to TDDB,” IEEE International
Reliability Physics Symposium (IRPS), April 2013.
832. X. Fong and K. Roy, ”Low-Power Robust Complementary Polarizer STT-MRAM (CPSTT) for
On-Chip Caches,” 2013 IEEE International Memory Workshop, May 2013, Monterey, California,
pp. 88-91.
833. V. Chippa, S. Chakradhar, K. Roy, and A. Raghunathan, ”Analysis and Characterization of Inherent Application Resilience for Approximate Computing,” IEEE/ACM Design Automation Conference (DAC), June 2013.
834. M. Sharad, D. Fan, and K. Roy, ”Ultra Low Power Computing With Resistive Crossbar Nets Using
Spin Neurons,” IEEE/ACM Design Automation Conference (DAC), June 2013.
835. C. Ho and K. Roy, ”A Physical Model to Predict STT-MRAM Performance Degradation Induced
by TDDB,” Device Research Conference (DRC), June 2013.
836. A. Akkala, S. Choday, S. Gupta, and K. Roy, ”Atomistic Tight-Binding based Study of Impact of
Underlap on Source to Drain Tunneling in Si FinFETs,” Device Research Conference (DRC), June
2013.
837. S. Gupta, A. Akkala, W. Choo, K. Yogendra, and K. Roy, ”Design Space Exploration of FinFETs
in Sub-10nm Technologies for Near-Threshold Circuits,” Device Research Conference (DRC), June
2013.
838. M. Sharad, K. Yogendra, and K. Roy, ”Energy Efficient Computing using Coupled Dual-Pillar Spin
Torque Nano Oscillators,” 2013 IEEE/ACM International Symposium on Nanoscale Architectures
(NaNOARCH), pp. 28-29.
839. M. Sharad, R. Venkatesan, A. Raghunathan, and K. Roy, ”Reading Spin-Torque Memory with SpinTorque Sensors,” 2013 IEEE/ACM International Symposium on Nanoscale Architectures (NaNOARCH),
pp. 40-41.
840. M. Sharad, R. Vekatasan, A. Raghunathan, and K. Roy, ”Domain-Wall Shift Based Multi-Level
MRAM for High-Speed, High-Density and Energy-Efficient Caches,” Device Research Conference
(DRC), June 2013.
841. X. Fong, and K. Roy, ”Robust Low-power Multi-terminal STT-MRAM,” Proc. of 13th Non-volatile
Memory Technology Symposium (NVMTS), August 2013.
842. M. Sharad, R. Venkatasan, A. Raghunathan, and K. Roy, ”Multi-level STT-MRAM Using Domain
Wall Magnet for Energy Efficient, High Density Caches,” IEEE/ACM International Symposium on
Low Power Electronics and Design (ISLPED), Sep. 2013, Beijing, China.
843. W. Griffin and K. Roy, ”Accelerated Variation Simulation through Parameter Reduction,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September
2013, Glasgow, Scotland.
74
844. X. Fong and K. Roy, ”A Hybrid Spin-Charge Mixed-mode Simulation Framework for Evaluating
Spin-Transfer Torque MRAM Bit-cells Utilizing Multiferroic Tunneling Junctions,” International
Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September 2013,
Glasgow, Scotland.
845. C.-H. Ho, G. Panagopoulos, and K. Roy, ”A Physics-Based Statistical Model for Reliability of STTMRAM Considering Oxide Variability,” International Conference on Simulation of Semiconductor
Processes and Devices (SISPAD), September 2013, Glasgow, Scotland.
846. C.-W. Lin, C.-H. Ho, C. Lu, M. Chao, and K. Roy, ”A Process/Device/Circuit/System Compatible
Simulation Framework for Poly-Si TFT Based SRAM Design,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), September 2013, Glasgow, Scotland.
847. V. Chippa, H. Jayakumar, D. Mohapatra, K. Roy, and A. Raghunathan, ”Energy Efficient Recognition and Mining Processor using Scalable Effort Design,” IEEE Custom Integrated Circuits Conference (CICC), September 2013.
848. K. Roy, M. Sharad, D. Fan, and K. Yogendra, ”Exploring Boolean and Non-Boolean Computing
with Spin Torque Devices,” IEEE International Conference on Computer-Aided Design, November
2013, invited paper.
849. T. Naphade, K. Roy, and S. Mahapatra, ”A Novel Physics-Based Variable NBTI Simulation Framework from Small Area Devices to 6T-SRAM,” IEEE Electron Devices Meeting (IEDM), December
2013.
850. M. Sharad, X. Fong, and K. Roy, ”Ultra-Low Energy Global Interconnects Based on Spin Torque
Switches,” IEEE Electron Devices Meeting (IEDM), December 2013.
851. K. Roy, M. Sharad, D. Fan, and K. Yogendra, ”Brain-Inspired Computing with Spin-Torque Devices,” IEEE design Automation and Test In Europe (DATE), Dresden, Germany, 2014.
852. S. Venkataramani, A. Ranjan, K. Roy, A. Raghunathan, ”AxNN: energy-efficient neuromorphic
systems using approximate computing,” IEEE design Automation and Test In Europe (DATE),
Dresden, Germany, 2014.
853. A. Ranjan, A. Raha, S. Venkataramani, A. Ranjan, K. Roy, A. Raghunathan, ”ASLAN: Synthesis of
approximate sequential circuits,” IEEE design Automation and Test In Europe (DATE), Dresden,
Germany, 2014.
854. L. Zhang, X. Fong, C. H. Chang, Z. H. Kong, and K. Roy, ”Highly reliable physical unclonable
function using spin-transfer torque MRAM,” Proc. of 2014 IEEE Int. Symp. on Circuits and
Systems, May 2014.
855. X. Fong, Mei-Chin Chen, and K. Roy, ”Generating true random numbers using on-chip complementary polarizer spin-transfer torque magnetic tunnel junctions,” in Proc. of 72nd Device Research
Conference (DRC), Jun. 2014, pp. 103-104
856. S. Venkatramani, A. Ranjan, K. Roy, and A. Raghunathan, ”AxNN: Energy Efficient Neuromorphic
Systems using Approximate Computing,” ACM/IEEE International Symposium on Low Power
Electronics and Design, La Jolla, California, August 2014.
857. S. Ramasubramanian, R. Venkatasan, M. Sharad, K. Roy, and A. Raghunathan, ”SPINDLE: SPIntronic Deep Learning Engine for Large-scale Neuromorphic Computing,” ACM/IEEE International
Symposium on Low Power Electronics and Design, La Jolla, California, August 2014.
858. V. Chippa, S. Venkatramani, K. Roy, and A. Raghunathan, ”StoRM: Stochastic Recognition and
Mining Processor,” ACM/IEEE International Symposium on Low Power Electronics and Design,
La Jolla, California, August 2014.
75
859. S.H. Choday, K. Kwon, and K. Roy, ”Workload Dependent Evaluation of Thin-Film Thermoelectric Devices for On-Chip Cooling and Energy Harvesting,” IEEE International Conference on
Computer-Aided Design, San Jose, California, November, 2014.
860. K. Yogendra, M.-C. Chen, X. Fong, and K. Roy, ”Domain Wall Motion based Low Power Hybrid
Spin-CMOS 5-bit Flash Analog Data Converter,” IEEE Symposium on Quality of Electronic Design,
March 2015.
861. A. Ranjan, S. Ramasubramanian, R. Venkatesan, V. Pai, K. Roy and A, Raghunathan, ”DYRECTAPE: A Dynamically Reconfigurable Cache using Domain Wall Memory Tapes,” Design, Automation and Test in Europe (DATE), March 2015.
862. S. Venkatramani, S. Chakradhar, K. Roy, A. Raghunathan, ”Computing Approximately and Efficiently,” Design, Automation and Test in Europe (DATE), March 2015.
863. A. Akkala, R. Venkatesan, A. Raghunathan, and K. Roy, ”Asymmetric Underlapped FinFET Based
Robust SRAM Design at 7nm Node,” Design, Automation and Test in Europe (DATE), March 2015.
864. A. Sharma, A. Akkala, and K. Roy, ”Sub-10 nm FinFETs and Tunnel-FETs: From Devices to
Systems,” Design, Automation and Test in Europe (DATE), March 2015.
865. Z. Pajouhi, X. Fong, and K. Roy, ”Device/Circuit/Architecture Co-Design of Reliable STT-MRAM,”
IEEE Design, Automation and Test in Europe (DATE), March 2015.
866. A. Sharma, A. Akkala, and K. Roy, P-channel Tunneling Field Effect Transistor (TFET): Sub10nm Technology Enablement by GaSb-InAs with Doped Source Underlap, IEEE Device Research
Conference, Columbus, Ohio, June 2015.
867. S. Venkataramani, S. Chakradar, K. Roy, and A. Raghunathan, ”Approximate Computing and the
Quest for Computing Efficiency,” ACM/IEEE Design Automation Conference, Invited paper,
June, 2015.
868. A. Ranjan, S. Venkataramani, X. Fong, K. Roy, and A. Raghunathan, ”Approximate Storage for
Energy Efficient Spintronic Memories, ACM/IEEE Design Automation Conference, June, 2015.
869. A. Sengupta and K. Roy, ”Spin-Transfer Torque Magnetic Neuron for Low Power Neuromorphic
Computing,” IEEE Joint Conference on Neural Networks (IJCNN), July 2015.
870. W. Cho and K. Roy, ”Leakage Reduction in Stacked Sub-10nm Double-Gate MOSFETs”, IEEE
2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD),
Washington DC, September 2015.
871. A. Sengupta, P. Panda, A. Raghunathan, and K. Roy, ”Neuromorphic Computing Enabled by
Spin-Transfer Torque Devices,” IEEE International Conference on VLSI Design, Kolkata, India,
January 2016.
872. K. Yoegndra, D. Fan, Y. Sim, M. Koo, and K. Roy, ”Computing with Coupled Spin Torque Nano
Oscillators,” IEEE Asia Pacific Design Automation Conference, invited paper, Macau, January
2016.
873. S. Venkatramani, K. Roy, and A. Raghunathan, ”Efficient Embedded Learning for IoT Devices,”
IEEE Asia Pacific Design Automation Conference, invited paper, Macau, January 2016.
874. A. Sengupta, K. Yogendra, D. Fan, and K. Roy, ”Prospects of Efficient Neural Computing with
Arrays of Magneto-metallic Neurons and Synapses,” IEEE Asia Pacific Design Automation Conference, invited paper, Macau, January 2016.
875. P. Panda, A. Sengupta, and K. Roy, ”Conditional Deep Learning for Energy-Efficient and Enhanced
Pattern Recognition,” IEEE Design, Automation and Test in Europe (DATE), March 2016.
76
876. G. Srinivasan, P. Wijesinghe, S. Sarwar, A. Jaiswal, and K. Roy, ”Significance Driven Hybrid
8T-6T SRAM for Energy-Efficient Synaptic Storage in Artificial Neural Networks,” IEEE Design,
Automation and Test in Europe (DATE), March 2016.
877. S. Sarwar, S. Venkatramani, A. Raghunathan, and K. Roy, ”Multiplier-less Artificial Neurons Exploiting Error Resiliency for Energy-Efficient Neural Computing,” IEEE Design, Automation and
Test in Europe (DATE), March 2016.
878. A. Sengupta, K. Yogendra, and K. Roy, ”Spintronic devices for ultra-low power neuromorphic
computation,” em IEEE International Symposium on Circuits and Systems, Montreal, Canada,
May 2016.
879. P. Panda, A. Sengupta, S. Sarwar, G. Srinivasan, S. Venkatramani, A. Raghunathan, and K.
Roy, ”INVITED- Cross-Layer Approximations for Neuromorphic Computing: From Devices to
Circuits and Systems,” ACM/IEEE Design Automation Conference (DAC), June 2016, Austin,
Texas. Invited Paper
880. Y. Shim, A. Sengupta, and K. Roy, ”Low-Power Approximate Convolution Computing Unit with
Domain-Wall Motion Based Spin-Memristor for Image Processing Applications,” ACM/IEEE Design Automation Conference (DAC), June 2016, Austin, Texas.
881. A. Sengupta, A. Jaiswal, and K. Roy, ”True Random Number generation Using Voltage Controlled
Spin-Dice,” IEEE Device Research Conference, 2016, pp. 117-118.
882. T. Srimani, B. Manna, A. Mukhopadhyay, K. Roy, and M. Sharad, ”Robust and High Sensitivity
Biosensor using Injection Locked Spin Torque Nano-Oscillators,” IEEE Device Research Conference,
2016, pp. 167-168.
883. J. Allred and K. Roy, ”Unsupervised Incremental STDP Learning Using Forced Firing of Dormant
or Idle Neurons,” IEEE Joint International Conference on Neural Networks (IJCNN), July 2016,
Vancouver, Canada.
884. P. Panda and K. Roy, ”Unsupervised Regenerative Learning of Hierarchical Features in Spiking
Deep Networks for Object Recognition,” IEEE Joint International Conference on Neural Networks
(IJCNN), July 2016, Vancouver, Canada.
885. B. Han, A. Sengupta, and K. Roy, ”On the Energy Benefits of Spiking Deep Neural Networks:
A Case Study,” IEEE Joint International Conference on Neural Networks (IJCNN), July 2016,
Vancouver, Canada.
886. C. Liyanagendra, K. Yogendra, K. Roy, and D. Fan ”Spin Torque Nano-Oscillator based Oscillatory
Neural Network,” IEEE Joint International Conference on Neural Networks (IJCNN), July 2016,
Vancouver, Canada. nominated for best paper award.
887. S. Ahasan, S. Maji, K. Roy, and M. Sharad, ”Digital LDO with Time-Interleaved Comparators for
Fast Response and Low Ripple,” IEEE Computer Society Annual Symposium on VLSI, July 2016.
888. A. Sengupta, B. Han, and K. Roy, ”Toward a Spintronic Deep Learning Spiking Neural Processor,”
IEEE BioCAS (Biomedical Circuits and Systems) Conference, October 2016, Shanghai, China.
889. P. Wijesinghe, C. Liyanagendra, and K. Roy, ”Fast, Low-Power Evaluation of Elementary Functions
using Radial Basis Function Networks,” IEEE Design Automation and Testin Europe, March 2017.
890. G. Srinivasan, A. Sengupta, and K. Roy, ”Magnetic Tunnel Junction Enabled All-Spin Stochastic
Spiking Neural Network,” IEEE Design Automation and Testin Europe, March 2017.
891. P. Panda and K. Roy,” Semantic Driven Hierarchical Learning for Energy-Efficient Image Classification,” IEEE Design Automation and Testin Europe, March 2017.
77
892. A. Reza, K. Hassan, D. Patra, Y. Cao, and K. Roy, TDDB in HfSiON/SiO2 Dielectric Stack:
Bttiker Probe Based NEGF Modeling, Prediction and Experiment , IEEE International Reliability
Physics Symposium, 2017.
893. A. Sengupta, A. Ankit, and K. Roy, ”Performance Analysis and Benchmarking of All-Spin Spiking
Neural Networks,” International Joint Conference on Neural Networks, May 2017.
894. C. Liyanagendra, P. Wejisinghe, A. Jaiswal, and K. Roy, ”Image Segmentation with Stochastic Magnetic Tunnel Junctions and Spiking Neurons,” International Joint Conference on Neural Networks,
May 2017.
895. P. Panda, G. Srinivasan, and K. Roy, ”EnsembleSNN: Distributed Assistive STDP learning for
Energy-Efficient Conditional Inference in Spiking Neural Networks,” International Joint Conference
on Neural Networks, May 2017.
896. G. Srinivasan, S. Roy, V. Raghunathan, and K. Roy, ”Spike Timing Dependent Plasticity Based Enhanced Self-Learning for Efficient Pattern Recognition in Spiking Neural Networks,” International
Joint Conference on Neural Networks, May 2017.
897. J. Allred and K. Roy, ”Convolving over Time via Recurrent Connections for Sequential Weight
Sharing in Neural Networks,” International Joint Conference on Neural Networks, May 2017.
898. A. Ankit, A. Sengupta, P. Panda, and K. Roy, ”RESPARC: A Reconfigurable and Energy-Efficient
Architecture with Memristive Crossbars for Deep Spiking Neural Networks,” ACM/IEEE Design
Automation Conference, June 2017.
899. K. Yogendra, M. Koo, and K. Roy, ”Energy Efficient Computation using Injection Locked Bias-field
Free Spin-Hall Nano-oscillator Array with Shared Heavy Metal,” IEEE International Symposium
on Nanoscale Architectures (NANOARCH), 2017.
900. Z. Azim and K. Roy, ”Spin-Torque Sensors with Differential Signaling for Fast and Energy Efficient
Global Interconnects,” IEEE/ACM International Symposium on Low Power Electronics and Design,
Taipei, July 2017.
901. S. Sarwar, P. Panda, and K. Roy, ”Gabor Filter Assisted Energy Efficient Fast Learning Convolutional Neural Networks,” IEEE/ACM International Symposium on Low Power Electronics and
Design, Taipei, July 2017.
902. Y. Shim, A. Jaiswal, and K. Roy, ”Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization,” International Conference on Computer Design )ICCD), 2017,
pp. 605-608.
903. A. Ankit, A. Sengupta, and K. Roy,TraNNsformer: Neural Network Transformation for Efficient
Crossbar Based Neuromorphic System Design, IEEE International Conference on Computer-Aided
Design of ICs, Irvine, California, November, 2017.
904. S. Jain, S. Sapatnekar, J. Wang, K. Roy, and A. Raghunathan, ”Computing-in-Memory with Spintronics,” IEEE Design and Test in Europe (DATE), March 2018.
905. A. Sengupta, Y. Shim, and K. Roy, ”Stochastic Switching of Nanomagnets for Post-CMOS Computing,” Bulletin of American Physical Society, March 2017, invited presentation.
906. D. Mikhailenko, C. Liyanagendra, A. James, and K. Roy, ”M 2 CA: Modular Memristive Crossbar
Arrays,” Intenational Symposium on Circuits and Syatems (ISCAS), Florence, Italy, May, 2018.
907. A. Agrawal and K. Roy, ”RECache: ROM-Embedded 8-Transistor SRAM Caches for Efficient
Neural Computing,” IEEE Signal Processing Symposium (SiPS), October 2018.
908. A. Ankit, A. Sengupta, and K. Roy, ”Neuromorphic Computing Across the Stack: Devices, Circuits
and Architectures.” IEEE Signal Processing Symposium (SiPS), October 2018.
78
909. A. Sengupta, G. Srinivasan, D. Roy, and K. Roy, ”Stochastic Inference and Learning Enabled by
Magnetic Tunnel Junctions,” International Electron Device Meeting (IEDM), December 2018, San
Francisco, Invited Paper.
910. A. Ankit, I. Hajj, S. Chalamalsetti, G. Ndu, M. Foltin, S. Williams, P. Faraboschi, W. Hwu,
J. Strachan, K. Roy, and D. Milijicic, ”PUMA: A Programmable Ultra-efficient Memristor-based
Accelerator for Machine Learning Inference,” The 24th International Conference on Architectural
Support for Programming Languages and Operating Systems (ASPLOS ’19), April 2019, Providence,
USA.
911. S. Dutta, A. Saha, P, Panda, W. Chakraborty, J. Gomez, A. Khanna, S. Gupta, K. Roy and S.
Datta, ”Biologically Plausible Ferroelectric Quasi-Leaky Integrate and Fire Neuron,” IEEE 2019
Symposia on VLSI Technology and Circuits, June 2019, Kyoto, Japan.
912. D. Roy, I. Chakraborty, and K. Roy, ”Scaling Deep Spiking Neural Networks with Binary Stochastic
Activations,” IEEE International Conference on Cognitive Computing, Milan, Italy, July 2019.
913. P. Panda, E. Soufleri, and K. Roy, ”Evaluating the Stability of Recurrent Neural Models during
Training with Eigenvalue Spectra Analysis,” IEEE Joint Conference on Neural Networks (IJCNN),
July 2019, Budapest, Hungary.
914. S. Sharmin, P. Panda, S. Sarwar, Chankyu Lee, W. Ponghiran and K. Roy, ”A Comprehensive
Analysis on Adversarial Robustness of Spiking Neural Networks,” IEEE Joint Conference on Neural
Networks (IJCNN), July 2019, Budapest, Hungary.
915. A. Jaiswal, A. Agrawal, I. Chakraborty, D. Roy, and K. Roy, On Robustness of Spin-Orbit-Torque
Based Stochastic Sigmoid Neurons for Spiking Neural Network,” IEEE Joint Conference on Neural
Networks (IJCNN), July 2019, Budapest, Hungary.
916. A. Jaiswal, A. Agrawal, I. Chakraborty, M. Ali, and K. Roy, ”Digital and Analog-Mixed-Signal
In-Memory Processing in CMOS SRAM,” Proceedings of the 2019 on Great Lakes Symposium on
VLSI, May 2019.
917. A. Ankit, I. El Hajj, S. Rahul Chalamalasetti, S. Agarwal, M. Marinella, M. Foltin, J. Paul Strachan,
D. Milojicic, W. Hwu, K. Roy, ”Enhancing the Precision of ReRAM-based Outer Products for
Efficient Neural Network Training,” 2019 Architectural Support for Programming Languages and
Operating Systems (ASPLOS), September 2019.
918. Deboleena Roy, Gopalakrishnan Srinivasan, Priyadarshini Panda, Richard Tomsett, Nirmit Desai,
Raghu Ganti, Kaushik Roy, ”Neural Networks at the Edge,” 2019 IEEE International Conference
on Smart Computing (SMARTCOMP), June 2019.
919. M. Parsa, J. Mitchell, C. Schuman, R. Patton, T. Potok, and K. Roy, ”Bayesian-based Hyperparameter Optimization for Spiking Neuromorphic Systems,” IEEE International Conference on Big
Data (Big Data), 2019, pp. 4472-4478.
920. N. Rathi, G. Srinivasan, P. Panda, and K. Roy, ”Enabling Deep Spiking Neural Networks with
Hybrid Conversion and Spike Timing Dependent Backpropagation,” International Conference on
Learning Representations (ICLR), April 2020.
921. G. Srinivasan, C. Lee, A. Sengupta, P. Panda, S. Sarwar, K. Roy, ”Training Deep Spiking Neural Networks for Energy-Effcient Neuromorphic Computing,” IEEE International Conference on
Acoustics, Speech, and Signal Processing (ICASSP), Invited paper, Barcelona, Spain, May 2020.
922. B. Han, G. Srinivasan, and K. Roy, ”RMP-SNN: Residual Membrane Potential Neuron for Enabling
Deeper High-Accuracy and Low-Latency Spiking Neural Network,” International Conference on
Computer Vision and Pattern Recognition (CVPR), June 2020.
79
923. Maryam Parsa, Catherine D. Schuman, Prasanna Date, Derek C. Rose, Bill Kay, J. Parker Mitchell,
Steven R. Young, Ryan Dellana, William Severa, Thomas E. Potok and Kaushik Roy, ”Hyperparameter Optimization in Binary Communication Networks for Neuromorphic Deployment,” International Joint Conference on Neural Networks (IJCNN), July 2020.
924. Krishna Reddy Kesari, Priyadarshini Panda, Gopalakrishnan Srinivasan and Kaushik Roy, ”Enabling Homeostasis using Temporal Decay Mechanisms in Spiking CNNs Trained with Unsupervised
Spike Timing Dependent Plasticity,” International Joint Conference on Neural Networks (IJCNN),
July 2020.
925. A. Aziz and K. Roy, ”Insulator-Metal Transition Material Based Artificial Neurons: A Design
Perspective,” 21st International Symposium on Quality Electronic Design (ISQED), 2020, pp. 444451.
926. K. Roy, I. Chakraborty, M. Ali, A. Ankit, and A. Agrawal, ”In-Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview,” ACM/IEEE Design Automation
Conference, July 2020.
927. I. Chakraborty, M. Ali, D. Kim, A. Ankit, and K. Roy, ”GENIEx: A Generalized Approach to
Emulating Non-Idealities in Memristive X-bars Using Neural Networks.” ACM/IEEE Design Automation Conference, July 2020.
928. M. Ali, A. Agrawal, and K. Roy, ”RAMANN: In-SRAM Differentiable Memory Computations
for Memory-Augmented Neural Networks,” IEEE/ACM International Symposium on LowPower
Electronics and Design (ISLPED), 2020.
929. S. Sanyal, A. Ankit, C. Vineyard, and K. Roy, ”Energy-Efficient Target Recognition using ReRAM
Crossbars for Enabling On-Device Intelligence,” IEEE Signal Processing Symposium (SiPS), 2020.
930. C. Lee, A. Kosta, A. Zhu, K. Chaney, K. Daniilidis, and K. Roy, ”Spike-FlowNet: Event-based
Optical Flow Estimation with Energy-Efficient Hybrid Neural Networks,” European Conference on
Computer Vision (ECCV), 2020.
931. S. Sharmin, N. Rathi, P. Panda, and K. Roy, ”Inherent Adversarial Robustness of Deep Spiking Neural Networks: Effects of Discrete Input Encoding and Non-Linear Activations,” European
Conference on Computer Vision (ECCV), 2020.
932. B. Han and K. Roy, ”Deep Spiking Neural Network: Energy Efficiency Through Time based Coding,” European Conference on Computer Vision (ECCV), 2020.
933. W. Ponghiran and K. Roy, ”Hybrid Analog-Spiking LSTM for Energy Efficient Computing on Edge
Devices,” IEEE Design and Test in Europe (DATE), Februray 2021.
934. N. Rathi, A. Agrawal, C. Lee, A. Kosta, and K. Roy, ”Exploring Spike-Based Learning for Neuromorphic Computing: Prospects and Perspectives,” IEEE Design and Test in Europe (DATE),
Februray 2021.
935. D. Roy, I. Chakraborty, T. Ibrayev, and K. Roy, ””On the Intrinsic Robustness of NVM Crossbars
against Adversarial Attacks” ACM/IEEE Design Automation Conferenence (DAC), 2021.
PATENTS
1. S. Prasad and K. Roy, “Circuit Activity Driven Multilevel Logic Optimization for Low Power
Reliable Operations,” US Patent 5487017, January 23, 1996.
2. K. Roy and S. Prasad, “Circuit Activity Driven State Assignment of FSMs Implemented in CMOS
for Low Power Reliable Operations,” US Patent 5515292, May 7, 1996.
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3. K. Roy and S. Nag, “Method of Segmenting an FPGA Channel Architecture for Maximum Routability and Performance,” US Patent 5598343, January, 1997.
4. D. Somasekhar, K. Roy, and J. Sugisawa, “Differential Current Switch Logic Gate,” US Patent
6014041, Jan. 11, 2000.
5. A. Keshavarzi, K. Roy, and V. De, “Multi Parameter Testing with Improved Sensitivity,” US patent
672695, October 1, 2002.
6. J. Kim, R. Joshi, C. Chuang, and K. Roy, “Sense-Amplifier Based Adder with Source Follower
Evaluation Tree,” US patent 6789099, 2004.
7. J. Kim, R. Joshi, C. Chuang, and K. Roy, “Sense-amp Based Adder with Source Follower Pass-Gate
Evaluation Tree, US patent 7,085,798 B2.
8. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Sense Amplifier Circuit,” US Patent 7,304,903,
Dec. 2007.
9. S. Bhunia, H. Mahmoodi, A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “Low Power Scan
Design and Delay Fault Testing Technique Using First Level Supply Gating,” US patent 7319343,
2008.
10. C. H. Kim, J. Kim, and K. Roy, “A Variation Tolerant SRAM Leakage Reduction Technique with
Improved Read Stability,” US Patent 7328413 B2, 2008.
11. S. Bhunia, N. Banerjee, H. Mahmoodi, Q. Chen, and K. Roy, “A Synthesis Approach for Active
Leakage Power Reduction Using Dynamic Supply Gating,” US Patent 7,454,738 B2, Nov. 2008.
12. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Self-Repair Technique Using Delay and Leakage
Monitoring for Nano-Scale SRAM,” US Patent Number 7,508, 697, March 24, 2009.
13. Q. Chen, S. Bhunia, H. Mahmoodi, and K. Roy, ”Apparatus and Methods for Determining Memory
Device Faults,” US Patent 7548473, June 2009.
14. J. Kulkarni and K. Roy, ”Memory Cell with Built-In Process Variation Tolerance,” US Patent
Number 7,672,152 B1, March 2, 2010.
15. J. Kulkarni and K. Roy, ”Static Random Access Memory Cell and Devices Using Same,” US Patent
Number 7,952,912, May 31, 2011.
16. K. Roy, V. Raghunathan, C. Lu, S. Park, ”Efficient Power Conversion for Ultra Low Voltage Micro
Scale Energy Transducer,” US Patent Number 0260536 A1, October 27, 2011.
17. C. Ho, C. Lu, D. Mohapatra, and K. Roy, ”Variation-Tolerant Self-Repairing Displays,” US Patent
Number US 8,994,396 B2, March31, 2015.
18. K. Roy and M. Sharad, ”Electronic Comparison systems,” US patent Number 9,489,618 B2, Nov.
8, 2016.
19. K. Roy, D. Lee, and X. Fong, ”Electronic Memory Including ROM and RAM,” US Patent Number
9,552,859 B2, Jan. 24, 2017.
20. K. Roy and M. Sharad, Electronic Comparison Systems, US patent 9,813,048, November 7, 2017.
21. A. Sengupta, S. Choday, Y. Kim, and K. Roy, ”Spin Orbit Torque based Electronic Neuron,” US
Patent 2017/0330070 A1.
22. A. Sengupta, Z. Azim, X. Fong, and K. Roy, ”Electronic Synapse Having Spin-orbit-torque Induced
Spike Timing Dependent Plasticity,” US Patent US 2017/0249550 A1.
23. S. Jain, A. Ranjan, K. Roy, and A. Raghunathan, ”System and Method for In-Memory Computing,”
US Patent Number US 10,073,733 B1, September 2018.
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24. A. Ranjan, S. Venkataramani, Z. Pajouhi, R. Venkatesan, A. Raghunathan, and K. Roy, Approximate Cache Memory, US patent 10,255,186, April 9, 2019
25. K. Roy and B. Jung, ”Vehicle battery current sensing system,” US Patent App. 16/466,281, 2020.
26. A Sengupta, Z Al Azim, XK Fong, K Roy, ”Electronic synapse having spin-orbit torque induced
spike-timing dependent plasticity,” US Patent 10,592,802, 2020.
27. AR Jaiswal, A Agrawal, K Roy, I Chakraborty, ”Multi-bit dot product engine,” US Patent Number
10,825,510.
28. AR Jaiswal, A Agrawal, K Roy, ”Memory device having in-situ in-memory stateful vector logic
operation,” US Patent Number 10,802,827.
SPECIAL ARTICLES OR REVIEWS
1. Low Power Design, An IEEE Design and Test Magazine Roundtable Discussions, IEEE Design &
Test, Winter 1995, pp. 84-90.
2. Industrial and University Test Research Collaboration, An IEEE Design and Test Magazine Roundtable
Discussions, IEEE Design & Test, March-April 2001, pp. 98-105.
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