This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2956098, IEEE
Transactions on Power Electronics
1
Coupled Inductor-Based High Voltage Gain DC-DC
Converter For Renewable Energy Applications
Afshin Mirzaee, IEEE student member, Javad Shokrollahi Moghani
Abstract—In this paper, a novel coupled inductor-based high
step-up DC-DC converter is proposed. The introduced converter
benefits from various advantages, namely ultra high voltage gain,
low voltage stress on the power switches, and continuous input
current with low ripple. Therefore, the presented converter is
suitable for renewable energy applications. By utilizing clamped
circuit, voltage spike of the active switch is clamped during
the turn-off process. Hence, a switch with low RDS−on can
be used which reduces the conduction losses as well as cost of
the converter. Furthermore, the energy of leakage inductance
is used to obtain zero voltage switching (ZVS) for the main
and auxiliary switches. Additionally, the output diode current
falling rate is controlled by leakage inductance; thus, reverserecovery problem of output diode is alleviated. The steady state
analysis and design considerations of the proposed converter
are discussed. Finally, a 250 W experimental prototype of the
presented converter is implemented to validate the converter
operation and the theoretical analysis.
Index Terms—High voltage gain, zero voltage switching (ZVS),
clamp circuit, continuous input current.
I. I NTRODUCTION
Global Warming is increasingly recognized as a serious,
worldwide public concern, mainly because of greenhouse
gases which result from the burning of fossil fuels like coal
and oil. Photovoltaics (PVs) and fuel cells (FCs) are promising
alternative energy sources to fossil fuels. However, the output
voltage of PV panels depends on the environmental specifications such as solar irradiation and ambient temperature.
Similarly, the output voltage of FCs is related to the amount
of load. According to the aforementioned shortcoming, the low
output voltage from PV and FCs must be increased to generate
required DC voltage (e.g. 400 Vdc ) for providing acceptable
ac utility voltage (e.g. 220 Vac single phase).
Another main factor, which should be considered, is the
input current ripple magnitude of the converter. Generally,
discontinuous input current may deteriorate the performance
of the maximum power point tracking (MPPT) system in
PV application. Furthermore, high ripple input current may
decrease the lifespan of FCs. Thus, a converter with continuous input current and low ripple is more preferred [1]–
[3].The conventional boost converter can be considered as a
suitable candidate for these high voltage gain applications.
Nevertheless, the voltage stress of the switch is as high as
the output voltage. Hence, a high-voltage switch with high
RDS,on should be employed, leading to high conduction
losses. Moreover, an ultra-high duty cycle is required for a
high voltage gain, which results in lower efficiency and also
serious reverse recovery problems.
Recently, many DC-DC converters with the various boosting
technique have been proposed to enhance the voltage con-
version ratio. The introduced converters include topologies,
namely switched-capacitor [4], [5], switched inductor [6],
[7], voltage lift [8], and voltage multiplier [9]–[14]. With no
doubt, these converters can achieve higher voltage conversion
ratio than the conventional boost converter. But in ultra-high
voltage gain applications, more power stages must be cascaded
in these converters; hence, more components are required.
Consequently, cost, complexity and conduction losses of the
converter are increased [15]. A promising alternative to increase the voltage gain of dc-dc converters is employing
coupled inductor. In these converters, turns ratio of the coupled inductor should be increased to a obtain wide voltage
conversion ratio [16]–[21]. However, a large value of turns
ratio increases the volume of coupled inductor core, winding
resistances and the value of leakage inductance which decrease
power density and efficiency of the converter. Moreover, stored
energy in the leakage inductance of coupled inductor results
in huge voltage spike across the semiconductors and high
power losses. Therefore, active snubber [22] and passive clamp
circuits [23] are presented to overcome these drawbacks.
Switching losses are another issue, which should be considered, in DC-DC converters. As switching losses decrease
efficiency, their reduction is of major concern in high step-up
DC-DC converters. Hence, achieving soft switching becomes
of paramount importance in these converters. To realize soft
switching, an auxiliary circuit is used in [24]. Although soft
switching is achieved, auxiliary switch and diode increase
circuit complexity. In [25], soft switching is provided by
utilizing the energy of leakage inductance. Keeping in mind
the advantages and disadvantages of the introduced topologies,
a new high voltage gain DC-DC converter is proposed. The
merits of the presented converter can be described as follows.
1) The proposed converter can achieve wide voltage conversion range in a small turns ratio. This feature means that the
voltage gain can be promoted by reducing the turn ratio of the
coupled inductor.
2) An active clamp circuit (ACC) is designed to absorb
the voltage spike across switches. Additionally, the ACC
causes switches with low on-state resistance to be adopted
to minimize conduction loss and improve efficiency.
3) The energy of leakage inductance is used to provide
Zero Voltage Switching (ZVS) for active switches. Hence,
the proposed converter can operate in a higher switching
frequency. As a result, the size of the magnetic core is reduced
and power density is increased.
4) Besides, switching loss of the presented high voltage gain
converter will be reduced without using an auxiliary circuit.
This paper is organized as follows. The topology descrip-
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Transactions on Power Electronics
2
Boost stage
Lin
Lk
Lm
NS
Saux
Cb
Dm
Do
0
Cc
t
TS
Vaux
GS
VCc  VCb
(n - 1)L m
iLm
Sm
d 2TS
DTS
0
Cm
Vin
d1TS
m
VGS
Proposed
Converter
VMC
NP
Co
RL
0
Clamp circuit
Fig. 1: The circuit prototype of the proposed high voltage gain
converter.
t
Vin - VCc
L in
Vin
L in
iLin
0
2nI o
iLk
2
D (n - 1)

t
VCb

(n - 1)Lm
t
VCc  VCb
2nI o
(n - 1)L m
2
(1 - D) (n - 1)

VCb
(n - 1)L m
t
0
tion and operation principles of the presented converter are
discussed in section II. In Section III, steady-state operation
and mathematical derivation of the introduced converter are
provided and its soft-switching performance is analyzed. In
section IV, the introduced converter is compared with some
former high step-up DC-DC converters. The dynamic analysis
of the proposed converter is discussed in section V. Section
VI then describes experimental results. Eventually, a brief
conclusion will be drawn in the section VII.
i Lk,max
i Sm,max
0
The circuit structure of the introduced high voltage gain DCDC converter is illustrated in Fig. 1. The proposed converter
consists of the input inductor Lin , primary winding of the
coupled inductance (Np ), two active switches including main
switch Sm and auxiliary switch Saux , clamp capacitor Cc ,
blocking capacitor Cb , capacitor Cm , diode Dm , output diode
Do , and output capacitor Co . The coupled inductor comprises
of an ideal transformer with a turns ratio of n ( n = Ns /Np ),
a magnetizing inductance Lm and the leakage inductance Lk
which is referred to the primary side of the coupled inductance.
According to Fig. 1, the diode Dm and the capacitor Cm are
the circuit elements of the Voltage Multiplier Cell (VMC),
which increases the voltage conversion ratio of the proposed
converter. The capacitor Cc and switch Saux are employed as
the clamp circuit. Hence, the energy of leakage inductance is
recycled to Cc , and the voltage stress of the main and auxiliary
switch is clamped to the voltage of capacitor Cc . In addition,
the recovered energy of the leakage inductance, which is stored
in capacitor Cc , can be transferred to the output. Thus, the
voltage gain of the proposed converter can be extended. In
order to simplify the steady state analysis of the proposed
converter, the ensuing assumptions are considered.
1-All components are ideal but the leakage inductance of the
coupled inductor is taken into account.
2-All capacitors are large enough; thus, their voltages are
ripple free.
3-The inductors Lin and Lm are considered large enough;
hence, their current ripple is negligible.
The key steady-state waveforms of the proposed high voltage
t
VCc  VCb
V

 in
2
D (n - 1) (n - 1)L m L in
2nI o
iSaux
i Saux,max
t
0
V - VCc

 in
2
(1 - D) (n - 1) (n - 1)L m
L in
2nI o
iDm
II. OPERATIONAL PRINCIPLE OF THE PROPOSED
CONVERTER
-i Lk,min
iSm
2nI o
D
2
VCb
i Dm,max
iDo0
t
2nI o
(1 - D)
2
i Do,max
0
t1
t0
Mode 1
t2
Mode 2
t3
Mode 3
t4
Mode 4
t5
Mode 5
t
t6
Mode 6
Fig. 2: Theoretical waveforms of the proposed converter under
CCM operation.
gain DC-DC converter under Continuous Conduction Mode
(CCM) for one switching cycle are illustrated in Fig. 2. Also,
the current flow path and equivalent circuit corresponding to
each mode is shown in Fig. 3. The operating modes of the
introduced converter are presented as follows.
Mode 1 [t0 -t1 ]: before t = t0 , the switch Saux is on and
the current iLk is negative. At t = t0 , the auxiliary switch is
turned off. The anti-parallel diode of the switch Sm turns on
due to the negative leakage inductance current.
Mode 2 [t1 -t2 ]: At t = t1 , the switch Sm is turned on and
ZVS is achieved. In this interval, the diode Do is forward
biased and capacitor Cm transfers its energy to the output.
Due to the positive voltage on leakage inductance, the current
iLk is linearly increased. The leakage inductance current can
be expressed as follows:
iLk (t) =
1
Lk
Z
t
t1
VLk2 dt + iLk,t1
(1)
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Transactions on Power Electronics
3
NP
Lin
+
Saux
+
Dm
-
Do
Vin
Vin
+
+
Co
Cc
-
-
Lin
NP
Lm
NS
+
Lm
Dm
Cc
-
Lk
Do
Co
+
-
Cb
+
Sm
RL
-
Lm
Lk
Cc
Co
NS
Cm
-
RL
+
-
Cc
Do
Co
Cb
Vin
+
-
RL
(e)
+
Sm
Cm
-
Dm
Dm
+
Saux
+
+
Sm
+
NP
Lm
NS
Cb
Do
Dm
(d)
Lin
Vin
RL
NS
Vin
NP
Saux
-
Cm
Saux
(c)
Lin
+
NP
Cm
+
Sm
Lk
-
Cb
Vin
+
Saux
Co
(b)
-
Lk
Do
Cc
-
(a)
Lin
Dm
+
Sm
RL
Cm
-
Sm
Cb
-
Cb
NS
+
Saux
Lm
Cm
-
NS
NP
+
Lm
Lk
-
Lk
+
Lin
-
Cc
Do
Co
+
-
RL
(f)
Fig. 3: Equivalent circuit and current flow path in each operating mode. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e)
Mode 5. (f) Mode 6.
Where
VCc − VCb + (n − 1)(Vo − VCm )
(2)
n
The clamp capacitor Cc is charged by the magnetizing energy.
Hence, the magnetizing inductance current is decreased. The
energy of input source is absorbed by the input inductance.
Therefore, the current iLin is increased and can be calculated
as follows:
Z t
1
Vin dt + iLin,min
(3)
iLin (t) =
Lin t1
VLk2 =
By using Kirchhoff’s current law (KCL), the current of the
main switch iSm can be calculated as follows.
iSm = iLin − iLk
(4)
This mode is finished when the output diode Do is reversebiased and the diode Dm turns on.
Mode 3 [t2 -t3 ]:In this mode, the switch Sm is on. The input
source energy is released to the input inductance the same
as the former mode. The leakage inductance current increases
linearly. The voltage across leakage inductance can be derived
as follows.
iL (t3 ) − iLk (t2 )
VLk3 = Lk k
DTs
(5)
niDm − iLm
iLk =
n−1
In this mode, energy of the capacitor Cc is transferred to the
capacitors Cb , Cm and the primary side of the coupled inductor. Thus, the current of magnetizing inductance is increased.
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Transactions on Power Electronics
4
The output diode Do is reverse-biased and the load energy is
provided by the output capacitor Co .
According to Kirchhoff’s Voltage Law (KVL), the following
relations can be obtained.
VCc − VCb − VLk3
(6)
VLm =
n−1
nVCc − VCb − nVLk3
VCm =
(7)
n−1
This interval ends when the main switch is turned off at
t = t3 .
Mode 4 [t3 -t4 ]: At the beginning of this mode, the switch
Sm is turned off. The currents iLk and iLin flow through antiparallel diode of the switch Saux . Then the gate signal of
switch Saux is applied and Saux is turned on with ZVS. The
capacitor Cc is charged by the input voltage Vin and input
inductor Lin . The input inductance current can be calculated
as (8).
Z t
1
(Vin − VCc )dt + iLin,max
(8)
iLin (t) =
Lin t3
Due to negative voltage across the leakage inductance, its
current is diminished. The leakage inductor current can be
achieved as follows.
Z t
1
iLk (t) =
VL dt + iLk,t3
(9)
Lk t3 k4
Where
VCb − (1 + n)VCm
(10)
n
During this mode the load is supplied by the output capacitor Co .
Mode 5 [t4 -t5 ]: At the beginning of this mode, the switch
Sm is turned off. The currents iLk and iLin flow through antiparallel diode of the switch Saux . Then the gate signal of
switch Saux is applied and Saux is turned on with ZVS. The
input voltage Vin and input inductor Lin are still released their
energy to the clamp capacitor. The leakage inductance current
is decreased linearly and can be achieved as (9).
As the previous mode, the load is supplied by the output
capacitor Co . This mode ends when the diode Dm is reversebiased and the output diode Do turns on.
Mode 6 [t5 -t6 ]: When this mode starts at t = t5 , the
output diode turns on and the energy of the capacitor Cm is
transferred to the output through the diode Do . The capacitor
Cc is still charged by input inductance Lin and input source
Vin . The leakage inductance current is linearly diminished.
The voltage across the leakage inductor can be calculated as
follows.
iL (t6 ) − iLk (t5 )
VLk6 = Lk k
(1 − D)Ts
(11)
niDo − iLm
iLk =
n−1
The magnetizing inductance energy is transferred to the clamp
capacitor and its current is decreased. By applying KVL, the
following equations can be written.
VLk4 =
VLm =
−(VCb + VLk6 )
n−1
(12)
VCb + nVLk6
(13)
n−1
is turned off and this mode ends.
Vo = VCm + VCc +
At t = t5 , the switch Saux
III. S TEADY S TATE ANALYSIS OF THE PROPOSED
CONVERTER
To simplify the analysis, the modes 1, 2, 4, and 5 are
not considered since their time duration with respect to the
switching period is negligible.
A. Voltage gain
In the time interval of the third mode, the input inductance
is charged by input source. Also, in mode 6, the voltage
across the input inductance is equal to Vin − VC1 . By applying
the volt-second balance principle across the inductor Lin , the
relation (14) can be obtained.
Vin D + (Vin − VCc )(1 − D) = 0
(14)
According to (14), the voltage VCc can be calculated as
follows.
Vin
(15)
1−D
By using ampere-second balance principle, the average current
of the capacitors Cm and Co is zero. Therefore, the average
current of diodes Dm and Do is equal to the output current.
According to Fig. 3, the following equations can be derived.
VCc =
Dimax
2Io
Dm
= Io ⇒ imax
(16)
Dm =
2
D
2Io
(17)
< iDo >= Io ⇒ imax
Do =
1−D
Also, the average current of the main switch is equal to Iin −
Io . Thus,
< iDm >= Io ⇒
< iSm >= Iin − Io ⇒ Iin − Io =
DTs (imax
Lk + ILin )
(18)
2Ts
The maximum leakage inductance current is obtained as
follows.
(2 − D)ILin − 2Io
(19)
imax
Lk =
D
The average current of the auxiliary switch is equal to −Io .
< iSaux >= −Io
min
(D − 1)(imax
Lk + iLk + ILin )Ts
−Io =
2Ts
(20)
Therefore, the minimum leakage inductance current is given
as (21).
(2 − 2D)ILin − 2Io
imin
(21)
Lk =
D(1 − D)
Based on the assumed conditions in section II, the input
and magnetizing inductance current are ripple free. According
to (5) and (11), the equations (22) and (23) are obtained as
follows.
n 2Io
(22)
iLk (t3 ) − iLk (t2 ) =
n−1 D
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Transactions on Power Electronics
5
n
2Io
(23)
n−11−D
Using equations (5), (11), (22), and (23), the voltage VLk3 and
VLk6 are given as (24) and (25), respectively.
2nVo
λ
VLk3 =
(24)
(n − 1)D2
2nVo
VLk6 = −
λ
(n − 1)(1 − D)2
(25)
fs Lk
λ=
RL
where fs and RL are the switching frequency and load
resistance, sequentially.
By applying the voltage-second balance principle across the
magnetizing inductance, the voltage across the capacitor Cb is
obtained as follows.
1.00
iLk (t6 ) − iLk (t5 ) = −
h
i
Vo
2n − 1
=
×Q
(28)
Vin
(n − 1)(1 − D)
where Q is the normalized voltage gain of the proposed
converter and defined as follows.
D2 (1 − D)2 (n − 1)2
Q= 2
(29)
2n λ(1 − 2D + 2D2 ) + D2 (1 − D)2 (n − 1)2
According to (28) and (29), the voltage gain of the proposed
converter relies on the value of leakage inductance, load
resistance and switching frequency. Fig. 4a illustrates the effect
of λ on the voltage gain of the introduced converter. The turns
ratio of the coupled inductance is equal to 1.2.
According to Fig. 4a, it can be inferred that the voltage gain
does not change noticeably under different values of λ. For
example, for Lk = 2µH, RL = 600Ω, fs = 50kHz, n = 1.2
and D = 0.5, the value of Q is approximately 0.97. Thus,
the real voltage gain is about 97% of the theoretical voltage
gain. The ideal voltage conversion ratio at λ = 0 (Lk = 0) is
expressed as follows.
Vo
2n − 1
M=
=
(30)
Vin
(n − 1)(1 − D)
Fig. 4b illustrates the theoretical voltage gain of the proposed converter versus duty cycle for different turns ratio
of the coupled inductor. It can obviously be observed that
the voltage transfer characteristic of the proposed converter
increases as the turns ratio decreases. Hence, smaller turns
ratio can be used in high output voltage applications. Also,
this feature may lead to lower winding turns which results in
lower power losses and smaller magnetic core volume [26].
Thus, Efficiency and power density of the introduced high
voltage gain converter can be increased.
G=
D=0.55
D=0.50
Q
0.90
0.85
0.80
0.75
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
´10
-3
(a)
50
n=1.2
n=1.6
40
Voltage gain
D
Vin − DVLk3 − VLk6 (1 − D)
(26)
1−D
The voltage across capacitor Cm can be achieved by substituting the equations (15), (24) and (26) into (7).
n−D
n−D
1−D
Vin −
VL +
VL (27)
VCm =
(n − 1)(1 − D)
n − 1 k3 n − 1 k6
By using the relations (15), (26) and (27), the voltage gain
of the converter can be calculated as (28).
VCb =
D=0.60
0.95
n=2
n=2.4
30
n=2.8
n=3.2
20
10
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Duty cycle
(b)
Fig. 4: Proposed converter characteristics (a) The effect of λ
on the voltage conversion ratio of the presented converter. (b)
Voltage gain of the proposed converter versus duty cycle for
different turns ratio.
B. Effect of leakage inductance on duty cycle and power
rating
In addition to reducing voltage gain, leakage inductance of
the coupled inductor decreases duty cycle of the main switch
and limits output power rating. These effects are discussed in
detail as follows.
1) Duty cycle loss: According to Figs. 2, the leakage
inductance causes duty cycle loss. In the other words, a time
is required to magnetize the leakage inductance. Thus, the
effective duty ratio is reduced by the time needed to energize
the leakage inductance [27]. Therefore,
Def f = D − d1
(31)
Additionally, demagnetization time of the primary inductance
is extended by the time which is required to de-energize Lk .
Hence,
0
Def f = 1 − D + d2
(32)
According to Fig. 2, the value of d1 can be achieved as below.
imin
VLk2
Lk − Iin
=
d1 Ts
Lk
(33)
Using the equations (2), (21), (26), (27) and (33), yields:
d1 =
Dλ(2n − 1)(D + 2n − 2nD)
(1 − D)[D2 (n − 1)2 + 4λn2 − 2λn]
(34)
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Transactions on Power Electronics
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Also, as is shown in Fig. 2, the value of d2 is derived by (35).
imax
Lk
− Iin
VLk5
=
d2 Ts
Lk
(35)
C. Voltage and current stress on the switches and diodes
According to Figs. 2 and 3, the voltage stress on the
switches can be calculated as (45).
Using the equations (10), (19), (26), (27) and (35) results in:
2λn2
d2 =
A+B
VSm = VSaux =
(36)
Where
−2λn3 (1 − D) + n2 (6λD − 2λ)
D(n − 1)(1 − D)
(37)
D(n − 1)(n2 − 2nD + n)
B=
2n − 1
2) Power rating limitation: Leakage inductance Lk reduces
current of the primary and secondary windings. According
to (6), when the main switch is turned on, the magnetizing
inductance current is given as follows.
A=
k 6=0
iL
Lm (t) =
VCc − VCb − VLk3
t + imin
Lm
2Lm (n − 1)DTs
0 < t < DTs
(38)
where
Vin (1 − α)
t + imin
Lm
Lm (n − 1)DTs
0 < t < DTs
2n(2n − 1)λ(1 − 2D + 2D2 )λ
α=
D2 (1 − D)2 (n − 1)2
=
(1 − α)2 + (1 − α)DTs
<1
1 + DTs
VDm = VDo =
n
n
Vin =
Vo
(n − 1)(1 − D)
2n − 1
(46)
The average current of the input inductor is equal to Iin .
Also, the ripple current of the input inductor is given as
follows.
Vin D
(47)
∆iLin =
Lin fs
(40)
From (40) and (41), it can be seen that the leakage inductance
decreases magnetizing inductance current. The stored energy
in inductance L at t = τ is calculated as follows.
1
2
(42)
WLt=τ = L(it=τ
L )
2
The difference between the magnetizing inductance energy at
s
t = DTs (WLt=DT
) and t = 0 (WLt=0
) is stored in Lm . Hence,
m
m
∆WLLmk 6=0
∆WLLmk =0
From (45), it can be seen that by decreasing turn ratio n, the
voltage stress of the main and auxiliary switch is reduced and
switches with less on-state resistance RDS−on can be used
which improves efficiency. The voltage stress on the diodes
Dm and Do can be obtained as follows.
(39)
By ignoring Lk (λ = 0), magnetizing inductance current can
be calculated as follows.
Vin
k =0
iL
t + imin
Lm
Lm (t) =
Lm (n − 1)DTs
(41)
0 < t < DTs
s
∆WLm (Sm : ON ) = WLt=DT
− WLt=0
m
m
1
t=DTs 2
2
∆WLm (Sm : ON ) = Lm [(iLm ) − (imin
Lm ) ]
2
Thus,
(45)
Hence, the minimum and maximum currents of the input
inductor are derived by (48) and (49), respectively.
According to (15) and (24)-(26):
k 6=0
iL
Lm (t) =
Vin
n−1
=
Vo
(1 − D)
2n − 1
(43)
imin
Lin = Iin −
∆iLin
2
(48)
imax
Lin = Iin +
∆iLin
2
(49)
According to KCL, the current of leakage and magnetizing
inductance can be achieved as follows.
iLk = iCb + iCm
iLm = (1 − n)iCb + iCm
(50)
According to ampere-second balance principle, the average
value of leakage and magnetizing inductance current are equal
to zero. Also, the ripple current of the magnetizing inductance
can be calculated as follows.
∆iLm =
DVin
(n − 1)Lm fs
(51)
Thus, the minimum and maximum current of the magnetizing
inductor can be expressed by (52).
max
imin
Lm = −iLm = −
DVin
2(n − 1)Lm fs
(52)
From (19), (21), (48) and (49), the maximum value of the
max
switches current imax
Sm and iSaux is given as follows.
(44)
According to (44), leakage inductance decreases the stored
energy in magnetizing inductance Lm . When the main switch
is turned off, the stored energy is transferred to the output.
Since the stored energy is reduced, the transferred energy will
be restricted. Therefore, the power rating will be limited by
leakage inductance [27].
max
max
imax
Sm = iLin + iLk
2(Iin − Io )
Vin D
imax
+
Sm =
D
2Lin fs
imax
Saux
min
min
imax
Saux = iLin + iLk
(D2 − 3D + 2)Iin − 2Io
Vin D
=
+
D(1 − D)
2Lin fs
(53)
(54)
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In order to limit input current ripple, the input inductor can
be calculated as:
DVin
Lin =
(55)
∆ILin fs
Where ∆ILin is the allowable ripple current on the input
inductance Lin .
The proposed converter operates in CCM if the magnetizing
inductor of the coupled inductor Lm be in CCM. Since the
secondary side of the coupled inductor is in series with the
capacitor Cb , according to ampere-second balance principle,
the average value of inductor currents iLk and iLm are zero. In
boundary conduction mode (BCM), when the auxiliary switch
is turned off, the current of diode Dm and capacitor Cm
reaches zero. Therefore,
s
s
it=T
= it=T
Lk
Ls
(56)
where iLs is the secondary side current of the coupled inductor
and given as follows.
iLs =
iLk − iLm
n
(57)
According to Figs. 2, the value of leakage inductance
current at t = Ts is equal to imin
Lk . Hence, in order to operate
in CCM, the following condition should be satisfied [28].
s
it=T
Lm ≥
∆iLm
2
(58)
By substituting (21), (51) and (57) in (58), the value of Lm
is given as:
(1 − D)2 D2 RL
(59)
Lm ≥
4n(2n − 1)fs
Depending on the converter power P, capacitor voltage VC ,
voltage ripple ∆VC , and switching frequency fs , the value of
each capacitor is designed [21]. Therefore, the value of the
switched capacitor Cm and output capacitor Co is calculated
as follows.
Io D
Co =
(60)
∆Vo fs
Cm =
Vo (1 − D)
∆VCm fs
(1 − Dmin )2
π 2 Lk fs2
nIo
2(n − 1)Dfs ∆VCc
Coss=600pF
Fig. 5: ZVS condition of main switch with respect to output
power, duty cycle and input voltage for different values of
Coss .
E. Soft-Switching Condition
According to interval 4, when the main switch is turned
off, the sum of iin and iLk flows through anti-parallel diode
of the auxiliary switch, parasitic capacitor of Sm and Saux is
charged and discharged, respectively. The ZVS condition for
Saux is given by (64).
max
imax
Lin + iLk > 0
(64)
max
Since the current values imax
Lin and iLk are positive, the ZVS
condition for Saux is always achieved. In order to realize the
ZVS condition for the main switch, the following constraint
should be satisfied.
1
1
Leq i2Saux > Coss VS2
2
2
m
a
(65)
Coss = Coss
+ Coss
iSaux = iLk − Iin
a
m
are the parasitic capacitor of Sm and Saux ,
and Coss
Coss
respectively. VS is the voltage stress across the switches and
is achieved by (45), Leq is the equivalent inductance which is
connected to the switches and it is approximately equal to Lk ,
and iSaux is the current of the auxiliary switch when it turned
a
m
off. This current charges Coss
, discharges Coss
and then flows
through anti-parallel diode of the main switch. Fig. 7 exhibits
ZVS region of the main switch with respect to output power,
duty cycle and input voltage for various values of Coss .
IV. C OMPARISON WITH OTHER TOPOLOGIES
(62)
By applying the ampere-second balance principle, the values
of the capacitor Cc is ascertained as (63)).
Cc =
Coss=3nF
Coss=1.4nF
(61)
The value of capacitor Cb is designed such that half of the
resonance period formed between leakage inductance Lk and
the blocking capacitor Cb is greater than the turn off period
of the switch Sm to avoid resonant ringing [29]. Therefore
Cb =
iLk[A]
D. Design of Inductors and Capacitors
(63)
The major parameters of the proposed converter and other
recently developed DC-DC converters are compared and presented in Table I. Also, related voltage gain against duty cycle
for the converters in [30]–[36] and the proposed converter are
illustrated in Fig. 6.
According to Table I and Fig. 6, the voltage gain of the
proposed converter is higher than the proposed converter in
[30]–[34]. This feature makes the proposed high voltage gain
converter a more suitable choice for high step-up applications. However, voltage gain of the converters in [35]–[37]
is more than the proposed converter at the expense of higher
component count. Also, in [35] and [36], two high voltage
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TABLE I: PERFORMANCE COMPARISON BETWEEN THE PROPOSED CONVERTER AND OTHER HIGH VOLTAGE GAIN CONVERTERS
Reference
Number of components
switch
diode
capacitor
core
Converter in [30]
2
3
4
1
Converter in [31]
1
4
5
2
Converter in [32]
1
4
2
2
Converter in [33]
2
8
5
2
Converter in [34]
2
2
3
1
Converter in [35]
1
5
2
3
Converter in [36]
1
5
3
3
Converter in [37]
1
5
5
1
Proposed Converter
2
2
4
2
Voltage gain in CCM
Voltage stress of switch (/Vo)
2n + 2 − nD
1−D
n+2+D
1−D
1 + n + nD
1−D
2 + nD
1−D
2+n
1−D
n+2
(1 − D)2
1 + nD
(1 − D)2
2n + 3
1−D
2n − 1
(n − 1)(1 − D)
1
2n + 2 − nD
1
2+n+D
1
1 + n + nD
1
2 + nD
1
2+n
1
n+2
1
1 + nD
1
2n + 3
n−1
2n − 1
40
Proposed converter
35
Converter in [30]
Converter in [31]
Voltage gain
30
Converter in [32]
Converter in [33]
25
Converter in [34]
Converter in [35]
20
Converter in [36]
15
10
5
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Duty cycle
Input current ripple
High
Low
High
High)
High
Low
Low
High
Low
of the state space model of the proposed converter, only mode
3 (main switch is ON) and mode 6 (main switch is OFF)
are considered [38]. The proposed converter is consisted of
eight independent state variables iLin , iLk , iLm , iLs , VCc ,
VCb , VCm and VCo . iLin is input inductance current, iLk
is the leakage inductance current, iLm is the magnetizing
inductance current and iLs is the secondary side current of the
coupled inductor. VCc is the clamp capacitor voltage, VCb is
the blocking capacitor voltage, VCm is the voltage of capacitor
Cm and VCo is the output capacitor voltage. According to
Fig. 3c, the state space equations when the main switch is ON
(dTs ) is written as follows.
Fig. 6: Voltage gain against duty ratio of the proposed converter and the converters in [30]–[36].
gain converters are connected in cascaded form. Hence, the
conversion efficiency is decreased. For instance, the efficiency
of the converter in [35] at full-load is 91.1%. In term of input
current ripple, the converters in [30], [32]–[34] and [37] suffer
high input current ripple. On the other hand, the introduced
converter employs an input inductance to reduce input current
ripple. Even though an extra inductor is used, the drawn
current from the input source will be a continuous current
with low ripple. Another advantage of the proposed converter
is using of dc-blocking capacitor. This capacitor is in series
with the coupled inductor and not only improves voltage gain
but also reduces the likelihood of core saturation.
V. DYNAMIC A NALYSIS OF THE PROPOSED CONVERTER
A. small-signal model of proposed converter
Since the switch Sm is the main control switch of the
proposed converter, the small-signal model can be derived by
the analysis on main switch Sm . In order to simplify derivation
Vin
diLin
=
dt
Lin
VCb
VC
VC (n − 1)
diLk
=
− c + m
dt
nLk
Lk
nLk
diLm
VCm − VCb
=
dt
nLm
VCm − VCb
diLs
=
dt
Ls
dVCc
iL
=− k
dt
Cc
dVCb
iLk − iLm
=
dt
nCb
dVCm
iLk − iLs
=
dt
Cm
dVCo
VCo
=−
dt
RL Co
(66)
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According to Fig. 3f, the state space equations when the main
switch in OFF (1 − d)Ts is obtained as (67).
perturbed. Then they are replaced by the sum of dc and small
ac terms as follows.
diLin
Vin − VCc
=
dt
Lin
diLk
(VCm + VCc − VCo )(1 − k)
=
dt
Lk
diLm
(VCm + VCc − VCo )k
=
dt
Lm
diLs
VCm + VCc − VCb − VCo
=
dt
Ls
iLk − iLs + iLin
dVCc
=
dt
Cc
dVCb
iLs
=
dt
Cb
dVCm
iLk (1 − n) − iLm
=
dt
nCm
dVCo
iLs − iLk
VCo
=
−
dt
Co
RL Co
īLin = ILin + ĩLin , īLk = ILk + ĩLk
īLm = ILm + ĩLm , īLs = ILs + ĩLs
V̄Cc = VCc + ṼCc , V̄Cb = VCb + ṼCb
V̄Cm = VCm + ṼCm , V̄Co = VCo + ṼCo
˜ V̄in = Vin + Ṽin ,
d = D + d,
Finally, the small signal model is derived.
(67)
where k is defined as follows.
k=
Lm
Lm + Lk
(71)
(68)
It is worth noting that the symbol x̄ is used to represent the
average value of a time-varying variable x and is defined as
(69).
Z
1 T
x̄ =
x(t)dt
(69)
T 0
The averaged equations are calculated as follows.
Vin
dīLin
VC (1 − d)
=
− c
dt
Lin
Lin
VCm (d(nk − 1) + n(1 − k))
dīLk
=
dt
nLk
VCc (2d − 1 + k(1 − d))
−
Lk
dVCb
VCo (d − 1)(k − 1)
+
−
nLk
Lk
VCo k(1 − d) VCc k(1 − d)
dīLm
=−
+
dt
Lm
Lm
(kd − kdn + kn)VCm
dVCb k
+
−
nLm
nLm
dīLs
VCm − VCb
VCc (1 − d) VCo (1 − d)
=
+
−
dt
Ls
Ls
Ls
dV̄Cc
iLs (d − 1) iLk (2d − 1) iLin (1 − d)
=
−
+
dt
Cc
Cc
Cc
dV̄Cb
diLk
iLs (d − 1) diLm
=
−
−
dt
nCb
Cb
nCb
dV̄Cm
d
(n − 1)(d − 1)
diLs
iL (d − 1)
= iLk (
+
)−
+ m
dt
Cm
nCm
Cm
nCm
dV̄Co
(iLk − iLs )(d − 1)
VCo
=
−
dt
Co
RL C o
(70)
In order to derive small signal modeling, the state variables,
input voltage and duty cycle of the proposed converter are
Ṽin
ṼC (1 − D) VCc d˜
dĩLin
=
− c
+
dt
Lin
Lin
Lin
˜
(VCm d + DṼCm )(nk − 1) + n(1 − k)ṼCm
dĩLk
=
dt
nLk
˜
˜
VC (2d − k d) + (2D − 1 − kD + k)ṼCc
− c
Lk
˜
(VCb d˜ + DṼCb ) (k − 1)(ṼCo (D − 1) + VCo d)
+
−
nLk
Lk
ṼCo k(1 − D) − kVCo d˜
dĩLm
=−
+
dt
Lm
k ṼCc (1 − D) − kVCc d˜ (kn + kD − knD)ṼCm
+
Lm
nLm
˜
˜ C )
k(1 − n)VCm d k(ṼCb D + dV
b
+
−
nLm
nLm
ṼCm − ṼCb
dĩLs
ṼC (1 − D) VCc d˜
=
+ c
+
dt
Ls
Ls
Ls
˜
ṼC (1 − D) VCo d
− o
+
Ls
Ls
ĩLs (D − 1) + ILs d˜ iLk (2D − 1) + 2ILk d˜
dṼCc
=
−
dt
Cc
Cc
iLin (1 − D) + ILin d˜
+
Cc
dṼCb
ĩLk D + ILk d˜ ĩLs (D − 1) + ILs d˜ ĩLm D + ILm d˜
=
−
−
dt
nCb
Cb
nCb
˜
˜
dṼCm
ĩL D + ILk d (n − 1)(ĩLk (D − 1) + ILk d)
= k
+
dt
Cm
nCm
˜
ĩL D + ILs d ĩLm (D − 1) + ILm d˜
− s
+
Cm
nCm
˜
ĩL (D − 1) + ILk d ĩLs (D − 1) + ILs d˜
dṼCo
= k
−
dt
Co
Co
ṼCo
+
RL C o
(72)
Using Laplace Transform (LT) and experimental parameters,
the control-to-output transfer function is derived as:
ṼCo
100s7 + 5.736e4 s6 − 1.805e9 s5 − 1.452e12 s4
(s) = 8
s + 3717s7 + 4.59e6 s6 + 3.39e9 s5 + 1.91e12 s4
d˜
1.311e15 s3 + 1.315e18 s2 + 5.721e19 s + 5.695e20
+
6.238e14 s3 + 8.251e16 s2 + 3.746e18 s + 5.397e19
(73)
According to transfer function, it is clear that the proposed
converter is an eight-order system which has right-half-plane
(RHP) zeros.
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TABLE II: PARAMETERS AND SPECIFICATIONS OF THE IMPLEMENTED PROTOTYPE
Symbol
Po
Vin , Vo
fs
Lin
Lm
Lk
Ns /Np
Cc , C b
Cm , Co
Sm and Saux
Dm and Do
Parameter
Output power
Input, Output voltage
Switching frequency
Inductor
Magnetizing inductor
Leakage inductance
Number of turns
Clamp, Blocking Capacitor
Switched, Output Capacitor
Power Switches
Diodes
Value
250 W
40V , 400V
50 kHz
400 µH
200 µH
2.8 µH
17/12
220µF ,68µF
47µF ,100µF
IXTP130N15X4
MUR860
Vo (200V/div)
VCc (100V/div)
Vin (50V/div)
iin (4A/div)
B. Controller design
In order to design the controller, the following transient
specifications should be considered.
• Steady state output voltage regulation < 1% of the rated
steady state value.
• Output voltage should remain stable for sudden load
change.
• Output voltage overshoot must be less than 10% of the
set point value.
According to the above specifications, Proportional-Integral
(PI) controller is used.
(a)
VCb (50 V/div)
VCm (100 V/div)
iLk (5A/div)
VI. E XPERIMENTAL R ESULTS
In order to validate the performance of the introduced high
step-up DC-DC converter, a 250W laboratory prototype has
been implemented which is shown in Fig. 7. The specifications
of the proposed converter are given in Table II. The input
and output voltages of the converter are 40V and 400V,
respectively. The converter operates in CCM condition with
a switching frequency of 50kHz. The experimental results
are illustrated in Figs. 8-11. It is worth mentioning that the
measured and calculated parameters of the proposed converter
are slightly different. This is because of the simplifying
assumptions which are adopted in the theoretical analysis of
the converter.
Isolated Supply
OScilloscope
STM32F407
DC Power Supply
Probe
Proposed Converter
Resistive Load
Current Probe
Fig. 7: The experimental prototype of the introduced converter.
(b)
Fig. 8: Experimental results of the proposed converter at power
of 250W (full-load). (a) Output voltage Vo , input voltage Vin ,
clamp capacitor voltage VCc and input inductance current iLin .
(b) Blocking capacitor voltage VCb , voltage of capacitor Cm ,
VCm and leakage inductance current iLk .
The output voltage Vo , input voltage Vin , input current iin ,
and clamp capacitor voltage VCc are shown in Fig. 8a. The
average value of input current in the experimental test (Iin
' 6.5A) is greater than the theoretical average value (Iin =
6.25A) because the components are not ideal. In addition, the
introduced converter has a low ripple continuous current at
its input stage which makes it proper for renewable energy
applications. Fig. 8b demonstrates the voltage of capacitors
Cb , Cm , and leakage inductance current.
The voltage stress and current of diodes Dm and Do are
illustrated in Fig. 9a. According to (46), the voltage across the
diodes Dm and Do is about 300V which is in accordance with
the experimental results. The voltage and current waveforms
of the main switch Sm is shown in Fig. 9b. From this figure,
it can be observed that the drain to source voltage of the main
switch has decreased to zero before it is turned on. Hence, the
ZVS operation is achieved. Fig. 9c exhibits the experimental
voltage and current of the auxiliary switch. Anti-parallel diode
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Vo (100 V/div)
Settling time
VDo (200 V/div)
iDo (4A/div)
VDm(200 V/div)
io (1A/div)
iDm (4A/div)
(a)
(a)
VSm
(50V/div)
Vin (20V/div)
iSm (8A/div)
Settling time
Vo (100 V/div)
ZVS Turn-on
(b)
Fig. 10: Closed loop experimental results. (a) Load change
from no load to full load and then from full load to no load.
(b) Input voltage change from 40V to 30V and back to 40V.
(b)
VSaux (50V/div)
iSaux(8A/div)
ZVS Turn-on
(c)
Fig. 9: Experimental waveforms at full-load for, (a) Voltage
and current of output diode Do ( iDo , VDo ) and diode Dm (
iDm , VDm ) (b) Main switch voltage and current ( VSm , iSm ).
(c) Auxiliary switch voltage and current (VSaux and iSaux ).
of the switch Saux is forward-biased then the auxiliary switch
is turned on. Therefore, Saux is switched on under ZVS
condition. It is evident that the voltage stress across Sm and
Saux are about 100V which is far lower than the output voltage
of 400V. Additionally, thank to the clamp capacitor, there is a
small voltage spike on the main and auxiliary switch.
The dynamic response of output voltage for step change
in load from no load to full load condition and vice versa is
illustrated in Fig. 10a. It is clear that the proposed converter is
able to regulate the output voltage during a large load variation
from full load to no load and back to full load which shows the
robustness of the closed loop system. The dynamic response
of output voltage, when the input voltage is changed from 40
V to 30 V and then from 30V to 40V, is shown in Fig. 10b.
It can be seen that when the supply voltage is reduced, the
output voltage remains stable and there is neither oscillation
nor overshoot. The settling time for the output voltage is
about 130ms. The measured efficiency curve of the proposed
converter against output power is depicted in Fig. 11a. As
shown in this figure, the full-load efficiency is about 96.5%.
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for power switches. Moreover, since the current falling rate of
the output diode is reduced by leakage inductance, the reverse
recovery problem of the output diode is alleviated. In order
to verify the theoretical analysis, the introduced converter is
implemented experimentally under the output power of 250W .
97
V
in
=40 V, V
out
=400 V
Efficiency [%]
96
95
R EFERENCES
94
93
92
50
100
150
200
250
300
Output power [W]
(a)
Copper losses
Switches losses
21.6%
32.7%
12.1%
17%
16.6%
Core losses
Diodes losses
Capacitors losses
(b)
Fig. 11: Efficiency and loss analysis of the proposed converter.
(a) Measured efficiency versus output power (b) Power loss
breakdown at full load.
Fig. 11b illustrates loss breakdown of the proposed converter at full load . It can be seen that about 40% of the power
losses in the proposed converter are conduction losses which
occur in the inductors windings and the capacitors equivalent
series resistor (ESR). Hence, using low ESR capacitors and
inductors with low winding resistance will enhance efficiency
of the proposed high step-up converter.
VII. CONCLUSIONS
A novel high voltage gain DC-DC converter is introduced
in this paper. The input current of the proposed converter
is continuous with a low ripple which makes it suitable for
renewable energy applications. The voltage gain, voltage stress
on the switches, and the number of the elements are compared
between the proposed converter and other recently developed
high step-up DC-DC converters. According to the presented
results, the voltage gain of the proposed converter is higher
than the other converters. In addition, the voltage stress on the
active switch is decreased and the voltage spike is clamped.
Hence, the conduction losses and cost are diminished by
using lower voltage switch with lower RDS−on . Energy of the
leakage inductance is used to provide zero voltage switching
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