Improving verification coverage for ESD (Electro Static Discharge) Ravikanth Kolluru (Reg No: 130942016) Mr. Nitesh J Trivedi Ms. Supritha B.S Sr.Staff Engineer Assistant Professor Infineon Technologies Dept of ECE Bangalore MIT, Manipal Agenda: Introduction Literature Survey Objective The methodology & Results References 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 2 Agenda: Introduction Literature Survey Objective The methodology & Results References 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 3 Introduction : ESD Basics What is ESD? The Transfer of charge b/w two bodies which are at different electrical potentials. Electrostatic charge 13/01/2015 Electrostatic discharge Electrostatic discharge to IC Copyright © Infineon Technologies 2011. All rights reserved. Page 4 Introduction: ESD Basics(contd..) If the design don’t have ESD protection then, ESD can affect the junctions, gate oxide in the transistors, wires ,vias. ESD through system To protect, clamping circuit are placed at key locations in the chip, especially at the i/o, power and ground pads. ESD through ESD protection circuit 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 5 ESD Protection circuit: An “ideal” protection circuit functions as a perfect switch that is Always electrically open during normal IC operation Instantaneously electrically closed in response to an ESD transient. Protection elements should have the following features: Must turn on fast(respond in 200ps) Must handle high ESD currents Must have low impedance only during ESD Not interfere with the circuit operation 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 6 Introduction: About ESD (contd..) ESD Discharge: clamp Intended ESD path Unintended ESD path Single Power Domain 13/10/2014 Two Power Domain Page 7 Agenda: Introduction Literature Survey Objective – Work definition – Problem definition The methodology & Results References 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 8 Literature Survey: Methodologies of ESD Verification: DRC-like Checks on layout – ‘ESDERCII’ To find ESD prone layout ‘structure’ like hot parasitic that can potentially trigger in ESD event and checks for protection. Topology Checks on Schematic netlist– ‘ESDSCHII’ To screen design netlist to grabs topologies that can blow up during ESD event. And to ensure adequate ESD Protection presence. Interconnect Checks – on layout – ‘ESDINT’ Resistance and Current Density Checks. To ensure protection are well connected (Metallization). 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 9 Agenda: Introduction Literature Survey Objective The methodology & Results References 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 10 Objective To improve ESD verification, increasing checks coverage Integration of static methodology of ESD verification 1. Integration of Resistance checks with DRC-like checks. 2. Reporting of Critical/Uncritical errors for DRC-like checks. 3. Integration of Resistance checks with Topology checks. 4. Reporting of Critical/Uncritical errors for Topology checks. Reporting of Redundant clamps in the design. 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 11 Agenda: Introduction Literature Survey Objective The methodology & Results References 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 12 Motivation for Integration of DRC-like & Resistance checks: ESD Verification Checks CDL schematic file Rule Set File Topology Checks GDS file GDS file DRC-like Checks Rule Set File Technology File Resistance Checks Interconnect Checks Current Density Checks DRC-like+ Topology (ESDERCII) [ESDERC +Topology] + Res (ESDERCII +Res) 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 13 DRC-like checks Hot Parasitic CLAMP’S VDD1 VDD2 N+ N+ N+ N+ CLAMP’S CLAMP’S P-Substrate Base-width VSS2 VSS1 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 14 Preset DRC-like checks verification flow (ESDERCII) : Start GDS file (Calibre PERC) VDD1 Get all the error layer information (𝑆𝑎𝑐𝑡𝑢𝑎𝑙 < 𝑆𝑐𝑟𝑖𝑡𝑖𝑐𝑎𝑙 ) … … . 𝑆𝒂𝒄𝒕𝒖𝒂𝒍 < 𝑆𝒄𝒓𝒊𝒕𝒊𝒄𝒂𝒍 VSS1 C.C.C >= Cr.C.C Waived.rdb Violations.rdb No Violations.rdb End 13/01/2015 VSS2 No Clamps? Clamp count (C.C.C) Yes . Go to next error Get the protection info of 1st error layer Yes VDD2 … ESDERC check engine . Rule set file C.C.C Cr.C.C 𝑆𝑎𝑐𝑡𝑢𝑎𝑙 𝑆𝑐𝑟𝑖𝑡𝑖𝑐𝑎𝑙 = = = = Connected Clamp Count (or) Clamp Count Critical Clamp Count Actual Spacing Critical Spacing Page 15 Newly proposed DRC-like checks verification flow(ESDERCII + Res): ESDERCII with Interconnect Resistances Start Rule set file Technology dependent files ESDERC check engine GDS file / (Calibre PERC) Get all the error layer information (𝑆𝑎𝑐𝑡𝑢𝑎𝑙 < 𝑆𝑐𝑟𝑖𝑡𝑖𝑐𝑎𝑙 Resistance Check engine (Apache Totem) Yes W.C.C.C>=Cr.C.C Clamps? . VSS2 Go to next error No Violations.rdb No Violations.rdb End 𝑆𝒂𝒄𝒕𝒖𝒂𝒍 < 𝑆𝒄𝒓𝒊𝒕𝒊𝒄𝒂𝒍 VSS1 Well Connected Clamp Count (W.C.C.C) 13/01/2015 / . ) Resistance Check Reports Waived.rdb … … Get the protection info of 1st error layer Yes VDD2 …. VDD1 C.C.C Cr.C.C 𝑆𝑎𝑐𝑡𝑢𝑎𝑙 𝑆𝑐𝑟𝑖𝑡𝑖𝑐𝑎𝑙 Copyright © Infineon Technologies 2011. All rights reserved. = = = = Connected Clamp Count (or) Clamp Count Critical Clamp Count Actual Spacing Critical Spacing Page 16 Results (DRC-Like+ Resistance): VDDOSC3 (LV) C.C.C Cr.C.C (5V)VDD C.C.C Cr.C.C =1 =1 W.C.C.C = 0 W.C.C.C = 3 𝑆𝒂𝒄𝒕𝒖𝒂𝒍 < 𝑆𝒄𝒓𝒊𝒕𝒊𝒄𝒂𝒍 VSS =3 =3 VSSP WELL CONNECTED (R<𝑅𝑐𝑟𝑖𝑡𝑖𝑐𝑎𝑙 ) NOT WELL CONNECTED (R>𝑅𝑐𝑟𝑖𝑡𝑖𝑐𝑎𝑙 ) Before Integration: 13/01/2015 After Integration: Copyright © Infineon Technologies 2011. All rights reserved. Page 17 DRC –like checks reporting after Integration Overview In case of Waived error (Critical): Reasons for Waiving & Worst connected clamp is reported. In case of Violation error (Uncritical): Cautions for Violation Best connected clamp is reported. ¬ To minimize the design effort to fix the violation, getting parasitic inactive. 19/01/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 18 DRC –like checks Reporting – For waived error Methodology followed for reporting the reasons for waiving: Start Get the protections(clamp info) connected to n1 & n2 VDD1 VDD2 … Get the error net names n1 &n2 Go to next error … … . VSS1 VSS2 Clamps b/w n1 & VSS* , n2 & VSS* >=Cr.C.C Display that clamp info & Worst connected clamp by comparing the resistance value Get the protections(clamp info) connected b/w n1 & n2 Display that clamp info & Worst connected clamp by comparing the resistance value End 19/01/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 19 DRC –like checks Reporting – For waived error (2) VDDP(5V) VDD (LV) C.C.C Cr.C.C C.C.C Cr.C.C =1 =1 W.C.C.C = 1 W.C.C.C = 3 VSS Before Flow improvements: 19/01/2012 =3 =3 VSSP After Flow improvements: Copyright © Infineon Technologies 2011. All rights reserved. Page 20 DRC –like checks Reporting – For Violation error Methodology followed for reporting cautions for violations Start Go to next error VDD1 VDD2 … Get the error net names n1 &n2 Get the protections(clamp info) connected b/w n1 & n2 … … Clamps b/w n1 &n2 ? Get the protections(clamp info) connected to n1 & n2 Clamps to n1 &n2 ? Display that there is no clamps Display that clamp info & Best connected clamp by comparing the resistance values . VSS1 VSS2 Display that clamp info & Best connected clamp by comparing the resistance values End 19/01/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 21 DRC –like checks Reporting – For Violation error (2) VDDP(5V) VDD (LV) C.C.C Cr.C.C C.C.C Cr.C.C =1 =1 W.C.C.C = 2 W.C.C.C = 1 VSS Before Flow improvements: 19/01/2012 =2 =3 VSSP After Flow improvements: Copyright © Infineon Technologies 2011. All rights reserved. Page 22 DRC –like checks Reporting – For Violation error(3) VDDP(5V) VDD (LV) C.C.C Cr.C.C =1 =1 C.C.C Cr.C.C W.C.C.C = 1 W.C.C.C = 2 VSS Before Flow improvements: 19/01/2012 =3 =3 VSSP After Flow improvements: Copyright © Infineon Technologies 2011. All rights reserved. Page 23 Motivation for Integration of Topology & Resistance checks: ESD Verification Checks CDL schematic file Rule Set File Topology Checks DRC-like Checks GDS file Technology File Resistance Checks Interconnect Checks Current Density Checks Topology + Resistance VDD VSS 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 24 Overview of ESD Verification checks : ESD Verification Checks CDL schematic file Rule Set File Topology Checks DRC-like Checks GDS file Technology File Resistance Checks Interconnect Checks Current Density Checks Topology + Resistance 19/01/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 25 Present methodology for Topology checks: Start VDD Rule set file Topology check engine CDL schematic file Critical Topology (Calibre PERC) ... Get all the critical topology information VSS Go to next error Get the protection info of 1st critical topology Yes Clamps? Report Violation Clamp count (C.C.C) Yes C.C.C >= Cr.C.C No No Report Violation Waived (OK) C.C.C = Connected Clamp Count (or) Clamp Count End 19/01/2012 Cr.C.C = Critical Clamp Count Copyright © Infineon Technologies 2011. All rights reserved. Page 26 Proposed methodology for Topology checks (Topology + Resistance) : Start Rule set file Technology dependent files VDD Topology check engine (Calibre PERC) CDL schematic file Critical Topology ... Get all the critical topology information Resistance Check engine (Apache Totem) VSS Go to next error Get the protection info of 1st critical topology Resistance Check Reports Yes No Clamps? Well Connected Clamp Count (W.C.C.C) Yes W.C.C.C>=Cr.C.C Waived (OK) Report Violation No Report Violation W.C.C.C = Well Connected Clamp Count End 19/01/2012 Cr.C.C Copyright © Infineon Technologies 2011. All rights reserved. = Critical Clamp Count Page 27 Results (Topology + Resistance): VDD C.C.C Cr.C.C =3 =3 W.C.C.C = 2 Cr.C.C =3 VSS Before Integration: 19/01/2012 After Integration: Copyright © Infineon Technologies 2011. All rights reserved. Page 28 Topology checks reporting after Integration Overview In case of Waived error: Reasons for Waiving ¬ To understand the which clamps made critical parasitic to uncritical parasitic. In case of Violation error: Cautions for Violation ¬ To minimize the design effort to fix the violation, getting parasitic inactive. 30/04/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 29 Methodology of Topology checks Integration/Reporting – For waived error Start Get the Critical Topology VDD*and VSS* Names VDD Go to next error Get the Protection Info (Clamps) Connected b/w that VDD*and VSS* Critical Topology ... VSS Open one file “Waived_device_info_Supply_Pad.LOG” (or) “Waived_Inverters.LOG” 1. Append the waived device name(only for Supply Pad Rule) 2. Display that Protection (clamp) info & 3. Worst connected clamp by comparing the resistance value This Methodology applied to 2 real-time SOC’s(full chip), and results are as expected End 29/04/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 30 Reporting results: For waived error (for inverter rule) VDD Clamp_Type _1 C.C.C =3 Cr.C.C =3 W.C.C.C = 3 Critical Topology Before Flow improvements: Clamp_Type _2 C.C.C = 2 Cr.C.C = 4 W.C.C.C = 1 VSS After Flow improvements: 29/04/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 31 Topology checks Reporting – For Violation error (2) VDD1 C.C.C Cr.C.C =3 =3 W.C.C.C = 2 After Flow improvements: 30/04/2012 VSS1 Copyright © Infineon Technologies 2011. All rights reserved. Page 32 Methodology of Topology checks Integration/Reporting – For violation Start Go to next error Get the error Topology VDD*and VSS* Names Critical Topology Get the Protection Info (Clamps) Connected b/w that VDD*and VSS* No Clamps b/w VDD* & VSS *? Display that “There is no protection(clamps)” VDD ... ....... VSS Yes C.C.C Cr.C.C W.C.C.C Cr.C.C - W.C.C.C Collect what are all clamp types are there and there critical clamp count from Tech file Calculate Cr.C.C -W.C.C.C Take minimum diff one Display that clamp info & Best connected clamp by comparing the resistance values ... C.C.C Cr.C.C W.C.C.C Cr.C.C - W.C.C.C This Methodology applied to TC23 and TC26(full chip), and results are as expected End 29/04/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 33 Reporting results: For violations (for inverter rule) VDD Clamp_Type _1 C.C.C =2 Cr.C.C =3 W.C.C.C = 1 Cr-W.C.C.C = 2 Critical Topology Clamp_Type _2 C.C.C = 2 Cr.C.C = 4 W.C.C.C = 1 Cr-W.C.C.C = 3 VSS Before Flow improvements: 29/04/2012 After Flow improvements: Copyright © Infineon Technologies 2011. All rights reserved. Page 34 Project status on April 2015. Tasks Status Integration of Resistance checks with DRC-like checks Done Implemented Reporting of violation/waived design error for DRC-like checks Done Integration of Resistance checks with Topology checks Done Implemented Reporting of violation/waived design error for Topology checks Done Reporting of Redundant clamp information Done Documentation of Completed tasks Done 30/04/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 35 Redundant clamps – for DRC checks The clamps which are not protecting any critical parasitic are called as Redundant clamps. VDD1 VDD2 … Detecting redundant clamp for topology checks which is power clamp is non trivial, unlike DRC-like where PDIIC is used dedicated for hot patristics. 29/04/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 36 Methodology for Reporting of Redundant clamps info Start Read DRC-like(ESDERCII) checks reports VDD1 … No Yes Parasitics? VDD2 Extract Unique Parasitic nets Compare each clamp nets with all parasitic nets Redundant Clamps? No No Parasitics Yes Get all redundant clamps Read Resistance Check Reports Get all redundant clamps Interconnect Resistances No Redundant Clamps No Yes Not Well Connected Clamp Well Connected Clamp End 29/04/2012 Copyright © Infineon Technologies 2011. All rights reserved. Page 37 Results: Redundant clamps present in TC23 (1) On TC23: 4 clamps are well connected Total 6 redundant clamps 2 clamps are Not well connected VDDOSC3 VDDP VDDP … … 29/04/2012 VDDM Copyright © Infineon Technologies 2011. All rights reserved. Page 38 Results: Redundant clamps present in TC26 (2) On TC26: Total 7 redundant clamps VDDFLEX VDDP_5V VDDM VDDP_5V VDDOSC3 Copyright © Infineon Technologies 2011. All rights reserved. VDDP_5V/3V3 … … … 29/04/2012 All 7 clamps are well connected Page 39 Agenda: Introduction Literature Survey Objective The methodology & Results References 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 40 References: [1] N. Trivedi., S. Chakravarthy. and E. Weidner (2013) “Optimized Netlist Checks - Full Chip ESD Verification”. EOS/ESD Symposium 2013. [2] David Alvarez., Nitesh J Trivedi. and Sreesha N Chakravarthy.(2013) CDM single power domain failures in 90nm [2] ESD Basics: EDA: http://esda.org/esd_fundamentals.html [3] Calibre PERC user manual [4] Perl Tutorial online http://www.tutorialspoint.com/perl/index.htm [5] Tcl Tutorial online http://www.tutorialspoint.com/tcl-tk/index.htm [6] Apache Totem Path finder user manual http://www.apache-da.com/products/totem/pathfinder [7] Cadence Virtuoso User Manual [8] Infineon internal documents 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 41 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 42 Any Questions ?? 13/01/2015 Copyright © Infineon Technologies 2011. All rights reserved. Page 43
