Digital Logic Gates 1. Figure 1: AND gate using NOR gates Input A 0 0 1 1 B 0 1 0 1 Output Z = (A+B)’ 1 0 0 0 B 0 1 0 1 Output Z = (A◦B)’ 1 1 1 0 2. Figure 2: OR gate using NAND gates Input A 0 0 1 1 3. Figure 3: Half Adder Input A 0 0 1 1 Output B 0 1 0 1 Sum 0 1 1 0 Carry Out 0 0 0 1 4. Figure 4: SR Flip – Flop Input A 0 0 1 1 Output B 0 1 0 1 Sum N/A 1 0 N/A Design 1 Z= A+B Carry Out N/A 0 1 N/A ̅+ B ̅∙B ̅= A ̅ Z̅ = A ̅∙B ̅ Z̿ = ̅̅̅̅̅̅ A Input A 0 0 1 1 B 0 1 0 1 Output ̅ 𝑨 1 1 0 0 ̅ 𝑩 1 0 1 0 ̅∙𝐁 ̅ 𝐙̿ = ̅̅̅̅̅̅ 𝐀 0 1 1 1 Design 2