Advanced Conformal Low Power RAK
October 2012
Contents
Introduction to the RAK
– Overview and goals
– Contents and requirements
– List of labs
Advanced Features of Conformal Low Power
– Power Intent Comparison
– Hierarchical CPF Integration
– CPF Macro Model
Other useful documents
– CPF 1.1 User Guide
– Conformal Low Power User Guide
– Recommended Pre-work : Beginner’s CLP-RAK
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© 2012 Cadence Design Systems, Inc. All rights reserved.
Overview
This RAK describes the advanced features of Conformal
Low Power.
This RAK describes how to do power intent comparison
between two CPFs, how to generate integrated CPF from
hierarchical CPF, and includes a detailed study of the
CPF macro model.
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© 2012 Cadence Design Systems, Inc. All rights reserved.
Goals
At the end of this RAK, you should be able to perform the
following tasks and understand their importance:
– Power intent comparison between two CPFs
– Integrating hierarchical CPF
– Coding macro models in CPF
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© 2012 Cadence Design Systems, Inc. All rights reserved.
Contents and Requirements
This RAK (Advanced_CLP-RAK.zip) contains the
following files/directories:
– This introduction presentation (Advanced_CLP-RAK-overview.pdf)
– Lab documents (Advanced_CLP-RAK_DOCS)
– Advanced_CLP-RAK_LABS_Instructions.pdf
– CLP-Hierarchical_Integration-Overview.pdf
– CLP-CPF_Macro_Model-Overview.pdf
– CPF_Macro_Model-4MixedSignal.pdf
– CPF_Macro_Model-Language_Training.pdf
– CPF_Macro_Model-Language_Tutorial.pdf
– Lab database (Advanced_CLP-RAK_LABS.tar.gz)
This RAK requires the following product licenses:
– Conformal Low Power
– RTL Compiler (Optional)
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© 2012 Cadence Design Systems, Inc. All rights reserved.
RAK Labs
The lab database includes the following labs:
–
–
–
–
–
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Lab 1: Compare Power Intent using CLP
Lab 2a: Hierarchical CPF Integration using CLP
LAB 2b: Verify Integrated Power Intent for Gate Synthesis
LAB 3a: Extract Macro Model from Liberty
LAB 3b: CPF Macro Model – PIA GUI Entry
© 2012 Cadence Design Systems, Inc. All rights reserved.
Power Intent Comparison
LEC engine of CLP has a new capability to carry out
comparison between input golden CPF and the synthesized
or derivative CPF (created by RC or EDI using “write_cpf”)
RTL
SDC
SDC
Power
SDC
Intent
SDC
Synthesis
Netlist
SDC
SDC
Compare
Power
SDC
Intent
SDC
– Derived CPF is written out after synthesis because instance
names change during grouping/ungrouping or flattening
– This feature can detect non-equivalencies between input and
derived CPF objects like number of power domains, nominal
condition, power modes etc.
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© 2012 Cadence Design Systems, Inc. All rights reserved.
Hierarchical CPF Integration
Hierarchical CPF Integration
merges block-level power intent
with top-level power intent
– Block-level power intent can be
used for verification at the block
level, before chip-level integration
– Integration supports combining the
top-level design with soft- and
hard-IP blocks that have low power
features
Block1.cpf
Block1
Top
u_block1
chip.cpf
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© 2012 Cadence Design Systems, Inc. All rights reserved.
CPF Macro Model
Hard macros and IP cells, such as RAM, are blackboxed
– .lib starts to describe some LP attributes, but is not complete
CPF macro models:
– Fully describe the LP intent of the blackbox
– Make it easier to verify the connections between blackboxes and
their surrounding logic
– Can represent hierarchical modules
– Can be used effectively for analog macros
CPF macro model can be generated using
– PIA GUI or text editor (manual coding)
– CLP by extracting LP attributes from Liberty
– Virtuoso Power Intent Export Assistant by extraction from schematic
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© 2012 Cadence Design Systems, Inc. All rights reserved.
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© 2012 Cadence Design Systems, Inc. All rights reserved.