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[UCI]I804:47020-000002292262
Doctoral Thesis
A Study on High Efficiency Bidirectional
Grid-tied Converters
Sung-Ho Lee (이 성 호)
Department of Electrical Engineering
Pohang University of Science and Technology
2016
고효율 양방향 계통 연계형 컨버터에
대한 연구
A Study on High Efficiency Bidirectional
Grid-tied Converters
DECE
이성호, Sung-Ho Lee, A study on High Efficiency Bidirectional
20110862
Grid-tied Converter, 고효율 양방향 계통 연계형 컨버터
에 관한 연구, Department of Electrical Engineering (Control
& Power Electronics Program), 2016, 140p, Advisor: BongHwan Kwon, Text in English.
ABSTRACT
This thesis presents three high efficiency grid-tied converter topologies and their
respective control algorithms. These converters are applicable to various industrial fields
such as energy storage systems (ESS), renewable energy systems, uninterruptible power
supply (UPS) systems, and electric vehicles (EV).
First, a high efficiency bidirectional grid-tied flyback converter that uses a single
power conversion technique and a control system for it are introduced. The proposed
converter consists of a bidirectional flyback dc-dc converter and an unfolding circuit.
Due to its switching control strategy, the proposed converter performs bidirectional
power conversion between the energy storage device and the grid through only single
step. From the model analysis, the inherent dynamic characteristics are figured out.
Based on the analysis, a control system is developed, which consists of a linear
feedback controller with a low pass filter, a repetitive controller, and a feed -forward
controller; this overcomes the constrains caused by a right-half-plane zero and a filter
resonance and makes the proposed converter achieve the desired control
i
performances and stability. In conclusion, the proposed converter can obtain high
efficiency using a single power conversion technique, and the developed control
system makes the proposed converter feasible.
Second, a high efficiency single-phase bidirectional inverter for a PV energy
system integrated with an energy storage system. The proposed single-phase inverter
is developed using the transformerless system configuration so that it provides high
power conversion efficiency, excellent power density, and low production cost.
Using its circuit structure and switching operation, the proposed inverter can
suppress the ground leakage current which is considered to be one of the most
important design parameters in a transformerless PV system. Therefore, the proposed
inverter gives the feasibility for the transforemrless system configuration in a PV
energy system integrated with an energy storage system and enhances the overall
performance of the bidirectional power converter system.
The third is a novel high efficiency three-phase bidirectional grid-tied converter with high
power density for high power applications. The proposed converter is composed of the threelevel dc-dc converter and the modified three-phase T-type three-level inverter. The threelevel converter circuit configuration gives smaller passive component size and lower switch
voltage stress compared to other two-level grid-tied converters. In addition, due to its novel
circuit structure, the proposed converter can use the active and passive components for only
two phases of the grid in the inverter stage and eliminate the leakage current problem. Thus,
because the proposed converter enables to not only decrease the number of components but
also make the transformerless configuration feasible, it provides higher efficiency and higher
power density compared to other high power grid-tied converters.
All proposed converters are analyzed theoretically, and implemented practically
to evaluate their performance. Finally, the experimental results show that the
proposed converters improve overall performance such as high power conversion
ii
efficiency, power density, and production cost with satisfying the standards for the
grid regulations.
iii
Contents
1
Chapter 1. Introduction
1.1. Background.…………………………………………………………….
1
1.2. Organization……...………….…………………..……………………...
7
Chapter 2. High Efficiency Bidirectional Grid-tied Converter using Single
9
Power-conversion Technique and Repetitive Control Scheme
2.1. Proposed Bidirectional Grid-tied Converter Using Single Power13
conversion Technique……………………………………………..….
2.2. Control System with Repetitive Control Scheme for the Proposed
18
Bidirectional Grid-tied Converter ……………………….……………..
2.3. Design Procedure………………………………….………………..…... 32
2.4. Experimental Results ……………………………….…………..……. 34
Chapter 3. Single-phase Transformerless Bidirectional Full-bridge Type
40
Inverter for a PV system integrated with an Energy storage
3.1. Analysis for Conventional Full-bridge Inverter Topology………..……. 43
3.2. Proposed Single-phase Transformerless Bidirectional Full-bridge Type
49
Inverter…………………………………………………………….........
3.3. Experimental Results ……………….………………………..…………. 58
Chapter 4. High Efficiency Three-phase Transformerless Bidirectional
66
Grid-tied Converter with High Power
4.1. Analysis of Three-level DC-DC Converter ………………...……..…... 72
4.2. Analysis of Modified Three-phase Inverter …………………………….. 84
4.3. Ground Leakage Current Analysis…………..…………………………. 89
4.4. Experimental Results ………………………………………………… 94
99
Chapter 5. Conclusion
iv
Appendix. Soft-switching Single Power-conversion OBC with High
Efficiency and High Power Density
102
A.1. Proposed Soft-switching Single-power Conversion OBC with High
Efficiency and High Power Density………. ………...……..…...
105
A.2. Experimental Results……………………………….………………..
118
* 요 약 문..........................................………………………………..
123
* References…………………………………………….……………….
126
v
List of Figures
1.1
Bidirectional grid-tied converter in grid-tied renewable energy systems…………2
1.2
Bidirectional grid-tied converter in EVs …………..……………………………….3
1.3
Configuration for the conventional bidirectional grid-tied converter. (a) LF
transformer type bidirectional grid-tied converter. (b) HF transformer type
bidirectional grid-tied converter ……………………………………...…………….5
2.1
Bidirectional grid-tied converter configurations. (a) Grid-tied converter with only
inverter stage. (b) Conventional two-stage grid-tied converter. (c) Single-power
conversion grid-tied converter...…………………………………........…………..10
2.2
Proposed bidirectional grid-tied converter using single power conversion technique
………………………………………………………………….............................13
2.3
Sub-operating modes for the discharging mode. (a) Stage 1. (b) Stage 2.…….........14
2.4
Equivalent circuit of the proposed bidirectional grid-tied converter........................18
2.5
Bode plots of the uncompensated system for the plant Gid……………………..….21
2.6
Block diagram for a conventional control system with a conventional PI
controller………………………………………………………………………….21
2.7
Bode plots of the compensated system by the conventional PI controller: the lowgain feedback controller, kp=0.03 (blue) and high-gain feedback controller, kp=0.5
(red). (a) Only P controller is used. (b) PI controller with ki=10 is used. ……........23
vi
2.8
Concept of a repetitive control……...……………………………………………..25
2.9
Block diagram for the developed control system with repetitive control scheme....26
2.10
Bode plots of the compensated system Gid(z)Cfb(z) by Cfb.…...…………....….....27
2.11
Nyquist plots of |H(z)| for kr=0.3 according to the phase-lead index, m………….29
2.12
Bode plots of the compensated system by the low-gain feedback controller is used
(blue); by the developed control system in Fig. 2.9 is used (red)………...........…. 30
2.13
Switching losses on the both switches in the half-cycle of the grid according to turns
ratio and magnetizing inductance under the following conditions: Pavg =250W,
fs=50kHz, Vg,rms=220V, and Vdc=48V..………………...…………………………. 34
2.14
Overall system configuration for the prototype ……...…………………………...35
2.15
250W prototype of the proposed bidirectional converter…………………….….35
2.16
Experimental waveforms for the grid voltage vg and grid current ig in discharging
mode when the conventional control system is applied. (a) Low controller gain, kp
=0.03. (b) Higher controller gain, kp=0.4....…………………….........………….....36
2.17
Experimental waveforms for the grid voltage vg and grid current ig when the
proposed control system in Fig. 2.9 is applied. (a) Discharging mode. (b) Charging
mode.…………………………………………………………………………….37
2.18
Experimental waveforms for v g and i g in the operation mode transientstate.……………………………………………………………………………….39
vii
2.19
Efficiency comparison according to the power conversion schemes: single-power
conversion scheme (black) and conventional two-stage power conversion scheme
(red)..…………………………………………………………………………….39
3.1
Ground leakage current path in the transformerless system configuration…...........41
3.2
Bidreictional grid-tied converter in a PV system integrated with an energy storage
(a)Without MPPT converter (b) With MPPT converter…..………………………..42
3.3
Conventional single-phase full-bridge inverter ………...………………………....43
3.4
High-frequency model of the full-bridge inverter with the bipolar PWM scheme. (a)
High-frequency equivalent circuit. (b) High-frequency model. (c) Simulation
results……………………..……………………………………………………….45
3.5
High-frequency model of the full-bridge inverter with the unipolar PWM scheme.
(a) High-frequency equivalent circuit. (b) High-frequency model. (c) Simulation
results……..……………………………………………………….....……………48
3.6
Proposed single-phase transformerless bidirectional full-bridge type inverter…..49
3.7
Sub-operating modes in the grid-tied inverter mode of the proposed inverter
according to switching states. (a) S1 on and S6 on. (b) S2 on and S6 on. (c) S3 on and
S5 on. (d) S4 on and S5 on…………….……………………………..…………51
3.8
Sub-operating modes in the PWM rectifier mode of the proposed inverter according
to switching states. (a) S1 on and S6 on. (b) S2 on and S6 on. (c) S3 on and S5 on. (d)
S4 on and S5 on……………………….……………………………..………….52
viii
3.9
High-frequency model of the proposed inverter………………………….........…53
3.10
Control block diagram of the proposed inverter…………………………………..56
3.11
Analog circuit implementation of the gate driver for S5 and S6 ……..……………..58
3.12
Overall system diagram for the prototype of the proposed single-phase bidirectional
inverter………………………………………………………………….……….59
3.13
Waveforms for the grid voltage vg and the grid current ig in the proposed inverter.
(a) Grid-tied inverter mode. (b) PWM rectifier mode…………………………..62
3.14
Comparison for the ground leakage current characteristic. (a) Full-bridge inverter
with the bipolar PWM scheme. (b) Full-bridge inverter with unipolar PWM scheme.
(c) Proposed inverter ………………………………………………………....63
3.15
Efficiency comparison according to the inverter topologies. (a) Grid-tied inverter
mode. (b) PWM rectifier mode…………………………………………………....65
4.1
Three-level converter/inverter topologies. (a) Three-level dc-dc converter. (b)
Three-phase three-level NPC inverter. (c) Three-phase three-level T-type inverter.
………………………………………………………………………………….....68
4.2
Circuit diagram for the proposed three -phase three-level transformerless
bidirectional grid-tied converter…………………………………………………..71
4.3
Theoretical waveforms in the discharging mode of the three-level dc-dc converter
(a) ddchg<0.5. (b) ddchg >0.5………………………………………………………..74
ix
4.4
Equivalent circuits according to sub-operating stage in the discharging mode...…..75
4.5
Equivalent circuits according to sub-operating stage in the charging mode……..76
4.6
Battery charging approach with CC and CV modes……....……………………….80
4.7
Control algorithm block diagrams in the charging mode…………………………..82
4.8
Control algorithm block diagrams in the discharging mode..……………………...83
4.9
Circuit diagram of the modified three-phase three-level inverter………….……....84
4.10
Switching pattern of T-type cell A………………..………………………………..85
4.11
Equivalent circuits for T-type cell A in the modified three-level inverter. (a) Mode1.
(b) Mode 2. (c) Mode 3. (d) Mode 4.......…………………………………….……..86
4.12
Control algorithm block diagram in the modified three-phase inverter…….……..88
4.13
High frequency modeling of the conventional grid-tied converter. (a) High
frequency equivalent circuit. (b) High frequency model.……………………….90
4.14
Simulation results for the ground leakage current in the conventional grid-tied
converter………………………………………....………………………………..91
4.15
High frequency modeling of the proposed grid-tied converter. (a) High frequency
equivalent circuit. (b) High frequency model…………….………………………..92
x
4.16
Simulation results for the ground leakage current in the proposed grid -tied
converter………………………………………....………………………………..93
4.17
Photograph for the experimental setup of the 10kW prototype…..………………..95
4.18
Implementation of a bidirectional switch in a T cell……………..………………..95
4.19
Experimental waveforms for the dc-link voltage Vdc and the dc-link capacitor
voltages Vdc1 and Vdc2………………………………………….....………………..97
4.20
Experimental waveforms for the three-phase grid currents iA, iB, iC…...…………..98
4.21
Experimental waveforms for the voltage vPE across the parasitic capacitor and the
leakage current ip………………………………………………….…...…………..98
4.22
Measured power efficiency under entire load conditions in the discharging
mode……………………………………………………………………………..98
A.1
Circuit configuration and control block diagram of the proposed OBC………….105
A.2
Key waveforms of the proposed OBC for D<0.5……………….………………..107
A.3
Equivalent circuits of the proposed OBC for D<0.5 during half switching period,
Ts/2………………………………………………………………………...........108
A.4
Key waveforms of the proposed OBC for D>0.5…...…………………………....112
A.5
Equivalent circuits of the proposed OBC for D>0.5 in the overlapped region.….113
A.6
Proposed control block diagram for the single power-conversion.…………….....114
xi
A.7
ZCS region of the proposed OBC according to circuit design.…………………...117
A.8
Experimental waveforms for the grid voltage vg, the grid current ig, and the output
current io.………………….…………………………………………..….……....119
A.9
Experimental results for the soft-switching technique on the switches (a) Gate
signal vs1_gs and switch current is1 of the main switch S1. (b) Gate signal vs1a_gs and
switch current is1a of the main switch S1 of the active- clamp switch S1a.Equivalnet
circuits of the proposed OBC for D<0.5 during half switching period,
Ts/2…………………………………………....………………………………..120
A.10
Experimental results for the soft-switching technique on the output diode D1
………………………………………………………………………………..120
A.11
Measured power factor according to the grid voltage level.……………….……..121
A.12
Conversion efficiency comparison according to the OBC topology…………...121
xii
List of Tables
1.1
Summary of grid requirement (IEEE 1547)………….……………………………...4
2.1
Power losses calculation in the conventional two-stage converter……………...….17
2.2
Power losses calculation in the proposed converter……………..……………...….17
2.3
Current and voltage stresses on the bidirectional flyback…………………..…...….33
3.1
Design parameters and components of the prototype ......…………………….….59
3.2
Summary of experimental results……………………………....…………………….….64
4.1
Parameters and components of the prototype for the proposed three-phase grid-tied
converter……………………………………………….........…………………….…94
A.1
Parameters and components of the prototype…..... ......…………………….….118
xiii
Chapter 1
Introduction
1.1 Background
With rapid growth of renewable energy systems such as photovoltaic (PV) energy
and wind power systems, the grid-tied energy storage systems which links an energy
storage device such as a battery and an ultra-capacitor to the main utility grid have
been receiving many attention as one of the most important aspects in modern
electrical grid systems [1], [2]. The grid-tied energy storage systems alleviate the
intermittency of the generated power by the renewable energy systems and carry out
the power quality managements [3]-[6].
Beside the compensation for intermittency of the renewable energy systems, the
grid-tied energy storage systems provides the following services [7]-[9] in various
industrial fields such energy storage systems (ESS) and electrical vehicles (EV):
1) It provides the energy stored during off-peak time during on-peak hours so that
home/commercial owners can cut peak demand and electricity cost.
1
AC bus
Wind power
PCS
Wind turbin
Utility grid,
1ϕ or 3ϕ
PV
PCS
PV array
Bidirectional
grid-tied
converter
Energy
storage device
Fig. 1.1 Bidirectional grid-tied converter in grid-tied renewable energy systems.
2) By enabling the management for load and outage, the increase the reliability
and stability on the system.
3) It also could make the utility grid maintain constant frequency.
To satisfy the aforementioned various functions and interface the energy storage
devices with the utility grid, a bidirectional grid-tied converter is essential; it carries
out the bidirectional power flow control depending on the power requirements.
Fig. 1.1 and 1.2 show the case examples of the bidirectional grid-tied converter in
the renewable energy systems and EVs, respectively. In the renewable energy systems,
when the renewable energy is much enough or the energy consumption is low, the
2
Bidirectional
Grid-tied
converter
Main
battery
Auxiliary
battery
inverter
motor
dc-dc
converter
Fig. 1.2 Bidirectional grid-tied converter in EVs
bidirectional grid converter transfers the energy from the utility grid to the energy
storage devices to obtain the preliminary energy. On the other hand, when the
renewable energy is not sufficient or during peak times, the bidirectional grid-tied
converter releases the stored energy in the direction of the utility grid. In EVs, as the
vehicles are the potential energy storage sources, they charge the electrical energy or
supply energy back to the grid through a bidirectional grid-tied converter [10]. These
energy transfer scenarios are so called grid to vehicle (G2V) or vehicle to grid (V2G);
this concept is considered as one of ESSs.
The acceptability of the bidirectional grid-tied converter is generally evaluated by
its power conversion efficiency, power density, cost, and reliability. Furthermore,
because the bidirectional grid-tied converter is interconnected with the grid, it should
3
TABLE 1.1
SUMMARY OF GRID REQUIREMENTS (IEEE 1547)
1)
Power quality requirements
Individual harmonics of maximum fundamental current (odd)
Order, h (%)
≤ 11
11-15
17-21
23-33
4.0
2.0
1.5
0.6
5
2
DC current injection limitation
2)
THD1
Less than 1% of the rated RMS current
Response to abnormal grid condition
Type
Voltage variation V, range (%)
Frequency variation f, (Hz)
Abnormal
condition
Disconnection time3 (sec.)
V < 50
0.16
50≤ V <88
2.00
110< V <120
1.00
V≥ 120
0.16
59.3< f <60.5
0.16
1. THD: Total harmonic distortion
2. RMS: Root-mean-square
3. Disconnection time: the time to disconnect a power converter with the utility grid when the abnormal
condition occurs
accommodate some standards for grid requirements such as IEEE standard 1547 [11],
[12] and IEC 61000 [13], [14]. The standards include the power quality requirements
and the response to abnormal grid condition as shown in Table 1.1.
4
Energy
storage
devices
Bidirectional
dc-dc
converter
Bidirectional
grid-tied
inverter
DC
LF
Transformer
Utility grid,
1ϕ or 3ϕ
DC
DC
AC
Bidirectional grid-tied converter
(a)
Energy
storage
devices
Bidirectional
dc-dc converter with
HF transformer
DC
Bidirectional
grid-tied
inverter
Utility grid,
1ϕ or 3ϕ
DC
DC
AC
Bidirectional grid-tied converter
(b)
Fig. 1.3 Configuration for the conventional bidirectional grid-tied converter. (a) LF transformer type
bidirectional grid-tied converter. (b) HF transformer type bidirectional grid-tied converter.
Fig. 1.3 shows the conventional bidirectional grid-tied converter configurations. It
consists of a bidirectional dc-dc converter and a bidirectional grid-tied inverter. The
dc-dc converter performs the charging/discharging operations by conducting the
bidirectional dc-dc power conversion between the energy storage devices and the dclink [15]-[20]. On the other hand, the grid-tied inverter works the dc-ac power
conversion satisfying the power quality introduced by the above grid requirements
[21]-[23]. As shown in Fig. 1.3 (a), the bidirectional converter has a line-frequency
(LF) transformer, which provides the galvanic isolation between the energy storage
devices and the utility grid. However, the presence of the LF transformer causes many
5
disadvantages such as low power conversion efficiency, poor power density, heavy
weight, expensive production cost and loud noise [24]-[26]. As a solution to overcome
drawbacks in the LF transformer type converters, the high-frequency (HF)
transformer type bidirectional grid-tied converters have recently introduced in [27][30]; these improve the overall performance for the bidirectional converters. However,
there are still performance challenges.
Having the abovementioned facts in mind, this dissertation is dedicated toward
developing high efficiency bidirectional grid-tied converter topologies. To achieve the
high performance bidirectional grid-tied converters, two methodologies are
introduced and utilized. The first method is the single power conversion technique;
this method facilitates the bidirectional power conversion between the energy storage
devices and the utility grid through only single step. Another method is to employ
transformerless system configuration. These methods can significantly improve the
overall performance of the bidirectional grid-tied converters such as power conversion
efficiency, density, and cost compared to the conventional bidirectional grid-tied
converters in Fig. 1.3.
6
1.2 Organization
This thesis concentrates on high efficiency bidirectional grid-tied converter
topologies and their respective control algorithms. According to power capability,
three different bidirectional grid-tied converter topologies are proposed and they are
theoretically analyzed and experimentally evaluated in each chapter.
In Chapter 1, the general research background is introduced. Also, the two
configurations of the conventional bidirectional grid-tied converters are investigated.
In Chapter 2, a high efficiency bidirectional grid-tied converter that uses a single
power conversion technique and a control scheme for it are presented. The proposed
converter consists of a bidirectional flyback dc-dc converter and an unfolding circuit.
By adjusting the pulse-width-modulation signal of the flyback, the proposed converter
performs bidirectional power conversion between the energy storage device and the
grid in only single power conversion. The control system for the proposed converter
is developed using the repetitive control scheme; this approach overcomes the control
problem caused by the right-half-plane zero of the flyback converter and ensures fast
reference tracking and good disturbance rejection while satisfying the desired stability.
Thus, the proposed converter can obtain high efficiency using a single power
conversion technique, and the developed control system makes the proposed converter
be feasible. The operation principle for the proposed converter and the analysis for its
developed control system are explained. Finally, experimental results for a 250W
prototype are represented to confirm the validity of the proposed converter and its
control system.
In chapter 3, a high efficiency single-phase bidirectional inverter for a PV energy
system integrated with an energy storage system. The proposed bidirectional inverter
is developed using the transformerless system configuration so that it provides high
power conversion efficiency, excellent power density, and low production cost. Using
its circuit structure and switching operation, the proposed inverter can suppress the
7
ground leakage current which is considered to be one of the most important design
parameters in a transformerless PV system. Therefore, the proposed transformerless
inverter gives the feasibility for the transforemrless system in a PV energy system
integrated with an energy storage system and enhances the overall performance of the
bidirectional grid-tied converter system. Efficiency and ground leakage current
characteristics in the proposed inverter are analyzed. Also, its bidirectional operation
principles and control method are described in detail. Finally, a 3kW prototype is
implemented to confirm the theoretical analysis and the validity of the proposed
single-phase bidirectional transformerless inverter.
In Chapter 4, a novel high efficiency three-phase bidirectional three-level grid-tied
converter with the high power density for high power application. The proposed
converter is composed of the three-level dc-dc converter and the modified three-phase
T-type three-level inverter; this three-level configuration gives lower switch voltage
stress and smaller passive component size, thereby improving the power conversion
efficiency compared to that of the conventional two-level converter. Furthermore, by
connecting S-phase of the grid to ground, the transformer can be eliminated, which
enhances the overall performances like the second proposed converter. Therefore, the
proposed grid-tied converter provides high efficiency and high power density from
three-level and transformerless system configuration. Finally, its theoretical analysis
and validity is confirmed from the experimental results using a 10kW prototype.
In Chapter 5, the conclusions are described with brief summaries for the three
proposed grid-tied converter topologies.
8
Chapter 2
High Efficiency Bidirectional Grid-tied
Converter using Single-power conversion
Technique and Repetitive Control Scheme
Small renewable energy applications such as a PV module integrated converter
system have been considered as a trend of future power system due to higher system
efficiency, more effective space utilization, easier maintenance that those of the other
PV systems [31], [32]. With this trend, the ESS application that corresponds the power
level is also necessary for the reliable operation of the small renewable energy system.
A system battery level is determined by connecting batteries in series/parallel. Fig.
2.1 (a) shows the bidirectional grid-tied power system which employs the single-stage
type converter. However, the system in Fig. 2.1 (a) needs many series-connected
batteries for ensuring high voltage battery level; this fact causes large space and high
system cost by a lot of battery monitoring system (BMS) modules. Thus, it is not
suitable for the small power applications that emphasize the importance of high power
9
vg
Vdc-link
Vdc
Grid-tied
inverter
vg
-
(high freq.)
-
+
+
High voltage
energy source
Utility grid
(a)
Grid-tied
inverter
-
(high freq.)
+
-
(high freq.)
Vdc_link
Low voltage
energy source
vg
-
bidirectional
dc-dc
converter
+
Vdc
vg
Vdc-link
+
Vdc
Utility grid
(b)
vg
Unfolding
circuit
-
(grid freq.)
+
-
(high freq.)
Low voltage
energy source
vg
-
vcf
+
Vdc
bidirectional
dc-dc
converter
+
vcf
Vdc
Utility grid
(c)
Fig. 2.1.
Bidirectional grid-tied converter configurations. (a) Grid-tied converter with only inverter
stage. (b) Conventional two-stage grid-tied converter. (c) Single-power conversion grid-tied converter.
density and low cost.
Fig. 2.1 (b) shows the conventional bidirectional grid-tied converters that have twostage circuit configuration with LF or HF transformer. The dc-dc converter stage of
two-stage allows that the system battery voltage can be reduced. However, this twostage circuit configuration causes low power conversion efficiency, poor power
10
density, and high cost. Furthermore, the configuration requires the two independent
controllers for each stage; this fact contributes to increase the system complexity.
These drawbacks stand out especially in small power applications.
To overcome the drawbacks of the two-stage converters, the bidirectional grid-tied
converters that use a single-power conversion technique have been recently
introduced in [33]-[35]. As shown in Fig. 1b, these bidirectional converters entail the
ac-dc power conversion through only one step, so that they achieve higher efficiency,
higher power density and more competitive price compared to the conventional twostage converters. To implement the single power conversion, their dc-dc converter
should cover wide operating ranges. However, because the grid-tied converters that
employ a DAB circuit in [33], [34] have only step-down function, they require high
transformer turns ratio to achieve the voltage matching of the grid level; this causes
high current stress and degrades power conversion efficiency. Moreover, the
conventional converters in [33], [34] require many switch components, so that its
production cost increases. Thus, these facts bring that the converter configuration
based on the DAB circuit does not fully strengthen the merits of the single power
conversion technique. The grid-tied converter in [35] is developed based on a
bidirectional flyback topology. The flyback is able to cover wide operating ranges by
providing both step-up and step-down functions, and its circuit structure is simpler
compared to the DAB. Thus, the converter that employs the flyback is more suitable
for the implementation of the single power conversion technique compared to the
converters in [33], [35]. However, to avoid the difficulty of the output current control
by a right-half-plane (RHP) zero in the continuous conduction mode (CCM) region,
it operates in only the discontinuous conduction mode (DCM) region; this causes high
power losses and low power capability. In conclusion, the converter in [36] cannot
11
optimize power conversion efficiency despite of employing the single-power
conversion technique. Furthermore, its switching pattern is determined according to
(transferred power direction). In this case, the switch control method becomes
complex, and the operating mode transition is discontinuous.
The repetitive controller is used to deal with periodic signals to track periodic
reference and to reject periodic disturbances. In repetitive control scheme, the
knowledge acquired from the previous trial is used to improve the control input for
the current trial. By conducting the same task repetitively, the control input is adjusted,
and an ideal control input with the zero tracking error can be finally obtained. Thus,
the repetitive controller has been successfully implemented and utilized in a number
of the periodic systems such as continuous casting process, hard disk drive, industrial
robotic manipulator, and grid-tied inverter systems [37]-[39].
In this chapter, a high efficiency bidirectional grid-tied flyback converter that uses
a single-power conversion technique and a control system for it are introduced. The
proposed converter consists of a bidirectional flyback converter and an unfolding
bridge, and carries out bidirectional power conversion between the energy storage
device and the grid through only single step. The bidirectional flyback operates in the
CCM region, which allows the proposed converter to enhance the power conversion
efficiency and power capability compared to the converter in [36]. The control system
is developed considering the dynamic characteristics of the proposed converter and is
composed of a linear feedback controller with a low pass filter, a repetitive controller,
and a feed-forward controller. The developed control system allows to overcome the
constrains caused by the inherent dynamics of the proposed converter and to ensure
the desired reference tracking and disturbance rejection performances with the desired
stability. In conclusion, the proposed converter can obtain high efficiency using its
12
circuit configuration and the single power conversion technique, and the developed
control system makes the proposed converter feasible.
2.1 Proposed Bidirectional Grid-tied Converter Using SinglePower Conversion Technique
2.1.1. Description and Operation Principle
Vdc
vg
vcf
Np : Ns
isec
io
ipri
Idc
Lm
vp
vcf S3
Cf
S5
Lf
ig
im
Vdc
vg
T
Cdc
S2
S1
S4
Discharing mode
vg
Vdc
S6
Charing mode
vg
PLL
Feed-forward
controller
D
d
∑
_
io
+
+
d
Current
controller
∑
|sinωt|
+
i*
o
Ig*
Fig. 2.2. Proposed bidirectional grid-tied converter using single-power conversion technique.
Fig. 2.2 shows the proposed bidirectional grid-tied converter circuit diagram; it
consists of a bidirectional flyback dc-dc converter with turns ratio n (=Ns/Np) of the
transformer T and an unfolding bridge circuit. The switches S1 and S2 of the
bidirectional flyback converter are driven at the high frequency and are operated
complementary to each other. Unlike the conventional bidirectional flyback dc-dc
converters, the operating point in the proposed converter is varied with half the grid
period, and the pulse width modulation (PWM) signal of the flyback is adjusted to
13
Np : Ns
isec
Lf
io
ipri
Idc
Lm
Cf
|vg|
im
Vdc
T
Cdc
S2
S1
(a) Stage 1
Np : Ns
isec
Lf
io
ipri
Idc
Lm
Cf
|vg|
im
Vdc
T
Cdc
S2
S1
(b) Stage 2
Fig. 2.3. Sub-operating modes for the discharging mode. (a) Stage 1. (b) Stage 2.
convert the dc voltage Vdc into the voltage vcf with the rectified sinusoidal waveform.
Furthermore, the PWM scheme accommodates the regulation of the output current io
to produce high quality waveform and to ensure low THD on the grid current ig. Thus,
this method facilitates the interface between the dc voltage source Vdc and the grid vg
with only the single-power conversion as shown in Fig. 2.2. The unfolding bridge
operates at the grid frequency; the switches S3 and S6 are turned on during the positive
half-cycle of the grid voltage vg, whereas S4 and S5 are turned on during the negative
half-cycle. The unfolding bridge only injects sinusoidal ac current into the grid or
extracts it from the grid.
The operation mode is classified according to the power direction; in the charging
mode, the power is transferred from the grid side to dc side while the power in the
14
discharging mode is transferred in the opposite direction of the charging mode. Fig. 2.
3 shows the sub-operating modes under the discharging mode; the energy from the dc
voltage source Vdc is stored in the magnetizing inductance Lm when the switch S1 is
turned on. Then, the stored energy is transferred to the grid side through S2. In the
charging mode, the current direction is reversed, and its sub-operating modes are
similar to those of the discharging mode.
2.1.2. High Efficiency Characteristic
The converter’s circuit configuration is one of the most important factors which
decide the power conversion efficiency. Consider that the converter circuit in Fig. 2.2
operates in the manner of the conventional two-stage converter as shown in Fig. 2.1b.
In this case, the bidirectional flyback performs the power conversion between the
battery and the high constant voltage source Vdc_link, and the switches S3-S6 works as
the full-bridge inverter that operates at the high frequency. The system parameters are
as follows: the rated average power P=250W, the nominal battery voltage Vdc =48V,
the grid voltage vg=220Vrms, and the grid frequency fg=60Hz. The circuit parameters
of the converter are represented as: the flyback converter’s switching frequency fs =
50kHz, the full-bridge inverter’s switching frequency fs_inv=16kHz, the dc-link voltage
Vdc_link=350V, the transformer turns ratio n=65/13, and the magnetizing
inductanceLm=50 The flyback switches S1 and S2 are IPP200N25N3G and
SCT2080KE. The switches S3-S6 are IPP60R074C6. With the parameters, Table 2.1
shows the power losses calculation of the conventional two-stage converter according
to the transferred average power in discharging mode. From Table 2.1, it is noticed
that in the power conversion manner of the conventional two-stage converter, both
stages yield the conduction and switching losses; especially, the switching losses are
15
dominant in the both stages.
The proposed converter in Fig. 2.2 employs the single-power conversion technique
as shown in Fig. 2.1c. As abovementioned, the unfolding bridge operates at the grid
frequency, and its switching loss is almost zero. Moreover, the dc-link electrolytic
capacitor with the rated high voltage is eliminated and is replaced with the filter
capacitor Cf; this contributes to reduce the converter size. The system parameters and
the semiconductor parts are the same as the aforementioned values. The circuit
parameters of the proposed converter are as follows: the flyback converter’s switching
frequency fs = 50kHz, the transformer turns ration n=57/13, the magnetizing
inductance Lm=40 μH, the filter capacitor Cf=0.68μF, and the filter inductor Lf=400μH.
With the parameters, Table 2.2 presents the power losses calculation of the proposed
converter. Table 2.2 indicates that the proposed converter has lower power losses
under all load conditions compared to those of the conventional two-stage converter.
In conclusion, despite the similar circuit structure, the proposed converter can
significantly reduce power losses and obtain higher efficiency by employing the
single-power conversion technique.
16
TABLE 2.1
POWER LOSSES CALCULATION IN THE CONVENTIONAL TWO-STAGE CONVERTER
Transferred average power
Losses
50W
250W
Flyback
Switching loss
2.021W
4.895 W
converter
Conduction loss
0.039 W
0.4 W
Full-bridge
Switching loss
1.761 W
6.596 W
inverter
Conduction loss
0.008 W
0.19 W
Gate drivers
loss
0.413 W
0.413 W
TABLE 2.2
POWER LOSSES CALCULATION IN THE PROPOSED CONVERTER
Transferred average power
Losses
50W
250W
Flyback
Switching loss
1.792 W
5.848 W
converter
Conduction loss
0.028 W
0.701 W
Unfolding
Switching loss
0W
0W
bridge
Conduction loss
0.008 W
0.19 W
Gate drivers
loss
0.293 W
0.293 W
17
2.2 Control System with Repetitive Control Scheme for the
Proposed Bidirectional Grid-tied Converter
2.2.1. Control Issue in the Proposed Converter
Lf
Rg io
|vg|
Lm
vp
Cf
vcf
im
Vdc
T
S1
S2
Rs2
Rs1
Fig. 2.4.
Equivalent circuit of the proposed bidirectional grid-tied converter
The proposed converter should perform the bidirectional power flow control and
satisfy the utility interface standard such as IEEE 1547 with only single step. The
output current io indicates the power flow direction, the transferred power level, and
power quality on the grid side. Thus, the single-power conversion in the proposed
converter can be made feasible by controlling the output current. Fig. 2.4 shows the
equivalent circuit of the proposed converter. In Fig. 2.4, Rs1 and Rs2 are the drain-tosource on-state resistances of the switches S1 and S2, respectively. Rg is an equivalent
resistance on the grid side including the parasitic resistance of the filter inductor Lf
and the drain-to-source on-state resistances of the unfolding switches. The PWM
signal makes S1 and S2 operate complimentarily in both operation modes, and the
proposed converter has only two sub-intervals: S1 on and S2 off, or S1 off and S2 on.
Thus, a model that can be used for both operation modes can be developed. Let the
duty ratio of the switch S1 define d. From Fig. 2.4, the averaged equations over one
switching period can be derived as
18
Lm
 vg (t )  Rs 2 im (t ) 
d im (t ) Ts
Ts 
 d (t ) Vdc  Rs1 im (t ) Ts  d '(t ) 


dt
n



Cf
Lf

d vcf (t )
Ts
dt

d '(t ) im (t ) Ts
 io (t ) Ts
n
d io (t ) Ts
 Vdc  vg (t )  Rg io (t ) Ts
dt
(2.1)
(2.2)
(2.3)
where <x(t)>Ts denotes the average of x(t) over Ts; d’(t) is defined as 1-d(t).
Considering that the current in an inductor and the voltage in a capacitor do not change
rapidly in steady-state, the duty ratio D is obtained as
D(t )
vg (t )
vg (t )  nVdc
.
(2.4)
and the magnetizing current Im in steady-state is
Im 
nI o
1  D(t )
(2.5)
where D and Im represent the operating points in steady-state, and Io is the output
current value at that point. Then, by applying the small signal modeling method to
(2.1)-(2.5), the control input-to-output current transfer function Gid(s) can be derived
~
~
as (2.6). io and d are the small ac variations of io and d. The transfer function in (2.6)
can be converted to a discrete-time transfer function, which will be used to in the
following section to connect the proposed converter system to the developed
controller. Using the backward difference method with the sampling period Tsam, the
discrete-time transfer function for (2.6) can be obtained as (2.7).
19
i
Gid ( s )  o 
d
 D ' k  I m Req 
Im
s

 nLm L f C f 
nL f C f


2


 Req
 Req Rg  2
Req Rg
Rg D '2
1
D'
s
s3  

 2

 2
s 
 Lm L f 
 L f C f n Lm C f
Lm L f   Lm L f C f n Lm L f C f



 
vg
D ' Rs 2
R
where Req  DRs1 
and k  Vdc  I m ( Rs1  s 2 ) 
n
n
n

Gid ( z ) 
io
d




(2.6)

3
4
3
a1Tsam
z  (aoTsam
 a1Tsam
)
2
3
2
z 4  (b2Tsam  3) z 3  (b1Tsam
 2b2Tsam  3) z 3  (boTsam
 b1Tsam
 b2Tsam  1) z
where a0 
b1 
D ' k  I m Req
Req
Rg D '2
Im
, a1 =
, b0 

,
nL f C f
nL f C f Lm
L f Lm C f n 2 L f Lm C f
(2.7)
Req Rg
Req Rg
1
D '2


, and b2 =

.
2
L f C f n Lm C f
L f Lm
Lm L f
Analysis of the transfer functions in (2.6) and (2.7) demonstrates that Gid includes
a RHP zero which imposes a limitation on a feedback controller’s gain and available
bandwidth. The RHP zero varies according to the operating points, and its minimum
value (worst case) is at the peak of the grid voltage under the maximum transferred
power. Thus, the controller should be designed to accommodate the minimum RHP
zero; this requirement makes the feedback controller gain be very low. Furthermore,
there is another issue in (2.6) and (2.7). Fig. 2.5 shows the open-loop Bode plot of the
uncompensated system for the plant Gid where the operating point is selected to be the
point with the minimum RHP zero. In Fig. 2.5, the resonant peak and the rapid phase
drop at the resonant frequency by the filter inductor Lf and the filter capacitor Cf are
observed. The feature results in the another constraint of the feedback controller gain
and available control bandwidth.
20
Fig. 2.5. Bode plots of the uncompensated system for the plant Gid.
v(z)
io*(z) + e(z)
_
Fig. 2.6.
Conventional feedback
PI controller, CPI
Plant
CPI
Gid(z)
+
+ io(z)
Block diagram for a conventional control system with a conventional PI controller.
Fig. 2.6 shows a conventional control system with a proportional-integral (PI)
controller where io*(z) is the reference of the output current, e(z) is the error signal,
and v(z) is the disturbances such as harmonics. From Fig. 2.6, the output response can
be obtained as follows:
io ( z )  G( z )io* ( z )  S ( z )v( z )
(2.8)
where G(z) is transfer function from the reference to the output current, and S(z) is the
sensitivity function; G(z) and S(z) are represented as
21
G( z ) 
io ( z )
io* ( z )

CPI ( z )Gid ( z )
1  CPI ( z )Gid ( z )
(2.9)
and
i ( z)
CPI ( z )Gid ( z )
S ( z)  o
 1
.
v( z )
1  CPI ( z )Gid ( z )
(2.10)
From (2.9) and (2.10), it indicates that a higher CPI(z)Gid(z) makes a smaller tracking
error and disturbance effect.
Fig. 2.7 shows the open-loop Bode plots of the compensated system for the plant
Gid by the conventional controller which is implemented as the PI controller as shown
in Fig. 2.6. To achieve acceptable reference tracking speed and disturbance rejection
performances, the high system gains at the grid frequency and its harmonics are
required. For this requirement, a high gain feedback controller is one of the promising
solutions. However, under circumstance where the controller gain should be limited
by the RHP zero and the LC filter resonance, because it raises the system gains at all
frequencies, the high gain feedback controller would make the system become
unstable. When the integral action is added, it only contributes to the system gain at
the origin as shown in Fig. 2.7b; this does not still contribute to increase the system
gains at the grid frequency and its harmonics. As a result, when the conventional
controller is applied to the proposed converter, there is a trade-off between the control
performance and system stability due to the inherent dynamic characteristics of the
proposed converter.
22
(a)
(b)
Fig. 2.7. Bode plots of the compensated system by the conventional PI controller: the low-gain
feedback controller, kp=0.03 (blue) and high-gain feedback controller, kp=0.5 (red). (a) Only P controller
is used. (b) PI controller with ki=10 is used.
23
Modified PI type controller which is called type-2 PI controller is introduced in
[40], [41]. This controller provides the high DC gain at the origin like the conventional
PI controller while the additional pole term functions a low-pass filter which
eliminates the unwanted high frequency components in the controller input such as
the switching frequency components and noise. The role and design method of the
additional pole term have already mentioned in [40]. Compared to the conventional
PI controller, the type-2 PI controller doesn’t have any additional function besides the
damping in the high frequency region; this means that the type-2 PI controller also
does not help to increase the system gains at the grid-frequency and its harmonics. To
ensure the control performance such as the fast reference tracking and disturbance
rejection like the grid voltage and its harmonics, the high kp gain is needed in both the
conventional PI controller and the type-2 PI controller. However, the type-2 PI
controller also has the limitation on increasing the controller gain by the right-halfplane (RHP) zero. In conclusion, when the conventional PI type controllers are
applied to the system, there is a trade-off between the control performance and system
stability.
24
2.2.2 Proposed Control system with repetitive control scheme
kth
Ctr_input
system
memory1
k -1th
Ctr_input
repetitive
controller
Fig. 2.8.
∑
+
yr
memory2
Concept of a repetitive control.
Fig. 2.8 shows concept of a repetitive control; by conducting the same task
repetitively, it adjusts a control input, and finally seeks an ideal control input with the
zero tracking error. A basic repetitive controller can be represented as
Crc _ bas ( z )  kr
zN
1 zN
(2.11)
where kr is the repetitive controller gain, and N is given as a sampling frequency, fsam
/a fundamental frequency, fo of a target system or object. In the transfer function in
(2.11), it is observed that there is a positive feedback with z-N. From a frequency point
of view, the transfer function in (2.11) has infinity gain at the frequencies lfo with
l=0,1,2,… This property assures zero-error tracking at these frequencies in closed loop.
Thus, the repetitive controller is effective in periodic systems such as the grid-tied
systems.
Considering the property of the repetitive control scheme, to overcome the
constraints and ensure desired reference tracking and disturbance rejection
performances, the control system is developed as shown in Fig. 2.9; this developed
control system consists of the linear feedback controller term Cfb, the repetitive
controller term Crc, and the duty ratio D in (2.4). Cfb is used to fulfill the desired
stability without Crc.
25
Developed Repetitive Controller, Crc
kr
+ +
z-N
Q(z)
v(z)
Ginv
Linear feedback
controller, Cfb
io*(z) +
_
+ +
Cfb
+
Gid(z)
+
+ io(z)
+
Duty ratio D
Fig. 2.9.
Block diagram for the developed control system with repetitive control scheme.
The linear feedback controller term Cfb is described as follows:
C fb ( z )  k p
dampTsam
1  dampTsam  z 1
.
(2.12)
where Tsam is the sampling period(=1/fsam). Cfb is derived by an integration with a
proportional controller and a low pass filter and is used to ensure the stability of the
system. To achieve the phase margin enough, the gain kp is set up to be low. The low
pass filter with the cut-off frequency ωdamp gives the early damping before reaching at
the resonant frequency; this mitigates the negative effect by the resonance of the LC
filter and gives the robustness for the unwanted controlling by the high frequency
control input and noise. Fig. 2.10 shows the bode plots of the compensated system
Cfb(z)Gid(z) by only Cfb(z); the system has a margin > 45°, so that it becomes stable.
In this case, kp and ωdamp in (2.12) are designed as 0.03 and 2π*3000 rad/s, respectively.
As shown in Fig. 2. 10, the desired stability is provided. However, with only Cfb(z),
the high system gains at the grid and harmonics frequencies are not provided. To
eliminate the periodic errors and ensure the control performances, the term Crc is
developed using the repetitive control scheme, and is represented as
26
Fig. 2.10.
Bode plots of the compensated system Gid(z)Cfb(z) by Cfb.
Crc ( z )  kr
z  N Q( z )
Ginv
1  z  N Q( z )
(2.13)
where kr is the repetitive controller gain, and N is given as the sampling frequency fsam
/ the grid frequency fg. As a low-pass filter, Q(z) allows tracking/rejecting periodic
signals within a specific frequency range and prevents from controlling at highfrequency region. Thus, the repetitive controller amplifies the system gains within
only the defined low-frequency region, so that it improves the output current tracking
performance while suppressing the grid disturbance for fundamental and low-order
harmonic frequencies. Q(z) can be digitally implemented as
Q( z ) 
cTsam
1  cTsam  z 1
(2.14)
where ωc of the low-pass filter Q(z) with unity gain. The transfer function Ginv is used
to compensate the phase delay in the digital implementation and is expressed as
follows:
27
Ginv ( z)  z m
(2.15)
where m is the phase-lead index. As the duty ratio D is predetermined according to
operating points, it helps to achieve the fast response and to alleviate the disturbance
effect by v(z) as a kind of feed-forward control inputs.
From Fig. 2.9, the relationship between the error e(z) and the inputs w(z)= io*(z)v(z) can be obtained as follows:
1  Q( z ) z  N [1  Gc ( z )]
e( z )

w( z ) 1  Q( z ) z  N [1  kr z mGc ( z )]
(2.16)
where Gc(z) is Cfb(z)Gid(z)/[1+Cfb(z) Gid(z)]. The transfer function in (2.16) can be
considered as three systems connected in cascade: 1-Q(z)z-N, 1-G(z), and 1-Q(z)z-N[1krzmGc(z)]. The first term 1-Q(z)z-N is a low-pass filter with unity gain and a time delay,
so that it is stable. The second term 1-Gc(z) has the same roots as Gc(z). Finally, the
term 1-Q(z)z-N[1-krzmGc(z)] can be described as a positive-feedback closed-loop
system with the term Q(z)z-N[1-krzmGc(z )] in the feedback path. Accordingly, if the
following sufficient conditions are satisfied as:
1) The closed-loop system Gc(z) without the repetitive controller Crc(z) is stable,
Q( z ) z  N [1  kr z mGc ( z )]
2)  z  N Q( z )[1  kr z mGc ( z )]
 Q( z )[1  kr z mGc ( z )]  H ( z )  1 z=e jTsam , 0< <

Tsam
the overall system in Fig. 2.9 becomes stable. The condition 1) is satisfied by
designing the linear feedback controller Cfb(z) as shown in Fig. 2.10. The condition 2)
28
Fig. 2.11.
Nyquist plots of |H(z)| for kr=0.3 according to the phase-lead index m.
is derived from the small gain theorem [42], [43], and designing kr and m that meets
the inequality is needed. Higher kr yields smaller periodic errors, so that kr is set up to
be high as long as satisfying the desired stability. Once kr is determined, the phaselead index m can be selected for satisfying the condition 2). Fig. 2.11 shows the
Nyquist plots of H(z). For m<15, the locus of the H(z) is the inside of the unity circle.
However, due to model uncertainty and complexity in the digital implementation, it
is difficult to choose the precise value. Thus, m is determined by adjusting in the
experiment. As a result, m is set as 3.
Fig. 2.12 shows the open-loop Bode plots of the compensated system by the
developed control system in Fig. 2.9. It is observed that the repetitive controller Crc(z)
amplifies the system gains at the grid and its low-order harmonics frequency
components within only the range defined by Q(z) although the feedback controller
gain is in the constrains circumstances by the RHP zero and the LC resonance. In
conclusion, the proposed control system in Fig. 2.9 improves the output current
reference tracking and disturbance rejection performances while satisfying the desired
stability.
29
Fig. 2.12.
Bode plots of the compensated system by the low-gain feedback controller is used (blue); by
the developed control system in Fig 2.9 is used (red).
From the Bode plots in Fig. 2.12, it is found that the repetitive controller gives
infinite gain at the certain frequencies; this characteristic looks similar to that of a
proportional resonant (PR) controller [44], [45]. The PR controller is represented as
s
CPR (s)  k p  krs 2
s  2
(2.17)
where krs is the resonant controller’s gain, and ω is the corresponding frequency
regulated by a PR controller. On the other hand, the classic repetitive controller can
be given as
Crc _ bas (s)  kr
eTos
1  eTos
(2.18)
where To is the fundamental period of the target system. Eqn. (2.18) can be expanded
as
30
 1 1
Crc _ bas ( s)  kr   
 2 To

1
2s
2s

 
2
2
 s s2   2
h 2 s  (ho )
o





(2.19)
where ωo is defined as 2π /To. As shown in Eqn. (2.18) and (2.19), the repetitive
controller looks like the combination of the multiple PR controllers; this is the reason
why PR control and repetitive control methods are seen similarly on a Bode plot. Both
the repetitive controller and the resonant action of the PR controller give infinite gain
at the certain frequency; this characteristic looks similar to each other. However, they
have distinct differences in the control method and the implementation aspects. In the
repetitive control scheme, unlike the PR controller using the only current error, the
knowledge obtained from the previous trial is used to adjust the control signal for the
current trial. Then, as the procedure is performed repetitively, the repetitive controller
yields the theoretically ideal control input with the zero tracking error. Moreover, one
repetitive controller like (2.18) compensates the frequency components within a
specific range from Q(z). On the other hand, because a PR controller provides an
infinite gain at only a selected resonant frequency, the parallel use of the several PR
controllers is required to compensate several frequency components such as the grid
and its harmonics frequencies; this fact brings heavy computation burden. Thus, for
compensating the several periodic signals, the repetitive controller is worked better
and implemented more easily compared to a PR controller.
2.3 Design Procedure
Assuming no power losses in the proposed converter, the transferred average power
Pavg and instantaneous power p(t) under the unity power factor condition can be
expressed as
31
Pavg  Vdc I dc 
Vg I g
2
p(t )  Vdci pri,avg (t )  vg (t )ig (t )  vg (t )io (t )  Vg I g sin 2 t
(2.20)
(2.21)
where Vg and Ig are the peak value of the grid voltage and current, respectively; ipri,avg
is the average primary current over a switching period, and ω is the grid angular
frequency. The instantaneous power in (2.21) has the fluctuating component with
twice the grid frequency. To keep the power on the dc source side constantly, the
power decoupling is required, and the dc capacitor Cdc is responsible for an energy
buffer. The fluctuating energy in (2.21) can be represented as
2
2

Vdc  
Vdc  
1


P
cos
2

t
dt

C
V


V

dc  dc
  dc
 
 avg
2
2
2
 
 



(2.22)
where ΔVdc is the ripple of the dc voltage. Thus, to obtain the desired value in ΔVdc,
Cdc should satisfy the following condition as
Cdc 
Pavg
Vdc Vdc
.
(2.23)
The transformer design affects the current and voltage stresses on the devices
thereby deciding the power conversion efficiency. The current stress on the
bidirectional flyback converter is related to both n and magnetizing inductance Lm;
whereas the voltage stresses are related to n (Table 2.3). Because reducing n reduces
the current stress on the primary side and reduces voltage stress on S2, this strategy is
preferred to the application of low voltage source on the primary side and high voltage
source on the secondary side. However, reducing n increases current stress on the
secondary side and increases voltage stress on S1. Thus, selection of n must consider
32
this trade-off between current stresses and voltage stresses. To determine the
appropriate n, the switching losses on the switches can be used because the losses
influence both current stress and voltage stresses. Fig. 2.13 shows the sum of the
switching losses on the switches in the half-cycle according to turns ratio n and
magnetizing inductance Lm. As n approaches 1, the switching losses increase rapidly,
but as n increases the losses converge on a certain value when n ≈ 4. Thus, this analysis
of switching losses indicates that the optimum choice is 4 ≤ n ≤ 5.
Eqns. (2.24) and (2.25) demonstrate that the peak current stress gradually decreases
as Lm increases. Thus, the power conversion efficiency increases as Lm increases.
However, because increasing Lm increases transformer size, the trade-off between the
efficiency and transformer size should be considered.
TABLE 2.3
CURRENT AND VOLTAGE STRESSES ON THE BIDIRECTIONAL FLYBACK
Stresses
Peak current on
primary side
Peak current on
secondary side
Peak voltage stress
on S1
Peak voltage stress
on S2
Value
I pri , pk 
Ig
Vdc
( nVdc  Vg ) 
I sec, pk 
1
2 Lm f s
I pri , pk
n
Vs1, pk  Vdc 
Vg
n
Vs 2, pk  nVdc  Vg
33
Vdc
Vg
nVdc  Vg
(2.24)
(2.25)
(2.26)
(2.27)
Loss
[W]
Lm [x10-5H]
n
Fig. 8.
2.13. Switching
Switching losses
both
switches
in the
of the of
gridthe
according
to turns ratio
and
Fig.
lossesononthe
the
both
switches
in half-cycle
the half-cycle
grid according
to turns
magnetizing
inductance under
the following
Pavg conditions:
=250W, fs=50kHz,
Vg,rms=220V,
and
ratio and magnetizing
inductance
under conditions:
the following
Pavg =200W,
fs=50kHz,
Vdc
=48V.
V
=220V, and Vdc=48V.
g,rms
2.4 Experimental Results
To confirm the validity of the proposed converter and its control system, a 250W
prototype was built and tested under the grid-tied condition. Using four lead-acid
batteries with 12V which are connected in series, the dc voltage source is set, and its
nominal voltage is 48V. The dc capacitor Cdc is determined by (2.23) to make the
voltage ripple percentage be below 5%. The turns ratio n and magnetizing inductance
Lm are designed based on the analysis in Section 2.3. The other parameters and parts
for the experiment are described in Section 2.1.2. The control system was
implemented using Microchip, dsPIC33EP512GM604 under 30kHz sampling
frequency. Besides the main control, the DSP chip is responsible to generating the
gate signals, checking overcurrent and overvoltage, and 12bits A/D conversion. Fig.
2.14 and 2.15 show the overall system configuration and the picture for the prototype,
respectively.
34
Np : Ns
io
Idc
Lm
S3
Cf
Lf
ig
vg
Vdc
T
Cdc
S2
S1
S1
S5
S2
PWM
generator
duty,d
S4
vg Vdc io Idc
S3 S4 S5 S6
Grid
polarity
detection
S6
Over/under
voltage
detection
Over
current
detection
PLL
Current control
system
dsPIC33EP512GM604
Single chip DSP
Fig. 2. 14. Overall system configuration for the prototype.
Fig. 2. 15. 250W prototype of the proposed bidirectional converter.
35
vg [100V/div.]
►
ig [2A/div.]
►
time [4ms/div.]
(a)
vg [100V/div.]
►
ig [2A/div.]
►
time [4ms/div.]
(b)
Fig. 2.16.
Experimental waveforms for the grid voltage vg and grid current ig in discharging mode when
the conventional control system is applied. (a) Low controller gain, kp =0.03. (b) Higher controller gain,
kp=0.5.
36
vg [100V/div.]
►
ig [2A/div.]
►
time [4ms/div.]
(a)
vg [100V/div.]
►
ig [2A/div.]
►
time [4ms/div.]
(b)
Fig. 2.17.
Experimental waveforms for the grid voltage vg and grid current ig when the proposed control
system in Fig. 2.9 is applied. (a) Discharging mode. (b) Charging mode.
37
Fig. 2.16 shows the experimental waveforms for the grid voltage vg and current ig
in the discharging mode when the conventional control system with the PI controller
is applied. As shown in Fig. 2.16a, the grid current cannot track its reference and then
it is distorted. When the controller gain increases to improve the control performance,
it makes the system become unstable. The results in the charging mode is similar to
that of the discharging mode.
Fig. 2.17 shows the experimental waveforms for the grid voltage vg and current ig
when the developed control system in Fig. 2.9 is applied. As shown in Fig. 2.17, the
grid current has the perfectly sinusoidal waveform with desired power level in both
operation modes; it is demonstrated that the proposed converter has bidirectional
power flow control capability, and the developed control system overcomes the
problem caused by the RHP zero and makes the proposed converter have high power
quality. In this case, THD in each mode was measured as 2.4% (discharging mode)
and 2.9% (charging mode). Fig. 2.18 shows the experimental waveforms for the
operation mode transition. From Fig.2.18, it is verified that the mode transition occurs
smoothly in the proposed converter.
Fig. 2.19 shows efficiency comparison according to the power conversion schemes.
The conventional two-stage grid-tided ac-dc converter in Fig. 2.1b consists the
conventional bidirectional flyback dc-dc converter with high dc-link voltage (350V)
and the full-bridge inverter with the high frequency unipolar PWM. As shown in Fig.
2.18, the proposed converter has much higher efficiency in both operation modes
under all load conditions. Thus, it noted that the single-power conversion technique
gives high efficiency characteristic to the proposed converter although they have the
similar circuit configuration. In the proposed converter, the maximum efficiencies in
the discharging mode and the charging mode are measured to be 96.0% and 95.4%.
38
vg [100V/div.]
►
ig [2A/div.]
time [40ms/div.]
Efficiency [%]
Fig. 2.18. Experimental waveforms for vg and ig in the operation mode transient-state.
96
94
92
90
88
86
Discharging mode
84
Charging mode
10
20
30
40
50
60
70
80
90 100
Load [%]
Fig. 2.19. Efficiency comparison according to the power conversion schemes: single-power conversion
scheme (black) and conventional two-stage power conversion scheme (red).
39
Chapter 3
Single-phase Transformerless Bidirectional
Full-bridge Type Inverter for a PV system
integrated with an Energy Storage
Transformerless system configuration is attractive as one of the methods to achieve
overall system performance. Its detail advantages are as follows:
1) High power conversion efficiency
2) Simple circuit structure and low production cost
3) Enhanced power density
4) Light weight
To encourage the merits of the transformerless system configuration, the ground
leakage current issue has to be considered. For safety reasons, various industrial
equipment such as the metal battery rack and the PV panel frame is generally required
to connect to the earth ground so that a parasitic capacitor Cp occurs between the
equipment and the ground. In the transformerless system, due to absence of galvanic
40
Equipment
(PV panel, Battery,
Motor, and etc)
Transformerless
power
converter
CP
Grid
iPE
Ground
Fig. 3.1.
Ground leakage current path.in the transformerless system configuration.
isolation, a current path through the parasitic capacitor appears as shown in Fig. 3.1,
and the current flowing though the path is so called the ground leakage current. If the
ground leakage current is strong, it would cause the degradation of the system
performance, the equipment damage, huge electromagnetic interference (EMI), and
even serious human electric shock incidences. So, to achieve the feasibility of the
transformerless system configuration and to obtain high efficiency, the ground leakage
current should be eliminated or suppressed. Especially, because in a PV system with
the transformerless configuration, the parasitic capacitor is much higher than those of
other applications [46], [47], and the ground leakage current issues appear more
seriously.
In this chapter, a novel high-efficiency single-phase bidirectional full-bridge type
inverter is proposed for a PV system integrated with an energy storage. The proposed
bidirectional inverter is applicable as shown in Fig. 3.2; the PV system and the energy
storage system are connected through the dc-link of the grid-tied converter, and they
share the bidirectional inverter. Thus, the operation of the inverter stage in the gridtied converter would affect the ground leakage current. Of course, the operation of the
dc-dc converter can affect the occurrence of the leakage current in the transformerless
system. However, this chapter focuses on only the inverter stage because the inverter
is essential regardless of a number of stages that forms the grid-tied converter.
41
CP
Bidirectional
dc-dc
converter
Energy
storage
devices
Bidirectional
inverter
High voltage
dc-lilnk
Grid
(a)
MPPT
converter
CP
Bidirectional
dc-dc
converter
Energy
storage
devices
Bidirectional
inverter
High voltage
dc-lilnk
Grid
(b)
Fig. 3.2.
Bidirectional grid-tied converter in a PV system integrated with energy storage. (a) Without
MPPT converter. (b) With MPPT converter.
The proposed bidirectional inverter is developed using the transformerless system
configuration so that it provides high power conversion efficiency, excellent power
density, and low production cost. Using its circuit structure and switching operation,
the proposed inverter suppresses the ground leakage current and gives the feasibility
for the transforemrless system configuration.
42
3.1 Analysis for Conventional Full-Bridge Inverter Topology
S1
+
S3
L1
A
+
Vdc
ig
VAB
Cdc
B
_
L2
+
vg
_
_
S2
S4
N
CP
Fig. 3.3.
vPE
Conventional single-phase full-bridge inverter.
The single-phase full-bridge inverter in Fig. 3.3 is widely used in various industrial
applications. This topology provides high power capability and bidirectional power
flow control with simple circuit structure. The full-bridge inverter can employ two
typical PWM schemes: bipolar PWM and unipolar PWM schemes.
In the bipolar PWM scheme, diagonally opposite switches are operated as switch
pairs. Due to bipolar PWM switching operation, the output voltage vAB has only two
levels: Vdc and -Vdc. As a result, the high current ripple across the inductors L1 and L2
causes high core losses. Moreover, during the freewheeling operation, the reactive
power exchange between the dc-link capacitor Cdc and the inductors occurs, which
causes additional losses. In the unipolar PWM scheme, one leg is operated at the highfrequency, and the other leg is operated at the grid frequency. This scheme allows vAB
to have three levels: Vdc, 0, and -Vdc; this leads to lower core losses than those in the
bipolar full-bridge inverter and eliminate the power losses by the reactive power
exchange during the freewheeling operation.
From the analysis of the full-bridge dc inverter, it is obvious that the full-bridge ac43
dc inverter with unipolar PWM scheme has higher efficiency than that with the bipolar
PWM scheme. Despite of high efficiency characteristic, the conventional unipolar
full-bridge inverter is not suitable for the transformerless systems with PV energy
system due to its higher ground leakage current [48], [49]; the detailed analysis is
represented in the following section 3.1.1.
3.1.1 Ground Leakage Current Analysis of Full-Bridge Inverter
There is a parasitic capacitance Cp between the negative terminal of the dc-bus N
and the ground as shown in Fig. 3.3. Because the magnitude of the ground leakage
current iPE is determined by the rate of change, dvPE/dt where vPE is the voltage across
the parasitic capacitor Cp, the high-frequency component in vPE brings about the
enormous ground leakage current. In the full-bridge inverter, vAN and vBN are highfrequency voltage sources that represent the midpoint voltage of each leg relative to
N. Thus, the analysis for the high-frequency model would help to understand the
leakage current in the topology.
The high-frequency equivalent circuit of the bipolar PWM scheme can be derived
using vAN and vBN regardless of the polarity of the grid voltage as shown Fig. 3.4 (a).
Since the grid frequency is very lower than the switching frequency, the influence of
the grid voltage on the high-frequency equivalent circuit can be negligible. Then, the
magnitude of the high-frequency voltage in vPE can be expressed using superposition
principle and Thévenin theorem. At first, when vBN turns off, the magnitude of the
high-frequency voltage vPE1 in the parasitic capacitor can be obtained as follows:
44
A
L1
B
L2
vAN
N
Cp
+v
PE
_
vBN
(a) High-frequency equivalent circuit.
Ls=L1//L2
v AN
2
vBN
2
+
Cp
vPE
_
(b) High-frequency model.
(c) Simulation results.
Fig. 3.4.
High-frequency model of the full-bridge inverter with the bipolar PWM scheme.
45
vPE1 
1
js C p
js Ls 
1
js C p
v AN
2
(3.1)
where ωs is the switching angular frequency. Secondly, when vAN turns off, vPE2 can
be obtained as follows:
vPE 2 
1
js C p
js Ls 
1
js C p
vBN
.
2
(3.2)
Using the superposition principle for the circuit in Fig. 3.4 (a), the final high frequency
model for the bipolar full-bridge inverter is derived as shown in Fig. 3.4 (b), and vPE
can be calculated as
vPE  vPE1  vPE 2 

1
1  s2 Ls C p
1
js C p
 v AN vBN 

1  2
2 
js Ls 
js C p
(3.3)
 v AN vBN 
 2  2 .


In the bipolar PWM scheme, the sum of the high-frequency voltage sources vAN /2 and
vBN /2 is the half of the dc-link voltage, Vdc/2. Since there are no high-frequency
components in vPE, the leakage current is very low. From the simulation results as
shown in Fig. 3.4 (c), it verified that vPE is almost constant, and the ground leakage
current flowing thorough Cp is very low.
In the same manner, the high-frequency equivalent circuit in the unipolar PWM
scheme can be derived as shown in Fig. 3.5 (a). Because the high frequency operation
46
leg according to the polarity of the grid voltage, two high-frequency equivalent circuit
exist in the unipolar PWM scheme. In order to find the high-frequency model easily,
let the grid voltage function g be defined as follow:
1, vg  0
g
0, vg  0.
(3.4)
Then, the magnitude of the high-frequency voltage VPE_HI in the parasitic capacitor
can be expressed as follows:
vPE 

1
js C p
v 
 v AN
g
 (1  g ) BN 
1 
2
2 
js Ls 
js C p
1
1  s2 Ls C p
vBN
 v AN
 g 2  (1  g ) 2

(3.5)

.

Then,

1

2
1  s Ls C p
vPE  
1

1   2 L C
s s p

 v AN
 2


 , for g  1

 vBN
 2


 , for g  0.

(3.6)
From (3.6), it is observed that the high frequency components is injected into vPE,
which causes a strong leakage current flows through the parasitic capacitor Cp. The
simulation results in Fig. 3.5 (c) verify the poor leakage current characteristic of the
unipolar full-bridge inverter.
In conclusion, the unipolar full-bridge inverter is not suitable for application to the
transformerless systems due to the strong leakage current although it can give the high
power conversion efficiency with the transformerless structure.
47
L1
A
A
L1
B
L2
vAN
L2
N
Cp
N
+v
PE
_
vBN
+v
PE
_
Cp
Negative half-cycle
Positive half-cycle
(a) High-frequency equivalent circuit
Ls=L1//L2
g
v AN
2
(1  g )
vBN
2
+
Cp
vPE
_
(b) High-frequency model
(c) Simulation results
Fig. 3.5.
High-frequency model of the full-bridge inverter with the unipolar PWM scheme.
48
3.2
Proposed Single-phase Transformerless Bidirectional
Full-bridge Type Inverter
3.2.1 Description and Operation Principle
S1
+
S3
L1
A
+
Vdc
ig
VAB
Cdc
B
_
+
vg
_
L2
_
S2
S4
S5
S6
N
Cp
vPE
Fig. 3.6. Proposed single-phase transformerless bidirectional full-bridge type inverter.
Fig. 3.6 shows the proposed single-phase bidirectional inverter, which consists of a
full-bridge circuit representing switches S1~S4 with additional switches S5 and S6. The
proposed inverter employs transformerless structure, which eliminates power losses
due to the transformer. Due to similar principle of the conventional unipolar fullbridge inverter, the proposed inverter leads to low core losses and prevents the reactive
power exchange. Thus, this topology in Fig. 3. 6 can achieve high efficiency by using
a transformerless structure and by minimizing losses. Moreover, the injection of the
high frequency component into the parasitic capacitor Cp is blocked due to the
operation of the additional switches S5 and S6.
The switching operation depends on the polarity of vg. In the positive half-cycle, S6
is turned on, and S5 is turned off. S1 and S2 are operated complementarily at high
49
switching frequency with sinusoidal PWM. In the negative half-cycle, S5 is turned on,
and S6 is turned off. S3 and S4 are driven complementarily at high switching frequency.
On the basis of the aforementioned switching operation, the proposed inverter
operates as a grid-tied inverter or a PWM rectifier. Fig. 3.7 and Fig. 3.8 show the suboperation modes in the grid-tied inverter mode and the PWM rectifier, respectively.
Assume that the dc-link voltage Vdc is constant with higher value than the peak value
of the grid voltage. In the grid-tied inverter mode, the operation principle is similar to
that of a buck converter. In the positive half-cycle, the inductor L1 is magnetized, and
ig flowing through L1 increases when S1 is turned on. At the same time, the power is
transferred to the grid side through the path shown in Fig. 3.7(a), and the voltage
equation is obtained as
Vdc  vg  L1
dig
dt
 0.
(3.7)
When S1 is turned off and S2 is turned on, ig decreases, and a freewheeling path is
provided as shown in Fig. 3.7(b). In this case, the voltage equation is expressed as
vg  L1
dig
dt
 0.
(3.8)
In the PWM rectifier mode, the proposed inverter operates as a boost converter with
PFC function. In the positive half-cycle, the energy from the grid is stored in L1 when
S2 is turned on. In this case, ig flowing through L1 increases in the opposite direction
of ig in the inverter mode, and the voltage equation is obtained as
vg  L1
dig
dt
 0.
50
(3.9)
+
S1
+
S3
S1
S3
L1
L1
+
Vdc
Cdc
L2
vg
Cdc
_
L2
S2
S4
S5
S6
S2
CP
vPE
S4
S1
S1
+
S3
S6
S3
L1
+
Vdc
Cdc
S5
(b)
L1
L2
vg
+
Vdc
Cdc
_
_
L2
vg
_
_
S2
CP
_
vPE
(a)
+
vg
_
_
CP
+
Vdc
S4
S5
S6
S2
CP
vPE
S4
S5
S6
vPE
(c)
(d)
Fig. 3.7. Sub-operating modes in the grid-tied inverter mode of the proposed inverter according to
switching states. (a) S1 on and S6 on. (b) S2 on and S6 on. (c) S3 on and S5 on. (d) S4 on and S5
on.
When S2 is turned off and S1 is turned on, the energy stored in L1 with the grid energy
is transferred to dc sources through the path shown in Fig. 3.7(a). Hence, the voltage
equation is obtained as
Vdc  vg  L1
dig
dt
 0.
(3.10)
The operation principle of each mode in the negative half-cycle is similar to that of
each mode in the positive half-cycle.
51
+
S1
+
S3
S1
S3
L1
L1
+
Vdc
Cdc
L2
vg
Cdc
_
L2
S2
S4
S5
S6
S2
CP
vPE
S4
S1
+
S3
Vdc
L2
vg
S1
S3
+
Vdc
Cdc
_
_
L2
vg
_
_
S2
S4
S5
S6
S2
CP
vPE
S4
S5
S6
vPE
(c)
Fig. 3.8.
S6
L1
+
Cdc
S5
(b)
L1
CP
_
vPE
(a)
+
vg
_
_
CP
+
Vdc
(d)
Sub-operating modes in the PWM rectifier mode of the proposed inverter according to
switching states. (a) S1 on and S6 on. (b) S2 on and S6 on. (c) S3 on and S5 on. (d) S4 on and S5
on.
3.2.2 Ground Leakage Current Analysis
vAN and vBN are considered as high-frequency voltage sources in the positive halfcycle and the negative half-cycle, respectively. The high-frequency equivalent circuit
of the proposed inverter can be derived according to the polarity of the grid voltage
as shown in Fig. 3.9. In the positive half-cycle, S6 is always turned on, and the negative
terminal N of the dc-bus is connected to the ground through S6; this means that vPE =
0 regardless of the high frequency switching operation. In the negative half-cycle, S5
is always turned on, and Cp is connected to the grid in parallel through S5. Therefore,
52
A
L1
B
L2
vAN
N
Cp
N
+
v
_ PE
Cp
A
L1
B
L2
vBN
+
v
_ PE
Negative half-cycle
Positive half-cycle
(a) High-frequency equivalent circuit
(b) Simulation results
Fig. 3.9.
High-frequency model of the proposed inverter.
the proposed inverter can block injection of high frequency components into the
parasitic capacitance and suppress the leakage current to be very low. Simulation
results in Fig. 3.9 (c) show that the high-frequency voltage in vPE is almost zero and
the low leakage current in Cp flows.
53
3.2.3 Bidirectional Power Control Algorithm
The proposed inverter performs bidirectional power control to balance power
between the grid and dc source. If a power difference occurs, Vdc varies; this means
that Vdc can be regulated by controlling the transferred power that is reflected in ig. To
regulate Vdc, a PI type controller is used. The output of the voltage controller is a grid
current command Ig*, and its equations is obtained as
I *g  kvp (Vdc  Vdc _ ref )  kvi  (Vdc  Vdc _ ref )dt
(3.11)
where kpv and kiv are the proportional and integral gains, respectively. Vdc_ref is the
reference of the dc-bus voltage. In this case, kvp is tuned as small as possible to have
less influence on the current control loop, and kvi is designed to have large time
constant.
As Ig* is the peak value of the grid current reference ig_ref, it represents the flow
direction and the transferred power level. Using Ig*, the proposed inverter controls the
grid current to obtain sinusoidal waveform and low total harmonic distortion (THD).
From (3.8) and (3.9), the average inductor voltage over a switching period Ts in the
positive half-cycle of the grid-tied inverter mode is given with the following the grid
current variation ∆ig as
L
(Vdc  vg )d1,inv  vg (1  d1,inv )  1 ig , vg  0
Ts
(3.13)
where d1,inv is the duty ratio of S1 in the inverter mode. The duty ratio d1,inv can be
derived as
54
d1,inv 
vg
L1

i , vg  0.
Vdc VdcTs g
(3.14)
In the PWM rectifier mode, considering (3.9) and (3.10), the average inductor voltage
over a switching period Ts in the positive half-cycle is obtained as
L
(Vdc  vg )d1,rec  vg (1  d1,rec )  1 ig , vg  0
Ts
(3.15)
where d1,rec is the duty ratio of S1 in the PWM rectifier mode. d1,rec can be derived as
d1,rec 
vg
L
 1 i , vg  0.
Vdc VdcTs g
(3.16)
Considering that the direction of ig in the inverter mode is opposite to that in the PWM
rectifier mode, the duty ratios d1,inv and d1,rec can be expressed as
d1 
vg
L1

 ig , v g  0
Vdc VdcTs
(3.17)
where d1 is the duty ratio of S1 in the positive half-cycle of both operation modes. In
the same manner, the duty ratio d3 of S3 in the negative half-cycle can be derived as
d3  
vg
L2

 ig , vg  0.
Vdc VdcTs
(3.18)
Assume that inductors L1 and L2 are equal to L, and the duty ratios d1 and d3 can be
considered to be d in each half cycle of vg. From (3. 17) and (3.18), the duty ratio d
can be calculated as follows:
55
Vdc_ref
+
∑
Vdc
Voltage
controller
ig_ref
I g*
X
+
∑
sin t
vg
PLL
Current
controller
dc
+
∑
abs
+
+
d
D
ig
vg
Vdc
Carrier signal
d
vg
+
S1
S2
S3
S4
S5
S6
Fig. 3.10.
Control block diagram of the proposed inverter.
d  D  d 
vg
L

i .
Vdc VdcTs g
(3.19)
The duty ratio d in (3.19) has two components. The first term is the nominal duty D,
and the second term is the control duty term ∆d. The nominal duty D is not a feedback term but a feed-forward term. D is responsible for making the first-order linear
relationship between ∆d and ∆ig and for alleviating the voltage disturbance. Thus, D
can reduce the burden of the feed-back controller and improve control environment.
As ∆d is the output of the feed-back controller, it is used to make the grid current ig
track its reference ig_ref and is implemented as follows:
d  k pc (ig _ ref  ig )  kic  (ig _ ref  ig )dt
(3.20)
where kpc and kic are the proportional and integral gains, respectively. Fig. 3.10 shows
the control block diagram of the proposed inverter.
3.2.4 Design Guideline
The dc-link capacitor Cdc functions as a buffer the power differences between the
56
grid and dc-source. Assume that the proposed inverter achieves unity power factor.
Then, the instantaneous power pg(t) on the grid side can be expressed as
pg (t )  Pg  Pg cos(2g t )
(3.21)
where Pg is the average power of pg. Assuming that the power Pdc on the dc side is
constant, and Pdc is equal to the average power Pg, the energy stored in the dc-link
capacitor Cdc can be calculated as

 Pdc  pg (t ) dt  2 Cdc (Vd 
1
Vd 2
Vd 2 
)  (Vd 
) 
2
2

(3.22)
where ∆Vdc is the ripple of the dc-link voltage. Thus, to obtain the desired value in
ΔVdc, Cdc should satisfy the following condition
Cdc 
Pg
gVd Vd
.
(3.23)
Inductors L1 and L2 perform as filter inductors in the grid-tied inverter mode and as
boost inductors in the PWM rectifier mode. For both operation modes, the inductance
of L1 and L2 can be decided considering the current ripple ∆ig when ig is its maximum
value. In this case, the duty ratio d of S1 and S3 is expressed as
Dmax 
Vg
.
Vd
(3.24)
Thus, to ensure ∆ig under certain desired value, the inductance L of L1 and L2 should
satisfy as follows
57
L
Vdc  vg
V (1  Dmax )
Dmax  dc
Dmax
ig f s
ig f s
(3.25)
where fs is the switching frequency.
3.3 Experimental Results
To verify the theoretical analysis and evaluate the validity of the proposed inverter,
a 3kW prototype was built and tested. The prototype was implemented in software
using Microchip dsPIC30F6015 and the analog control method. If the gate driver
circuits for S5 and S6 is implemented, it causes some constraints such as the digital
system delay and digital PLL error. Thus, in the digital implementation, a large deadtime between the gate signals for S5 and S6 is required to avoid grid short circuit; it
increases THD on the grid current and gives the negative effect on the power quality.
To overcome the drawback of the digital implementation for the grid-frequency
switches, the analog control method is employed. Fig. 3.11 shows the gate driver
circuit for S5 and S6; the circuit detects the polarity of the grid voltage and transfers
directly the gate signals to S5 and S6.
VDD
Comparator
(LM393)
+
vg
vgs_6
VDD
Comparator
(LM393)
+
RPull-up
vgs_5
-
Fig. 3.11.
RPull-up
+
Analog circuit implementation of the gate drivers for S5 and S6.
58
TABLE 3.1
DESIGN PARAMETERS AND COMPONENTS OF THE PROTOTYPE
Parameters
Symbols
Value
Nominal battery voltage
Vbat
144V
Nominal dc-link voltage
Vdc
360V
Grid voltage
vg
220Vrms
Grid frequency
fg
60Hz
Average power
Pg
3kW
Switching frequency
fs
16kHz
Filter inductors
L1, L2
2mH
dc-link capacitor
Cdc
2200μF
Parasitic capacitor
Cp
0.3μF
Switches (MOSFETs)
S1-S6
FCA75N60N
Table 3.1 shows the major experimental parameters. The capacitance of Cdc is
calculated by (3.23) to ensure that ∆Vdc is less than 3% of the nominal dc-bus voltage.
From (3.25), the inductance of L is decided to ensure that ∆ig is less than 10% of the
maximum value of ig at 3kW. Because the proposed inverter is possible for applying
to various applications, it should suppress the leakage current even in the worst case.
In this experiment, considering the system integrated with a PV system, the parasitic
capacitance Cp is set up to be 0.1 µF/kW because a system with the crystalline silicon
PV module has the relatively higher parasitic capacitance compared to other systems.
MOSFET,
FCA76N60N
S1 S2 S3 S4
+
S1
S3
OV/OC
Protection
L1
+
vg
_
Vdc
Cdc
L2
vg
+
S2
S4
S5
PLL
ig
LM393
_
PWM generator
Vdc
S6
Vdc_ref
Voltage
controller
Current
controller
dsPIC30F6015
Cp
Film capacitor
0.3μF
Fig. 3.12.
Overall system diagram for the prototype of the proposed single-phase bidirectional inverter.
59
Fig. 3. 12 shows the overall system diagram of the prototype.
Fig. 3.13 shows experimental waveforms of the grid voltage vg and the grid current
ig in the proposed inverter. In the grid-tied inverter mode shown in Fig. 3.13(a), ig was
sinusoidal and in phase with vg. In this case, THD of ig was measured as 2.9%. In the
PWM rectifier mode shown in Fig. 3.13(b), ig was sinusoidal where THD was
measured as 3% and 180° out of phase with vg; this means that the power flow
direction is opposite in the grid-tied inverter mode. Thus, the results indicate that the
proposed inverter can perform bidirectional power flow control between the grid and
dc source.
Experiments were performed to evaluate the leakage current characteristic of the
conventional full-bridge inverter and the proposed inverter. Fig. 3.14 shows the
voltage across the parasitic capacitor vPE and the leakage current iPE in the grid-tied
inverter mode according to topologies. In the bipolar full-bridge inverter shown in Fig.
3.14(a), vPE had a grid frequency, and ip was quite low with the measured rms value
of 84 mA. In the unipolar full-bridge inverter, vPE rapidly changed with high frequency
components, and a strong leakage current occurred shown in Fig. 3.14(b). In this case,
the measured rms value of iPE was 2.6 A. In the proposed inverter shown in Fig. 3.14(c),
vPE remained constant during the positive half-cycle and was equal to vg during the
negative half-cycle. Because vPE did not have high frequency components, and dvp/dt
was low. Thus, iPE was suppressed with the measured rms value of 30 mA. The
experimental result of each topology in the PWM rectifier mode was similar to that of
the grid-tied inverter mode.
Figs. 3.15 shows the efficiency comparison according to topologies. The bipolar
full-bridge inverter had the lowest efficiency in both the operation modes. Although
the efficiency characteristics of the unipolar full-bridge inverter and the proposed
60
inverter were similar in the theoretical analysis, the proposed inverter had higher
efficiency than the unipolar inverter in practice because the unipolar full-bridge
inverter had additional power losses due to the strong leakage current. In the grid-tied
inverter mode of the proposed inverter, the maximum efficiency was 99% in the gridtied inverter mode and 98.8% in the PWM rectifier mode, respectively.
61
vg [250V/div.]
ig [20A/div.]
time [4ms/div.]
(a)
vg
vg [250V/div.]
ig
ig [20A/div.]
time [4ms/div.]
(b)
Fig. 3.13.
Waveforms for the grid voltage vg and the grid current ig in the proposed inverter. (a) Grid-
tied inverter mode. (b) PWM rectifier mode.
62
vPE [100V/div.]
iPE [1A/div.]
time [4ms/div.]
(a)
vp [100V/div.]
ip [5A/div.]
time [4ms/div.]
(b)
63
vp [100V/div.]
ip [1A/div.]
time [4ms/div.]
(c)
Fig. 3.14.
Comparison for the ground leakage current characteristic (a) Full-bridge inverter with the
bipolar PWM scheme. (b) Full-bridge inverter with the unipolar PWM scheme. (c) Proposed inverter.
A summary of experimental results at 3 kW is presented in Table 3.2.
TABLE 3.2
SUMMARY OF EXPERIMENTAL RESULTS
Inverter mode
Topologies
Efficiency
Leakage
current
PWM rectifier mode
Efficiency
Leakage
current
Bipolar full-bridge inverter
96.3%
84mA
96.2%
81mA
Unipolar full-bridge inverter
98.0%
2.6A
98.0%
2.4A
Proposed inverter
98.8%
30mA
98.7%
28mA
64
Efficiency [%]
99
98
97
96
95
Proposed converter
Unipolar converter
Bipolar converter
94
93
10
20
30
40
50
60
70
80
90 100
Load [%]
Efficiency [%]
(a)
99
98
97
96
95
Proposed converter
Unipolar converter
94
Bipolar converter
93
10
20
30
40
50
60
70
80
90 100
Load [%]
(b)
Fig. 3.15.
Efficiency comparison according to the inverter topologies. (a) Grid-tied inverter mode. (b)
PWM rectifier mode.
65
Chapter 4
High Efficiency Three-phase Transformerless
Bidirectional Grid-tied Converter with
High Power Density
Three-phase bidirectional grid-tied converters are generally used in high power
applications (>5kW). Conventional three-phase grid-tied converter topologies have
been developed based on the two-level configuration [52]-[56]. However, as the
requirement for the rated power capacity increases, increases in the passive
component size and the rating of the semiconductor devices are inevitable in the
conventional two-level grid-tied converters.
To mitigate these drawbacks and improve the power density, some studies have
introduced high power converters with high power density obtained with the softswitching technique [57]-[60]; these converters enable to the increase of the switching
frequency by eliminating switching losses and decreasing their passive component
size. However, the converters require complex circuits for the soft-switching circuit
configuration and semiconductor devices with higher voltage and higher current
66
ratings. Furthermore, considering high power capability, insulated gate bipolar
transistors (IGBTs) are preferable to MOSFETs in high power applications; IGBTs
have a lower frequency switching mechanism compared to that of MOSFETs. Thus,
the soft-switching technique is not effective as the method for improving the power
density in the high power applications that require simple circuit structure and
semiconductor devices with a high power rating.
A multilevel converter technique is considered as another solution to improve
power density; this enables to increase the effective frequency applying to the passive
components in the power converters, thus, improves the power density. In addition,
the multilevel technique allows the lower voltage stress on devices compared to the
conventional two-stage converters; this characteristic provides the reduction of the
switching losses without any soft-switching technique and facilitates the use of the
lower cost components. Among the various multilevel converters, the three-level
converters are commonly used. In the dc-dc stage of three-phase three-level grid-tied
converters, the three-level bidirectional converter as shown in Fig. 4.1 (a) has been
employed [61], [62], and this can be flexibly modified to multiphase type converters
as introduced in [63], [64]. In the three-phase inverter stage, neutral point clamped
(NPC) three-level inverter in [65]-[69] as shown in Fig. 4.1 (b) and T-type three-level
inverter [70]-[74] as shown in Fig 4.1 (c) are widely used. Compared to two-level
inverters, the T-type inverter reduces switching loss and switching noise. Moreover,
the T-type inverter has lower conduction loss compared to that of the NPC inverter.
Thus, the T-type inverter has the highest efficiency among the T-type, NPC and twolevel inverters in the medium switching frequency range [72], [75].
67
L1
S1
iL1
Cdc1
Vdc1
S2
N
C1
S4
Cdc2
Vdc2
S3
(a)
Cdc1
S1A
S1B
S1C
S2A
S2B
S2C
N
Cdc2
S3A
S3B
S3C
S4A
S4B
S4C
(b)
68
iA
LA
iB
LB
iC
LC
R
S
T
Cdc1
S1C
S1B
S1A
iA
LA
iB
LB
iC
LC
R
A
S4A
S2A
N
S4B
C
Cdc2
S4C
S
B
S2B
S2C
S3B
S3A
T
S3C
(c)
Fig. 4.1. Three-level converter/inverter topologies. (a) Three-level dc-dc converter. (b) Three-phase
three-level NPC inverter. (c) Three-phase three-level T-type inverter.
A transformerless system configuration can be applied for the three-phase
bidirectional grid-tied converter system; while this provides many advantages as
mentioned in Chapter 3, such a configuration also suffers from the ground leakage
current problem. However, the conventional three-phase three-level grid-tied
converters also suffer from the ground leakage current problem.
In a low voltage system, the utility grid is generally composed of delta connections
to remove the zero sequence [76]. For ungrounded delta connection systems, one of
the grounding methods is to connect the one-phase corner of the delta winding to the
earth ground; this method is the so called corner ground.
This chapter proposes a novel high efficiency three-phase bidirectional grid-tied
converter with high power density for high power applications. The proposed
converter is composed of a three-level dc-dc converter and a modified three-phase Ttype three-level inverter as shown in Fig. 4.2. Compared to the two-level grid-tied
converter, the three-level converter circuit structure contributes to achieve higher
69
power density and efficiency by decreasing the passive components size and
decreasing switching losses. Beside three-level converter circuit structure, it is
noticeable that S-phase of the grid is connected to the ground; this structure enables
not only the use of the active and passive components but also the elimination of the
leakage current. Thus, due to its novel circuit structure, the proposed converter can
achieve high efficiency and high power density compared to other conventional high
power grid-tied converters.
Section 4.1 describes the operation and control algorithm of the dc-dc converter
stage. In section 4.2, the modified three-phase T-type three-level inverter is analyzed.
Then, section 4.3 describes the verification of the tranformerless configuration of the
proposed converter. Finally, its theoretical analysis and validity are confirmed based
on the experimental results on a 10kW prototype.
70
71
Vbat
L2
L1
iL2
S3
v2 S4
v1 S2
S1
iL1
Cdc2
n
Cdc1
S4C
S4A
S2C
S3A
S2A
A
S3C
S1C
C
Modifired three-phase inverter
Vdc2
Vdc1
S1A
iC
iA
LC
LA
Fig. 4.2. Circuit diagram for the proposed three-phase three-level transformerless bidirectional grid-tied converter.
Three-level dc-dc converter
C2
C1
ibat
T
S
R
4.1 Analysis of Three-level DC-DC Converter
4.1.1 Operation Principle
The switching operation of the three-level dc-dc converter is classified into
different operation modes. In the charging mode, switches S1 and S3 operate at the
high frequency, and switches S2 and S4 operate as the freewheeling diodes. The carrier
signals for S1 and S3 are generated with a 180° phase difference; this means that the
converters are driven in the interleaved manner. In the discharging mode, the converter
plays a role of the a three-level step-up converter; S2 and S4 operate as the boost
switches in the interleaved manner while S1 and S3 remain to be turned off.
To simplify the analysis of the converter, voltages Vdc1 and Vdc2 are assumed to be
half of the dc-link voltage Vdc, and inductors L1 and L2 can be assumed to have the
same value L. Figs. 4.3 and 4.4 show the theoretical waveforms and the equivalent
circuits according to sub-operating stages when the converter operates in the
discharging mode. Let ddchg be the duty ratio of the switches S2 and S4. Fig. 4.3(a)
shows the waveforms when ddchg <0.5. Prior to t0, both S2 and S4 are turned off.
Stage 1[t0-t1]: Stage 1 starts when S2 is turned on at t0. The energy from the battery
is stored in L1. The current iL1 flowing through L1 increases as follows:
iL1 (t )  iL1 (t0 )+
Vbat
(t  t0 ).
2 L1
(4.1)
On the other hand, the current iL2 flowing through L2 decreases as
iL 2 (t )  iL 2 (t0 ) 
Vdc  Vbat
(t  t0 ).
2 L2
72
(4.2)
Stage 2[t1-t2]: In the beginning of stage 2, S2 is turned off and the energy stored in
L1 and L2 is then transferred to the grid. In this stage, both iL1 and iL2 decrease with the
same slope given in (4.2). The converter can be in this stage only if the duty ratio ddchg
is less than 0.5.
Stage 3[t1-t2]: In this interval, S4 is turned on, and the energy from the battery is
stored in L2. Thus, iL2 increases as
iL 2 (t )  iL 2 (t2 )+
Vbat
(t  t2 ).
2 L2
(4.3)
In this stage, iL1 still decreases with the same slope as in stage 2.
Stage 4 is enacted only if the duty ratio ddchg is greater than 0.5. In the stage, because
the positive voltages are applied to both L1 and L2, the inductor currents
simultaneously increase with the slope Vbat/L.
In the charging mode, the switches S1 and S3 are driven with the duty ratio dchg. This
mode has four sub-operating stages according to the switching state of the switches
S1 and S3, and the current flow is represented in Fig. 4.5. In stage 1, S1 is turned on,
and S3 is turned off. In stage 2, both switches are turned off, and this stage is present
only if dchg is less than 0.5. Stage 3 occurs when the S1 is turned on, and S3 is turned
off. If both switches are turned on, the converter is in stage 4; this stage appears when
dchg is greater than 0.5.
73
S2
S4
on
off
off
on
iL1
iL2
iBat
t0
Stage
t1
1
t2
2
t3
3
t4
2
ddchgTs
(a) ddchg<0.5
off
S2
on
off
S4
on
iL1
iL2
iBat
t0
stage
t1
4
t2
t3
1
4
t4
3
ddchgTs
(b) ddchg>0.5
Fig. 4.3. Theoretical waveforms in the discharging mode of the three-level dc-dc converter.
74
ibat
L1
S1
iL1
ibat
Cdc1
Cdc1
N
C2
L2
S4
iL2
N
Vbat
C2
Cdc2
L2
Vdc2
S3
L1
S1
iL1
ibat
Vdc1
S2
L2
S4
iL2
L1
Vdc2
Cdc1
Vdc1
N
Vbat
C2
L2
Cdc2
S1
iL1
S2
C1
N
C2
Cdc2
(b) Stage 2
Cdc1
C1
S4
iL2
S3
(a) Stage 1
ibat
Vdc1
S2
C1
Vbat
S1
iL1
Vdc1
S2
C1
L1
Vdc2
S4
iL2
S3
S3
(c) Stage 3
(d) Stage 4
Fig. 4.4. Equivalent circuits according to sub-operating stage in the discharging mode.
75
Cdc2
Vdc2
ibat
L1
S1
iL1
ibat
Cdc1
Cdc1
C2
L2
S4
iL2
n
Vbat
C2
Cdc2
L2
Vdc2
S3
L1
S1
iL1
ibat
Vdc1
S2
C2
L2
S4
iL2
L1
Vdc2
Cdc1
Vdc1
n
Vbat
C2
Cdc2
S1
iL1
S2
C1
n
Vbat
Cdc2
(b) Stage 2
Cdc1
C1
S4
iL2
S3
(a) Stage 1
ibat
Vdc1
S2
C1
n
Vbat
S1
iL1
Vdc1
S2
C1
L1
L2
Vdc2
S3
S4
iL2
S3
(c) Stage 3
(d) Stage 4
Fig. 4.5. Equivalent circuits according to sub-operating stage in the charging mode.
76
Cdc2
Vdc2
The switching functions sw1 and sw2 are determined by the switching operation of
the three-level dc-dc converter and are defined as follows:

1, for S1 on or S2 off
sw1 (t )  

0, for S1 off or S2 on
(4.4)

1, for S3 on or S4 off
sw2 (t )  

0, for S3 off or S4 on.
(4.5)
and
Using (4.4) and (4.5), the voltage v1 and v2 are obtained as
v1 (t ) 
Vdc
sw1 (t )
2
(4.6)
v2 (t) 
Vdc
sw2 (t ).
2
(4.7)
and
Then, from (4.6) and (4.7), the following equations can be derived as
L1
L2
diL1
 vc1  v1
dt
(4.8)
diL 2
 vc 2  v2 .
dt
(4.9)
where vc1 and vc2 are the capacitor voltages for C1 and C2, respectively. In the
discharging mode, the average voltage V1 for v1 over one switching period Ts can be
calculated by
V1 
1
Ts

Ts
0
v1 (t )dt 
1
Ts

Ts
0
Vdc
V
sw1 (t )dt  dc (1  d dchg ).
2
2
77
(4.10)
Since both S2 and S4 have the same duty ratio ddchg, the average voltage V2 for v2 is
also the same value in (4.10). Using (4.8)-(4.10), the average capacitor voltages VC1
and VC2 for the battery side capacitors C1 and C2 are derived as
VC1  VC 2 
Vdc
(1  d dchg ).
2
(4.11)
Because the sum of VC1 and VC2 is Vbat, the average capacitor voltages across the
battery side capacitors in (4.11) are re-expressed as
VC1  VC 2 
Vbat
.
2
(4.12)
From (4.11) and (4.12), the value Ddchg of ddchg in the steady-state is derived as
Ddchg  1 
Vbat
.
Vdc
(4.13)
In the charging mode, the average capacitor voltages VC1 and VC2 can be derived as
VC1  VC 2 
Vdc
d chg .
2
(4.14)
From (4.14), it is observed that VC1 and VC2 in the charging mode are also half of the
battery voltage. Thus, the value Dchg of dchg in steady-state can be obtained as follows:
Dchg 
Vbat
.
Vdc
The battery current ibat is derived as follows:
78
(4.15)
dvc1
dt
(4.16)
dvc 2
d (Vbat  vc1 )
dv
 iL 2  C2
 iL 2  C2 c1 .
dt
dt
dt
(4.17)
ibat  iL1  C1
ibat  iL 2  C2
Assuming that C1=C2, the battery current ibat is obtained from (4.16) and (4.17) as
ibat 
iL1  iL 2
.
2
(4.18)
4.1.2 Control Scheme of the Three-level dc-dc Converter
In the charging mode, both the constant current (CC) and constant voltage (CV)
modes are used to achieve fast and stable charging operation, as shown in Fig. 4.6
[77]. Using this approach, the converter maintains the battery current constant at its
reference value Ibat* in the CC mode. Then, once the battery voltage Vbat reaches the
battery voltage reference Vbat*, the charging operation mode is changed into the CV
mode. Assuming that L1=L2=L, the battery current ibat can be expressed using the
inductor currents iL1 and iL2. Because the converter operates in the symmetrical
interleaving manner, average values of both iL1 and iL2 are the same as the battery
current ibat. Thus, the battery current can be regulated by controlling the inductor
current. For easy analysis, let iL1 or iL2 be defined as iL. Depending on the duty ratio
dchg of the charging mode, the average voltage equation over one switching period for
the inductor L is given by
L
iL
Ts
V
 Vbat Vdc 
  dchg  bat (1  dchg )
2
 2 2

79
(4.19)
Vbat*
Vbat
ibat*
ibat
CC Mode
Fig. 4.6.
CV mode
t
Battery charging approach with CC and CV modes.
where ∆iL is the inductor current variation. Hence, the duty ratio dchg is given by
dchg 
Vbat 2 L iL

 Dchg  dc ,chg
Vdc
VdcTs
(4.20)
and is composed of the nominal duty ratio Dchg, and the controlled duty ratio dc,chg. To
force the inductor current to track its current command Ibat, a PI-type current controller
is utilized as follows:
dc ,chg  k p ie  ki  ie dt
(4.21)
where kp and ki are the proportional and integral gains, respectively, and the current
error ie is given by
*
ie  ibat
 iL .
(4.22)
As the battery is charged, the battery voltage increases, and the charging mode is
changed from the CC mode to the CV mode when the battery voltage reaches its
battery voltage reference. In the CV mode, the controlled duty ratio is yield from the
80
voltage controller, which is a PI- type controller.
In the discharging mode, only the CC mode is used, and the average voltage
equation over one switching period for the inductor L is obtained according to the duty
ratio ddchg
L
V 
iL Vbat
V

d
 bat  dc  (1  ddchg ).
Ts
2 dchg  2
2 
(4.23)
From (4.24), the duty ratio ddchg is derived as
d dchg  1 
Vbat L iL

 Ddchg  dc ,dchg .
Vdc 2VdcTs
(4.24)
which Ddchg and dc,dchg are the nominal duty ratio and the controlled duty ratio in the
discharging mode, respectively. dc,dchg is similar to dc,chg in (4.20) and is generated by
the controller as described by (4.21).
To ensure power quality and stable operation, the dc-link voltage balancing control
should be accommodated in both operation modes. As the controller output, the
balancing duty ∆d is generated, and its equations is expressed as
d  k p ,balance (Vdc1  Vdc 2 )
(4.25)
where kp,balance is the proportional gain of the dc-link voltage balancing controller. In
the charging mode, if Vdc1 is higher than Vdc2, ∆d is added to the duty ratio D1 of S1.
On the other hand, if Vdc1 is lower than Vdc2, the converter performs the dc-link voltage
balancing by adding -∆d to the duty ratio D3 of S3. Thus, the duty ratios D1 and D3 are
expressed as
81
D1  dchg  d1
(4.26)
D3  dchg  d2
(4.27)
where the duties ∆d1 and ∆d2 are determined according to the polarity of ∆d, and are
derived as

d , for d  0
d1  

0,
for d  0

0,
for d  0
d 2  

d , for d  0
(4.28)
(4.29)
.
The control algorithm in the charging mode is obtained from (4.20)-(4.22) and (4.26)(4.29), as shown in Fig. 4.7.
VDC1
+
∑
Kp,balancing
∑
mode
selector
+
∑
current
controller
Δd1
+
voltage
controller
Vbat
ibat*
duty
selector
dc-link voltage
balancing controller
VDC2
Vbat* +
Δd
dc,chg
+
∑
∑
dchg
Δd2
+ D
chg
Vbat
Vdc
iL
Fig. 4.7. Control algorithm block diagrams in the charging mode.
82
+
+
D1
carrier signal
+
+
∑
+
D3
shifted
carrier signal
In the discharging mode, if Vdc1 is higher than Vdc2, the converter increases Vdc2 by
adding ∆d to the duty ratio D4 of S4. On the other hand, if Vdc1 is lower than Vdc2, ∆d
has a negative value, and the converter carries out the dc-link voltage balancing by
adding -∆d to the duty ratio D2 of S2. Thus, the duty ratios D2 and D4 are derived as
follows:
D2  ddchg  d2
(4.31)
D4  ddchg  d1.
(4.32)
Fig. 4.8 shows the control algorithm in the discharging mode.
VDC1
+
∑
VDC2
ibat* +
∑
iL
Δd
Kp,balancing
duty
selector
dc-link voltage
balancing controller
current dc,dchg
controller
+
∑
+
ddchg
Δd2
+
+
∑
+
D2
Ddchg
Vbat
1Vdc
Δd1
carrier signal
+
+
∑
+
D4
shifted
carrier signal
Fig. 4.8. Control algorithm block diagrams in the discharging mode.
83
4.2 Analysis of Modified Three-phase Inverter
T-type cell A
S1A
S1C
iA
Cdc1
LA
R
A
S4A
Vdc
S2A
n
S
C
Cdc2
S4C
S2C
S3A
iC
LC
T
S3C
T-type cell C
Fig. 4.9. Circuit diagram of the modified three-phase three-level inverter.
The proposed three-phase three-level inverter as shown in Fig. 4.9 performs the
current control for each phase. That is, a phase current ix is regulated by the switching
operation of each T-type cell (S1x, S2x, S3x, and S4x) where x represents A or C.
Fig. 4.10 shows the switching pattern of the T-type cell A for the phase R. During
the positive half-cycle of the grid voltage vRS, the switches S1A and S2A are driven at
high frequency and operate complementary to each other, and S4A is always turned on.
On the other hand, in the negative half-cycle of vRS, the switches S3A and S4A are
operated complementarily at high frequency, and S2A is always turned on. The suboperation mode for a T-type cell in the discharging mode is divided into four modes
as shown in Fig. 4.11; Mode 1 and Mode 2 show the current flow and switching state
during the positive half-cycle; Mode 3 and Mode 4 occur during the negative halfcycle.
84
vRS
S1_A
S2_A
S3_A
S4_A
Fig. 4.10. Switching pattern of T-type cell A.
85
S1A
S1A
Vdc
2
LA
S4A
S2A
Vdc
2
iA
A
S4A
S2A
LA
iA
LA
iA
A
n
n
Vdc
2
Vdc
2
S3A
S3A
(a) Mode 1
(b) Mode 2
S1A
Vdc
2
S1A
LA
S4A
S2A
Vdc
2
iA
A
S4A
S2A
A
n
n
Vdc
2
Vdc
2
S3A
(c) Mode 3
S3A
(d) Mode 4
Fig. 4.11. Equivalent circuits for T-type cell A in the modified three-phase three-level inverter.
Assume that the two dc-link capacitors Cdc1 and Cdc2 have a sufficiently large
capacitance and that their voltages are balanced. As shown in Fig. 4.11, both dc-link
capacitor voltages Vdc1 and Vdc2 can be considered as constant voltage sources with
half of the dc-link voltage Vdc/2. Then, based on Fig. 4. 11, the average equation for
LA over one inverter switching period Ts,inv in the positive half-cycle can be obtained
as follows:
LA
iA  Vdc


 vRS  d1 A  vRS (1  d1A )
Ts ,inv  2

(4.33)
where d1A is the duty ratio of the switch S1A, and ∆iA is the current variation of iA. In
the same manner, the average equation for LA in the negative half-cycle is
86
LA
iA  Vdc


 vRS  d3 A  vRS (1  d3 A )
Ts ,inv  2

(4.34)
where d3A is the duty ratio of the switch S3A. The duty ratios d1A and d3A can be
considered to be dA in each half cycle of vRS. From (4. 33) and (4.34), the duty ratio dA
can be calculated as follows:
d A  DA  d A 
2 vRS
Vdc

2 LA
 iA .
VdcTs ,inv
(4.35)
The duty ratio dA in (4.35) has two components: the first term is the nominal duty ratio
DA, and the second term is the control duty term ∆dA. The nominal duty ratio DA is a
kind of a feed-forward controller. Since ∆dA is the yield from the output of the feedback controller, it is used to make the phase current iA track its reference iA_ref and is
implemented as follows:
d A  k pc (iA _ ref  iA )  kic  (iA _ ref  iA )dt
(4.36)
where kpc and kic are the proportional and integral gains of the inverter, respectively.
From (4.35), it is noted that the current control of the inverter is similar to the unipolar
PWM manner of the single-phase inverter introduced in Chapter 3. The current control
for the phase T is also carried out in the aforementioned manner. The operation and
control methods are similar to those of the charging mode.
As mentioned in Chapter 3, Vdc fluctuates according to the power difference
between the battery and the grid. Thus, a grid current command Ig* is obtained from
the voltage controller in (3.11). Finally, the control algorithm for the modified threephase three-level inverter of the proposed system is shown in Fig. 4.12.
87
R-phase current control
*
Vdc_ref
+
∑
Vdc
Voltage
controller
Current
limiter
I
iA
*
+
Ilimit
∑
ie
Current
controller
ΔdA
+
∑
dA
+ D
A
iA
Vrs
sin ωt
Vd
sin ωt
PLL
vrs
T-phase current control
Fig. 4.12. Control algorithm block diagram in the modified three-phase inverter.
88
dC
4.3 Ground Leakage Current Analysis
In this section, high frequency models for the conventional and proposed grid-tied
converters are represented for the evaluation of the ground leakage current
characteristics according to the converter topologies. Based on the analysis, the
feasibility of the proposed converter as the transformerless system applications is
verified.
Due to the absence of a transformer, the galvanic connection between the battery
and the grid exists through the parasitic capacitance Cp1 of the battery terminal to the
ground. In addition, because a grid-tied converter should accommodate integration
with various applications such as PV energy systems through the dc-link, a
capacitance Cp2 is present between the dc-link and the ground.
For a conventional grid-tied converter that consists of a three-level dc-dc converter
shown in Fig 4.2 and the conventional three-phase T-type three-level inverter shown
in Fig. 4.1 (c), the high frequency equivalent circuit can be represented as shown in
Fig. 4.13 (a). The voltage v1n (or v2n) between the point 1(or 2) and the midpoint n of
the dc-link capacitor is determined according to the switching operation of the
switches S1, S2, S3, and S4. The voltage v1n and v2n are obtained as follows:
 Vdc
 , for S1 on
v1n   2
0, for S2 on

(4.37)
 Vdc
, for S3 on

v2 n   2
.
0, for S4 on

(4.38)
and
On the other hand, the voltage between the midpoint of each leg (A, B, and C) and the
89
L1
1
V1n
VAn
VBn
n
L1
Cp1
2
V2n
vPE1
VCn
Cp2
A
LA
B
LB
C
LC
vPE2
(a)
VAn
3
VBn
3
VCn
3
Leq
iPE
vPE
Cp
(=Cp1//Cp2)
(b)
Fig. 4.13. High frequency modeling of the conventional grid-tied converter. (a) High frequency
equivalent circuit. (b) High frequency model.
point n is determined according to the switching operation of each leg. Thus, the
voltages vAn, vBn, and vCn can be defined as follows:
 Vdc
 2 , for S1 X on

vXn  0, for S2 X and S4 X on
 V
 dc , for S3 X on
 2
90
(4.39)
20
10
0
-10
-20
iA
iB
iC
200
100
0
-100
vPE
-200
iP
5
0
-5
Fig. 4.14. Simulation results for the ground leakage current in the conventional grid-tied converter.
where X= A, B, C. From Fig. 4.13(a), it is observed that Cp1 and Cp2 are connected in
parallel and can therefore be expressed as Cp (=Cp1+Cp2) in the high frequency
equivalent circuit, and the controlled voltage sources v1n and v2n in the dc-dc converter
do not determine the voltage across Cp. Assuming that the inductances of LA, LB, and
LC are equal to Linv. Then, using superposition principle and Thevenin theorem, the
high frequency model for the conventional grid-tied converter with the T-type threelevel inverter can be obtained as shown in Fig. 4.13 (b) where Leq is the equivalent
inductance and its value is LA//LB//LC or Linv/3. From the model in Fig. 4.13(b), the
voltage vPE across the parasitic capacitor CP can be calculated as follows:
vPE  
1
 vAn  vBn  vCn 
.
1  s Linv C p 
3

2
(4.40)
Based on (4.40), vPE varies according to the high frequency switching states of each
leg. The high frequency components in vPE causes high ground leakage current iP that
flows through CP. Fig. 4.14 shows the simulation results for the ground leakage
91
L1
1
V1n
VAn
A
LA
n
L2
Cp1
2
n
V2n
VCn
vPE1
Cp2
C
LC
vPE2
(a)
iPE
vPE
Cp
(=Cp1//Cp2)
(b)
Fig. 4.15. High frequency modeling of the proposed grid-tied converter. (a) High frequency equivalent
circuit. (b) High frequency model.
current analysis of the conventional three-phase T-type three-level inverter obtained
with the simulation parameters of battery voltage VBAT= 360 V, dc-link voltage Vdc =
640 V, grid voltage vg = 210 Vrms, rated power Prated = 10 kW, inductance L1 =L2 Linv =
1 mH, and parasitic capacitor capacitance CP = 1 μF. From Fig. 4.14, it is seen that
vPE changes rapidly according to the high frequency switching operation, producing
high ground leakage current. Furthermore, the observed grid currents indicate that the
conventional converter has low grid power quality.
The high-frequency equivalent circuit for the proposed converter in Fig. 4.2 is
92
30
ia, ib, ic
20
10
0
-10
-20
-30
0
vPE
-100
-200
-300
-400
10
iPE
5
0
-5
-10
Fig. 4.16. Simulation results for the ground leakage current in the proposed grid-tied converter.
derived in the same manner, as shown in Fig. 4.16a. In the equivalent circuit, the
grounded S-phase of the grid is directly connected to the midpoints of the battery and
dc-link capacitors. This connection fixes the voltage vPE across the parasitic capacitor
Cp to a constant value and enables the proposed converter to eliminate the leakage
current, thereby making the transformerless configuration feasible. Fig. 4.16b shows
the high-frequency model for the proposed grid-tied converter. This model verified
that the high-frequency switching operation of the proposed converter does not affect
the voltage vPE. Fig. 4.16 shows the simulation results for the ground leakage current
analysis of the proposed grid-tied converter; these correspond to the results obtained
from the high frequency model. In conclusion, due to the absence of the leakage
current, the proposed converter can use the transformerless system configuration.
93
4.4 Experimental Results
To verify the theoretical analysis and evaluate the validity of the proposed threephase three-level grid-tied converter, a 10 kW prototype was built and tested. Fig. 4.
17 shows the prototype of the three-phase three-level transformerless bidirectional
grid-tied converter. The hardware specifications for the prototype are represented in
Table 4.1. The bidirectional switches of the inverter are implemented using one IGBT
module and two diodes connected in series as shown in Fig. 4.18. The overall
algorithm for the proposed three-phase three-level grid-tied converter is digitally
implemented in the software using a micro control unit, Microchip dsPIC33EP256MU810 with has 60 MIPs, 16-bit, fixed-point and peripheral circuits such as 12-bit
ADC, and 6-ch PWM. For the experiment, 36 batteries with 12V/26Ah are connected
in series and used as the dc source.
TABLE 4.1
PARAMETERS AND COMPONENTS OF THE PROTOTYPE
FOR THE PROPOSED THREE-PHASE GRID-TIED CONVERTER
Parameters
Symbols
Value
Nominal battery voltage
Vbat
360V
Grid voltage
vRS, vST, vTR,
210Vrms
Grid frequency
fg
60Hz
Rated average power
P
10kW
Switching frequency
fs
15kHz
Inductors on the battery side
L1, L2
1mH
Filter Inductors on the grid side
LA, LC
1mH
Capacitors on the battery side
C 1, C 2
5μF
DC-link capacitors
Cdc1, Cdc2
4700μH
Symbols
Part number
Switches of dc-dc converter
S1, S2, S3, S4
BSM100GB60DLC
Leg switches of inverter
S1, S2, S3, S4
SKM100GB125DN
Switches
S2A, S4A, S2C, S4C
BSM100GB60DLC
Diodes
D1A, D2A, D1C, D2C
FDS100BA60
Parameters
Bidirectional
switches
94
Battery stack
Oscilloscope
Proposed converter
Fig. 4.17. Photograph for the experimental setup of the 10kW prototype
S4X
n
X
S4X
n
X
S2X
S2X
Bidirectional switches
Alternative
Fig. 4.18. Implementation of a bidirectional switch in a T cell.
95
Fig. 4.19 shows the dc-link voltage Vdc and the dc-link capacitor voltages Vdc1 and
Vdc2. From the experimental result, it is apparent that Vdc is divided equally between
the dc-link capacitors Cdc1 and Cdc2; the difference between Vdc1 and Vdc2 is almost zero.
It is seen that the proposed converter is capable of balancing the dc-link capacitor
voltages by using the three-level dc-dc converter’s balancing algorithm.
Fig. 4.20 shows the experimental waveforms for grid currents iA, iB, and iC at full
load in the discharging mode. As shown in Fig. 4.20, each grid current has nearly
perfect sinusoidal form and a desired power level. In this case, THD is measured as
2.6%. Therefore, it is verified that the proposed converter and its control system
provide reliable ac power to the grid in line with grid regulations.
Fig. 4.21 shows the voltage vPE and leakage current iP in the discharging mode. Fig.
4.21 verified that the proposed converter has constant vPE (−180 V), which is equal to
−VPV/2. Accordingly, the leakage current iP is quite low, with a measured RMS value
of 46 mA that satisfies the leakage current standard VDE-0126-1-1. From the
experimental results, it is seen that none of the high frequency switching operations
of the proposed converter affects the voltage vPE, resulting in a significantly reduced.
The results in the charging mode are similar to those of the discharging mode.
Fig. 4.22 shows the measured power efficiency of the proposed converter under all
load conditions in the discharging mode. This results show that the three-level stepup converter and the modified three-phase T-type inverter provide high efficiency with
improved switching and conduction performance. The maximum efficiency of the
proposed converter is 97.4% and the efficiency at rated power is 97.2% in the
discharging mode. The results in the charging mode are similar to those of the
discharging mode.
96
Vdc [100 V/div.]
Vdc1 [100 V/div.]
Vdc2 [100 V/div.]
►
Time [20 ms/div.]
Fig. 4.19. Experimental results for the dc-link voltage Vdc and the dc-link capacitor voltages Vdc1 and
Vdc2.
iA [10 A/div.]
iC [10 A/div.]
►
iB [10 A/div.]
Time [4 ms/div.]
Fig. 4.20. Experimental waveforms for the three-phase grid currents iA, iB, and iC.
97
►
iP [200 mA/div.]
►
vPE[100V/div.]
Time [10 ms/div.]
Fig. 4.21. Experimental waveforms for the voltage vPE across the parasitic capacitor and the
leakage current iP..
Efficiency [%]
98
97
96
95
94
10
20
30
40
50 60
Load [%]
70
80
90
100
Fig. 4.22. Measured power efficiency under entire load conditions in the discharging mode
98
Chapter 5
Conclusion
This thesis presents three high efficiency grid-tied bidirectional converter
topologies and their respective control algorithms. The proposed grid-tied converters
are theoretically analyzed and experimentally evaluated in each chapter.
First, a high efficiency grid-tied bidirectional flyback converter and its novel
control system are introduced, and theoretical analysis and experimental results are
presented. By using the single power conversion technique, the proposed converter
can perform bidirectional power conversion between the energy storage device and
the grid in only one step. To encourage the merits of the single power conversion
technique, the bidirectional flyback converter topology is selected. Then, considering
its dynamic characteristic, a novel control system with a repetitive control scheme is
developed. This overcomes the constrains caused by the RHP zero of the flyback and
the filter resonance and makes the proposed converter achieve the desired control
99
performances and stability. In conclusion, the proposed converter can improve power
conversion efficiency using the novel power conversion method, and the developed
control system makes many advantages of the proposed converter feasible.
Experimental results on a 250 W prototype verify that the proposed converter has
higher efficiency than that of the conventional grid-tied converters with several power
conversion steps, and its control system satisfies both performance and stability.
Second, a high efficiency single-phase bidirectional transformerless inverter for a
PV system with an energy storage is introduced. The proposed bidirectional inverter
eliminates the transformer, thereby improving the overall system performance
characteristics such as efficiency, cost, and weight. Furthermore, its circuit structure
and operation address the issue of the ground leakage current that is crucial for
transformerless PV applications. Thus, the proposed converter makes the
tranformerless system configuration feasible and achieves high efficiency. Finally, a
3 kW prototype was implemented to confirm the validity of the proposed bidirectional
inverter. The experimental results showed that the efficiency at 3 kW 98.8% in the
inverter mode and 98.7% in the PWM rectifier mode. Furthermore, the obtained
results indicated that the leakage current was suppressed by approximately 30 mA in
both operation modes.
Third, a high efficiency three-phase three-level bidirectional transformerless gridtied converter for high power applications is presented. The proposed three-phase
grid-tied converter is composed of a three-level dc-dc converter and a modified threephase T-type three-level inverter. This three-level configuration results in the smaller
passive component size and the lower switch voltage stress, thereby improving the
power density and reducing the switching losses compared to those of the
conventional two-level converter. Furthermore, by connecting the S-phase of the grid
100
to the ground, the transformer can be eliminated and power conversion can be carried
out with only the two T-type switch cells for two-phases; this characteristic results in
the lower power losses, the cheaper cost, the smaller converter size, and the simpler
control system. Thus, the proposed three-phase three-level bidirectional transformerless grid-tied converter represents an approach for achieving high power density that
is suitable for high power applications and gives high efficiency due to the
aforementioned advantages in the circuit configuration. To verify the theoretical
analysis and evaluate the validity of the proposed three-phase grid-tied converter, a
10 kW prototype was built and tested. Experiments on the prototypes verified the
performance of the proposed converters and their control systems.
The three bidirectional grid-tied converters are useful in various industrial fields
such as ESSs, renewable energy systems, and EV systems.
101
Appendix
Soft-switching Single-power conversion OBC
with High Efficiency and High Power Density
As concerns for environmental pollution and energy saving are gradually growing,
development of the vehicles with electric propulsion, such as electric vehicle (EV)
and plug-in hybrid EV (PHEV), has recently accelerated [78]-[80]. Since these
vehicles use partially or fully the batteries as the power sources, an on-board charger
(OBC) which charges the batteries by connecting to the utility grid is necessary. Thus,
the OBC is one of the key components in EV and PHEV. The research challenge of
the OBC includes conversion efficiency, power density, reliability, and production
cost. The conversion efficiency quantifies the fuel saving and emission reduction, so
that it should be maximized [81]. Furthermore, due to the characteristic of the
automotive applications, the OBC should be compact size and have long life-time [82],
[83].
Conventional OBCs are two-stage converter configuration; they consist of an ac-dc
102
converter with the power factor correction (PFC) [84], [85] followed by an isolated
dc-dc converter [86]-[90]. The previous work in [91] introduces a two-stage OBC
with a boost PFC converter and a full-bridge phase-shift converter; it provides almost
unity power factor and reliable operation. Although the soft-switching technique is
essential because the power density increases with the switching frequency, the OBC
in [91] has disadvantages such as the hard switching operation of its PFC stage,
narrow zero-voltage switching (ZVS) range of its full-bridge switches, and a serious
reverse recovery problem of the rectifier diodes in the dc-dc stage. Another OBC in
[92] employs an interleaved boost PFC converter and an LLC resonant converter. Due
to following facts: 1) an increase of the effective switching frequency by interleaved
technique, and 2) the soft-switching operation of all components in the dc-dc stage,
the OBC has higher efficiency and power density compared to the OBC in [91].
However, OBCs in both [91] and [92] have inherently high circuit complexity and
low efficiency due to their two-stage circuit configurations. They also have a highvoltage dc-link electrolytic capacitor which is not suitable for automotive applications
due to its short life time [93].
The single-stage circuit configuration is an alternative that may overcome the
drawbacks of the conventional two-stage OBCs [93]-[95]. However, the single-stage
approach performs the ac-dc power conversion depending on the circuit design
without any PFC control; this fact causes poor power factor and huge harmonics. In
[19A], A single-stage OBC with an additional valley-fill circuit is developed; the use
of the additional circuit provides the high power factor, but causes additional power
losses and highly complex circuit structure.
In this appendix, a novel OBC with high efficiency and high power density is
introduced and analyzed. The proposed OBC is developed by utilizing the single
103
power conversion technique introduced in Chapter 2. The proposed OBC consists of
a full-bridge diode rectifier, an active-clamp current-fed push-pull resonant converter,
and only one controller. The proposed OBC gives the soft-switching technique to all
components that operate at the high frequency. Using a novel control algorithm, the
proposed OBC performs both the PFC control and output power control with only one
power-processing step. Moreover, by eliminating the high voltage dc-link electrolytic
capacitor, the proposed OBC can ensure compact size and long life time. Thus, the
proposed OBC has the following advantages:
1) Due to the soft-switching technique and the single-power conversion approach,
the proposed OBC can achieve high efficiency and high power density.
2) The absence of the bulky electrolytic capacitor expects that the proposed OBC
has longer life time and smaller size compared to the conventional OBCs in [91],
[92].
3) Without any additional circuit, the proposed converter can provide high power
factor using the developed control algorithm unlike the OBC in [96].
The description of the operation principle and the relevant analysis for the proposed
OBC is represented in the following section. Finally, a 2kW for the proposed OBC is
implemented, and its performance and validity are evaluated based on experimental
results.
104
A. 1 Proposed Soft-switching Single-power Conversion OBC
with High Efficiency and High Power Density
is1a
S1
S2
ip2
+
-
-
is1
Np: Np: Ns
is2
iCr2
is
D2
id2
Cr2
Co
Vbat ..
vcr2
-
+
vp2
Ci
vi
vs
vcr1
-
+
vg
Llk
-
+
-
L
T
+
ip1 im
Lm vp1
iCr1
Cr1
+
S2a
id1
D1
-
ii
io
-
S1a
ig
is2a
+
vc
+
+
Cc
-+
Vi
ii
D
ΔD
∑
+
Dn
+
current
controller
∑
+
ii*
 Vi 
voltage
Im  
* controller
V
m
I
  m
*
Vbat
∑
+
Vbat,ref
PFC rule
Fig. A.1. Circuit configuration and control block diagram of the proposed OBC.
Fig. A.1 shows the circuit configuration and the control block diagram of the
proposed OBC; this consists of a full-bridge diode rectifier, a dc-dc converter, and a
controller. As shown in Fig. A.1, the proposed OBC controls both the input current
and the output voltage with only one controller; this is the distinct difference
compared to the conventional single-stage ac-dc converters which perform only the
output regulation.
The dc-dc converter is derived from a current-fed push-pull converter. It employs
an active-clamp circuit and a series resonant circuit. The active-clamp circuit is
composed of the auxiliary switches S1a, S2a, and the clamping capacitor Cc. The activeclamp circuit increases conversion efficiency by reducing the switching losses on the
switches and by recycling energy stored in the leakage inductance Llk. Moreover, this
circuit limits voltage stresses across the switches and avoids damage by surge voltage.
The series resonant circuit consists of the leakage inductance Llk, and the voltage
doubler rectifier circuit. This resonant circuit alleviates the reverse recovery problem
105
on the rectifier diodes D1 and D2 by providing ZCS turn-off for the diodes.
A.1.1. Description and Operation Principle
The proposed OBC regulates the input current and output power by adjusting pulsewidth-modulation (PWM) signals of the switches. The main switches S1 and S2 have
the same duty D, and their PWM signals are generated with the 180° phase difference.
S1a and S2a operate complementarily with S1 and S2, respectively.
To analyze the steady-state operation of the proposed OBC, several
assumptions are made as following:
1) All switches S1, S2, S1a, and S2a are considered as ideal switches except for their
body diodes.
2) Since the switching frequency fs is much higher than the grid frequency fg, it is
assumed that the input voltage Vi is constant during one switching period Ts.
3) For symmetric operation, Cr1 is identical with Cr2.
4) The clamp capacitors Cc is large enough, so the clamp capacitor voltage is the
constant voltage Vc.
5) The transformer T is composed of an ideal center-tap transformer with the
primary winding turns Np, the secondary winding turns Ns, the magnetizing
inductance Lm, and the leakage inductance Llk.
The operation region is determined whether the duty D is less than 0.5 or not. Fig.
A. 2 and A. 3 show the theoretical waveforms and the equivalent circuits during half
switching period in the region for D<0.5. In this region, six operation modes exist
during one switching period. However, due to the symmetrical operation, it is possible
for understanding the steady-state operation in this region with the analysis for only
half period. Before Mode 1a, the current ip1 flows into negative direction, and the
secondary current is remains to be zero.
106
vs1_gs
t
vs2_gs
t
ip1
t
im
t
is1
t
is2
t
is1a
t
is2a
t
is
t
id1
t
id2
t
t0
Mode
t1 t2 t3
1a
2a 3a
DTs
Ts
Fig. A.2. Key waveforms of the proposed OBC for D<0.5.
107
t4 t5 t6
4a
5a 6a
Cc
io
S2a
T
Llk
Lm
D1
+
S1a
Cr1
L
Co
Vbat ..
+
S1
D2
S2
Cr2
-
Vi
Np: Np: Ns
Mode 1a
Cc
io
S2a
T
Llk
Lm
L
D1
+
S1a
Cr1
ii
Co
Vbat ..
+
S1
D2
S2
Cr2
-
Vi
Np: Np: Ns
Mode 2a
Cc
io
S2a
T
Lm
L
Llk
D1
+
S1a
Cr1
ii
Co
Vbat ..
+
S1
D2
S2
Cr2
-
Vi
Np: Np: Ns
Mode 3a
Fig. A.3.
Equivalent circuits of the proposed OBC for D<0.5 during half switching period, Ts/2.
Mode 1a [t0, t1]: At t0, the switch S1 is turned on. At that time, ip1 flows through the
body diode of S1, so that S1 is turned on in zero-voltage state. During this mode, the
primary voltage vp1 is the positive voltage with half of the clamp capacitor voltage,
Vc/2. The magnetizing current im increases as
108
im (t )  im (t0 ) 
Vc
(t  t0 ).
2 Lm
(A.1)
In this mode, the power is transferred to the batteries across the transformer. The
secondary current is flows through D1, and the state equations are obtained as follows:
Llk
dis
dt
is  Cr1
 nVc  vCr1
(A.2)
dvCr1
dv
 Cr 2 Cr 2
dt
dt
(A.3)
where n is turns ratio of the transformer and it is given by Ns/2NP. Also, vcr1 and vcr2 are the
voltages across Cr1 and Cr2, respectively. Since Vbat is constant, is can be rewritten as
is (t )  Cr1
dvcr1 (t )
d (Vbat  vcr1 (t ))
dv (t )
 Cr 2
 Cr cr1
dt
dt
dt
(A.4)
where the equivalent resonant capacitance Cr is Cr1+Cr2. Using Eqns. (A.2) and (A.4),
the voltage vCr1 across Cr1, and the secondary current are derived as
vCr1 (t )  nVc  (nVc  vCr1 (t0 ))cos r (t  t0 )
is (t ) 
nVc  VCr1
sin r (t  t0 )
Zr
(A.5)
(A.6)
where Vcr1 is the average voltage of vcr1. Also, the angular resonant frequency ωr and
the characteristic impedance Zr for the series resonant circuit are given by
r 
1
Llk Cr
, Zr 
Llk
.
Cr
(A.7)
Considering that iL is the sum of the primary currents, and the sum of the
109
magnetomotive forces of all windings is zero, the current is1 flowing through S1 is
calculated as
i (t ) nV  V
is1 (t )  i p1 (t )  L  c Cr1 sin r (t  t0 )
2
Zr
im (t0 ) 
Vc
(t  t0 ).
2 Lm
(A.8)
In the end of this mode, the resonance is finished, and the secondary current is becomes
zero.
Mode 2a [t1, t2]: At t1, the diode current id1 becomes zero, and the diode D1 is turned
off with zero-current; this means that D1 does not have the reverse recovery loss. In
this mode, im still increases linearly as (A.1) and is equal to ip1 because no current
flows on secondary side.
Mode 3a [t2, t3]: This mode begins when S1 is turned off. At the same time, ip1 flows
through the body diode of S1a. After short dead time, S1a is turned on in zero-voltage
state while its body diode is conducted. During this interval, the voltages vp1 and vp2
are zero, and the current im is maintained to be constant. In the end of this mode, S2a
is turned off.
The operations Mode 4a-6a for the remaining half period are similar to the
operations of Mode 1a-3a, respectively.
From the volt-second balance for L, the clamp capacitor voltage Vc can be derived,
and be represented as
Vc 
Vi
.
1 D
(A.8)
Eqn. (A.5) indicates that the average voltage Vcr1 of vcr1 is given by nVc. Due to the
110
symmetric operation, the average voltage Vcr2 of vcr2 is also nVc. The sum of Vcr1 and
Vcr2 is the battery voltage Vbat. Thus, the relationship between the input voltage and
the battery voltage is represented as
Vbat
N
2n
1

 s
Vi
1 D N p 1 D
(A.9)
Average value of the secondary current is during the half switching period Ts/2 is the
same as the output current io, and can be derived as
2
Ts
t1 I s , peak
t
0
2
sin r (t  t0 )dt  io
(A.10)
where Is,peak is the peak value of is during one switching period. From (A.6) and (A.10),
Is,peak can be obtained as
I s, peak 
nVc  VCr1 r io

Zr
s
(A.11)
Fig. A.4 show the theoretical waveforms in the region for D>0.5. As shown in Fig.
4, when D is greater than 0.5, there is an interval in which the gate signals of the
switches S1 and S2 is overlapped as Mode 3b in Fig. A.4, and the equivalent circuit is
shown in Fig. A.5. During this interval, the voltages vp1 and vp2 are zero, and the
current im is held constant, as in Mode 3a when D<0.5. Thus, the operations in this
region is analogous to that of the region for D<0.5, so that its detail description is
omitted.
111
vs1_gs
t
vs2_gs
t
ip1
t
im
t
is1
t
is2
t
is1a
t
is2a
t
is
t
id1
t
id2
t
t0
Mode
t1 t2 t3
1b
2b 3b
DTs
Ts
Fig. A.4. Key waveforms of the proposed OBC for D>0.5.
112
t4 t5 t6
4b
5b 6b
Cc
io
S2a
T
Llk
Lm
D1
+
S1a
Cr1
L
Co
Vbat ..
+
S1
D2
S2
Cr2
-
Vi
Np: Np: Ns
-
Mode 3b
Fig. A.5.
Equivalent circuits of the proposed OBC for D>0.5 in the overlapped region.
A.1.2. Control Algorithm for Single-power conversion scheme
The proposed OBC does not include an additional circuit for PFC. Thus, the control
algorithm for both the input current and the output voltage regulations with only one
power conversion process should be accommodated.
According to the switching operation of the main switch, the average voltage
equation for the inductor L during half the switching period can be derived as
V
di
1
(Vi  C ) D  (Vi  VC )(  D)  L i
2
2
dt
2L
ii
Ts
(A.12)
where ∆ii is the input current variation. From (12), the duty D is derived as follows:
D  1
Ns
Vi
ii
 2L
 Dn  D
N p Vbat ,ref
nVbat ,ref Ts
(A.13)
where Vbat,ref is the reference battery voltage. The nominal duty Dn and the feedback
control duty ∆D are defined as
Dn  1 
Ns
Vi
ii
, D  2 L
N p Vbat ,ref
nVbat ,ref Ts
113
(A.14)
PFC rule
Vbat,ref
+
∑
Vbat
Fig. A.6.
voltage
controller
Im*
 Vi  i *
I∑m*   i
∑
 Vm  +
Vi
ii
current
controller
ΔD
∑
+
+
Dn  1 
Ns
Np
D
Vi
Vbat ,ref
Proposed control block diagram for the single-power conversion.
Eqn. (A.14) indicates that Dn is decoupled from the original nonlinear system in
(A.13), and as a consequence, the relation between ∆D and ∆ii becomes linear. In
conclusion, the nominal duty Dn contributes to converting the nonlinear system to a
first-order linear system, and to alleviating the burden on the feedback controller.
Under the unity power factor, the input voltage Vi and the input current ii are the
absolute values of the grid voltage vg and the grid current ig, respectively and they are
expressed as
Vi  Vm sin t , ii  I m sin t
(A.15)
where Vm and Im are the maximum values of vi and ii, and ω is the angular frequency
of the grid.
Fig. A.6 shows the proposed control block diagram for the single-power conversion.
As shown in Fig. A.6, the input current reference ii_ref is derived using the knowledge
obtained from the input voltage Vi as follows:
V 
ii _ ref  I m*  i 
 Vm 
(A.16)
where Im* is the amplitude of the input current reference. The voltage controller aims
to eliminate the difference between Vbat_ref and the sensed battery voltage Vbat by
adjusting the value Im*; this means that Im* is yielded from the voltage controller. In
114
the proposed control system, the voltage controller is easily implemented with a PI
controller. To obtain the high power factor, it is necessary for matching the phase of
the grid current ig with that of the input voltage vg. Since the input voltage Vi includes
the information about the phase of vg, the synchronization with vg can be achieved
using Vi. Thus, without the complex computation burden, the input current reference
which is synchronized with vg can be obtained as (A.16). For the current controller, it
is simply implanted with the proportional controller because its output value ∆D has
the linear first-order relation with ∆i. Consequently, the duty ratio D is obtained by
adding the nominal duty Dn and the feedback control duty ∆D.
A.1.3. Control Algorithm for Single-power conversion scheme
The soft-switching technique allows the proposed OBC to have high power
conversion efficiency and high power density. In this section, the soft-switching
conditions for the proposed OBC are introduced.
The ZVS turn-on for S1a and S2a is naturally obtained by the stored energy in Lm and
Llk. However, to achieve the soft-switching of the main switches S1 and S2, a specific
converter design is required. To achieve the ZVS turn-on of S1 and S2, the switch
currents is1 and is2 should be in the negative direction before each gate signal is
transferred to the corresponding switch. Because the average secondary current is_avg
is zero, the average magnetizing current im_avg is the same as the average current ip1_avg
of ip1. Also, due to the fact that the proposed OBC has the symmetrical circuit design
and operation, the relationship between im_avg and ii is represented as
im _ avg
ii
.
2
(A.17)
Assuming there is no power loss, the instantaneous input power is equal to the
115
instantaneous output power po, the following relationship is given by
pin  vi ii  Voio  po
(A.18)
where io is the output current. Then, the average current im_avg in (A.17) can be
reexpressed from (A.9) and (A.18) as follows:
im _ avg 
nio
.
1 D
(A.19)
At t0, the current is1 flowing through the main switch S1 is the magnetizing current im.
From Eqns. (A.9), (A.18), (A.19), and the waveforms in Fig. A.2 and A.4, is1 at t0 can
be derived as
im
2
ni
V
 o
bat DTs
for D  0.5
1  D  4nL ,

m

.
 nio  Vbat (1  D)Ts , for D  0.5
1  D
4nLm
is1(t0 )  im _ avg 
(A.20)
To satisfy the ZVS condition of S1 in (20), the switch current is1 should be negative at
t0. Then, Lm is designed to meet for all operating points within the grid period as
V 2 D (1  Dmin )
Lm  bat min
4n2 f s po, peak
(A.21)
where Dmin is the minimum duty, fs is the switching frequency, and po,peak is peak
instantaneous output power in a certain average power level. Due to the symmetrical
operation, the ZVS condition for S2 is equal to that of S1 as (A.21).
To achieve the ZCS turn-off of D1 and D2, the half resonant period should meet the
116
following conditions as

for D <0.5
   DTs ,
 r

   (1  D)T , for D  0.5
s

 r
(A.22)
Eqn. (A.22) indicates that D1 and D2 are turned off with the zero current in all
operating points for D<0.5 if the resonant frequency is greater than the switching
frequency. On the other hand, the ZCS region for D>0.5 is determined according to
the design of the equivalent resonant capacitor Cr as
Cr 
1
(A.23)
2
rc
Llk
where the critical angular resonant frequency ωrc is defined as πfs/Dcri. The critical
duty Dcri is the maximum duty in the ZCS region. Fig. A.7 shows the critical resonant
capacitor Cr to satisfy the ZCS turn-off of D1 and D2 on accordance with the variation
Critical resonant capacitance [F]
of the duty.
Non-ZCS region
Llk = 0.3 H
Llk = 0.5 H
ZCS region
Llk = 0.8 H
Llk = 1.0 H
Duty ratio, D
Fig. A.7.
ZCS region of the proposed OBC according to circuit design.
117
A. 2 Experimental Results
To evaluate the feasibility of the proposed OBC, a 2kW prototype was built and
tested. The grid voltage range is from 110 to 240Vrms, and the nominal grid voltage is
set up to be 220Vrms. The nominal battery voltage is designated as 360V. To use the
minimum duty Dmin to be about 0.2, the turns ratio n was set up to be 20/48. Then,
considering the ZVS condition in (A.19), the magnetizing inductance Lm was
determined as 80μH. The resonant capacitors Cr1 and Cr2 are selected based on the
ZCS condition of the diodes in (A.23), and each corresponding value is 2μF. The major
experimental parameters for the prototype are listed in Table I. The control algorithm in
Fig. 6 is digitally implemented using a single DSP chip, dsPIC33EP512GM604
(Microchip); which is responsible for providing the gate signals, sensing the current
and voltage with 12bit A/D conversion.
TABLE A.1
PARAMETERS AND COMPONENTS OF THE PROTOTYPE
Parameters
Symbols
Value
Grid voltage
vg
120-240Vrms
Grid frequency
fg
60Hz
Battery voltage
Vbat
360V
Switching frequency
fs
70kHz
Primary winding turns
Np
24turns
Secondary winding turns
Ns
20turns
Magnetizing inductance
Lm
88μH
Leakage inductance
Llk
0.5μH
Input inductor
L
0.8mH
Input capacitor
Ci
1μF
Clamp capacitor
Cc
4.4μF
Resonant capacitors
Cr1, Cr2
2μH
Output capacitor
Co
4.4μF
Components
Symbols
Part
Switches
S1, S2, S1a, S2a
FCA76N60N
Output diodes
D1, D2
BYV34X-600
Bridge diode on the grid side
-
KBPC3506
118
vg [150V/div.]
►
ig [10A/div.]
io [10A/div.]
►
Time [4ms/div.]
Fig. A.8.
Experimental waveforms for the grid voltage vg, the grid current ig, and the output current io.
Fig. A.8. shows the grid voltage vg, the grid current ig, and the output current io.
From Fig. A.8, it is observed that ig has almost perfect sinusoidal form with the
synchronization with vg. In this case, the power factor is measured to be 0.999. The
current io has twice frequency (120Hz) of the grid as shown in Fig. 8. The low
frequency current ripple inevitably exists in an approach that eliminates the
electrolytic capacitor. However, in [97], it is verified that the ac impedance is much
smaller than the dc impedance at twice the grid frequency ripple, so the charging
current with a low frequency ripple does not affect the battery life time.
Figs. A.9 and A.10 show the soft-switching techniques on the proposed OBC. As
shown in Fig. A.9, when the switches are turned on, the switch currents is1 and is1a
flow through their body diodes; it is clear that all switches obtain the ZVS turn-on. In
secondary side, as shown in Fig. A.10, the diode current id1 become zero before the
diodes D1 is turned off, respectively. Thus, it is expected that the proposed OBC can
reduce the switching losses on all components which operate at high frequency due to
its soft-switching techniques.
119
vs1_gs [10V/div.]
►
is1 [10A/div.]
►
Time [4s/div.]
(a)
►
vs1a_gs [10V/div.]
is1a [10A/div.]
►
Time [4s/div.]
(b)
Fig. A.9.
Experimental results for the soft-switching technique on the switches (a) Gate signal
vs1_gs and switch current is1 of the main switch S1. (b) Gate signal vs1a_gs and switch current is1a of the
main switch S1 of the active- clamp switch S1a.Equivalnet circuits of the proposed OBC for D<0.5 during
half switching period, Ts/2.
►
vd1 [250V/div.]
id1 [20A/div.]
►
Time [4s/div.]
Fig. A.10.
Experimental results for the soft-switching technique on the output diode D1.
120
Power factor
1
0.99
0.98
0.97
0.96
0.95
0.94
120
160
180
200
220
240
Grid voltage [Vrms]
Measured power factor according to the grid voltage level.
Efficiency [%]
Fig. A.11.
140
98
96
94
92
90
88
Proposed OBC
Single-stage OBC in [19]
Two-stage OBC in [14]
86
10
Fig. A.12.
20
30
40
50
60
70
80
90 100
Load [%]
Conversion efficiency comparison according to the OBC topology.
Fig. A.11 shows the measured power factor according to the input voltage level.
The power factor is greater than 0.99 in the whole input voltage range. The result in
Fig. A.11 indicates that the proposed OBC can achieve high power factor without any
additional circuit for PFC. Fig. A.12 shows the efficiency comparison to the
conventional OBC topologies. As shown in Fig. A.12, the proposed OBC has higher
efficiency than the other OBC topologies under the entire load conditions. In the
proposed OBC, the maximum efficiency and the rated efficiency are measured to be
96.4% and 96.1%.
121
The proposed OBC The proposed OBC employs a single power conversion method
and soft-switching technique, and thereby significantly improves conversion
efficiency. In addition, the proposed control algorithm enables the proposed OBC to
perform both the PFC control and output power control without any complex circuit
structure or the need for several power-conversion steps. In conclusion, because of
these advantages, the proposed OBC is suitable for the use in the automobile
applications that require high efficiency, high density, and high reliability.
122
요 약 문
고효율 양방향 계통 연계형 컨버터에 대한 연구
신 재생 에너지원 및 전기 자동차와 같은 새로운 에너지 시장의 등장은
기존 계통 전력 시스템의 현대화를 부추기고 있다. 배터리와 같은 에너지
저장 장치의 계통과의 결합은 안정적인 전력 공급, 효율적인 부하 관리,
주파수 조정과 같은 다양한 기능을 제공하여 전력 시스템의 신뢰도 및
안정성을 개선한다. 이 경우, 계통과 에너지 저장 장치를 연동을 시키는
양방향 계통 연계형 컨버터가 요구되며, 이것의 성능 지표에는 전력 변환
효율, 전력 밀도, 제작 단가, 그리고 전력 품질 등이 있다. 기존의 양방향
계통 연계형 컨버터는 이단 구성에 변압기를 가지는 회로 구조가 주류를
이루었다. 하지만 구조적 특성상 효율 및 전력 밀도 그리고 제작 단가
면에서 불리하며 개선이 요구된다.
본 논문에서는 3개의 고효율 양방향 계통 연계형 컨버터 토폴로지를
제안한다. 성능 향상을 위해 적용된 방법론으로는 단일 전력 변환 또는
무 변압기 형 구조 채택이 있다.
첫 번째 제안하는 컨버터는 양방향 플라이백 dc-dc 컨버터와 unfolding
회로로 구성된다. 이 컨버터는 기존의 이단 구조를 가지는 양방향 계통
연계형 컨버터와 달리 플라이백의 펄스 폭을 계통의 순시 전압의 크기에
따라 주기적으로 조절함으로써 에너지 저장 장치와 계통 간의 단일 전력
123
변환을 수행한다. 제안하는 컨버터의 제어 시스템은 반복 제어 방식을
사용하여 개발되었다. 이는 플라이백의 우반면 영점과 LC 필터의 공진에
의한 제어기 이득 값이 제한되는 상황에서 기준치 추종 및 외란 제거
성능을 보장하도록 하여 제안하는 컨버터의 단일 전력 변환의 타당성을
부여한다. 따라서 제안하는 양방향 플라이백 컨버터는 단일 전력 변환을
통해 시스템의 효율을 향상 시키고, 개발된 제어 시스템은 제안하는
양방향 컨버터의 실효성을 제공한다.
두 번째로는 제안하는 단상 양방향 인버터는 에너지 저장 장치를
가지는 태양광 시스템에서 적용될 수 있다. 제안하는 인버터는 기존 계통
연계형 컨버터 시스템에서와 달리 변압기를 제거하여 효율, 전력 밀도,
그리고 제작 단가와 같은 모든 성능 지표를 개선한다. 제안하는 회로의
구조와 스위칭 동작을 통해 무 변압기 태양광 시스템의 주요 변수 중
하나인 대지 누설 전류를 제거할 수 있다; 이는 제안하는 인버터를 통한
무 변압기 시스템의 적용을 가능케 하여 양방향 계통 연계형 컨버터
시스템 전체의 성능을 향상을 도모한다.
세 번째로 제안하는 삼상 양방향 계통 연계형 컨버터는 3-level dc-dc
컨버터와 변형된 삼상 T 형 3-level 인버터로 구성되어 있다. 제안하는
계통 연계형 컨버터는 3-level 구성을 통해 기존의 2-level 구성의 컨버터와
비교해 수동 소자의 크기와 스위칭 손실을 효과적으로 줄일 수 있다. 뿐
만 아니라, 새롭게 고안된 회로 구조를 이용하여 인버터 단에 삼상 중
한상에 대한 소자 수를 줄이며, 동시에 누설 전류를 제거할 수 있게 된다.
124
따라서 본 컨버터 토폴로지는 소자 수의 감소와 무 변압기 형 시스템
구조 채택이 가능한 구조이기에 기존의 대용량 계통 연계형 컨버터에서
제시한 방법에 비해 보다 효과적으로 효율과 전력 밀도 모두를 향상 시킬
수 있었다.
제안하는 모든 컨버터는 실험을 통해 이론적 분석을 검증하고, 실험
결과는 제안하는 컨버터가 계통과 관련된 규정을 만족시키며 전력 변환
효율, 전력 밀도, 제작 단가 등 전반적인 성능을 향상시킴을 보여주었다.
이를 토대로 제안하는 고효율 양방향 계통 연계형 컨버터는 에너지 저장
시스템, 신 재생 에너지 시스템, 전기 자동차와 같은 다양한 산업 분야에
적용함에 따라 긍정적인 효과를 가져올 것이라 기대할 수 있다.
125
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