COMP1030 LAB 6
ARM Assembly Language
Programming
Control Flow (If-else/Loops)
Nov 02, 2020
Outline
• Discuss CW
• Feedback
• Examples of Control Flow
• (If-else, Loops),
• Branch & Comparison Instructions
• Addressing
• Assembly Directives
• Practice
Course Work 40%
• Type of Course: (01 Test, 01 Assignment)
• Marks: 20% + 20% of the total marks
• Date for Test: 9th – 15th November (Exact date/time will
be notified later in Lab Class)
• Date for Assignment: 30th Nov to 6th Dec (Exact date of
submission will be notified later)
• Syllabus for the test: Lab (1–7)
topics/Examples/Practice Exercises (refer the weekly
Class materials)
• Syllabus for the Assignment: Related to Lab (1-to-9)
Topics/Examples/ Practice Exercises.
• Note: Questions for Assignment will be posted later.
Last Week
Branch and Comparisons
Conditional Execution/Predicated Execution
Control Flow Instructions
Examples:
o
B/BL
o
EQ/NE
o
CMP
o
Loop/If-else
if-then-else statement
≤
A :: B?
C0
>
LDR
LDR
CMP
BLE
LDR
B
L1: LDR
L2: STR
…
R0,A
R1,B
R0,R1
L1
R0,=1
L2
R0,=0
R0,C
C1
- or –
LDR
LDR
CMP
ITE
LDRGT
LDRLE
STR
R0,A
R1,B
R0,R1
GT
R0,=1
R0,=0
R0,C
Loops: Basic Structure
initialization
done?
body of loop
…
top: CMP
B{cond}
…
…
B
done:
…
done
top
Loops: Predetermined #Iterations
for (n = 0; n < 100; n++)
{
top:
n = 0,1,…,99
done:
}
LDR
CMP
BGE
…
ADD
B
R0,=0
R0,#100
done
R0,R0,#1
top
Software Interrupt (SWI) instruction &
SVC
Software Interrupt (SWI & SVC)
• Main purpose is to cause a processor exception to occur
• Used to cause a SWI exception to occur
• This is the main mechanism in the ARM instruction set by
which User mode code can make calls to privileged
Operating System code.
• Software Interrupt or SWI in the older notation, and SVC in
the newer notation.
• SVC (Supervisor) entered on reset and when a Software
Interrupt (SWI) instruction is executed
While Loop
whl
LT
end
CMP
BEQ
BLT
SUB
B
SUB
B
SWI 2
R0, R1
end
LT
R0, R0, R1
whl
R1, R1, R0
whl
; a > b?
; if a == b done
; branch if a < b
;a=a-b
; loop again
;b=b-a
; halt the emulator
ARM’s conditional branches
• Converting HLL code to ARM code
Converting High Level Language (HLL) code to
ARM code
if (P == Q) X = P – Y ;
Converting HLL code to ARM code
Now consider a more complicated example of a C construct
with a compound predicate:
if ((a == b) && (c == d)) e++; with a compound predicate:
if ((a == b) && (c == d)) e++;
IF I > 25 THEN J = K + 12 ,
• Assume I is in r0, J in r1, and K in r2
• We can simplify the code by using conditional execution as
follows.
Addressing (Load/Store Instructions)
Load and Store Instructions
• Can we use MOV to copy data from memory to
register ?
• Registers >>>>>>Memory ……………(STR instruction)
• Registers <<<<<<Memory ……………(LDR Instruction)
• LDR and STR are used for Single Register Transfer
• LDR load a 32-bit memory address into a Register
(destination),
• STR store a value of a register into a 32-bit memory
location.
Load and Store Instructions
Syntax:
LDR {cond} Rd, Source Address.
STR {cond} Rs, Destination Address.
The LDR instruction uses a register as pointer.
When a register is used as address pointer, we
enclosed it into square brackets [] when writing
instructions.
LDR R5, [R1] ;
Example Load/Store
0x00000011
R0
0x00000A00
R1
0xFFFFFFFFB
R2
0xFEEDC0DE
R3
0x00000A00
R4
0x0000BEAD
R5
R6
R7
R8
…
…
R15
LDR R5, [R1]
Contents
0xAAAAAAAA
Address
0x000009FC
0x0000BEAD
0x00000A00
0x55555555
0x00000A04
When a register is used as address pointer, we enclosed
it into square brackets [] when writing instructions LDR
R5, [R1] ;.
In this example the LDR instruction uses the contents of
R1 as an address and fetches what is stored in the
memory at that address pointing by R1, to R5.
When you execute this instruction LDR R5, [R1], the
content stored in memory which is pointing by R1 will
be stored into R5.
Example Load/Store
LDR R5, [R1]
Contents
0xAAAAAAAA
Address
0x000009FC
0x0000BEAD
0x00000A00
0x55555555
0x00000A04
0x00000011
R0
0x00000A00
R1
0xFFFFFFFFB
R2
0xFEEDC0DE
R3
0x00000A00
R4
0xAAAAAAAA
0x000009FC
0x0000BEAD
R5
0xFEEDC0DE
0x00000A00
R6
0x55555555
0x00000A04
STR R3, [R1]
R7
R8
…
…
If we want to copy a value from a register out of some memory
location, then STR instruction is used.
STR R3, [R1]
R15
The STR instruction used the first operand R3 as source of data and
the second operand R1 pointing to the destination .
So we can say, the STR uses the address stored in R1.
Example Load/Store
• Now, How we can modify the address pointer?
• [The real power of LDR/STR instructions]
Example Load/Store
0x00000011
R0
0x00000A00
R1
0xFFFFFFFFB
R2
0xFEEDC0DE
R3
0x00000A00
R4
0x0000BEAD
R5
0x55555555
R6
LDR R5, [R1]
STR R3, [R1]
LDR R6, [R1, 4]
Contents
0xAAAAAAAA
Address
0x000009FC
0x0000BEAD
0x00000A00
0x55555555
0x00000A04
0xAAAAAAAA
0x000009FC
0xFEEDC0DE
0x00000A00
0x55555555
0x00000A04
R7
R8
…
…
In this case, the value 4 is added to the stored
value in R1, and the result of that addition is used
as desired memory R15
address. So before fetching
data from memory, it will add 4 to change the
address pointer R1, but the stored value of R1 is
not changed.
0xAAAAAAAA
0x000009FC
0xFEEDC0DE
0x00000A00
0x55555555
0x00000A04
Memory access operations
• They have a conditional execution field, bits 31-28 of the
op-code, and can be conditionally executed like other ARM
instructions.
• This facility makes it possible to write code like
Assembler Directives
Assembler Directives
• Commands to the assembler that direct the
assembly process
• Executed at assembly time
• It directs the Assembler to perform
• They Assign the program to certain areas in
memory
• Define symbols
• Define memory for storage
• Table or fixed data in memory
• Allow references to other program
Assembler Directives
Directives
Explanation
AREA
It instructs the assembler to assemble a new code or data section
CODE
Contains machine instructions. READONLY is the default
DATA
Contains data, not instructions. WRITEONLY is the default
READONLY
Indicates this area should not be written to.
WRITEONLY
Indicates this may be read from or written to.
ENTRY
Indicate entry point of a program
END
Indicates end of a program
DCB
Define Constant byte (8 bits)
DCW
Define Constant word (16 bits)
DCD
Define Constant Data (32 bits) [Tables, Name, Message, Subroutine Addresses]
EQU
Gives a symbolic name to a numeric constant, a register-relative value or
a PC-relative value., ABC EQU 2 ; assign 2 to ABC
ALIGN
It align the current location within the code to a word (4 byte) boundary.
EXPORT
Export function name to be used by external modules
SPACE
Reserves a zeroed block of memory. [ALIGN must be used]
Assembler Directives
• EQU — equate a name with something
Val EQU 42
 So here, Val is a label, EQU is assembler directive, and
42 is a constant.
 This would mean we can use Val to mean 42 in our code
 Equates are replaced at assembly time — like #defines
are in C
 Makes the code much more readable
Practice Exercises