ADPLL Performance Summary
State-of-the-Art ADPLL
[1] ISSCC 2008
[2] ISSCC 2010
[3] ISSCC 2010
[4] ISSCC 2011
Technology
0.13um CMOS
90nm CMOS
65nm CMOS
65nm CMOS
Supply Voltage
1.5V
1.2V
1.2V
1.2V
Reference
Frequency
Output Frequency
50MHz
40MHz
40MHz
40MHz
3.67GHz
2.1-2.8GHz
3-3.6GHz
2.9-4GHz
Loop Bandwidth
500kHz
500kHz
3MHz
312KHz
TDC gate delay
6ps
5ps
4ps
--
In-band Phase
Noise
Spur
-108dBc/Hz
@ 400kHz
-53dBc
-105dBc/HZ
@200kHz
40dBc
-104dBc/Hz
@400kHz
-57dBc
-101dBc/HZ
@200kHz
-42dBc
Power
Consumption
39mW
9.72mW
80mW
4.5mW
Reference
• [1] C. M. Hsu, et al., “A Low-noise, Wide-BW 3.6GHz Digital ΔΣ
Fractional Synthesizer with a Noise Shaping Time-to-Digital
Converter and Quantization Noise Cancellation,” ISSCC Dig. Tech.
Papers, pp. 340-341, Feb. 2008.
• [2] T.Tokairin, et al.,” A 2.1-to-2.8GHz All-Digital Frequency
Synthesizer with a Time-Windowed TDC,” ISSCC Dig. Tech. Papers,
pp. 470-471, Feb 2010
• [3] M.Zanuso, et al.,”A 3MHz-BW 3.6GHz Digital Fractional-N PLL
with Sub-Gate-Delay TDC, Phase-Interpolation Divider, and Digital
Mismatch Cancellation,” ISSCC Dig. Tech. Papers, pp. 476-477, Feb
2010
• [4] Tasca, D, et al., “A 2.9-to-4.0GHz fractional-N digital PLL with
bang-bang phase detector and 560fsrms integrated jitter at
4.5mW power” ISSCC Dig. Tech. Papers, pp. 88-90, Feb 2011