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MT6328 PMIC Technical Brief
Version:
Release date:
1.0
2014-09-17
Specifications are subject to change without notice.
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT6328
PMIC Technical Brief
Confidential A
Document Revision History
Revision
1.0
Date
2014-09-09
MediaTek Confidential
Author
Luke Tsai
Description
Initial draft
© 2014 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT6328
PMIC Technical Brief
Confidential A
Table of Contents
Document Revision History ............................................................................................. 2
Table of Contents .............................................................................................................. 3
1
Overview .................................................................................................................. 4
1.1
Features ..................................................................................................................................... 4
1.2 Applications ............................................................................................................................... 4
1.3 General Descriptions................................................................................................................. 4
1.4 Ordering Information ................................................................................................................5
1.5 Top Marking Definition .............................................................................................................5
1.6 Pin Assignments and Descriptions .......................................................................................... 6
2
MT6328 Packaging .................................................................................................. 11
2.1 Package Dimensions ................................................................................................................ 11
Appendix ........................................................................................................................ 12
Lists of Tables and Figures
Table 1-1. MT6328 pin descriptions ............................................................................................................ 6
Figure 1-1. MT6328 VFBGA 206 (6.6x6.6mm) pin assignment ................................................................ 6
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT6328
PMIC Technical Brief
Confidential A
1
1.1
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1.2
Overview
Features
Handles all 2G/3G/4G smart phone
baseband power management
Input range: 2.5 ~ 4.5V
5 buck converters and 28 LDOs
optimized for specific 2G/3G/4G smart
phone subsystems
Full-set high-quality audio feature:
Supports uplink/downlink audio CODEC.
32K RTC oscillator for system timing, 1.8
and 2.8V clock buffer output
Flexibility for various configurations of
indicator LED current source: 2 ISINK
SPI interface
Li-ion battery charging function
USB Battery Charging Specification ver
1.1/1.2 (BC1.x) Compliance
Over-current and thermal overload
protection
Programmable under voltage lockout
protection
Watchdog reset
Flexibility hardware PMIC reset function
Power-on reset and start-up timer
Precision voltage, temperature, and
current measurement fuel gauge
206-pin VFBGA package
phones, containing 5 buck converters and 28
LDOs optimized for specific 2G/3G/4G smart
phone subsystems.
LED drivers support up to 2 channels of LEDs
with independent control. Flexible control
includes register mode, PWM mode and breath
mode.
Sophisticated controls are available for powerup, battery charging and the RTC alarm.
MT6328 is optimized for maximum battery life,
allowing the RTC circuit to stay alive without a
battery for several hours.
MT6328 adopts SPI interface and 2 SRCLKEN
control pins to control buck converters, LDOs,
and various drivers; it provides enhanced
safety control and protocol for handshaking
with BB.
MT6328 is available in a 206-pin VFBGA
package. The operating temperature ranges
from -25 to +65°C.
Applications
MT6328 is ideal for power management of 2G,
3G and 4G smart phones and other portable
systems.
1.3
General Descriptions
MT6328 is a power management system chip
optimized for 2G/3G/4G handsets and smart
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MT6328
PMIC Technical Brief
Confidential A
1.4
Ordering Information
Order #
Marking
MT6328V/A
1.5
Temp. range
Package
-25 ~ +65°C
VFBGA 206L
Top Marking Definition
MT6328V/A
YYWW: Date code
$: Random code
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MT6328
PMIC Technical Brief
Confidential A
1.6
Pin Assignments and Descriptions
Figure 1-1. MT6328 VFBGA 206 (6.6x6.6mm) pin assignment
Table 1-1. MT6328 pin descriptions
A1,B1
A2,B2
A3,B3
C3
Ball
Symbol
AVDD45_VSYS22
VSYS22
AVSS45_VSYS22
VSYS22_FB
I/O
PWR
O
GND
I
Description
Power supply of VSYS22
SW node of VSYS22
VSYS22 ground
BUCK VSYS22 feedback pin
B4,C5,C4
AVDD45_VCORE1
PWR
Power supply of VCORE1
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MT6328
PMIC Technical Brief
Confidential A
Ball
A5,A6,B5
B6,C6,D6
C1
C2
A11,B10,B11,C10,D10
Symbol
VCORE1
AVSS45_VCORE1
AVSS45_VCORE1_FB
VCORE1_FB
AVDD45_VPROC
A7,B7,B8,C7,D7
VPROC
A9,B9,C8,C9,D9
AVSS45_VPROC
GND
VPROC ground
B15
C16
B13,C13,D13
A12,B12,C12
C11,D11,D12
E13
C14
A16
A15
A14
B14
C15
B16
D5,E5,E6,E7,E8,E9,
E10,E11,E12,F11,F12,
G6,G7,G8,G9,G10,G
11,G12,H6,H7,H8,H
9,H10,H11,H12,J6,J
7,J8,J9,J10,J11,K7,K
8,K9,K10,K11,L7,L8,
L9,L10,L11,L12
T13
T8
K1
AVSS45_VPROC_FB
VPROC_FB
AVDD45_VLTE
VLTE
AVSS45_VLTE
AVSS45_VLTE_FB
VLTE_FB
AVDD45_VPA
VPA
AVSS45_VPA
VPA_FB
AVDD45_SMPS
AVSS45_SMPS
I
I
PWR
O
GND
I
I
PWR
O
GND
I
PWR
GND
Remote sense on ground of VPROC
BUCK VPROC feedback pin
Power supply of VLTE
SW node of VLTE
VLTE ground
Remote sense on ground of VLTE
BUCK VLTE feedback pin
Power supply of VPA
SW node of VPA
VPA ground
BUCK VPA feedback pin
Power supply of buck controller
Ground of buck controller
AVSS45_LDO
GND
LDO ground
AVDD45_LDO1
AVDD45_LDO2
AVDD45_LDO3
PWR
PWR
PWR
Power supply input of LDO group1
Power supply input of LDO group2
Power supply input of LDO group3
T11
AVDD45_LDO4
PWR
Power supply input of LDO group4
M2
H3
J2
E1
F1
G1
P9
T16
F10
F9
J1
E4
H2
T14
E3
AVDD45_LDO5
AVDD22_LDO1
AVDD22_LDO1
AVDD22_LDO2
AVDD22_LDO3
AVDD22_LDO4
VTCXO_0
VTCXO_1
VRF18_0
VRF18_1
VM
VSRAM
VCAMD
VCAMA
VCAMIO
PWR
PWR
PWR
PWR
PWR
PWR
O
O
O
O
O
O
O
O
O
Power supply input of LDO group5
Power supply input of SYS LDO group1
Power supply input of SYS LDO group1
Power supply input of SYS LDO group2
Power supply input of SYS LDO group3
Power supply input of SYS LDO group4
VTCXO_0 output voltage
VTCXO_1 output voltage
VRF18_0 output voltage
VRF18_1 output voltage
VDRAM output voltage
VSRAM output voltage
VCAMD output voltage
VCAMA output voltage
VCAMIO output voltage
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I/O
O
GND
I
I
PWR
O
Description
SW node of VCORE1
VCORE1 ground
Remote sense on ground of VCORE1
BUCK VCORE1 feedback pin
Power supply of VPROC
SW node of VPROC
© 2014 MediaTek Inc.
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT6328
PMIC Technical Brief
Confidential A
H5
F2
K2
K4
R9
R10
T15
P11
R11
N11
F3
R13
R12
R14
R15
H4
J4
E2
D2
D3
M7
Ball
Symbol
VCAMAF
VIO18
VIO28
VMC
VMCH
VEMC_3V3
VEFUSE
VUSB33
VSIM1
VSIM2
VCN18
VCN28
VCN33
VAUD28
VAUX18
VGP1
VIBR
PWRKEY
EXT_PMIC_EN
RESETB
WDTRSTB_IN
D4
PMU_TESTMODE
I
L4
L3
N5
L6
K6
M6
N2
N6
P4
P8
R5
M12
M14
P14
N13
VREF
AVSS45_VREF
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_CSN
UVLO_VTH
HOMEKEY
FSOURCE
SRCLKEN_IN0
SRCLKEN_IN1
AVDD18_AUXADC
ACCDET
AUXADC_VIN
AVSS18_AUXADC
O
GND
IO
IO
I
IO
I
I
PWR
I
I
PWR
I
I
GND
N3
BATSNS
I
N4
ISENSE
I
M4
VSYSSNS
PWR
N1
M1
D15
CHG_DP
CHG_DM
CS_P
I
I
I
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I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
O
I
Description
VCAMAF output voltage
VIO18 output voltage
VIO28 output voltage
VMC output voltage
VMCH output voltage
VEMC_3V3 output voltage
VEFUSE output voltage
VUSB33 output voltage
VSIM1 output voltage
VSIM2 output voltage
VCN18 output voltage
VCN28 output voltage
VCN33 output voltage
VAUD28 output voltage
VAUX18 output voltage
VGP1 output voltage
VIBR output voltage
PWRKEY button
Ext PMIC enable pin
System reset release signal
Watchdog reset from AP
PMU test mode signal (tied to GND in normal
operation)
Bandgap reference voltage
Ground for bandgap
SPI control interface
SPI control interface
SPI control interface
SPI control interface
UVLO threshold control pin
HOMEKEY button
EFUSE power source
Source clock enable pin 0
Source clock enable pin 1
1.8V power supply of AUXADC
Accessory detection input
AUXADC input
AUXADC ground
Negative terminal for battery's charging current
sensing resistor
Positive terminal for battery's charging current
sensing resistor
VSYS supply input for internal block and UVLO
detection
USB D+ for BC1.x standard
USB D- for BC1.x standard
Fuel gauge ADC input pin
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT6328
PMIC Technical Brief
Confidential A
E15
J5
P13
Ball
Symbol
CS_N
FCHR_ENB
TREF
R1
VCDT
I
R2
VDRV
O
P2
BATON
I
P3
CHRLDO
O
R8
AVDD28_RTC
O
R7
AVSS28_RTC
GND
T6
XIN
IO
R6
XOUT
IO
T1
R3
M9
P5
R4
R16
P15
N14
T2
T3
T5
F15
G15
H14
F13
G13
G14
F16
E16
N15
N16
D14
E14
M15
M16
L13
K13
L14
K14
H15
H16
XOSC_EN
ENBB
RTC32K_2V8
RTC32K_1V8_0
RTC32K_1V8_1
ISINK0
ISINK1
AVSS45_ISINK
DVDD18_IO
DVDD18_DIG
DVSS18_IO
AU_FLYN
AU_FLYP
AU_REFN
AVSS18N_AUD
AVDD18_AUD
AVSS18_AUD
SPK_P
SPK_N
AU_MICBIAS1
AU_MICBIAS0
AVDD45_SPK
AVSS45_SPK
AU_VIN0_N
AU_VIN0_P
AU_VIN1_N
AU_VIN1_P
AU_VIN2_N
AU_VIN2_P
AU_HPL
AU_HPR
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I/O
I
I
O
O
O
O
O
O
IO
IO
GND
PWR
O
GND
O
O
GND
PWR
PWR
GND
O
O
O
O
PWR
GND
I
I
I
I
I
I
O
O
Description
Fuel gauge ADC input pin
Force charging disable pin
TREF output voltage
Fractional charger input voltage for charger
detection
Charger current drive output
Battery NTC pin for battery and its temperature
sensing
CHRLDO output voltage
RTC LDO output. Supply of RTC macro where
backup battery can be added.
RTC ground
32K crystal connection port while using crystal to
generate 32kHz clock
32K crystal connection port while using crystal to
generate 32kHz clock
XOSC_EN control of RF chip
ENBB control of RF chip
VRTC domain 32kHz clock output
VIO18 domain 32kHz clock output
VIO18 domain 32kHz clock output
ISINK channel 0
ISINK channel 1
ISINK ground
Digital IO power
VDIG18 output voltage
Digital IO ground
Flying capacitor bottom
Flying capacitor top
Audio reference ground
Audio -1.8V supply
1.8V power supply of Audio
Audio DL ground
Positive output of internal speaker amp
Negative output of internal speaker amp
Microphone Bias 1
Microphone Bias 0
Power supply of SPK
GND of internal speaker amp
Microphone channel 0 negative input
Microphone channel 0 positive input
Microphone channel 1 negative input
Microphone channel 1 positive input
Microphone channel 2 negative input
Microphone channel 2 positive input
Earphone left channel output
Earphone right channel output
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Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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MT6328
PMIC Technical Brief
Confidential A
Ball
J12
J14
K15
M10
N8
K12
K16
M8
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Symbol
CLK26M
AU_HSN
AU_HSP
AUD_DAT_MISO
AUD_DAT_MOSI
AVSS28_AUD
AVDD28_AUD
AUD_CLK
I/O
I
O
O
IO
IO
GND
PWR
I
Description
26MHz clock input
Handset negative output
Handset positive output
Audio control interface
Audio control interface
Audio UL ground
2.8V supply of Audio UL
Audio control interface
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MT6328
PMIC Technical Brief
Confidential A
2
2.1
MT6328 Packaging
Package Dimensions
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MT6328
PMIC Technical Brief
Confidential A
Appendix
MediaTek Confidential
© 2014 MediaTek Inc.
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