2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN)
New realizations of OTRA based sinusoidal oscillator
Rajeshwari Pandey1, Neeta Pandey2, Gurumurthy Komanapalli3, Alok Kumar Singh4, Rashika Anurag5
1,2,3,4,
5
Department of Electronics and Communication
Delhi Technological University, Delhi, INDIA
1
rajeshwaripandey@gmail.com,2n66pandey@rediffmail.co
m, 3murthykgm@gmail.com, 4aloksingh.dce@gmail.com,
Department of Electronics and Communication,
JSS Academy of Technical Education, NOIDA,
Uttar Pradesh,
5
raashika@rediffmail.com
Abstract— Two new topologies of OTRA based sinusoidal
oscillators are presented. The first topology makes use of lossless
integrators. whereas the second topology is designed using a
second order all pass section. The proposed topologies can be
made fully integrated by implementing the resistors using
matched transistors operating in linear region, which facilitates
electronic tuning of oscillation frequency. The non-ideality
analysis of the circuits is also given and for high frequency
applications self compensation can be used. Workability of the
proposed oscillators is verified through PSPICE simulations
using 0.5ȝm AGILENT CMOS process parameters. The total
harmonic distortion (THD) for both the designs is found to be
quite low.
OTRA has been extensively used as an analog building block
for realizing a number of sinusoidal oscillators [8,9,13-21]
which can be classified as those providing single phase [1315], quadrature phase [8,9 16-19] and multiphase [20,21]
ouputs.
In this paper two new realizations of OTRA based sinusoidal
oscillators have been presented. One of the proposed
configurations makes use of two lossless integrators connected
in inverting and non inverting mode respectively whereas the
other configuration uses a second order allpass section with
unity feedback to form close loop. The proposed structures
can be made fully integrated by implementing the resistors
using matched transistors operating in linear region and thus
can be tuned electronically.
Keywords— Sinusoidal oscillator, OTRA, THD, Analog signal
processing
II.
I.
INTRODUCTION
Oscillators are an important class of circuits and find wide
application in communication, instrumentation, measurement,
and control systems [1]. For these applications low value of
total harmonic distortion (THD) is an essential requirement as
higher harmonics have detrimental effects on electrical
equipment. A variety of sinusoidal oscillators using op-amps,
a representative voltage mode analog building block; are
available in the literature [1-3]. However, these configurations
are limited in their high frequency operations due to lower
slew rate and constant gain-bandwidth product of the op-amps.
Over the last few decades current-mode (CM) processing
has emerged as an alternative design technique using current
signals for signal processing [4]. The CM circuits are low
impedance node networks; hence result in low time constant.
This improves system performance in terms of speed and slew
rate. Current- mode signal processing has resulted in
emergence of numerous analog building blocks as mentioned
in [senani] and references cited therin which are used for
realization of various signal processing and generation
circuits. The circuit element Operational Transresistance
Amplifier (OTRA) [5] is one among those and is a current
controlled voltage source (CCVS). Several high performance
CMOS OTRA topologies have been proposed in literature [57] leading to growing interest in OTRA based analog signal
processing and generation circuits [5, 8-21]. In recent past
978-1-4799-5991-4/15/$31.00 ©2015 IEEE
CIRCUIT DESCRIPTION
The OTRA is a high gain current input voltage output device.
The circuit symbol of OTRA is shown in Fig. 1 and the port
characteristics are given by (1), where Rm is transresistance
gain of OTRA. For ideal operations the Rm of the OTRA
approaches infinity and forces the input currents to be equal.
୮
Ͳ
቎ ୬ ቏ ൌ ൥ Ͳ
୫
VO
Ͳ
Ͳ
െ ୫
Ͳ ୮
Ͳ൩ ቎ ୬ ቏
Ͳ ୓
(1)
Figure1. OTRA Circuit symbol
The input and output terminals of the OTRA are characterized
by low impedance, thus the response limitations incurred by
capacitive time constantscan be ignored [5].
913
2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN)
CIRCUIT I
Symbols ‘p’ and ‘n’ represent the non-inverting and the
inverting terminals of the OTRA. As can be seen from the
figure, the voltages at the drain and the source terminals for
both MOSFETs are equal. On taking the difference of the
currents flowing in the two transistors, the non linearity gets
The first proposed oscillator configuration is shown in Fig.2.It
consists of two lossless integrators forming a closed loop,
connected in inverting and non inverting modes respectively.
Figure 2 Circuit I
The characteristic equation of the Circuit I can be deduced as
ଶ
‫ܥ ݏ‬ଵ ‫ܥ‬ଶ ܴଶ ܴଵ ൅ ͳ ൌ Ͳ
Figure 3 Circuit II
(2)
The frequency of oscillation (FO) from (2) can be deteremined
as
FO: ݂ ൌ
ଵ
ଶగ
ଵ
ට஼
(3)
భ ஼మ ோమ ோభ
From (3) it is clear that the circuit of Fig.2 results in sustained
oscillations and the FO can be adjusted by varying either
resistors or capacitor values.
cancelled out. The resistor value realized can be expressed as
CIRCUIT II
ܴൌ
The second design topology is shown in Fig.3. It is based on a
single second order allpass section with unity feedback to form
close loop. Routine analysis of the circuit of Fig. 2 results in
following characteristic equation as
Where
ௐ
‫ܭ‬ே ൌ ߤ‫ܥ‬ை௑ ʹ‫ ݏ‬ଶ ܿଵ ܿଶ ൅ ‫ݏ‬ሾʹ
௖భ
ோమ
൅ʹ
௖మ
ோభ
െ
௖భ
ோభ
ሿ൅
ଶ
ோభ ோమ
ൌͲ
Figure 4. The MOS based resistor
‫ܥ‬ଵ ൌ Ͷ‫ܥ‬ଶ ǡ ܴଶ ൌ Ͷܴଵ FO: ݂ ൌ
ଵ
ට
ଶ஠ େ
ଵ
భ େ మ ୖభ ୖమ
(4)
ଵ
଼஠ୖେ
(9)
KN needs to be determined for the transistors being used to
implement the resistors and ȝ, COX and W/L represent
standard transistor parameters. The MOS based
implementation of Circuit I is shown in Fig.5 (a) and that of
circuit II is depicted in Fig. 5(b).
(5)
III.
(6)
NON IDEAL ANALYSIS
The output of the oscillators may deviate due to non ideality of
OTRA in practice. Ideally the transresistance gain Rm is
assumed to approach infinity. However, practically Rm is a
frequency dependent finite value. Considering a single pole
model for the trans-resistance gain, Rm can be expressed as
Denoting C2 and R1 by C and R respectively and using (5) the
FO can be rewritten as
݂ൌ
(8)
௅
From this characteristic equation the condition of oscillation
(CO) and frequency of oscillation (FO) can be obtained as
CO:
ଵ
௄ಿ ሺ௏ೌ ି௏್ ሻ
(7)
ܴ௠ ሺ‫ݏ‬ሻ ൌ ቆ
The current differencing property of the OTRA makes it
possible to implement the resistors connected to the input
terminals of OTRA, using MOS transistors with complete non
linearity cancellation [5]. Each resistor requires two matched
n-MOSFETs connected in a manner as shown in Fig 4 which
represents a typical MOS implementation of resistance
connected at negative input of OTRA.
ோబ
ೞ
ഘబ
ଵା
ቇ
(10)
Where ܴ଴ is dc transresistance gain. For high frequency
applications the transresistance gain ܴ௠ (s) reduces to
ܴ௠ ሺ‫ݏ‬ሻ ൌ ൬
ଵ
௦஼೛
൰
where
‫ܥ‬௣ ൌ
ଵ
ோబ ఠబ
Taking this effect into account (2) modifies to
914
(11)
2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN)
‫ ݏ‬ଶ ሺܿଵ ൅ ܿ௣ ሻሺܿଶ ൅ ܿ௣ ሻܴଵ ܴଶ ൅ ͳ ൌ Ͳ
and ‫ܥ‬ଶ =25 pF, for circuit II . The simulated value of FO for
both the topologies was observed to be 160 KHz. For Circuit I,
the simulated steady state time domain output and
corresponding frequency spectrum are shown in Fig.6 and
those for Circuit II are depicted in Fig.7.
(12)
From (12) it is found that FO for circuit I changes to
݂ൌ
ଵ
ଶగ
ටሺ஼
ଵ
(13)
భ ା஼೛ ሻሺ஼మ ା஼೛ ሻோభ ோమ
(a)
(a)
(b)
Figure.6 Output of Circuit I (a) Steady state (b) Frequency spectrum
(b)
Figure.5. The MOS-C realization of proposed circuits. (a) Circuit I
(b) Circuit II
Due to nonideality effect of OTRA the characteristic equation
of circuit II modifies to
ଶ
ʹ‫ ݏ‬ሺܿଵ ൅ ܿ௣ ሻሺܿଶ ൅ ܿ௣ ሻ ൅ ‫ݏ‬ሾʹ
ଶ
ோభ ோమ
ሺ௖భ ା௖೛ ሻ
ோమ
൅ʹ
ሺ௖మ ା௖೛ ሻ
ோభ
ൌͲ
െ
(a)
ሺ௖భ ା௖೛ ሻ
ோభ
ሿ൅
(14)
This results in modified FO as
݂ൌ
ଵ
ଶగ
ටሺ஼
ଵ
భ ା஼೛ ሻሺ஼మ ା஼೛ ሻோభ ோమ
(15)
The effect of Cp in (13) and (15) can be eliminated by preadjusting the values of capacitors C1, C2 thus achieving self
compensation.
IV.
(b)
Figure.7 Output of Circuit I (a) Steady state (b) Frequency spectrum
The percentage total harmonic distortion (THD) as recorded in
Table 1 is 2.89% for Circuit I. Similarly for Circuit II the THD
is observed to be 1.07% as has been listed in Table 2.
SIMULATION RESULTS
The proposed sinusoidal undamped oscillators are verified
through simulations using the CMOS implementation of the
OTRA proposed in [6]. The SPICE simulations are performed
using 0.5 ȝm CMOS process parameters provided by MOSIS
(AGILENT). Supply voltages taken are ±1.5V. Both the
topologies are designed for an FO of 159 KHz for which the
component values are taken as ܴଵ ൌ ܴଶ ൌ ͳͲȳǡ ‫ܥ‬ଵ ൌ ‫ܥ‬ଶ ൌ
ͳͲͲ’ for circuit I and ܴଵ ൌ ͳͲȳǡ ܴଶ ൌ40ȳ,‫ܥ‬ଵ =100 pF
CONCLUSION
Two new topologies of OTRA based sinusoidal oscillators are
presented. The first topology makes use of lossless integrators.
whereas the second topology is designed using a second order
all pass section. Both the topologies are electronically
tunable. Workability of the proposed oscillators is verified
915
2015 2nd International Conference on Signal Processing and Integrated Networks (SPIN)
through PSPICE simulations using 0.5ȝm AGILENT CMOS
process parameters. The total harmonic distortion (THD) for
both the designs is found to be quite low.
Table I. Total harmonic distortion for circuit I
Harmoni Frequency Fourier Normalized
(hz)
Compone Component
c
nt
No
1
1.600E+05 2.764E-01 1.000E+00
phase
(deg)
Normalized
phase(deg)
-1.784E+02
0.000E+00
-1.356E+02
2.211E+02
2
3.200E+05 4.466E-03
1.616E-02
3
4.800E+05 3.722E-03
1.347E-02
-1.408E+02
3.943E+02
4
6.400E+05 3.330E-03
1.205E-02
-1.529E+02
5.605E+02
5
8.000E+05 2.856E-03
1.033E-02
-1.669E+02
7.249E+02
6
7
8
9.600E+05 2.266E-03
1.120E+06 1.653E-03
1.280E+06 1.180E-03
8.199E-03
5.980E-03
4.267E-03
-1.798E+02
1.719E+02
1.727E+02
8.904E+02
1.420E+03
1.600E+03
9
1.440E+06 9.843E-04
3.561E-03
-1.785E+02
1.427E+03
10
1.600E+06 9.813E-04
3.550E-03
-1.747E+02
1.609E+03
Communication and Computer Technology, ICCCT-12, pp.77 -80,
2012.
[6] Rajeshwari Pandey, Neeta Pandey, Gurumurthy Komanapalli and
Rashika Anurag, “OTRA Based Voltage Mode Third Order Quadrature
Oscillator,” ISRN Electronics Volume 2014, Article ID 126471, 5 pages
[7] Cem Cakir, Ugur Cam, and Oguzhan Cicekoglu, “Novel Allpass Filter
Con¿guration Employing Single OTRA,” IEEE transactions on circuits
and systems—ii: express briefs, vol. 52, no. 3, pp.122-125, 2005
[8] Ahmet Gokcen and Ugur Cam “MOS-C single ampli¿er biquads using
the operational transresistance ampli¿er,” Int. J. Electron. Commun.
(AEÜ),vol.63, pp. 660–664, 2009.
[9] Rajeshwari Pandey and Mayank Bothra “Multiphase Sinusoidal
Oscillators Using Operational Trans-Resistance Amplifier”, 2009 IEEE
Symposium on Industrial Electronics and Applications (ISIEA 2009).
[10] Rajeshwari Pandey,Neeta Pandey,Mayank Bothra and Sajal K. Paul
“Operational Transresistance Ampli¿er-Based Multiphase Sinusoidal
Oscillators” Journal of Electrical and Computer Engineering Volume
2011, Article ID 586853, 8 pages doi:10.1155/2011/586853
TOTAL HARMONIC DISTORTION = 2.899574E+00 PERCENT
Table II. Total harmonic distortion for circuit II
Frequenc
y
(hz)
Fourier
Compone
nt
1
1.600E+05
8.371E-02
Normalize
d
Componen
t
1.000E+00
Harmonic
No
Phase
(deg)
-8.806E-01
Normalize
d
Phase(deg
)
0.000E+00
2
3.200E+05
7.362E-04
8.794E-03
1.122E+01
1.298E+01
3
4
4.800E+05
6.400E+05
3.345E-05
2.786E-04
3.996E-04
3.328E-03
-2.769E+01
-4.849E+00
-2.505E+01
-1.327E+00
5
8.000E+05
3.295E-04
3.936E-03
2.009E+01
2.449E+01
6
9.600E+05
1.451E-04
1.734E-03
-5.222E-01
4.761E+00
7
1.120E+06
1.527E-04
1.824E-03
-2.931E+01
-2.315E+01
8
1.280E+06
1.213E-04
1.449E-03
1.093E+01
1.798E+01
9
1.440E+06
1.008E-04
1.204E-03
3.406E+01
4.198E+01
10
1.600E+06
1.110E-04
1.326E-03
5.452E+00
1.426E+01
TOTAL HARMONIC DISTORTION = 1.075666E+00 PERCENT
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[4]
[5]
operational transresistance amplifiers with MOS-C realization,” Turkish
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employing single operational transresistance amplifier,” Analog
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