ECE 415/515 –ANALOG INTEGRATED
CIRCUIT DESIGN
OPAMP DESIGN AND SIMULATION
© Vishal Saxena
OPAMP DESIGN PROJECT
R2
vin/2
vout
R1
CL
vin
vout
VCM
RL
VCM
CL
(a)
ECE415/EO
VCM
-vin/2
(b)
R1
CL
R2
ECE515
DESIGN SPECIFICATIONS
TWO-STAGE OPAMP
TWO-STAGE OPAMP: MILLER COMPENSATION
MILLER COMPENSATION EQUATIONS
TWO-STAGE OPAMP: ZERO-NULLING R
VOLTAGE BUFFER COMPENSATION
COMMON-GATE COMPENSATION
CLASS-A STAGE: SLEWING
CLASS-AB STAGE: FLOATING MIRROR
TELESCOPIC+CLASS-AB STAGE
Vbias2
Vbias5
• Note that in this schematic,
Indirect compensation is used.
• Cc is connected between
vout and an internal lowimpedance node
• For Miller compensation,
connect Cc between nodes 1
and 2.
• Vbias5 is generated using a
replica bias circuit
FOLDED-CASCODE STAGE
FOLDED-CASCODE WITH CLASS-AB OUTPUT
• Note that in this
schematic, Indirect
compensation is used.
• Cc is connected
between vout and an
internal lowimpedance node
• For Miller compensation,
connect Cc between
nodes 1 and 2.
FC+CLASS-AB+RAIL-TO-RAIL INPUT
GAIN ENHANCEMENT
• Note that in this
schematic, Indirect
compensation is used.
• Cc is connected
between vout and an
internal lowimpedance node
• For Miller compensation,
connect Cc between
nodes 1 and 2.
CADENCE SPECTRE STB ANALYSIS
SPECTRE STB ANALYSIS
• The STB analysis linearizes the circuit about the DC operating point and computes the
loop-gain, gain and phase margins (if the sweep variable is frequency), for a feedback
loop or a gain device [1].
• Refer to the Spectre Simulation Refrence [1] and [2] for details.
EXAMPLE SINGLE-ENDED OPAMP SCHEMATIC
STB ANALYSIS TEST BENCH
• Pay attention to the iprobe component (from analogLib)
• Acts as a short for DC, but breaks the loop in stb analysis
• Place the probe at a point where it completely breaks (all) the loop(s).
DC ANNOTATION
•
Annotating the node voltages and DC operating points of the devices helps debug the design
•
Check device gds to see if its in triode or saturation regions
SIMULATION SETUP
BODE PLOT SETUP
• Results->Direct Plot-> Main Form
OPEN-LOOP RESPONSE (BODE PLOTS)
•
•
Here, fun=152.5 MHz, PM=41.8°
Best to use the stb analysis with circuit is in the desired feedback configuration
•
Break the loop with realistic DC operation points
SMALL STEP RESPONSE
10mV
Observe the ringing (PM was 41°)
▪ Compensate more (↑ Cc and/or ↑ gm2)
LARGE STEP RESPONSE
500mV
Note the slewing in the output
▪ Class-A: I2/CL
▪ Class-AB: ISS/CC
XF ANALYSIS (FOR CMRR, PSRR)
• For CMRR and PSRR plots, you can use xf analysis.
• Set up your testbench sources for the supplies (of course), but also a source
representing the common mode voltage.
• Then run an xf analysis and tell it where the output of the circuit.
• You can then plot the transfer function from every source to the differential
output of the circuit.
http://www.designers-guide.org/books/dg-spice/ch3.pdf
XF ANALYSIS
• XF analysis
simultaneously
computes individual
transfer functions from
every independent
source to a single
output.
TWO-STAGE OPAMP COMPENSATION
TECHNIQUES
MILLER COMPENSATION
VDD
Compensation capacitor (Cc) between the output of
the gain stages causes pole-splitting and achieves
dominant pole compensation.
VDD
VDD
M3
M4
M7
1
220/2
750Ω
vm
M1
M2
vp
iC ff
M6TL
M6BL
iC fb
CC
10pF 2
Vbias4
▪ Due to feed-forward component of the
compensation current (iC).
100/2
M8T
The second pole is located at
100/2
M6BR
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
CL
30pF
Vbias3
M6TR
An RHP zero exists at
vout
M8B
The unity-gain frequency is
x10
A benign undershoot in step-response due to the RHP
zero
❖All the op-amps presented have been designed in AMI C5N 0.5μm CMOS process with scale=0.3 μm and Lmin=2. The op-amps drive a 30pF off-chip load
offered by the test-setup.
DRAWBACKS OF MILLER COMPENSATION
VDD
• The RHP zero decreases phase
margin
VDD
VDD
M3
M4
M7
1
▪ Requires large CC for compensation
(10pF here for a 30pF load!).
220/2
vm
M1
M2
vp
CC
vout
2
10pF
M6TL
M6BL
Vbias3
M6TR
M8T
M6BR
M8B
Vbias4
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
CL
30pF
100/2
100/2
x10
• Slow-speed for a given load, CL.
• Poor PSRR
▪ Supply noise feeds to the output through
CC.
• Large layout size.
INDIRECT (AHUJA) COMPENSATION
VDD
• The RHP zero can be eliminated by
blocking the feed-forward compensation
current component by using
VDD
VDD
VDD
M3
vm
M4
M1
M9
1
ic
M2
MCG
vp
M7
220/2
Cc
2
vout
CL
A
30pF
M6TL
M6BL
Vbias3
M6TR
M10T
100/2
M8T
Vbias4
M6BR
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
100/2
M10B
M8B
x10
An indirect-compensated op-amp
using a common-gate stage.
▪ A common gate stage,
▪ A voltage buffer,
▪ Common gate “embedded” in the cascode diffamp, or
▪ A current mirror buffer.
• Now, the compensation current is fed-back
from the output to node-1 indirectly
through a low-Z node-A.
• Since node-1 is not loaded by CC, this
results in higher unity-gain frequency (fun).
INDIRECT (CASCODE) COMPENSATION
VDD
VDD
VDD
M4T
M3T
M3B
A
Vbias2
ic
M4B
VDD
VDD
VDD
M3
M4
M7
M7
1
220/2
110/2
Vbias5
1
M1T
vm
M1
M2
vp
CC
1.5pF
M6TL
M6BL
vout
2
CL
vm
A
M1B
M2B
30pF
CC
vp
1.5pF
vout
2
CL
ic
30pF
Vbias3
M6TR
M8T
Vbias4
M6BR
M8B
50/2
Vbias3
50/2
30/2
M8T
M5T
Vbias4
30/2
M5B
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 44/2.
M2T
Indirect-compensation using
cascoded current mirror load.
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
M8B
100/2
100/2
Indirect-compensation using
cascoded diff-pair.
Employing the common gate device “embedded” in the cascode structure for indirect compensation
avoids a separate buffer stage.
✓
✓
Lower power consumption.
Also voltage buffer reduces the swing which is avoided here.
INDIRECT COMPENSATION:
MODELING
C
c
ic
Rc
A
vin
A1
A2
1
Differential
Amplifier
vout
The compensation
current (iC) is indirectly
fed-back to node-1.
2
Gain Stage
Block Diagram
vout
ic 
1 sCc  Rc
1
2
+
gm1vs
R1
+
Cc
C1
gm2v1
C2
R2
vout
Rc
-
-
Small signal analytical model
RC is the resistance
attached to node-A.
Resistance roc is
assumed to be large.
The small-signal model
for a common gate
indirect compensated opamp topology is
approximated to the
simplified model seen in
the last slide.
gmc>>roc-1, RA-1,
CC>>CA
INDIRECT COMPENSATION: EQUATIONS
j
 un

p3
p2
z1
p1
• Pole p2 is much farther away from fun.
•
Can use smaller gm2=>less power!
• LHP zero improves phase margin.
• Much faster op-amp with lower power and
smaller CC.
• Better slew rate as CC is smaller.
LHP zero
EFFECT OF LHP ZERO ON SETTLING
• Ringing in closed-loop step response
•
•
Magnitude (dB)
Causes gain flattening and degrades PM
Hard to push out due to topology restrictions
40
20
0
-20
-40
180
135
90
45
Used to be a benign undershoot with the RHP zero, here it can
be pesky
Is this settling behavior acceptable?
• Watch out for the ωz,LHP for clean settling
behavior!
• When using indirect compensation be aware of
the LHP-zero induced transient settling issues
0
2
4
10
6
10
8
10
10
Frequency (Hz)
Closed Loop Step Response
1
0.9
0.8
0.7
0.6
Amplitude
•
•
60
Phase (deg)
• In certain cases with indirect compensation, the
LHP-zero (ωz,LHP) shows up near fun.
Bode Diagram
80
0.5
0.4
0.3
0.2
0.1
0
0
0.2
0.4
0.6
Time (sec)
0.8
1
1.2
-7
x 10
Small step-input settling in follower
configuration
REFERENCES
1. The Designer’s Guide to SPICE and Spectre: http://www.designersguide.org/books/dg-spice/
2. Spectre User Simulation Guide, pages 160-165: http://www.designersguide.org/Forum/YaBB.pl?num=1170321868
3. M. Tian, V. Viswanathan, J. Hangtan, K. Kundert, “Striving for Small-Signal
Stability: Loop-based and Device-based Algorithms for Stability Analysis of
Linear Analog Circuits in the Frequency Domain,” Circuits and Devices, Jan
2001. http://www.kenkundert.com/docs/cd2001-01.pdf
4. https://secure.engr.oregonstate.edu/wiki/ams/index.php/Spectre/STB
5. Saxena V, Baker R.J., “Indirect feedback compensation of CMOS op-amps,”
IEEE WMED 2006.
REFERENCES
6. Saxena V, Baker R.J., “Indirect compensation techniques for three-stage
CMOS op-amps,” IEEE MWSCAS 2009.
7. Saxena V., Baker R.J., “Indirect compensation techniques for three-stage
fully-differential op-amps,” IEEE MWSCAS 2010.
8. Saxena V. “Indirect Feedback Compensation Technique for Multi-Stage
Operational Amplifiers,” MS Thesis, Boise State University, 2007.