Horizontal Technologies RF Test & Measurement Spectral Monitoring/ SigInt Radio Prototyping LabVIEW RIO for RF (FPGA-based processing) PXI Platform (Chassis, controllers, baseband modules) RF hardware building blocks – synthesizers, microwave components,… 1 Communications Design (initial prototype) • • • • Low Cost Flexible Portable Radio (design verification) • • • • • Calibration Low Phase Noise Precise measurement Real-time High Bandwidth 2 Communications Design in LabVIEW LabVIEW Modulation Toolkit • Analog and Digital modulation formats AM, FM, PM ASK, FSK, MSK, GMSK, PAM, PSK, QAM Custom • Visualization 2D and 3D Eye, Trellis, Constellation • Modulation Analysis BER, MER, EVM, burst timing, frequency deviation, ρ (rho) • Impairments Additive White Gaussian Noise (AWGN) DC offset, Quadrature skew, IQ gain imbalance, phase noise • Equalization, Channel Coding, Channel Models 3 FPGA Processing with NI FlexRIO • • • • • • Xilinx Virtex-5 SXT-series FPGAs Direct access to FPGA GPIO Use with adapter module for I/O Peer-to-peer streaming • 800 MB/s across PXI Express backplane • 16 simultaneous streams Onboard DRAM • 2x 256 MB banks • 1.6 GB/s per bank Enhanced Synchronization • Share PXI 10 MHz reference clock or DSTAR_A with adapter module http://zone.ni.com/devzone/cda/tut/p/id/4799 http://sine.ni.com/nips/cds/view/p/lang/it/nid/208164 4 Field Programmable Gate Array (FPGA) PROGRAMMABLE INTERCONNECT I/O BLOCK Source: Xilinx CONFIGURABLE LOGIC BLOCK (CLB) A semi-conductor device containing many gates (logic devices). A wiring list downloaded to the FPGA determines the gate connections and the functionality. 5 5 LabVIEW FPGA Code Abstraction Counter Analog I/O LabVIEW FPGA I/O with DMA VHDL 6 ~4000 lines How: From LabVIEW to Hardware Translation Optimization Synthesis Bit Stream VHDL Generation Analysis Logic Reduction Place and Route Timing Verification Generation Download / Run 7 LabVIEW FPGA IPNet ni.com/ipnet Maths Signal Processing Data Manipulation and Transfer RF and Communications Digital Protocols Data Acquisition Signal Generation Control Sensor Simulation Encryption Vision More than 200 IP cores and examples 8 IP Integration Node Use Core Generator or Custom VHDL Configure IP Integration Node and Generate Simulation Model Use the IP Block Using Standard LabVIEW I/O Interfaces 9 Direct Access to Preexisting Xilinx CORE Generator IP Libraries 10 NI PXI Express System Streaming Rates 800 MB/s Streaming to/from Controller Memory Can sustain 7 unidirectional streams at 800 MB/s for a total of 5.6GB/s 700 MB/s 700 MB/s Streaming to/from Disk PeerPeer-toto-Peer Streaming Can sustain 4 streams at 700 MB/s for 2.8GB/s/direction (5.6GB/s 5.6GB/s total system) Can sustain 8 streams at 700 MB/s for 5.6GB/s/direction (11.2GB/s 11.2GB/s total system) Host PC Payload Generation Vector Signal Generator FPGA Coding Arbitrary Waveform Generater Modulation Upconverter An example... Payload Analysis RF OUTPUT Demodulation RF INPUT RF INPUT Decoding Diversity Processing Downconverter Downconverter Digitiser Digitiser Vector Signal Analyser Vector Signal Analyser Shared Local Oscillator 12 PXIe-8133 Payload Generation PXIe-5663 PXIe-7965R Coding Arbitrary Waveform Generater Modulation Upconverter An example... Payload Analysis RF OUTPUT Demodulation RF INPUT RF INPUT Decoding Diversity Processing Downconverter Downconverter Digitiser Digitiser PXIe-5673 PXIe-5673 Shared Local Oscillator 13 NI-Ettus Research “USRP”: Universal Software Radio Peripheral • Most popular R&D platform for SDR / Communications • PC-hosted computation: USB 2.0 / Gigabit Ethernet GNU Radio the gnu software radio C++ 14 TX SMA RX SMA ? BUS 15 Signal Processing (PC) Software Radio | Receiver I (t ) cos(2πf ct ) + Q(t ) sin(2πfct ) BUS I(t) Mixer ADC RX o SMA 0 Amp o 90 Mixer Tunable Oscillator fc ADC Q(t) fc = center frequency of interest 16 Signal Processing (PC) Software Radio | Receiver Support multiple antennas RX 1 SMA Antialiasing filters BUS Switch Mixer LPF ADC LPF ADC 1 Gb Ethernet RX 2 o SMA Amp 0 o 90 Mixer 900 MHz Tunable Oscillator 40 MHz 100 MS/s ADC LPF • Low pass filters chosen to be below 50MHz Nyquist criteria. 17 Signal Processing (PC) Software Radio | Receiver RX 1 SMA BUS Switch Mixer LPF ADC RX 2 o SMA Amp 0 Mixer 900 MHz Tunable Oscillator 3.2 Gb/s o 90 LPF 1 Gb Ethernet ADC 40 MHz 100 MS/s ADC LPF Data Rate Calculation: 100 Million Samples/sec x 16 bits/Sample x 2 = 3.2 Gigibits/second BUS = 1 Gb Ethernet … down-conversion is needed to ~ 25 MS/s or less. 18 Signal Processing (PC) Software Radio | Receiver RX 1 SMA Mixer LPF ADC DDC: Digital Down-converter LPF ADC DDC: Digital Down-converter RX Control RX 2 o SMA BUS FPGA Switch Amp 0 o 90 Mixer 900 MHz Tunable Oscillator 1 Gb Ethernet 40 MHz 100 MS/s ADC LPF Data Rate Calculation: 100 Million Samples/sec x 16 bits/Sample x 2 = 3.2 Gigibits/second BUS = 1 Gb Ethernet … down-conversion is needed to ~ 25 MS/s or less. 19 Signal Processing (PC) Software Radio | Receiver LPF DAC Digital Upconverter LPF DAC DUC: Digital Up-converter TX Control Mixer RX 1 TX 1 o Amp SMA 0 o 90 Mixer Switch Tunable Oscillator Mixer LPF ADC DDC: Digital Down-converter LPF ADC DDC: Digital Down-converter RX Control RX 2 o SMA Amp BUS FPGA 0 o 90 Mixer Tunable Oscillator NI USRP-2920 System Diagram 20 Signal Processing (PC) Radio | NI USRP System Diagram PXI RF System NI PXIe-5450 NI PXI-2598 NI PXI-5690 NI PXIe-5611 RF RF Signal Generator RF Switch Gain/Attenuator Upconverter NI PXIe-8133 Controller NI PXI-5652 NI PXI-5690 NI PXIe-5601 RF Downconverter NI PXIe-5622 RF Signal Analyzer NI PXI-5652 RF Signal Generator NI PXIe-1075 Chassis 21 NI USRP Tunable RF Transceiver Front Ends Signal Processing and Synthesis NI LabVIEW to develop and explore algorithms NI Modulation Toolkit and LabVIEW add-ons to simulate or process live signals Frequency Range 50 MHz – 2.2 GHz (NI-2920) 2.4 GHz & 5.5 GHz (NI-2921) Applications FM Radio TV GPS GSM ZigBee Safety Radio OFDM Passive Radar Dynamic Spectrum Access 1 Gigabit Ethernet to PC Plug-and-play capability Up to 25 MS/s baseband IQ streaming 22 NI-USRP Driver Software Initialize Configure Start Read IQ Stop 23 Close NI-USRP Driver Software Initialize Configure Start Read IQ Stop 24 Close Teaching Lab | Packet Radio & OFDM Digital Communications Labs by Dr. Robert Heath, UT Austin 1 2.1 2.2 3 4 5 6 7 8 AWGN Simulator Modulation /Demodulation Pulse Shaping Energy Detection Equalization Frame Detection Intro to OFDM Frequency Correction & Sync OFDM Channel Coding (Ships in Bundle) Communications Systems Labs by Dr. Sachin Katti, Stanford 1 Source Coding 2 Packet Communication, Sync, and Channel Correction 3 Modulation 4 Demodulation 5 Design Challenge: Packet based Transceiver (FREE: ni.com/courseware) 25 Source Decoding Channel Decoding Demodulation Downconversion Upconversion Modulation Channel Coding Source Coding Digital Communication System Communications Channel 26 Digital Communication System NI Modulation Toolkit NI Modulation Toolkit 27 Digital Communication System NI Modulation Toolkit NI USRP NI Modulation Toolkit NI USRP 28 Stanford University - Networked Systems Group Needs: • Exposure to real-world signals • Recruit students to RF/Communications early • Prepare students for research Solution: • SDR Platform • Lower learning curve • Maintainable • Affordable “The course evaluations for our class was fantastic. Students rated the class 4.94/5.0, likely one of the highest ratings among all classes in the School of Engineering at Stanford.” Dr. Sachin Katti, ECE Stanford, CA 29