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Hello fellas welome back.
We shall examine the two fundamental architectures used by computer systems in this
lesson and this lesson
comes with a bit of exciting history.
As some of you may know John von Neumann introduced the design of the stored
program computer.
This design is known as the von Neumann architecture and it started a new Epoch of
computers. Von
Neumann introduced a number of parameters for his universal computer.
He said a computer consists of memory an arithmetic logic unit a control unit and input
and output
Also he says all part of the computer are connected together by a bus.
Also the computer structure is independent of the computed problem and the computer is
programmed with
the content of the memory.
He gives more parameters but I wouldn't talk about all of them.
This is the structure of the universal computer proposed by John von Neumann in 1947.
Data is passed to the blocks using the data bus and the control unit controls all other
using the control bus.
Today we are able to integrate the control unit and the arithmetic logic unit into a single
circuit which we call the CPU or the pocessor. Because of this technological
advancement we are
able to simplify the von Neumann architecture.
This is the von Neumann architecture used today in modern computers.
Notice that there is a single bus running from th CPU to the memory.
IO devices are simply connected to this bus.
Next let's take a look at the other architecture, the HARVARD architecture.
As you may know the Mac 2 computer was introduced at Harvard in 1947.
It wasn't as modern as the von Neumann
machine but it introduced a slightly different architecture.
It separated memory for data from memory for instructions thereby coming up with a
structure like this,
with two buses connected to the CPU one for data and one for instructions.
We often simplify the structure of the von Neumann machine to something like this.
The CPU on one side, memory on the other side and a single bus connecting the CPU
and memory and this bus is
known as the data and instruction bus. The Harvard architecture is often simplified into
something like
CPU on one side, memory on the other side and two buses connecting the CPU and
One bus for data another bus for instruction. There are many differences between the
Harvard system and the
von Neumann system
in terms of implementation, cost and performance.
I'll just mention a few differences here.
First and foremost the single bus is simpler for control unit design and therefore
development of control
units become faster and cheaper.
The von Neumann architecture offers a common memory for both data and instructions.
While the Harvard architecture offers separate memory for data and instructions This
allows the
Harvard system to perform two simultaneous memory fetches which the von Neumann
system is not capable
So this is all there is to it, this is very straightforward.
And yes I'll see you in the next lesson.
Hello fellas welocome back. In these next three lessons
we shall look at some of the core extensions that can be placed next to the ARM core.
These extensions improve performance, manage resources and provide extra
functionalities and are
designed to provide flexibility in handling particular applications.
Each ARM family has different extensions available to it.
There are three hardware extensions ARM wraps around the core.
In this lesson we shall take a look at the very first one which is the cache and tightly
As I've mentioned earlier the cache is a block of fast memory placed between the core
and the main memory.
It allows for more efficient fetches from some memory types with a cache the processor
core can run
for majority of the time without having to wait for data from slow external memory.
Most ARM based embedded systems use a single level cache internal to the processor.
ARM has two forms of this
fast accessible memory.
The first form is used with the von Neumann architecture.
And this form which we are currently looking at combines both data and instruction into a
single unified
cache. The load and control and AMBA bus interface units simply helps connect the
memory system to the
AMBA bus which connects to the main memory.
The secondary form of fast accessible memory used by arm is used with the Harvard
and this form has separate fast accessible memories for data and instruction.
And as you may recall the cache provides an overall increase in performance but at the
expense of predictable
execution. Real time systems are deterministic systems they require execution time to be
This can be achieved using the second form of fast accessible memory
called the tightly coupled memory or the TCM. The TCM is a fast SRAM located close to
the core
and guarantees the clock cycles required to fetch instructions or data. TCMs appear as
in address map and it can be accessed very fast.
So in effect they work like the cache. In fact by using
the TCMs and the cache ARM processors have both extra performance boost in our
predictable realtime response.
This is what the modified architecture looks like. The logic and control unit is placed
between the memory management unit and thr core and by memory management unit
I mean the Data TCM, Instruction TCM, Data Cache, Instruction Cache. The TCM and
the cache are
connected to the main memory using the AMBA bus interface like the other two
we just looked at.
So this is all there is to it,
you don't need to understand how to draw this diagram or how to be able to decode it or
anything but it's just
an introduction to fast accessible memory and how the cache memory works.
Because I'm sure you hear about cache memory all the time when you are reading your
mobile phone specifications
or just reading specifications dealing with embedded devices.
This is how cache and tightly coupled memory works.
I'll see you in the next lesson.
Hello fellas welcome back. In this lesson we shall give a very short overview of another
often found close to the ARM core.
This is for memory management. As we have described earlier embedded systems often
use multiple memory
devices and therefore it's usually necessary to have a method to organize these devices
and protect
the system from applications trying to make improper access to the hardware.
This can be achieved using some forms of memory management hardware. ARM cores
have two different types of
memory management hardware.
The first is known as the MPU, the memory protection unit and the MPU provides a form
of limited protection.
And the second is the MMU the memory management unit which provides a much more
comprehensive protection.
There is also the third option of not using memory protection hardware at all.
Non-protected memory is fixed and provides little flexibility and it is normally used for
small and
simple embedded systems that require no protection.
MPU employs a rather simple system that uses a limited number of memory regions.
These regions as we
shall see, are controlled by a set off special registers and each region is defined with
access permissions.
MPU is often used for systems that require memory protection but the systems do not
have very
complex memory maps.
So with a system that has a simple memory map and requires the memory protection the
MP you can simply be
used. The MMU you on the other hand like I just said is very comprehensive.
The M.M. you uses a set of translation tables to provide control over memory.
These tables are stored in the main memory and provide a virtual to physical address
map as well as access
We shall talk a bit more about memory management when we're writing code to
demonstrate how they work.
So this is all there is for memory management now
and I'll see you in the next lesson.
Hello fellas welcome back.
In this lesson we shall explore
another common extension that you find very close to the ARM core which is the coprocessor. The co-processor
extends the features of the core by extending the instruction set or by providing other
registers. More than one co-processor can be added to the ARM core through
the co-processor interface. A dedicated co-processor could take care of the
cache memory, the TCM and other memory management systems. Another coprocessor could just
be that to provide hardware floating point functionality.
Actually the ARM instruction set supports a connection of up to 16 co-processors. These
are numbered from co-processor 0 through core processor 15.
We shall explore the floating point co-processor on the cortex M4 in this course.
So this is a very short introduction of it. I'm going to write actual code to access the coprocessor
and use it for real work.
And I will see you in the next lesson.