A computer should be capable of executing following instructions:
Instruction Set (38 instructions) for the Single-Bus Processor Architecture
Sl.No. Instruction
Action
Op Code
1 NOP
No action
00
2 STP
01
Exit the program ( JUD 00)
3 JUD xx
02
[PC]  xx
4 JUP xx
03
[PC]  [PC] + xx
5 CUD xx
04
[SP]  [SP]–1, [[SP]] [PC], [PC]  xx
6 CUP xx
05
[SP]  [SP]–1, [[SP]] [PC], [PC]  [PC] + xx
7 RTU
06
[PC][[SP]], [SP][SP]+1
8 Unused
07
9 JUR <rn>
08-0F
[PC]  <rn>
10 JCD<fl> xx
10-17
[PC]  xx if <fl> = 1
11 JCA<fl>
18-1F
[PC]  [AR] if <fl> = 1
12 CUR <rn>
20-27
[SP]  [SP]–1, [[SP]] [PC], [PC]  [<rn>]
13 CCD<fl> xx
[SP]  [SP]–1, [[SP]] [PC], [PC]  xx if <fl> = 1 28-2F
14 CCA<fl>
[SP]  [SP]–1, [[SP]] PC], [PC]  [AR] if <fl> = 1 30-37
15 RTC<fl>
38-3F
[PC][[SP]], [SP][SP]+1 if <fl> = 1
16 PSH <rn>
40-47
[SP]  [SP]–1, [[SP]]  [<rn>]
17 POP <rn>
48-4F
[<rn>]  [[SP]], [SP]  [SP]+1
18 MVA <rn>
50-57
[<rn>]  [AR]
19 MVR <rn>
58-5F
[AR]  [<rn>]
20 MVI <rn> xx [<rn>]  xx
60-67
21 STA <rn>
68-6F
[[AR]]  [<rn>]
22 STD <rn>] xx [xx]  [<rn>]
70-77
23 LDA <rn>
78-7F
[<rn>]  [[AR]]
24 LDD <rn> xx [<rn>]  [xx]
80-87
25 NOT <rn>
88-8F
[<rn>]  [<rn>]’
26 INC <rn>
90-97
[<rn>]  [<rn>] + 1
27 DCR <rn>
98-9F
[<rn>]  [<rn>] – 1
28 ADA <rn>
A0-A7
[AR]  [AR] + [<rn>] + CY
29 SBA <rn>
A8-AF
[AR]  [AR] – [<rn>] - CY
30 XRA <rn>
B0-B7
[AR]  [AR]  [<rn>]
31 ANA <rn>
B8-BF
[AR]  [AR]  [<rn>]
32 ORA <rn>
C0-C7
[AR]  [AR]  [<rn>]
33 ADI <rn> xx [<rn>]  [<rn>] + xx
C8-CF
34 SBI <rn> xx [<rn>]  [<rn>] - xx
D0-D7
35 XRI <rn> xx [<rn>]  [<rn>]  xx
D8-DF
36 ANI <rn> xx [<rn>]  [<rn>]  xx
E0-E7
37 ORI <rn> xx [<rn>]  [<rn>]  xx
E8-EF
38 RRC <rn>
F0-F7
Rotate [<rn>] right with CY  LSB
39 RLC <rn>
F8-FF
Rotate [<rn>] left with CY  MSB
<rn> is a placeholder in Instructions using a register: <rn>= R0/R1/R2/R3/R4/R5/R6/R7.
xx represents an instruction operand (number in Hex code) following the Op Code.
<fl> is a placeholder in Branch instructions: <fl> = Z / NZ / C / NC / P / M / PO / PE implies
that the selected flag FL = Z / Z’ / CY / CY’ / S / S’ / Parity Odd / Parity Even.
One architecture was discussed in the course (shown below) which is capable of executing above
instructions.
Architecture based on a Single Internal Data Bus
ESM
LSM
Data
Bus
Operand
Register (OR)
Stack
(SM)
EOR
ROR
LOR
Stack Address
ESP
ISP
DSP
LSP
A
Flags
EPC
IPC
LPC
Program
Counter (PC)
SAF
ALU
Accumulator
(AR)
PM Address
EPM
B
CI
Stack Pointer
(SP)
EAR
RAR
LAR
DM Address
Program
Memory (PM)
Data I/O &
Memory (DM)
EDM
LPM
LIR
Instruction
Register (IR)
Register Array
(RG)
ERG
LDM
LRG
SRG
SFL
RMS
Control Unit
(Microinstruction
Sequence
Generator)
Selected
Flag FL
(FL = 0 if
EFL = 0)
Flag Register
EFL
Microinstruction (Control Signals to all the Modules)
Nomenclature:
EXY : Enables the Output of the module XY on to the Data Bus;
LXY : Enables the Data Input applied to module XY to be loaded into the module at the next Active Clock edge;
IPC, ISP, DSP : Enable Incrementing PC, Incrementing SP and Decrementing SP at the next Active Clock edge;
SXY : Function Select bits for module XY; R0R / RAR : Clears the register OR / AR.
The ALU has 16 functions (4-bit Select SAF):
10 Logic functions A, B, A’, B’, A OR B, (A OR B)’, A AND B, (A AND B)’, A XOR B, (A XOR B)’;
6 Arithmetic functions A + 1, A − 1, A + B + C, A – B – C, 2*A (left shift, C  MSB), A/2 (right shift, C  LSB).
The ALU generates 4 flags – Zero (Z), Carry (C), Sign (S), Parity (P). Flags are not affected by the Unary Logic
functions. Only the C flag is affected by the Shift functions. All flags are affected by the other ALU functions.
The Microinstruction Sequence Generator is Reset, resulting in the next FETCH if RMS = 1 AND FL = 0,
where FL is the FLAG selected by SFL, subject to the condition EFL = 1, i.e. EITHER if the selected FLAG is NOT
set OR if no FLAG is selected (EFL = 0).
You are required to modify that architecture to:
a. Propose a Von Neumann architecture for this Computer.
b. Design the ALU of this processor which can perform addition, subtraction and logical functions as
shared in the above table. Consider the memory can store data of 4 bits (i.e. A of 4 bit and B of 4
bit) only.
c. Execute instruction # 4, 16, 18, 32 & 37 in the proposed architecture. Show the microinstruction
in every clock cycle.
d. Can a processor be designed using Von Neumann architecture supporting parallel processing
using Arithmetic and/or Instruction pipeline? If yes, then propose the changes (in both cases:
Arithmetic and Instruction pipeline) required in the architecture proposed in step a.
e. To remove the resource conflict which may arise due to parallel processing, which hardware
solution that you would like to propose?
Instructions:
1.
2.
3.
4.
5.
6.
7.
8.
It is an open resource assignment therefore you may refer any book/notes/internet resource.
The assignment carries 10 marks. Individual sub question carries 2 marks of weightage.
All assumptions in proposing the design must be mentioned in the first page of response sheet.
It is an open-ended design problem therefore may have multiple answers depending on chosen
design approach.
Use your imagination to propose the design. You are free to choose any hardware in designing
and proposing this architecture.
Collaboration among students is allowed but if found that two or more students have submitted
the same answers then zero marks will be awarded to all such students.
You are required to submit your answers in one pdf file on or before July 15, 2020 (6 PM) after
which your response will not be considered for evaluation and therefore any such defaulter will
get zero marks in this evaluation component.
The file needs to be uploaded on https://exam.niituniversity.in/ only.