National University of Computer and Emerging Sciences
School of Engineering
Islamabad Campus
Remote Final Exam
Total Time: 03 Hrs
Total Marks: 80
Weightage: 40%
ELEC 523 – Analog &
Discrete Electronics
Monday, June 29, 2020
Course Instructor
2:00Pm – 5:00Pm
Rashad Ramzan
_____________________________________________ _____________________
Student Name
Roll No
Section
Signature
Instructions:
1. This exam is open books, open notes.
2. Write legibly with permanent ink-pens. Blue pens are preferred.
3. Use blank A4 size white sheets (used for photo copying) to attempt the exam (portrait
format unless a diagram or table requires landscape). Each sheet of the A4 paper MUST
have the Roll Number, Name, the course code, name of the course and Signature of the
student at the top.
4. For this part, a sample template had been provided to everyone earlier. Use a print of the
template (but write the answers by hand) or use the ones you made by hand.
5. Read the questions carefully for clarity of context and understanding of meaning and
make assumptions wherever required.
6. Once the time is up, use Microsoft Lens, Cam Scanner or an equivalent App to scan all the
handwritten answer sheets/pages in order and convert them into a SINGLE PDF FILE.
7. PDF filename format: EE523-RRRR.pdf where RRRR is your roll number. NOTE that only
ONE PDF FILE IS ACCEPTABLE.
8. When the time of this part of exam is up (5:00 PM), you are supposed to submit within 10
minutes (DO NOT DELAY), i.e., before 5:10 PM.
9. Two submissions must be made, one on the email and the other one the PERSONAL Dr.
Rashad and Dr. Hassan Whatsapp Numbers to EE_523ADE@nu.edu.pk (Email Subject:
EE523 – Final Exam).
About This Exam:
10. All questions carry equal marks (10). There are a total of 08 questions for 80 marks to be
attempted in 03 Hrs.
11. Ample time is being provided if you do the question yourself and do not try to locate the
material from book or notes. All rough work, if any, MUST be the on the side of same
sheet. Extra work would help the instructor understand your thought process.
12. There is no negative marking.
Total
Marks
Q-1
Q-2
Q-3
Q-4
Q-5
Q-6
Q-7
Q-8
Total
10
10
10
10
10
10
10
10
80
CLO2
CLO2
CLO3
CLO1
CLO3
CLO4
Marks Obtained
CLO
CLO5 CLO5
National University of Computer and Emerging Sciences
School of Engineering
Islamabad Campus
Course CLOs.
1. MOS transistor fundamental and introduction to the CMOS manufacturing technology
[PLO-3, PLO-5]
2. Analyze and design the different configurations of single stage amplifiers, multistage
amplifiers and their frequency response
3. Analysis and design of current mirrors combined with actively loaded single stage
amplifiers and effect of negative feedback on these circuits [PLO-3, PLO-5]
4. Description of electronics noise and its calculation for the single stage and differential
amplifiers [PLO-3, PLO-5]
5. Analysis and design of CMOS differential amplifier and OTAs [PLO-3, PLO-5]
Final Remote Exam
Spring 2020
Page 2 of 6
National University of Computer and Emerging Sciences
School of Engineering
Islamabad Campus
Q1. (7+1+2=10) {Single Stage Amplifiers}
In the circuit shown on right.
a) Draw Ac-equivalents and write the expressions for
(Gv=Vo/Vsig), Rin and Rout. (6+0.5+0.5=7)
b) Identify the basic drawback in this circuit? How we
can mitigate this drawback (1)
c) Draw the DC Equivalent circuit and find the
necessary conditions on the biasing (VG and VD
values) so that we have the maximum swing at the
output. Show the swing level on diagram (2)
{C1, C2,C3 are coupling capacitors}
Q2. (1+3+4+2 = 10) {Frequency Response}
In the circuit shown on right.
a) Calculate the mid band gain.
b) Draw appropriate equivalent circuit
and draw the approximate gainfrequency plot showing the low
frequency behavior of the circuit.
c) Draw appropriate equivalent circuit
and draw the approximate gainfrequency plot showing the high
frequency behavior of the circuit
(consider Cgs and Cgd only, ignore
all others)
d) Which steps you will take to increase the BW of this amplifier while keeping the Gain, Rin and
Rout same. (You can propose the changes in the circuit diagram or transistor size or power, etc.
or whatever you like! Crisp and to the point answer are highly desired, no long stories. )
Q3. (6.5+3.5= 10) {Multistage Amplifiers & Feedback}
a) Draw Ac-equivalent and write
the
expressions
for
(Gv=Vo/Vsig), Rin and Rout.
(5+0.5+1=6.5)
b) Identify the feedback in this
circuit and what will happen to
Gv, Rin and Rout if we remove the
feedback completely. Draw the
ac-equivalent and rewrite the
expression. The derivation is
not needed. (3.5)
Final Remote Exam
Spring 2020
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National University of Computer and Emerging Sciences
School of Engineering
Islamabad Campus
Q4. (5+2+3=10) {BJT and Semiconductor Manufacturing}
a) Draw ac-equivalents and write the expressions for (Gv=Vo/Vsig), Rin and Rout. (2+1.5+1.5=7)
b) Diffusion, sputtering, ion implantation are three different process used in semiconductor
manufacturing. What process or processes (from above) are suitable to implant the boron
(or phosphorous) in the intrinsic Si substrate? {Please give the bulleted to the point reasons.
Please do not cut paste the irrelevant text from net. }
c) Wet and dry oxidations are two process to grow the SiO2. Which type of Oxidation process
is used in the follwing and why? (one line reason only)
a. Epitaxial layer protection oxide
b. Gate Oxide
c. Spacer Oxide
d. Ion Implantation Barrier Oxide
e. Plsma Etching Stop Oxide
f. LI Oxide
Final Remote Exam
Spring 2020
Page 4 of 6
National University of Computer and Emerging Sciences
School of Engineering
Islamabad Campus
Q5. (4+2+2+2=10) {Current Sources}
For the current mirror shown here. λP = 0.05V-1, λN = 0.04V-1, µpCOX = 50µA/V2, µnCOX =
110µA/V2, VTHn = VTHp = |0.7|V, and IREF =10 µA; We need the Iout1= Iout2 =100 µA. The W/L of
M1 is 360µm/180 µm.
a) Design the W/L ratios of the M0,
M2, M3, and M4 so that we meet
the desired goal. (1)
b) Find out the output resistance of the
M0 and M4.
c) Find out the minimum VDS needed
for Mo and M4 to work as current
mirrors.
d) If we want to increase the output resistance by 5 to 10 times for this current mirror, what will
the new proposed circuit, draw the schematic? {no calculations or derivation are needed}
Q6. (5+4+1= 10) {Noise in the Circuits}
In the circuit shown
e) Calculate the total output referred voltage
noise PSD of the amplifier. Then refer the
noise to the input of the amplifier.
f) Is the voltage noise you calculated
sufficient to model the noise of amplifier?
If not? Please calculate the input referred
noise current to model the circuit noise
appropriately.
g) What role Rsig plays in this circuit. Assume
it may change from 1K to 10MΩ.
Q7. (8+2 = 10) {Differential Pair and OTA}
a) Design the single stage differential amplifier (OTA) as
shown in Fig that meet the following requirements,
Also calculate the unity gain bandwidth (GBW or ɷUG)
of the designed OTA , The OTA parameters are a) VDD
= 2.5, b) VSS = -2.5, c) CL = 6pF, d) SR ≥ 10 V/µs, e)
Differential Gain ≥ 100, f) -1.5 V ≤ ICMR ≤ 2 V, g) PDiss
≤ 600µW, h) frequency @ P1 ≥ 100kHz, i) λP = 0.05V-1, j)
λN = 0.04V-1, k) µPCOX = 50µA/V2, l) µNCOX = 110µA/V2,
m) VTHn = VTHp = |0.7|V, n) All (W/L) should be less than
100.
b) Calculate the worst input common mode range if a)
VDD = 4 ±0.5V, b) VSS = 0V, c) ISS = 100µA, d) VTHn = VTHp =
|0.7 ± 0.1|V, e) µNCOX = 110µA/V2 ± 10%, f) µPCOX =
50µA/V2 ± 10%, g) (W/L)1 = 5, h) (W/L)3 = 2, i) (W/L)5 =
50
Final Remote Exam
Spring 2020
Page 5 of 6
National University of Computer and Emerging Sciences
School of Engineering
Islamabad Campus
Q8. (8+2 = 10) {Opamp-OTA Design}
a) For the Op-amp shown in figure below calculate the Parameters are λP = 0.05V-1, λN = 0.04V-1,
µPCOX = 50µA/V2, µNCOX = 110µA/V2, VTHn = VTHp = |0.7|V,
a. Differential Gain,
b. Frequency Response
c. Phase Margin
d. Input Common Mode Ranges
e. Slew Rate
f. Total Power dissipation
g. Compensation resistor to remove Right Half Plane zero.
h. Also draw bode plot of the op-amp
(1+1+1+1+1+1+1+1=8)
b) Mathematically evaluate the presence of systematic offset in the op-amp shown in Figure. If
offset exist, how can it be changes without altering gain of op-amp. (2)
The End of Exam!
Best of Luck!
Final Remote Exam
Spring 2020
Page 6 of 6