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Application of microelectronics in
high energy physics and space
technology
Jankowski, M., Cichalewski, W., Makowski, D., Orlikowski,
M., Napieralski, A.
M. Jankowski, W. Cichalewski, D. Makowski, M. Orlikowski, A. Napieralski,
"Application of microelectronics in high energy physics and space
technology," Proc. SPIE 10034, 11th Conference on Integrated Optics:
Sensors, Sensing Structures, and Methods, 100340B (2 September 2016);
doi: 10.1117/12.2244312
Event: 11th Integrated Optics - Sensors, Sensing Structures and Methods,
2016, Szczyrk, Poland
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Invited Paper
Application of microelectronics in
high energy physics and space technology
a
M. Jankowski*a, W. Cichalewskia, D. Makowskia, M. Orlikowskia, A. Napieralskia
Department of Microelectronics and Computer Science, Lodz University of Technology,
Wolczanska 221/223, 90-024, Lodz, POLAND
ABSTRACT
Department of Microelectronics and Computer Science of Lodz University of Technology has long traditions and high
expertise in field of design of electronic systems of various kinds and for several applications. DMCS has expertise in
design of PCB (Printed Circuit Board) based and ASIC (Application Specific Integrated Circuit) based analog, mixedsignal and digital system designs. DMCS design teams participated in numerous national and international scientific
research programs and grants. A series of commercial contracts was also conducted in DMCS. Many of these works
finished with introduction of new systems into scientific installations or putting new product into general markets.
Several DMCS achievements have been successfully patented.
Such extensive experience in connection with wide field of scientific activities, enabled application of DMCS
capabilities to quite different and even unusual electronic system applications aimed at work in extreme environments..
Keywords: high energy physics, space technology, accelerators, radiation detection, integrated systems
1. DMCS AND DESY COOPERATION
1.1 Introduction
The DMCS is cooperating with the Deutsches Electronen Synchrotron (DESY) in Hamburg in scope of design,
development and implementation of various subsystems of linear accelerators for free electron lasers projects (FLASH
and XFEL). This collaboration has been started in 2002 when bilateral agreement between Technical University of Lodz
and DESY has been signed. Additionally in order to participate in new accelerators technology developments, DMCS
became a member of TTC (Tesla Technology Collaboration) in 2005. This community is responsible for the
superconducting niobium cavities technology standardization and extension for current and future high energy physics
experiments as free electron lasers (e.q. FLASH, XFEL) or linear colliders (e.q. ILC).
Cooperation between DESY and DMCS have been supported by two European projects in scope of 6th and 7th
Framework program: Coordinated Accelerator Research in Europe (CARE) and European Coordination for Accelerator
Research and Development (EuCARD).
1.2 Free electron lasers projects in DESY
Nowadays, free electron lasers gain more and more attention from different scientific areas. The laser light with
parameters of: high brilliance (up to 5*10E33(photons/s/mm^2/mrad^2/0,1%bandwith), short wavelength (down to 0.05
nm) and high time resolution (up to 27 k laser flashes per second) will be provided for the European X-ray Free Electron
Laser (European X-FEL) users. This facility will allow conducting studies in subatomic scale. High repetition rate and
high resolution of this device will give response to questions about: biomolecules movement, solids forming process,
chemical reaction progress and many others. That is why possible FEL users’ community is constantly growing.
1.3 Superconducting accelerator as a part of FEL
Both FLASH and XFEL use linear accelerators to accelerate electron bunches to energies of range of GeV. Mentioned
components consists of superconducting niobium cavities (designed and produced in TESLA technology). These
*jankowsk@dmcs.pl; phone +48 (42) 631 26 49; fax +48 (42) 636 03 27; www.dmcs.pl
11th Conference on Integrated Optics: Sensors, Sensing Structures, and Methods, edited by Przemyslaw Struk,
Tadeusz Pustelny, Proceedings of SPIE Vol. 10034, 100340B · © 2016 SPIE
CCC code: 0277-786X/16/$18 · doi: 10.1117/12.2244312
Proc. of SPIE Vol. 10034 100340B-1
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superconducting resonators are supplied with electro-magnetic wave (in ~1,5 ms long pulses) of frequency of 1,3 GHz.
Electrons acceleration is achieved in standing wave inside resonator.
Since particles are accelerated in electromagnetic field its amplitude and phase (in respect to the beam) parameters have
to be carefully monitored and controlled in order to provide optimal cavity to electron beam energy transfer.
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Accelerating field parameter regulation is provided by digital low-level Radio Frequency (LLRF) control system (see
figure 1). In the system, the small fraction of transferred power signal (from niobium resonator) is down-converted to
based-band frequency and sampled in analog to digital converters. Information about accelerating field signal envelope
amplitude and phase is compared to required energy profile and achieved error signal is amplified in proportional
controller. Composed control signal is transferred and up-converted to 1,3 GHz frequency. Such signal is amplified in a
chain of microwave amplifiers and distributed to individual resonator. One of the additional challenges is LLRF system
configuration for described TESLA based system where one LLRF system controls several niobium cavities in the same
time (1 up to 4 cryomodules – 8 cavities each).
Currently LLRF system hardware has been developed according to electronic standard of MTCA.4 (Micro
Telecommunication Computing Architecture [1].
1.4 Participation in LLRF system design
Scientists and researchers from DMCS are cooperating with DESY and other project partners in the scope of design,
development, prototyping and implementation of major components of LLRF systems for FLASH and XFEL projects.
Mentioned team activities are present in every level of system realization which are hardware, firmware and software.
Hardware activities:
In scope of hardware the department team has been involved in design, prototyping and commissioning of FPGA based
control algorithms realization board (TCK7). Additionally digital part of frequency up-converter (Vector Modulator VM) board has been specified, designed and integrated as a part of cooperation work (see figure 2) [2].
On top of this DMCS is participating also in the overall MTCA hardware platform integration.
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LLRF system firmware development:
Our team members were coauthors of LLRF control loop algorithms (P controller, MIMO controller) realized on the
level of FPGA devices. Designed and implemented components for signals transformation (field parameters detection,
signals filtering, error signal evaluation, control signal computation and others) have been in incorporated in the overall
control loop structure and optimized (for minimum chip resources usage and low algorithm latency).
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Software development and implementation:
The complex LLRF system requires comprehensive software which provides such functions as hardware components
management, configuration, measurement data transfer, data archiving, etc.
DMCS team members have been and are actively cooperating with project partners in specification, development and
implementation of following software layers:
•
low level Linux driver for software-hardware data exchange (over PCI-Express),
•
main low level server for LLRF system management. Since this is major interface between LLRF hardware and
system user its reliability and robustness are essential from the point of view of system availability and
performance,
•
slow control algorithms. Several algorithms needed for operation, performance optimization, system availability
maximization, error handling have been developed, evaluated and implemented. Among the others one can
mention about: microwave high power amplifiers linearization, superconducting cavities working parameters
automatic adjustment (loaded quality factor and frequency detuning compensation), vector modulator
imperfections compensation, etc.
•
hardware components management servers (e.q. drift calibration module (DCM) server, power supply module
(PSM) server).
1.5 Superconducting cavities fine mechanical tuning – piezo operation
Since 2003 one of the main study subjects is precise cavity frequency control. Superconducting cavities in presence of
high accelerating field gradients (in a range of 25 MV/m) are mechanically deformed due to the Lorentz force. This
dimension change results in cavity frequency modifications (in a range of one to two resonator bandwidths). In order to
achieve same accelerating conditions (for fixed main oscillator frequency) additional RF power has to be provided from
the high power RF part.
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Resonance control is achieved by means of piezo-electric components excitation (figure 3) [3] . This regulation allows
for cavity supply power reduction which has to be spent in presence of resonator frequency shift [4,5].
The piezo devices are controlled and supplied by developed piezo driver which provides DC and AC signals (up to
+ 70V) for static and dynamic detuning compensation (see figure 4).
Over 10 years of experience with tuner research resulted in advance firmware development and complex software
preparation. System has been integrated with main LLRF controller in order to minimize RF power consumption.
Figure 3. Cavity mechanical fixture with piezo components (model).
1.6 Superconducting cavities cryo-modules tests software preparation
One part of XFEL construction phase is testing and evaluation of every XFEL cryo-module (8 superconducting cavities
each) at the dedicated facility Advanced Module Test Facility (AMTF) [3]. One of the major components of this
evaluation is part during which main parameters of the cavity and module are determined
As a part of cooperation with DESY- DMCS team has been responsible for development, implementation, evaluation
and maintenance of high level software used for:
•
cavities motor based frequency tuners characterization,
•
cavities piezo based frequency tuners characterization,
•
cavities loaded quality factor ranges determination,
•
cavities frequency modes determination,
•
measurement data storage in local and global DESY cavity database,
•
visualization of the measurement results,
•
automatic report generation.
Thanks to this software it is possible to perform evaluation of new cryo-modules (before they will be installed in the
accelerator tunnel) and accept it for installation or give a recommendation for possible repair/improvements activities.
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Figure 4. Overview of the piezo driver board.
1.7 Software for optical synchronization system
In such complex infrastructures like FEL experiments one of issue is to provide synchronization on the level of several
femtoseconds (10fs in case of FLASH/XFEL setups). This task is especially challenging for devices which are located in
the different parts of the project in the distance of several hundred of meters from each other. That is why DESY have
developed laser-based synchronization system (instead of RF based one). This system consists of lasers and optical
setups which are either custom made or commercial solutions.
This precise synchronization is possible also thanks to provided control hardware/software solutions.
Our team activities are mainly focused on software components development for optical synchronization system in
FLASH project. Within this subject mainly two tasks are realized:
•
development and implementation of laser phase-locking server. This software is used for synchronization
between laser repetition rate and other sources (like RF or different laser) ,
•
development and implementation of server for phase-locking of the fiber link stabilization units. This software
main task is to minimize drift of laser pulses at the end of the link (located in different places in the FLASH
experiment).
2. DMCS ACTIVITIES IN ITER PROJECT
2.1 Software for optical synchronization system
As the global energy consumption increases, the provision of efficient and clean energy sources becomes an urging
necessity. One of the most promising ways of energy production is the use of the nuclear fusion in thermonuclear
reactors, such as tokamaks in which the plasma is confined in a toroidal shape using magnetic fields. Both the substrates
and products of the Deuterium-Tritium fusion are not radioactive and are environmentally friendly.
The Lodz University of Technology is also involved in the design of the world’s largest thermonuclear reactor called
ITER. ITER is a large-scale scientific experiment conducted together by researchers from the European Union, India,
Japan, Korea, Russia, China and the United States. It is built on the experience gained from the latest experiments, like
Joint European Torus (JET) and Tore Supra. It will be the most technologically advanced tokamak so far. It is assumed
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to be able to produce 500 MW of energy with efficiency coefficient of 10. The machine is now being constructed at
ITER, non-profit scientific institution in Cadarache, France. As the site construction process progresses, the need for
development of sophisticated control and monitoring system is emerging. The technology being the result of the ITER
project will be able to be commercialized in 2050, but the tokamak assembly should start in 2018 and till then the
concept for its instrumentation shall be finished. Building and operating of the machine requires multidisciplinary effort
not only by the physicists but also by the engineers. The scientific contribution of Poland to the project is currently
limited to physicists involved in plasma experiments. Polish scientists are missing the unique opportunity to gain an
experience in the area of technology and engineering. It is crucial for Poland to get involved in technological aspects of
the experiment and create international network of competence. Since, EU tends to reduce CO2 production the new
technology of energy production is especially crucial for Poland.
2.2 Scope of works
Lodz University of Technology is responsible for a design, development and testing a use cases of data acquisition
systems. The data acquisition systems are built using various platforms Advanced Telecommunications Computing
Architecture (ATCA), MicroTelecommunications Computing Architecture (MicroTCA), and PCIe eXtensions for
Instrumentation (PXIe). The big advantage of xTCA (MicroTCA and ATCA) systems is embedded health monitoring
and advanced system management based on Intelligent Platform Management Interface (IPMI).
2.3 Software for optical synchronization system
A typical Data AcQuisition (DAQ) system is composed of several data acquisition modules, data concentrator and
processing unit, SCADA (Supervisory Control and Data Acquisition) system, data archiver and external processing unit.
The simplified block diagram of the data acquisition system is presented in figure 5.
Analog signals (
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The first prototype was designed the ATCA standard [6-9]. The indisputable advantage of the ATCA standard is its
availability as high as 99.999 %. All architectures providing appropriate number of high-speed links can be used. The
data acquisition modules are the digital-to-analogue multichannel converter boards using the AMC (Advanced
Mezzanine Card) form factor, equipped with the programmable FPGA circuits and one or more gigabit Ethernet
interfaces. All the AMC modules are attached to the Gigabit Ethernet switch, which concentrates the traffic into one 10
Gb Ethernet link connected to the Data Processing unit equipped with several multicore-CPUs. The data processing unit
handles the communication protocol and ensures reliable reception of all the data. This unit is also connected to external
SCADA monitors, additional coprocessors providing computational power, the database that stores data from selected
channels and an additional link allowing controlling of the plant system. The throughputs of all the communication links
in the system are presented in figure 6. The photograph of the cubicle with ATCA-based DAQ system is presented in
figure 7.
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Legend
Throughput required
13.44 Gbit/s
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Figure 6. Block diagram of the system with estimated throughputs.
2.4 The second prototype
The second prototype, Image Acquisition System (IAS) was designed using the MicroTCA.4 standard [10-13]. The
image acquisition system is dedicated for operation with high-resolution fast cameras equipped with Camera Link
interface. Image data provided by the digital camera is received by the frame grabber card and transmitted to the host via
PCIe interface. The modular structure of MicroTCA.4 architecture allows connecting various cameras to a single MTCA
chassis. The system supports nanosecond synchronization with the time reference using IEEE1588 Precision Time
Protocol.
Data from the digital cameras are transferred to the frame grabber module, realized as an Advanced Mezzanine Card
(AMC). The MicroTCA chassis is connected to an external CPU blade via PCIe cable. The image data from the frame
grabber card are transferred using high-performance DMA bulk transfers directly to the host computer memory. The
received data are further processed and send next via 10 Gb Ethernet network for archiving and machine control.
Low level firmware was developed for Xilinx Virtex 5 FPGA. The high level software support for the IAS includes lowlevel Linux drivers, libraries for all components and high-level EPICS-based environment for system control and
monitoring.
2.5 The third prototype
The third prototype was developed using NI PXIe hardware. The PXIe based use case is dedicated for Neutron Flux
Measurement (NFM). The system measures the total emission of neutrons from plasma and therefore allows calculating
the fusion power and its evolution in time domain. The analog signal from the neutron detector is connected to a fast
digitizer module. The pulsed signal is first digitized and then forwarded to a fast real-time data processing unit that
operates in the required mode.
In the PXIe-based NFM Plant I&C implementation the signals from the fission chambers are acquired by a four-channel
ADC module NI 5761R attached to FlexRIO PXIe-7966R located in the NI PXIe-1065 chassis. The NI PXI-6683H
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timing module ensures the synchronization of the system to the ITER time using TCN. The PXIe chassis is connected via
the PCI Express link to the ITER fast controller CPU running CODAC Core System [14]. The ITER CODAC core
system was applied to acquire, process, archive and display measured neutron parameters.
Figure 7. The data acquisition system based on ATCA specification.
3. SPACE-ORIENTED ACTIVITIES AT DMCS
3.1 Introductory works
Other field of scientific research and exploration in DMCS is microelectronics. Part of these activities is focused on
application specific integrated circuit (ASIC) applications in tough environmental conditions.
At first, such works were related to high energy physics application and were aimed at detection of high-energy particle
hits. A part of a multi-project ASIC designed in DMCS (figure 8) consisted of a shift register block based on D-type
latch cells (figure 9), with their inverter cells having intentionally unsymmetrical power levels. It was a measure or
obtaining more susceptibility to effects of high particle energy hits. the Polish semiconductor process line in Piaseczno,
near Warsaw, was used for design of the mentioned ASIC. Such introductory works were a good start for new, largescale projects.
3.2 Project for ESA
For some time, DMCS has been and is involved in an international project of an ASIC intended for operation in open
space conditions, including radiation. DMCS is one of contractors working in a specially founded consortium. The
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consortium members are, also: Astri Polska z o. o. company (a daughter-company of Airbus Space and Defence – former
Astrium), Space Research Center of Polish Academy of Sciences and Integrated Systems Development S.A. (ISD) from
Greece. The circuit has been proposed and accepted by European Space Agency (ESA) in course of one of its tenders.
The role of DMCS is to co-design the ASIC [16] in cooperation with a team Astri Polska.
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3.3 Space grade electronics – requirements
Main property of systems for space applications is ability to operate without any maintenance, which in case of satellites
can mean of too tens of year. So far, many electronic components and subsystems are designed in classic way, as PCBbased circuits. Though, this is well grounded approach, it has its drawbacks. Most important are:
•
sensitivity to a space environment: passive and active analog elements change their parameters over time due to
harsh environment influence [17-19].
•
damage caused by high energetic particles, e.g. Single Event Effects (SEE) [20].
•
Time-consuming and expensive design and development process due to huge number of electronics elements in
discrete electronics [21].
Compared to discrete electronics, ASIC approach provides several improvements:
•
Additional process/design steps that improve resistance to TID, SEE and Single Event Latch-up (SEL).
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•
Lower number of system components, which means more uniform environment impact on the system as well
as simpler reliability analysis 22].
•
Reduction of the whole system dimensions, mass and power requirements.
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3.4 The ASIC under design
The designed ASIC is a DC/DC converter controller [16]. It is environmental issues what makes the circuit design a far
more untypical and demanding process. One of them is rad-hardness of the final circuit. If the typical CMOS technology
process is utilized, there is a need for design and qualification of rad-hard component libraries. This is a long and
expensive process (rad-hardness by design). The consortium has chosen other way by selecting a specially optimized
Silicon on Insulator (SoI) technology process. Thus, the design became rad-hard by process and much easier to
completed.
The DC/DC converter under design is an analog ASIC, though several mixed-signal and digital approaches were
discussed with ESA and may be focused on, later. The general circuit architecture is shown in figure 10. The most
crucial sub circuits of the designed converter are: voltage error amplifier, current error amplifiers, PWM comparator,
voltage reference, output stage driver. The designed DC/DC converter ASIC shall work in voltage- and current-based
control modes. Also, a cooperation of two converters are to be possible, so as complex scheme of DC/DC voltage
conversion can be realized without necessity of new hardware application.
3.5 The project product
Task of the project, apart from ASIC design and characterization, is to provide a space application ready circuit. Though
intended for launcher and satellite applications, the designed ASIC must be competitive on a more general market of
extreme environment applications. Design of the ASIC [23] will be finished by specialized space qualification process
[24], and here Space Research Center has very much experience obtained during their project related to FPGA based
designs of DC/DC converters. What interesting, the qualification process may in fact one of the most time-consuming
stages of the project
4. CONCLUSIONS
Achievements presented in this paper clearly show long-term and in-depth involvement of DMCS in research related to
design of electronic systems intended for operation in extreme environments, most of which are harsh radiation
conditions typical for a few very distinct field of electronic system application. Achievements in such demanding fields
of research and application show valuable abilities and expertise of DMCS design teams and gives wide possibilities of
participation in cutting-edge research projects and final industrialization of obtained results.
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Figure 10. Architectural diagram of the designed DC/DC analog integrated controller [16].
ACKNOWLEDGEMENTS
Presented works are supported by Polish National Science Center grants No. 5091/B/T02/2011/40 and UMO2013/11/B/ST7/01742, Internal University Grants, and ESA funding scheme for project MISAC - Mixed Signal ASIC
Controller for RF DC/DC Power Converters.
REFERENCES
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