Instruction
Operation
ACI DATA
[A]
[A]+DATA+[Cy]
ADC REG
[A]
[A]+[r]+[CY]
ADC M
[A]
[A]+[[HL]]+[CY]
ADD REG
[A]
[A]+[r]
ADD M
ADI DATA
[A]
[A]
ANA REG
Addressing
Codes
Mode
Imm
CE data
Bytes
T-States
2
7
M/C
Cycles
FR
Flags
ALL
Reg
1000 Isss
1
4
F
ALL
Reg Ind
8E
1
7
FR
ALL
Reg
1000 Isss
1
4
F
ALL
[A]+[[HL]]
[A]+DATA
Reg Ind
Imm
1
2
7
7
FR
FR
ALL
ALL
[A]
[A] and [r]
Reg
1
4
F
ALL
ANA M
ANI DATA
[A]
[A]
[A] and [[HL]]
[A] and DATA
86
C6 data
1010
0sss
A6
E6 data
1
2
7
7
FR
FR
ALL
ALL
CALL addr
[[SP]-1
[PCH]]
[[SP]-2]
[PCL]
[SP]
[SP]-2
[PC]
Addr
CD addr
3
18
CC addr
--DO-Else
PC
DC addr
3
9 OR 18
CM addr
--DO--
FC addr
3
CMA
[A]
2F
1
CMC
[Cy]
1
4
F
Cy
CMP REG
[A] - [r]
1
4
F
ALL
CMP M
[A] - [[HL]]
Reg Ind
3F
1011
1sss
BE
1
7
FR
ALL
CNC addr
[[SP]-1]
[PCH]]
[[SP]-2]
[PCL]
[SP]
[SP]-2
[PC]
Addr
Else
PC
PC+3
Imm/Reg
Ind
D4 addr
3
9 OR 18
SR/SRR
WW
NONE
CNZ addr
--DO--
C4 addr
3
9 OR 18
CP addr
--DO--
F4 addr
3
CPE addr
--DO--
EC addr
3
CPI addr
[A] - DATA
[[SP]-1
[PCH]]
[[SP]-2]
[PCL]
[SP]
[SP]-2
[PC]
Addr
Else PC
PC+3
FE data
2
SR/SRR
WW
SR/SRR
9 OR 18
WW
SR/SRR
9 OR 18
WW
7
FR
Imm/Reg
Ind
E4 addr
3
9 OR 18
Imm/Reg
Ind
CC addr
3
10 OR 18
27
1
4
CPO addr
PC+3
[A]
[Cy]
CZ addr
--DO--
DAA
Eqvlt BCD of [A]in[A]
Reg Ind
Imm
Imm/Reg
Ind
Imm/Reg
Ind
Imm/Reg
Ind
Implied
Implied
Reg
Imm/Reg
Ind
Imm/Reg
Ind
Imm/Reg
Ind
Immediate
SRRWW NONE
SR/SRR
WW
SR/SRR
9 OR 18
WW
4
F
SR/SRR
WW
SR/SRR
WW
F
NONE
NONE
NONE
NONE
NONE
NONE
ALL
NONE
NONE
ALL
Instruction
Operation
DAD Rp
[HL]
[HL] + [Rp]
DCR REG
[r]
DCR M
[[HL]]
DCX Rp
[Rp]
DI
[r] -1
Addressing
Mode
Reg
Reg
00Rp100
1
00ss
s101
Bytes
T-States
M/C
Cycles
Flags
1
10
FBB
Cy
1
4
F
ALLnot
Cy
ALLnot
Cy
Reg Ind
35
1
10
FRW
Reg
00Rp100
1
1
6
S
NONE
Disable Interrupt
NONE
F3
1
4
F
NONE
EI
Enable Interrupt
NONE
FB
1
4
F
NONE
HLT
IN PORT
System Halts
[A]
[PORT]
NONE
Direct
1
2
5
10
FBB
FRI
INR REG
[r]
76
DB data
00ss
s100
1
4
F
INR M
[[HL]]
34
1
10
FRW
NONE
NONE
ALLnot
Cy
ALLnot
Cy
INX Rp
[Rp]
1
6
S
NONE
JC addr
JM Addr
JMP Addr
JNC Addr
JNZ Addr
JP Addr
JPE Addr
JPO Addr
JZ Addr
LDA ADDR
[PC]
[PC]
[PC]
[PC]
[PC]
[PC]
[PC]
[PC]
[PC]
[A]
addr, if Cy=1
Addr, if S=1
Addr
Addr, if Cy=0
Addr, if Z=0
Addr, if S=0
Addr, if 1s=even
Addr, if odd 1s
Addr, if Z=1
[Addr]
3
3
3
3
3
3
3
3
3
3
7 OR 10
7 OR 10
10
7 OR 10
7 OR 10
7 OR 10
7 OR 10
7 OR 10
7 OR 10
13
FR/FRR
FR/FRR
FRR
FR/FRR
FR/FRR
FR/FRR
FR/FRR
FR/FRR
FR/FRR
FRRR
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
LDAX Rp
[A]
[[Rp]]
Reg Ind
1
7
FR
NONE
LHLD ADDR
[L]
[H]
[Addr]
[Addr+1]
Direct
3
16
FRRRR
NONE
LXI Rp DATA [Rp]
DATA
Imm
3
10
FRR
NONE
MOV REG, R
[r2]
Reg
1
4
F
NONE
1
7
FW
NONE
2
7
FR
NONE
36 data
2
10
FRW
NONE
0
01DD
D110
1011
OSSS
1
4
F
NONE
1
7
FR
NONE
1
4
F
ALL
[Rp] -1
[r] +1
[r1]
[r]
data
No Operation
MOV REG, M [r]
ORA REG
[r]
DATA
MVI M, DATA [[HL]]
NOP
[[HL]] + 1
[Rp] +1
MOV M, REG [[HL]]
MVI REG,
DATA
[[HL]] - 1
Codes
[A]
[[HL]]
[A] or [r]
Reg
Reg Ind
Reg
Imm
Imm
Imm
Imm
Imm
Imm
Imm
Imm
Imm
Direct
Reg Ind
Imm
Imm/Reg
Ind
NONE
Reg Ind
Reg
00Rp
0011
DA addr
FA addr
C3 addr
D2 addr
C2 addr
F2 addr
EA addr
E2 addr
CA addr
3A addr
000X
1010
2A addr
Rp 0001
data
01DD
DSSS
0111
0sss
00DD
D110
Instruction
ORA M
ORI DATA
OUT PORT
PCHL
POP PSW
POP Rp
PUSH PSW
PUSH Rp
RAL
RAR
RC
RET
RIM
Operation
[A] [A] or [[HL]]
[A] [A] or DATA
[PORT] [A]
[PC] [HL]
[f] [[SP]]
[A] [[SP]+1]
[SP]
[SP]+2
[rl] [[SP]]
[rh] [[SP]+1]
[SP]
[SP]+2
[[SP]-1] [A]
[[SP]-2] [F]
[SP]
[SP]-2
[[SP]-1] [rh]
[[SP]-2] [rl]
[SP]
[SP]-2
[An+1]
[An],
[Cy]
[A7]
[Ao]
[Cy]
[An]
[An+1],
[Cy]
[Ao]
[A7]
[Cy]
if Cy=1 [PCL]
[[SP]]
[PCH]
[[SP]+1]
[SP]
[SP]+2
Else [PC]
[PC]+1
[PCL]
[[SP]]
[PCH]
[[SP]+1]
[SP]
[SP]+2
Read Interrupt Mask
[An+1]
[An]
[Ao]
[A7]
[Cy]
[A7]
[PCL]
[[SP]] [PCH]
[[SP]+1]
[SP]
RM [Minus]
[SP]+2 IF S=1 else PC
PC+1
RNC [nocarry] --DO--IF Cy=0
RNZ [no zero] --DO--IF Z=0
RP [plus]
--DO--IF S=0
RPE [P even]
--DO--IF P=1
RPO [P odd]
--DO--IF P=0
RLC
RRC
[An]
[A7]
[Cy]
[An+1]
[A0],
[A0]
Addressing
Codes
Mode
Reg Ind
B6
Imm
F6 data
Direct
D3 data
Reg
E9
7
7
10
6
M/C
Cycles
FR
FR
FRO
S
ALL
ALL
NONE
NONE
Bytes
T-States
1
2
2
1
Flags
Reg Ind
F1
1
10
FRR
NONE
Reg Ind
11 Rp
0001
1
10
FRR
NONE
Reg Ind
F5
1
12
SWW
NONE
Reg Ind
11 Rp
0101
1
12
SWW
NONE
Implied
17
1
4
F
Cy
Implied
1F
1
4
F
Cy
Reg Ind
D8
1
6 OR 12
S/SRR
NONE
Reg Ind
C9
1
10
FRR
NONE
Implied
20
1
4
F
NONE
Implied
7
1
4
F
Cy
Reg Ind
F8
1
6 OR 12
S/S RR
NONE
Reg Ind
Reg Ind
Reg Ind
Reg Ind
Reg Ind
D0
C0
F0
E8
E0
1
1
1
1
1
6 OR 12
6 OR 12
6 OR 12
6 OR 12
6 OR 12
S/S RR
S/S RR
S/S RR
S/S RR
S/S RR
NONE
NONE
NONE
NONE
NONE
Implied
0F
1
4
F
Cy
Instruction
Operation
[[SP]-1]
[PCH]
[[SP]-2]
[PCL]
[SP]
[SP]-2
[PC]
8*n
[PCL]
[[SP]] [PCH]
[[SP]+1]
[SP]
[SP]+2 IF Z=1
RST n
RZ
Addressing
Mode
Codes
Bytes
T-States
M/C
Cycles
Flags
Reg Ind
11XXX1
11
1
12
SWW
NONE
Reg Ind
C8
1
6 OR 12
S/S RR
NONE
1
4
F
ALL
1
2
7
7
FR
FR
ALL
ALL
SBB REG
[A]
SBB M
SBI DATA
Reg Ind
Imm
Direct
22 addr
3
16
SIM
SPHL
STA ADDR
[A] [A]-[[HL]]-[Cy]
[A] [A]-DATA-[Cy]
[Addr]
[L]
[Addr+1]
[H]
Set Interrupt Mast
[SP]
[HL]
[Addr]
[A]
1001
1sss
9E
DE data
Implied
Reg
Direct
1
1
3
4
6
13
F
S
FRRW
NONE
NONE
NONE
STAX Rp
[[Rp]]
Reg Ind
1
7
FW
NONE
STC
[Cy]
1
4
F
Cy
SUB REG
[A]
1
4
F
ALL
SUB M
SUI DATA
XCHG
[A] [A]-[[HL]]
[A]
[A]-DATA
[HL]
[DE]
1
2
1
7
7
4
FR
FR
F
ALL
ALL
NONE
XRA REG
[A]
[A] xor [r]
1
4
F
ALL
XRA M
XRI DATA
[A]
[A]
[L]
[H]
[A] xor [[HL]]
[A] xor DATA
[[SP]]
[[SP]+1]
Reg Ind
Imm
30
F9
32 addr
000X
0010
37
1001
OSSS
96
D6 data
EB
1010
1SSS
AE
EE data
1
2
7
7
FR
FR
ALL
ALL
Reg Ind
E3
1
16
SHLD ADDR
XTHL
F
S
R
I
DDS
SSS
[A]-[r]-[Cy]
[A]
1
[A]-[r]
Reg
Implied
Reg
Reg Ind
Imm
Reg
Reg
Machine cycle types
Four period instruction fetch
Six clock period instruction fetch
Memory Road
I/O Read
W
O
B
X
FRRWW NONE
FRRWW NONE
Memory Write
I/O Write
Bus Idle
Variable or Optional binary digit
Binary digits identifying a destination register } {B=000, C=001, D=010, E=011, H=100
{L=101,
BC=00,
Memory
Register HL=10,
Binary digits identifying a source register }
Rp
=110,
pair DE=01,
A=111
SP=11
This is prepared by Mr. S.V.Viraktamath E&CE Dept, SDMCET