Proceedings of ESSCIRC, Grenoble, France, 2005 A 5.5 V SOPA Line Driver in a Standard 1.2 V 0.13 µm CMOS Technology Bert Serneels, Michiel Steyaert and Wim Dehaene ESAT-MICAS, KU-Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium bert.serneels@esat.kuleuven.ac.be Abstract: In this work a high voltage line driver, using a SelfOscillating Power Amplifier (SOPA) in a digital 1.2 V 0.13 µm CMOS technology is presented. A self-biasing cascode topology allows the line driver to operate at 4.5 times the nominal supply voltage. Oxide breakdown and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The realized prototype delivers a 35 MHz PWM square wave with a 4.6 V swing in a 7.1 Ω load with an efficiency of 62%. The chip achieves a Spurious Free Dynamic Range (SFDR) of 52 dB while driving a 1 MHz sine wave. A missing tone power ratio (MTPR) of 50 dB has been measured for a DMT signal up to 1.1 MHz with a crest factor of 14 dB. 1. Introduction Recently, there is an increasing interest in high voltage design techniques due to the rise of deeper-submicron and nanometer technologies. These technologies provide an answer to the growing integration density of VLSI circuits and the low-power requirements of complex signal processing applications. However, a major drawback of the gate-length scaling is the low nominal supply voltage of the devices. The supply voltage has to scale with the gate-length for keeping the electric field across the channel of the devices within limits to ensure reliable operation. As a consequence, the design of analog circuits with high output power requirements is running into its limits. A relatively unexplored area in the field of high voltage design is the design in standard CMOS technologies due to reliability issues like breakdown mechanisms and hot carrier effects. However, high voltage design techniques in mainstream CMOS technologies are gaining a lot of interest nowadays for their cost advantage and integration prospects. The idea is to find the correct operating point to limit the voltage across the terminals of the transistors. Most reported high voltage line drivers use more expensive compound silicon technologies like e.g. DMOS and BiCMOS [1–3]. Others are constructed with area consuming external components [4]. In this paper a high voltage line driver in a pure digital CMOS technology is presented. The high voltage output buffer generates an output swing of four times the nominal 0-7803-9205-1/05/$20.00 ©2005 IEEE 303 supply voltage in a low impedance load, without exceeding the nominal operating conditions of the devices. 2. System Description The presented line driver is an enhancement on the SOPA technique [5]. A high voltage output buffer is integrated within the SOPA structure for providing the necessary output voltage swing in a low voltage deep-submicron CMOS technology. The SOPA is an asynchronous switching type amplifier that combines low distortion and high efficiency for signals with a high crest factor. The self oscillation modulates the signal so it can be transferred to the line with a high linearity. The block diagram of the presented line driver is depicted in figure 1. The SOPA is constructed with a non-clocked comparator followed by a high voltage buffer. The output of this buffer is fed back to the comparator using a loop filter. The high voltage buffer has a push-pull output stage comprised of five stacked transistors. The cascode transistors are driven by a cascode-bias circuit. The buffer is preceded by a non-overlapping switching (NOS) circuit to minimize the short-circuit current during operation. Since the buffer operates at a higher voltage, the short-circuit current can lead to a considerable amount of power dissipation. The circuit has a symmetrical power supply. This approach uses two level shift circuits that provide the correct offset voltage for the tapered buffers (TB), which drive the large outer transistors of the pushpull structure. The advantage is an equal delay path from the output of the comparator to the outer stacked transistors of the high voltage buffer. When no input signal is applied, a limit cycle oscillation occurs in the loop as explained in [5]. The frequency of this self oscillation is set by the cut-off frequency of the loop filter. The self oscillation dithers the input signal, linearizing the comparator and the high voltage buffer for frequencies lower than the limit cycle. Two basic SOPA’s are connected in a bridge configuration using a signal transformer to provide a higher output voltage swing and a galvanic decoupling towards the line. 3. Circuit Implementation Figure 2 shows the schematic of the high voltage buffer with the cascode bias circuit. The working principle of Paper 5.H.1 Proceedings of ESSCIRC, Grenoble, France, 2005 TB in NOS Vdd/2 LevelShift Down 5VDD (4VDD/5VDD) g9 4VDD n8 (5VDD/4VDD) M9 n7 (5VDD/3VDD) (4VDD/3VDD) g7 out M8 MB5 n5 (5VDD/VDD) M6 n10 MBB4 5 V 2 DD (4VDD/VDD) MBB3 LPF (3VDD/2VDD) 2VDD Figure 1: Block diagram of the improved SOPA. M7 MB4 MBB5 (3VDD/2VDD) n6 (5VDD/2VDD) (4VDD/2VDD) g6 MBB6 3VDD TB M10 g8 MB6 Cascode-bias Circuit Vdd/2 LevelShift Up 5 V 2 DD out (5VDD/0) g5 n9 M5 MBB2 MB3 n4 (4VDD/0) (3VDD/VDD) g4 MBB1 M4 MB2 n3 (3VDD/0) (2VDD/VDD) g3 this output stage is based on the techniques used in [6], where the gates of the cascode transistors are set by a resistive ladder network. The capacitors parallel with the resistors counteract the overshoot during transients on the gates of the cascodes due to their parasitic gate-drain capacitance. In the presented high voltage buffer, transistors MB1 to MB6 and MBB1 to MBB6 perform the function of the resistive ladder network. All transistors are used as switches. This means that in the on-state they are in the triode region resulting in a low impedance. In the off-state, they are in the cut-off region, resulting in a high impedance. Assuming that VDD is the nominal supply voltage of the technology used, all voltages on the internal nodes of the buffer are written in function of VDD , as shown in figure 2. For reasons of clarity, the supply voltage is now defined between 0 and 5VDD . Consider the transition of the output from high (5VDD ) to low (0). The signals arriving from the tapered buffers switch M10 off and M1 on. Node n1 gets discharged and M2 is switched on, which in turn discharges node n2 . Now, M3 and MB1 are switched on. This results in a discharging of respectively node n3 and node g3 . The same reasoning accounts for M4 − MB2 and M5 − MB3 discharging the nodes n4 −g4 and out−g5 . Also, with the discharging of node g4 , MBB1 is switched off and MBB2 is switched on. The discharging of node g5 has three effects. First, MBB4 is switched off. Secondly, M6 is switched off when node n5 is discharged till VDD , which in turn switch MB4 off. Finally, MBB3 is switched on. MBB3 discharges together with MBB2 node g6 . This switches MBB6 on and MBB5 off. M7 is switched off when node n6 is discharged till 2VDD . MBB6 discharges node g7 , which switches M8 off when node n7 is discharged till 3VDD . The same reasoning can be made for the transition of the output from low (0) to high (5VDD ). Since this switching does not occur immediately for all transistors at the same time, it is decided to use only 90% of the nominal supply voltage for the devices. The lowering of the nominal supply voltage results in a voltage headroom for the transistors during transients. Figure 3 shows a transient simulation of the drain-source, gate-source an d gate-drain voltage of the transistors M1 to M5 of the high voltage output buffer with a 6 Ω load at 50 MHz. Ox- 304 M3 MB1 n2 (2VDD/0) VDD g2 (0/VDD) M2 n1 (VDD/0) g1 M1 0 Figure 2: Schematic of the high voltage buffer. ide breakdown is prevented since the voltage over the gate oxides never exceeds the nominal supply voltage. Also, only the drain-source voltage of M4 exceeds the nominal supply voltage. But since this peak still stays below VDD + 10%, hot carrier degradation is minimized. The same results are also obtained for the other transistors in the push-pull network and in the cascode bias circuit. The level shifters use the same cascode topology as the high voltage buffer. Due to the symmetrical supply, only an offset of three times VDD has to be overcome. Figure 4 shows the schematic of the up-level shifter. It consists of two branches that are switched differentially. The upper inverters (B and C) are used to restore the voltage levels. To significantly speed up the level shifter, a capacitor CU is added so that the pMOS gate couples up or down with the nMOS gate. Since the level shifters only have a small capacitive load, namely the input of the tapered buffers, the on-resistance is of no importance and the diode-configured transistors MD can be added. The transistors MD lower the voltage drop over the cascode transistors in order to ensure reliable operation. The downlevel shifter is constructed in the same way as the up-level shifter. Figure 5 depicts the schematic of the comparator. The comparator is a non-clocked cross-coupled latch structure . It consists of a preamplifier followed by a differential cross coupled pair. The extra positive feedback coming from the nand set-reset latch enables faster comparison. The comparator and the high voltage buffer, with the NOS and the level shifters, are designed to have a higher speed than the limit cycle frequency in order to minimize its influence on the limit cycle oscillation and thus the linearity of the complete system. Proceedings of ESSCIRC, Grenoble, France, 2005 NAND-latch Preamplifier Cross-coupled latch NAND-latch Figure 5: Schematic of the comparator. 3VDD B C out 2VDD MD MD MD MD VDD (a) Drain-Source voltage 2VDD CU VDD A in 0 Figure 4: Schematic of the up-level shifter. 4. Measurements The chip has been processed in a mainstream 1.2 V 0.13 µm triple well CMOS technology. The triple well process permits the connection of the source of every transistor with its bulk without substrate losses. This keeps the gate-bulk voltage within the nominal operating conditions . All measurements are performed single ended, before the coupling transformer. The supply voltage used for the comparator and the NOS is 1.1 V. The supply voltage for the high voltage buffer is 5.5 V, which is more than 4.5 times the nominal supply voltage of the technology used. When no input signal is applied, a limit cycle oscillation of 35 MHz occurs in the loop, which is set by the RC-loopfilter. Figure 6 shows a measurement of the resulting output wave. An output swing of 4.6 V into a 7.1 Ω load resistance with an efficiency of 62% is achieved. Figure 7 shows the line driver output spectrum up to 10 MHz when a 1 MHz signal is applied. A 52 dB SFDR is obtained. An MTPR measurement has been performed to derive xDSL specifications. For these measurements a DMT signal consisting of 256 tones with a tone spacing of 4.3125 kHz is applied to the line driver. Tones 1-32 are (b) Gate-Source voltage (c) Gate-Drain voltage Figure 3: Simulation of the drain-source, gate-source and gate drain voltages of the transistors M1 to M5 . 305 Proceedings of ESSCIRC, Grenoble, France, 2005 2.5 2 Output Voltage [V] 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 20 40 60 80 100 120 140 160 180 200 Time [ns] Figure 6: Time domain measurement. Figure 9: Chip photograph. -10 5. Conclusions Output Power [dBm] -20 This paper describes a 5.5 V SOPA line driver in a standard 1.2 V 0.13 µm CMOS technology. No extra process steps nor compound silicon technologies are used. The feasibility of integrating a SOPA line driver operating at a high voltage in a digital low voltage technology is demonstrated. The use of stacked devices with a self biased cascode topology resulted in a reliable, linear high voltage output buffer. An output swing of four times the nominal supply voltage was reached in a 7.1 Ω load with an efficiency of 62%. An MTPR of 50 dB has been achieved for a DMT test signal with a crest factor of 14 dB. -30 52dB -40 -50 -60 -70 1 2 3 4 5 6 7 8 9 10 Frequency [MHz] Figure 7: Measured spectrum for a 1 MHz signal. 6. Acknowledgments left blank to form the the upstream band. Tones 50, 100, 150, 200 and 226 are left out as antenna-tones. Figure 8 shows a 20 kHz zoomed spectrum around the antenna tone at the highest and most critical frequency. An MTPR of 50 dB with a noise level density of < −134 dBm/Hz has been measured for driving a 13.4 dBm DMT signal with a crest factor of 14 dB. For an output power of 16.3 dBm an MTPR of 38 dB is still achieved. This demonstrates the possibility of integrating a high voltage buffer within the SOPA structure for driving ADSL G-lite signals. Figure 9 shows a chip photograph of the presented line driver. The area is 2.6x4.3mm2. Almost one half of this area is taken by the stacked devices, to keep their onresistance sufficiently low. The authors would like to thank STMicroelectronics Belgium for the processing and their collaboration within the MIDAS project. References: [1] B. Zojer, R. Koban, and J. Pichler, “A broadband high-voltage SLIC for a splitter-and transformerless combined adsl-lite/pots linecard,” in ISSCC Digest of Technical Papers, Feb. 2000, pp. 304–305. [2] M. Cresi, et al., “An ADSL central office analog front-end integrating actively-terminated line driver, receiver and filters,” in ISSCC Digest of Technical Papers, Feb. 2001, pp. 304–305. [3] R. Benton, et al., “A high-voltage line driver (HVLDR) for combined voice and data services,” in ISSCC Digest of Technical Papers, Feb. 2001, pp. 302–303. [4] N. P. Sands, et al., “An integrated analog front-end for VDSL,” in ISSCC Digest of Technical Papers, Feb. 1999, pp. 246–247. [5] T. Piessens and M. Steyaert, “SOPA : A highefficiency line driver in 0.35µm CMOS using a selfoscillating power amplifier,” in ISSCC Digest of Technical Papers, Feb. 2001, pp. 306–307. [6] B. Serneels, T. Piessens, M. Steyaert, and W. Dehaene, “A high-voltage output driver in a standard 2.5V 0.25µm CMOS technology,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 576–583, 2005. 0 Output Power [dBm] -10 -20 -30 -40 -50 -60 -70 -80 965 970 975 980 985 Frequency [kHz] Figure 8: MTPR measurement around tone 226. 306