3/16/2020
CMOS Digital VLSI Design - - Unit 10 - Week 8
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Unit 10 - Week 8
Course
outline
Assignment 8
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Week 1
Week 2
Week 3
Due date: 2020-03-25, 23:59 IST.
1) Under negative clock skew, does the performance of a register with combinational block in
terms of maximum frequency of operation
1 point
Improves
Degrades
No-change
Not able to deduce the result due to lack of information
2) When the clock and the data path are in the same direction
1 point
Negative Skew is observed
Positive Skew is observed
Week 4
Week 5
Week 6
Week 7
No skew is observed
Both positive as well as negative skew are possible depending on the delay of the input signal
3) If tjitter is the jitter period, then the total time available to complete a combinational operation 1 point
is
tjitter
tjitter/2
Week 8
2 tjitter
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Quiz :
Assignment 8
(assessment?
name=80)
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CMOS Digital VLSI Design - - Unit 10 - Week 8
4 tjitter
4) Matched interconnect paths will help to reduce
1 point
Skew
Jitter
Skew and Jitter
None of the these
5) In a pipelined architecture, if there are three block which are pipelined the operating
frequency is
1 point
Increases by three times
Decreases by three times
Increases by one and half times
Decreases by one and half times
6) In a latch based clocking, if TCLK is the time period of the master clock, then the amount of 1 point
time allotted for combinational computation is
TCLK
TCLK/2
2 TCLK
No relation exists
7) For an edge triggered clock, the sampling of a data is done at
1 point
Rising edge
falling edge
none
Both
8) For
a self-timed Adder circuit, the generation signals are passed through1 point
which gate
TG
PTL
None
Deep threshold devices
9) The difference in timing between Read Request and the moment is available at the output is 1 point
defined as
Read Access Time
Write Access Time
Write Cycle Time
Read Cycle time
10)In a 6T SRAM cell, the ratio of Pull-up to Pull-down is approximately
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1 point
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CMOS Digital VLSI Design - - Unit 10 - Week 8
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