Combinational Logic Student Design Problem: Date of Birth Digital Electronics © 2014 Project Lead The Way, Inc. Design Specifications Design a combinational logic circuit that meets the following design specifications: • There are three (3) three inputs and seven (7) outputs. • As the inputs count from 000 to 111, the outputs (a – g) will generate the logic to display a date of birth (DOB) on a 7-segment display. • The 7-segment display is a common cathode display. • The DOB will be displayed in the MM-DD-YY format. X Y Z Date of Birth 7-Segment Display Driver Logic Circuit a b c d e f g 2 Example – DOB 02/13/10 X Y Z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Display February 13, 1910 (02-13-10) is the date of birth of William Shockley. Shockley, along with John Bardeen and Walter Brattain, invented the transistor while working at Bell Labs in the 1940s. 3 Date of Birth Truth Table X Y Z 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Display a b c d e f g 4 Date of Birth Truth Table X Y Z a b c d e f g 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 0 1 0 0 1 1 1 1 0 0 1 1 0 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 Display 5 K-Map for Segment (a) X Y Z 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 Display a 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 XY Z Z 1 1 XY 0 0 XY 0 1 XY 1 0 XY XYZ YZ a XYYZ XYZ 6 Segment (a) – AOI Logic X Y Z a 7 K-Map for Segment (b) X Y Z 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 Display b 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 XY Z Z 1 1 XY 0 1 XY 1 1 XY 1 0 XY YZ XZ b XYYZ XZ 8 Segment (b) – NAND Logic X Y Z b 9 K-Map for Segment (c) X Y Z 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 Display c Z Z XY 1 0 XY 0 1 XY 1 1 XY 1 0 YZ YZ 1 1 0 1 0 1 1 0 1 1 1 1 1 XY c YZYZ XY 10 Segment (c) – NOR Logic X Y Z c 11 All Segments a XYYZ XYZ b XYYZ XZ c YZYZ XY da eXYXYZ f XYZ XYZ g XY XYZYZ 12 X Y Z Complete Date of Birth Circuit 02-13-10 AOI Common Cathode 7-Segment Display Segment a & d NAND Segment b NOR Segment c AOI Segment e NAND Segment f NOR Segment g 13