MECE606: Embedded Systems Project
Project Description
In this work, you will have to implement an IP core for implementing sorting (You need to
basically write a Verilog module for sorting numbers). The IP should support both ascending and
descending order of sorting. Whether to sort in ascending or descending order may be controlled
from software. This IP has to be then implemented in the PL part of the Zynq chip and controlled
with the software running on the PL.
DRAM
PS
Sorting IP
PL
Minimum features required
1. Should be able to store specified amount of random numbers starting from the given
location in the external DRAM memory
2. An API to stream the numbers from DRAM to the IP core and back. The API should take
the starting address where numbers are stored and the number of items to sort
Deliverables
1.
2.
3.
4.
IP and software source code
Demonstration of the operation in lab
A report stating the resource utilization, timing performance and power consumption
Software implementation of the sorting and comparison with hardware implementation
in terms of throughput
Evaluation criteria
1. Correctness of the implementation
2. Throughput (Numbers sorted/sec)
3. Any additional features
Plagiarism
Your submitted code with go through Turnitin plagiarism checking software. Strict action will be
taken if copying of code is found between teams. At the same time, you are encouraged to discuss
your ideas. If the difference between cooperation and plagiarism is not clear, you can read it here
(http://teaching.eng.cam.ac.uk/content/plagiarism-cooperating-and-cheating)
Deadlines
Code, Report: November 20 (Hard deadline since the last day of lecture is on Nov 22)
Lab demonstration: November 21 and 22.