W
H
I
T
E
P
A
P
E
R
Printed Circuit Board
Routing at the Threshold
Advanced Technology for the New Millennium
By Dave Wiens
May 2000
Printed Circuit Board Routing at the Threshold
Advanced Technology for the New Millennium
I.
MARKET AND TECHNOLOGY FORCES DRIVE CHANGE . . . . . . 1
II.
ADVANCES IN ROUTING TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . 4
THE PACKAGING EFFECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DEALING WITH HIGH DENSITY . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
III. HIGH-SPEED DESIGN CHALLENGES . . . . . . . . . . . . . . . . . . . . . . . . . 8
IV. INTRODUCING AUTOACTIVE RE: . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
THE NEXT-GENERATION DESIGN ENVIRONMENT
FROM MENTOR GRAPHICS
I. Market and Technology Forces Drive Change
Printed circuit board routing was once considered a quiet backwater of the design world. The
cutting edge had moved far away from a technology where all the big problems had been solved.
The few analysts who wrote about board design and its associated software tool development used
words like mundane and static to describe what was essentially a technological steady state.
Industry experts advised aspiring PCB designers to look elsewhere for true technical challenges.
Then everything changed, turning conventional wisdom on its head. Gradually at first and then
with gathering momentum, the field of PCB design underwent a major transformation. Rapid
advances in IC-related technologies suddenly demanded that PCB designers reinvent their craft.
Today, we are seeing what Dataquest calls “a resurgence of CAD [which has] become a noticeable
influence on EDA.” In a recent study, Dataquest noted that although printed circuit board placeand-route tools surged in importance during the past year, users were not satisfied with their
performance. Clearly, EDA vendors must respond with a new generation of advanced tools for the
heart of printed circuit design — at the heart of which is the PCB router.
The Big Picture
During the past several years, we have witnessed an unparalleled wave of technological innovation and rapid market adoption. Spurred on by global competitive pressures, new product introductions have come fast and furiously. Sustaining this blistering pace means decreasing both the time
and cost of product design cycles. To successfully collapse design cycles in this way, manufacturers
must achieve a significant increase in productivity, the holy grail of the technology-driven marketplace. It follows that design tools must also become more productive to facilitate attainment of this
goal. In today’s environment, you get your PCB done right the first time, or pay a heavy price.
—
1
—
Time-to-Market/Cost
Reliability/Quality
Form Factor/Size
Complexity/Performance
Figure 1. Market Drivers
These primary market drivers require that the printed circuit board design process —
and place-and-route tools — become more productive in a hurry.
Development schedules are shrinking at a dizzying rate — and so are the sizes of the products
themselves. Suddenly everything is shrinking, from cell phones, laptops and digital cameras to the
integrated circuits and printed circuit boards that drive them. The push for smaller form factors is
accompanied by equally insistent demands for more functionality and better performance. Make it
smaller and faster, more powerful, feature-rich and reliable — all at the same time. No wonder the
challenges for PCB designers are growing. Now more than ever, their software tools must help
them deliver measurably better products within the framework of an efficient and cost-effective
design process.
In routing terms, this translates into faster routes, higher completion rates, and fewer iterations.
It also means producing smaller, denser boards with fewer layers, manufactured at less cost. In
addition, it implies the ability to handle the newest improvements in chip, packaging, and fabrication technologies as they emerge. Finally, the router itself must be seamlessly integrated into the
core design environment, as well as easy to use. All this may sound straightforward, but only the
most sophisticated PCB routers are truly up to the task.
The IC Connection
The breathtaking rate of technological progress in the IC arena is responsible for the present
advances — and pressures — in printed circuit board design. Foreseen by Moore’s Law, die sizes are
shrinking as capacity increases, aided by the use of ever-finer process technologies. In conjunction,
signal switching times are accelerating. These combined effects translate directly into added
complexity for the PCB designer downstream. Faster clock speeds and device edge rates have introduced a host of high-speed issues into the board routing process — issues which threaten to
lengthen design cycles, increase costs, and adversely affect product quality if not properly addressed.
The corresponding improvements in IC packaging technology have proven to be just as challenging. High-density, fine-pitch packages like the ball grid array (BGA) house devices with pin
counts higher than 1000 while occupying minimal board space. The benefits these packages provide
— the ability to create smaller, denser, higher-performance boards — come with a price, however.
—
2
—
The reduced space between a larger number of package pins dramatically increases routing challenges, and can require the use of advanced fabrication techniques to compensate. The truth is, the
newest packages are testing the limits and revealing the weaknesses of some entrenched PCB routers.
Crunch Time for PCB Routers
For many years, the only way to pack more functionality onto a printed circuit board was to
increase the board size and the number of layers, which, in turn, raised production costs. Those
days are over. Now the preferred method is to reduce both board and package size, while maintaining or increasing pin counts. This is a tall order and it’s only going to get harder as package
counts rise. A recent Dataquest report bears this out.
More than 300
2.2
current
future
2.0
150 to 199
4.4
4.0
100 to 149
8.9
4.0
75 to 99
2.2
14.0
50 to 74
8.9
26.0
25 to 49
22.2
34.0
10 to 24
26.7
8.0
5 to 9
17.8
8.0
4 or less
6.7
0
5
10
15
20
25
30
35
Figure 2. PCB Package Count [Dataquest, “Clock Speed and the Verification Crisis,” November 1998]
The expected increase in package count will exacerbate the existing problems inherent
in routing smaller, denser boards.
Perhaps not surprisingly, those designing more complex boards today anticipate that their next
designs will take them even longer.
Current
Future
13.6
More than 1 Year
28.1
11.4
25 to 52 Weeks
14.3
25.0
13 to 24 Weeks
28.6
34.1
4 to 12 Weeks
19.5
15.9
Less than 4 Weeks
9.5
0
5
10
15
20
25
30
35
Figure 3. PCB Concept to Finished Board [Dataquest, “Clock Speed and the Verification Crisis,” November 1998]
Although markets are clamoring for shorter product design cycles, in reality complex board designs
are actually taking longer. Designers are struggling with higher edge rates, smaller and denser packages, not to mention the resulting signal integrity and timing issues.
—
3
—
Because layout and routing comprise a major portion of PCB design, it seems clear that
performing those activities more efficiently will have a direct impact on shortening the entire cycle
and enhancing overall productivity. Along those lines, a recent Printed Circuit Design Magazine
market survey concluded that “more automation of layout and routing tasks can be done, and
tools need to be both interactive and automatic.” Similar sentiments were expressed at this year’s
Printed Circuit Board Design Conference West, where attendees stated that “the PCB community
needs easier-to-use place-and-route tools.”
The changing times require a robust printed circuit board routing solution, one that addresses
high-speed issues, handles new packaging and fabrication requirements, is both automatic and interactive, integrated, and easy to use. Only then will the community of printed circuit board designers
be well equipped to manage the growing technical challenges in the months and years ahead.
II. Advances in Routing Technology
The Packaging Effect
What makes an autorouter productive? Speed, completion rate, high route quality, ability to
apply and maintain high-speed rules, and the support of current packaging and fabrication technologies are all important factors. Yet historically, changes in packaging and fabrication technology have generating the most important improvements in router performance and productivity.
Routers that could not keep pace with those technological advances eventually faded away, to be
replaced by the next standard.
Figure 4. Router Evolution
Next-generation routing technology is necessary to handle the newest device packages, including
successive generations of the ball grid array, chip scale packaging, and chip-on-board, among others.
A Brief History of Routing
In the days of through-hole components, gridded routers dominated. Because through-holes
were relatively large and pin-to-pin spacing was wide, the task of routing traces between pads was
generally a straightforward exercise. With the advent of surface mount technology, pin pitches
began to shrink. The big advantages surface mount offered at the time were smaller footprints and
higher pin counts, as many as 84 per device. While the first surface-mount components featured pin
—
4
—
pitches of 25 mils, they decreased over time to around 11 mils. Minimum trace widths and clearances decreased accordingly, putting a tremendous strain on existing routers. The finer the grid, the
slower the router ran until, eventually, the gridded router was replaced by the gridless or shapebased variety. Shape-based routers took hold in the mid-1990s, through the era of the pin grid
array and the leadless chip carrier, and into the present day. They proved to be better than their
predecessors at handling a variety of components and pitch sizes, especially finer-pitched devices.
The most prevalent shape-based routers — with algorithms based on 90-degree angles —
performed well until faced with high-density, fine-pitch attach packaging, at which point certain
fundamental shortcomings of the 90-degree approach became abundantly clear.
Enter Attach Technology
During the past several years, diminutive ball grid arrays and chip scale packaging (CSP) has
grown in popularity. Fine-pitch attach technology also includes packages such as flip chip (with as
many as several thousand I/Os), multichip module (MCM), and direct chip attach (DCA). As pin
counts routinely exceed 500, chip vendors have adopted the BGA in ever-greater numbers and
more quickly than originally anticipated. The dense array of solder balls on the BGA’s lower side
far outstrips the I/O capacity of the conventional quad flat package (QFP). BGAs are also attractive to board designers and manufacturers, because of their smaller form factor, better electrical
performance, and lower power consumption. In 1998, 42 percent of PCB designers reported using
BGAs, and that number is growing. To date, development of successive BGA generations has also
been on the fast track. Where early ball grid arrays featured a ball pitch of 1.27 mm, today’s finepitch BGAs (FPBGA) now feature 0.8 to 0.5 mm ball pitches.
Chip scale packaging is another attach technology that is enjoying an enthusiastic reception, especially in Japan, where it is prized for its small form factor and reasonable cost, making it particularly
useful in portable consumer electronic applications. “CSP is best suited to applications requiring
mounting of devices with low pin counts on very small, dense PCBs,” according to Dataquest.
FCBGA 1.0mm
MG PCBGA 1.00mm
EPBGA 1.27mm and 1.00mm
HBGA 1.27mm
PBGA 1.27mm
MFBGA 1.0mm
FCCSP 0.5mm
FFBGA 0.8mm
DCA
FFBGA 0.5mm
Rip Chip
1995
1996
1997
1998
1999
2000
2005
Figure 5. A High-Density Fine-Pitch Package Road Map
[Dataquest, “Next-Generation High-Density Packaging Technology,” December 1998]
The attach technology juggernaut will continue to pick up steam over the next couple of years
because it effectively fulfills current market needs. This has far-reaching implications for printed
circuit board routing. Routers that are not equipped to handle the associated issues will have a
hard time surviving this packaging paradigm shift.
—
5
—
The Key: Native 45-Degree Routing
The large number of fine-pitch pins on a given device, the growing number of devices on a
board, and decreasing board sizes overall, make today’s routing challenges more difficult than ever.
Smaller pads, shrinking trace widths, and tighter clearances create problems for the existing 90degree-angle routers. The difficulty is amplified by the presence of numerous staggered pin connectors. In addition, 90-degree routing fails to adequately address the critical BGA escape problem,
unable to provide the necessary 45-degree-angle via fanout from tightly packed solder ball pins.
Figure 6a. Native 45-degree Routing
Only true 45-degree routing gives the designer the flexibility to deal with the twin problems
of growing density and scarce real estate. Here the router automatically runs multiple traces
between staggered pin connectors.
Figure 6b. Fanout
Sophisticated 45-degree fanout algorithms are required to properly solve the BGA escape problem.
Escape routes between densely packed vias and pins can become very difficult to negotiate, requiring
native 45-degree-angle routing capability to snake through. Such an algorithm should also be able to
fanout unconnected or zero net pins, in order to accommodate the widespread use of programmable
devices and the resulting need to render every design pin testable.
Some 90-degree routers attempt to include 45-degree angles as a post-process, which is, in
essence, a productivity killer. Because the entire board is first routed with 90-degree-angle traces,
the designer is not able to make the best use of already-limited board space. Certain areas are
simply not available, crippling the router performance. Other capabilities useful for some highspeed designs—such as trace corner chamfering—are also virtually impossible to perform with a
90-degree router. In summary, when vendors attempt to retrofit 90-degree routers to meet current
challenges, they end up compromising speed, performance, and adherence to high-speed design
rules. In the end, it’s the designer who loses.
The ideal solution is a fully integrated, shape-based, native 45-degree PCB design system, where
placement, interactive and automatic routing all run within a unified environment, using the same
editor. In this situation, the designer can actually build the via fanout into the BGA footprint during
—
6
—
layout and then rely on the automatic router to rapidly complete the task, optimizing escape routes
according to pre-established design constraints. If interactive intervention is subsequently required,
any changes the designer makes will automatically incorporate 45-degree angles as needed.
Dealing with High Density
The market demand for products with greater functionality and performance in ever-smaller
and lighter form factors is pushing printed circuit board design forward at a breakneck and sometimes painful pace. In the process, it is becoming obvious that traditional interconnect technology
is no longer sufficient for the new generation of smaller, denser boards. Through-vias are too large
and unwieldy to work with BGAs and other miniature, high I/O components. Adding board layers
is not an option either; on the contrary, designers are seeking to decrease layer counts, in order to
fulfill corporate directives calling for lower production costs and reduced manufacturing times.
Advanced, finer-geometry interconnect appears to be the answer for achieving denser routing and,
at the same time, lowering the number of layers. The challenge for the PCB designer is managing
the higher level of complexity this technological solution brings with it. Once again, it is the router
that lies at the heart of the effort.
Routers and the Microvia Revolution
In response to the current dilemma, microvia technology has finally come into its own. Long
considered promising but expensive, microvias are now becoming more viable, as burgeoning
demand and process advances drive the associated manufacturing costs down. Tiny microvias have
become the method of choice for routing designs containing BGA and CSP components. The
smallest of these vias are 50 microns — or 2 mils — on 125 micron — or 5 mil — pads. The proliferation of microvias has also revived the popularity of blind and buried vias, as a way to facilitate
signal escape from dense, attach-technology arrays. The microvia revolution has been made
possible by several noteworthy manufacturing developments: buildup fabrication processes
pioneered in Europe and Japan, and enhancement of laser and plasma drilling techniques.
Clearly, the PCB router must incorporate advanced interconnect features to ensure the correct
functioning of designs utilizing microvias. New requirements include allowing vias between any
two layers, with rules and delay values per via span. Support for blind and buried microvias is
essential: a blind via connects the surface layer with one or more internal layers, and a buried via
interconnects internal layers only. Microvia support should be included in the automated routing
capabilities, to further decrease route times and, hence, the entire design cycle.
To achieve the tightest wiring densities possible, vias can also be placed within pads. Called viaunder-pad or via-in-pad, this feature is necessary when routing pinouts located in the center or
interior of a high I/O array. Surrounding pin density can often make it impossible to run traces
through these congested areas, resulting in an incomplete route. To access an interior pin, the
router must be able to automatically drop a microvia directly through the corresponding pad,
allowing the signal to exit to another layer, thus sidestepping the top-level density problem.
—
7
—
100 µm 8 - Layers (4 core FR4 and 2 build-up layers)
L1
L2
L3
L4
L5
L6
L7
L8
A
B
D
C
E
F
Via Type
Hole Size
Pad Size (L1)
Pad Size (L2)
PVH
.125
.275
.275
IVH1
.250
.500
.700
IVH2
.250
.500
.700
Rule
Min. Dist Note
A
A
A
B
C
D
E
F
A
A
A
B
C
D
E
F
F
.800
.800
.700
.400
.400
.400
.400
.400
.700
.700
.700
.450
.300
.450
.300
.450
.450
w/inner layer
connection
1 with & 1 w/o inner
layer connection
w/o inner layer
connection
Same as "F"
Different Net
Rules
w/inner layer
connection
1 with & 1 w/o inner
layer connection
w/o inner layer
connection
Same Net
Rules
Same as "F"
IVH2 w/inner
layer connection
IVH2 w/o inner
layer connection
Figure 7. Buildup Technology Enables Microvias
In this eight-layer board, the middle four layers — or core — contain through-vias and are
manufactured in the traditional fashion. In contrast, the top and bottom two layers are created
using a combination of photo definition and sequential lamination processes. High-density boards
created in this way are useful for computer, telecommunications, and military/aerospace applications.
The technology is also applicable for MCMs.
III. High-Speed Design Challenges
High-speed issues — including both timing and signal integrity — are now taking center stage
for designers of digital printed circuit boards. Customarily, high speed has referred to boards with
clock speeds of 50 MHz or above. By that measure, somewhere between 50 and 60 percent of
board designers are presently coping with high-speed effects. But the magnitude of the problem is
actually much greater still. As Dataquest puts it:
Even engineers who are merely updating “old” or “slow” boards using current
devices on the market today are confronting board design problems they never
before experienced. High-speed design issues are actually more a function of
fast device edge rates than clock speeds. Boards are entering the realm of
high-speed design with clock speeds of only 10 MHz.
Other experts concur. Industry veteran Claude Jodoin said recently, “All PCB designs are
becoming high-speed designs.” As the speed of individual devices on the board increases, the passive
interconnect — including device packaging — begins to behave like a transmission line, producing
parasitic effects that negatively impact overall system performance. Advanced high-speed design
requires an awareness of these interrelationships and the ability to solve the resulting problems.
Another indicator of the growing challenge for designers is the rise in the number of critical or
high-speed nets on a board. In the past, only two to five percent of nets were considered critical;
today that number commonly surpasses 50 percent. In some high-end applications, the number of
critical nets per board can reach 90 percent. With the average number of nets per board around
5000, today’s designers have their hands full managing the consequences of high speed.
—
8
—
No Response
2%
8%
Not Applicable
9%
>200 MHz
41%
7%
151-200 MHz
8%
101-150 MHz
51-100 MHz
25%
<50 MHz
Figure 8. Increase in High-Speed Designs
In September 1998, half of designers responding to this Printed Circuit Design Magazine
survey indicated they were doing designs of 50 MHz or above.
A Closer Look
Design Density
Device Switching Time
Clock Speeds
Conditions are ripe for a wave of signal integrity and timing problems to strike the board design
world. Why? Because three critical factors are rapidly converging: board densities are increasing,
clock frequencies are climbing, and device switching speeds are dipping into the 0.5-nanosecond
range. Resulting signal integrity issues can include increased noise, ringing, reflections, coupling,
ground bounce and crosstalk; if unresolved, they cause serious signal degradation. In turn, timing
issues such as excessive gate delays, excessive interconnect delays, clock skew and signal instability
can give rise to troubling switching errors. Boards suffering from such high-speed effects exhibit
intermittent symptoms that can be difficult to diagnose, but ultimately compromise reliability and
may eventually lead to product failure. Obviously, such an outcome is as undesirable as it is costly.
The question for board designers — many of whom are unfamiliar with electrical engineering principles — is how to successfully navigate this potential minefield, delivering a high-quality endproduct on schedule and within budget.
Figure 9. High-Speed Technology Drivers
—
9
—
The Right Tools
“Rule-of-thumb” or overly conservative design rules are no match for the new era of high speed.
Nor are many present-day printed circuit board routers. In order to successfully handle high-speed
boards, a router must be able to apply an extensive set of complex design constraints, both automatically and interactively.
Important high-speed design constraints include:
Timing
Signal integrity
◆
Maximum net length or delay
◆
Differential pairs
◆
Matched length or delay
◆
Layer restrictions
◆
Skew control
◆
Trace width range
◆
Delay formulas
◆
Routing topology and priority
◆
Pin connection order
◆
Termination scheme
◆
Controlled impedance
The router must be able to perform customizable, automatic net tuning, to ensure that the physical design is always meeting all predefined constraints. The same capability should also be available interactively; this makes it possible for engineers to place and route critical components and
nets up front, before handing the board over to the designer. This type of process flow is common
practice where high-speed designs are concerned. Ideally, all activity takes place within a single,
integrated editing environment, so that design rules are instantly available at every stage in the
process, from early constraint definition — again, often done initially by an engineer — through
logic design and physical layout.
The ability to auto-route and tune differential pairs is particularly important for high-speed
design. It’s not unusual to encounter complex, high-performance boards that contain 1000–2000
differential pairs, particularly in the areas of computers, networking, and telecommunications.
Differential pairs are typically used to reduce signal degradation over long distances, sometimes
between several boards. For that reason, boards intended for telecommunications base stations
often make heavy use of differential pairs.
The Right Process: Left Shift
High-speed designs should be subject to early and frequent signal analysis and verification, from
the schematic phase on. The combination of adherence to design constraints and the availability of
integrated analysis tools guarantees that the resulting high-speed board will be correct by construction. This approach also minimizes design iterations, especially later in the process when they can
cost more.
This philosophy, called Left Shift, works best when engineers and designers have access to an
integrated system, one that unifies all phases of design — from schematic capture through various
types of analysis to placement and routing — with a single editor and a shared rules and design
database. This saves the PCB designer from having to reenter design constraints, and simplifies
simulation at successive stages in the process. Layout analysis is typically done after component
placement, to generate more accurate electrical models, and again after interconnect routing.
Although relatively late in the design process, this analysis yields the most accurate results possible,
because it allows verification against rules using actual interconnect. At this time, all nets can be
scanned for problems and crosstalk analysis performed.
—
10
—
Engineer
Designer
Design Process
▲
Design
Concept
▲
Design
Capture
▲
▲
▲
▲
Logic
Board
Critical
Complete
Verification Definition Place/route Layout
▲
Final
Review
▲
Mechanical
Packaging
▲
Mfg.
Output
Left Shift
Figure 10. Addressing the High-Speed Problem Earlier
In the past, signal integrity analysis hasn’t been done until the layout stage. To avoid costly and
time-consuming iterations later, analysis should begin early and continue throughout the entire
design process. Moving analysis forward in this way is referred to as the Left Shift.
IV. Introducing AutoActive RE:
The Next-Generation Design Environment
from Mentor Graphics
The market and technology changes now affecting printed circuit board design are fundamental,
fast moving, and irreversible. Routers that were built to address the issues of another era are no
longer adequate to manage today’s challenges, as many PCB designers are discovering. PCB
routers for the next generation of designs must deliver uniformly higher performance; handle the
latest developments in IC, device packaging, and board fabrication technology; include advanced
high-speed design features; provide both automatic and interactive capabilities; and, above all, be
easy to learn and use. PCB design tools from Mentor Graphics were designed to meet every one of
these key requirements, as described previously in detail. Even more importantly, the router has a
documented history of improving productivity, often by as much as 20 times over other solutions.
AutoActive RE — A New Paradigm
At the heart of the advanced design solution from Mentor Graphics is the revolutionary
AutoActive™ Route Environment. Because this PCB design environment is built on top of the
autorouter, the two are seamlessly integrated. This unique single editing environment enables
instant access to both automatic and interactive processes at every point in the board design
process. The same powerful proprietary algorithms are available all the time, whether the user is
modifying placement, invoking the autorouter, or interactively routing specific nets. In addition, all
design rules are automatically obeyed by all editing functions. Finally, switching back and forth
between automatic and interactive routing is a transparent process for the designer, greatly
enhancing productivity, reducing design cycle times, and expediting engineering changes.
One algorithm in particular — called push and shove — automatically adjusts placement and
routing in real time, as the user makes interactive modifications. For instance, when the user drops
a new component onto an already-routed section of the design, the editor dynamically pushes,
shoves, and automatically re-routes traces — all done with 45-degree-angle routing. The same is
true when a user interactively selects and routes one or more nets in the design. And, all changes
automatically adhere to the design rules in place.
—
11
—
The AutoActive technology is leveraged across two Mentor Graphics product lines for PCB
design. AutoActive RE is the core environment of Expedition PCB and — as Destination
AutoRoute — is tightly integrated with Board Station®.
Advanced features of AutoActive RE products include:
◆
Native 45-degree routing
◆
Advanced interconnect support (microvias)
◆
Shape-based database technology
◆
Custom pad stack definition
◆
Customizable, multi-pass
autorouting control
◆
Placement modification
◆
Interactive editing performance
◆
Interactive test point generation
◆
Multiple output formats
◆
Design for manufacturability
◆
Rules defined by area
◆
Tight integration with the entire
design system
◆
Automated, high-speed net tuning
◆
Dynamic hazard checking
◆
Impedance and timing control
◆
Differential pair routing
◆
Bus routing
◆
BGA fanout
Proven Results
In a rigorously conducted series of customer benchmarks that pitted the Mentor Graphics
Destination AutoRoute tool against Cadence’s CCT SPECCTRA, results repeatedly confirmed
superior routing performance by Destination AutoRoute. In the following examples, the logic
design input for both Destination AutoRoute and CCT was created using Board Station, so benchmark control conditions were identical.
Benchmark #5
Board Size:
Layers:
Technology:
Components:
Connections:
6.37x5.82 in.
16 (12 signal, 4 plane)
SMT
477
3054
Results:
Destination AutoRoute
99.99% (11 opens)
Elapsed Time: 6 hours
CCT SPECCTRA
80%
Elapsed Time: 6+ days (to get to 80%)
The design contained extensive high-speed rule sets including delay formulas, max
stub lengths for forced order nets, maximum vias, and net class clearance rules. The
specified rules were impossible to follow given the original placement. Destination
AutoRoute reported this immediately upon entry into the design. CCT took a week to
determine that the rules were not achievable. Destination AutoRoute completed the
design in less than one day; about 2.5 hours were spent in autorouting and the
remainder in completing the 11 opens, tuning, and cleaning.
—
12
—
Benchmark #7
Board Size:
Layers:
Technology:
Components:
Net Count:
Connections:
7x12.5 in.
12 (6 signal, 6 plane)
Double-sided SMT and through
1482
1366
4014
Results:
Destination AutoRoute
Elapsed Time: <3 hours
CCT SPECCTRA
Elapsed Time: 64 hours
In addition to being completed much more quickly (21X), the Destination
AutoRoute design used fewer vias than the design done with CCT. Despite the dramatic
improvement in overall routing time achieved by Destination AutoRoute, the customer
believes that the single most significant productivity gain from Destination AutoRoute
will come when doing ECOs. The ease of making incremental changes with the push
and shove capability really “lit up their eyes.”
Lucent Technologies also found Destination AutoRoute to be the ideal solution for that
company’s high-performance routing needs. During an extensive evaluation of Destination
AutoRoute, Lucent designers ran multiple designs through the tool and, in each case, saw a
substantial reduction in cycle time for both automatic and interactive routing.
Productivity Makes the Difference
In the final analysis, the PCB router that can deliver the greatest gains in productivity will win
the designer’s confidence, especially now, as market pressures intensify to reduce both the time and
cost of product design cycles. Users of the product suite from Mentor Graphics report the
following improvements when compared with other solutions:
Routing time reduction: from days to several hours
Total design cycle reduction: decreased from 16 weeks to 2 weeks
Product cost reduction: from 6 to 4 layers ($1 per layer with volume of 1,000,000 boards)
Shorter learning curve: from many months to several weeks
PCB design tools from Mentor Graphics make a concrete contribution to the customer’s bottom
line by dramatically reducing routing times; improving route quality and manufacturability; and
decreasing production costs. These benefits will only become more important as we head into a
new millennium, one that promises ever-greater technological advances to come.
Visit our web site at www.mentor.com for the latest product news.
Copyright © 2000 Mentor Graphics Corporation.
Board Station is a registered trademark and AutoActive, Destination PCB, and Expedition PCB are trademarks
of Mentor Graphics Corporation.
All trademarks mentioned in this document are trademarks of their respective owners.
Corporate Headquarters
Mentor Graphics Corporation
8005 SW Boeckman Road
Wilsonville, OR 97070-7777
Phone: 503-685-7000
Sales and Product Information
Phone: 800-547-3000
503-685-8000
Silicon Valley Headquarters
Mentor Graphics Corporation
1001 Ridder Park Drive
San Jose, California 95131 USA
Phone: 408-436-1500
Fax: 408-436-1501
North American Support Center
Phone: 800-547-4303
Europe Headquarters
Mentor Graphics Corporation
Immeuble le Pasteur
13/15, rue Jeanne Braconnier
92360 Meudon La Forêt
France
Phone: 33 (0) 1-40-94-74-74
Fax: 33 (0) 1-46-01-91-73
Pacific Rim Headquarters
Mentor Graphics (Taiwan)
Room 1603, 16F
International Trade Building
No. 333, Section 1, Keelung Road
Taipei, Taiwan, ROC
Phone: 886-2-87252000
Fax: 886-2-27576027
Japan Headquarters
Mentor Graphics Japan Co., Ltd.
Gotenyama Hills
7-35, Kita-Shinagawa 4-chome
Shinagawa-Ku, Tokyo 140
Japan
Phone: 81-3-5488-3030
Fax: 81-3-5488-3021
Printed on Recycled Paper
5-00-WCI
MISC-191