28 nm FD SOI Technology platform RF FoM
B. Kazemi Esfeh1, V. Kilchytska1, V. Barral2, N. Planes3, M. Haond3, D. Flandre1, J.-P. Raskin1
1
2
ICTEAM, Université catholique de Louvain, 1348 Louvain-la-Neuve, Belgium
CEA-Leti, MINATEC Campus, 17, rue des Martyrs, 38054 Grenoble Cedex 9, France
3
ST-Microelectronics, 850 rue J. Monnet, 38926 Crolles, France
Email: babak.kazemiesfeh@uclouvain.be, Tel: (+32) 10472153
Abstract – This work provides a detailed study of 28 nm fullydepleted silicon-on-insulator (FD SOI) ultra-thin body and buried
oxide (BOX) (UTBB) MOSFETs for high frequency applications.
RF figures of merit (FoM), i.e. the current gain cut-off frequency
(fT) and the maximum oscillation frequency (fmax), are presented
for different transistor geometries. The parasitic gate and
source/drain series resistances, as well as capacitances and their
effect on RF performance are analyzed.
Keywords: FD-SOI MOSFET; UTBB; RF FIGURES OF MERIT.
INTRODUCTION
UTBB FD SOI technology is a well-known promising
approach to satisfy ITRS requirements on device
downscaling [1]. 28 nm FD SOI platform was
demonstrated to provide good electrostatic features,
leading to high immunity to short channel effects (SCE)
and digital FoM. Many other advantages widely
discussed in literature include thermal properties
improvement, variability reduction thanks to undoped
channel and good threshold voltage control by back gate
scheme [2]. However, up to know only few studies were
devoted to investigation of RF FoM of these innovative
devices [3, 4]. [4] mentions achievable fT and fmax values
without deep analysis and does not include extraction of
parasitic capacitances and resistances of great
importance for RF FoM of advanced devices.
This work firstly provides detailed analysis of fT and fmax
versus gate length (Lg) and finger width (Wf). Secondly,
the transconductance (gm), parasitic gate resistance (Rg),
source and drain resistances (Rd and Rs), total gate
capacitance (Cgg) and its intrinsic (Cggi) and extrinsic
(Cgge) parts are extracted and their effect on RF FoM is
analyzed. Particular attention is paid to distinguishing
intrinsic (‘useful’) and extrinsic (‘parasitic’) components.
EXPERIMENTAL DETAILS
UTBB FD SOI devices were fabricated at STMicroelectronics [2]. Si body, BOX and equivalent gate
oxide thicknesses are 7 nm, 25 nm and 1.3 nm,
respectively. The channel is strained and rotated by 45°
from the <100> plane. The ground-plane implantation
under the BOX is well-type. Multi-finger devices are
designed and embedded in CPW (Coplanar Waveguide)
pads for RF characterization. For the measured devices
Lg ranges from 25 nm to 0.5 µm. For 30 nm gate length,
Wf ranges from 5 µm to 0.3 µm. S-parameters are
measured in a frequency range from 45 MHz up to 110
GHz under saturation (Vds =1 V) and cold (Vds = 0 V)
conditions for different applied gate voltages (Vgs). The
CPW feed line pads are de-embedded thanks to a
978-1-4799-7439-9/14/$31.00 ©2014 IEEE
dedicated open structure for each device. Therefore,
effect of interconnections on extrinsic capacitances is
eliminated from S-parameter measurements. fT and fmax
are extracted from the measured S-parameters
extrapolating H21 and MAG to 0 dB at Vds= 1 V and Vgs
at the maximum gm. The total capacitances are obtained
from measured S-parameters in deep depletion regime
(Vds = 0 V and Vgs < Vthreshold) [5]. The parasitic gate
resistance is extracted in strong inversion (Vgs >
Vthreshold) under cold condition (Vds = 0 V) [6].
RESULTS AND DISCUSSION
According to the MOSFET small-signal equivalent
circuit (Fig. 1) [3], fT and fmax are expressed by [3], [78]:
Fig.1. Small-signal equivalent circuit used for modeling the RF
behavior of UTBB MOSFETs [3].
fT »
»
gm
1
2 p Cgs (1+ Cgd Cgs ) + ( Rs + Rd ) ( Cgd Cgs ( gm + gd ) + gd )
gm
2 p Cgg
f max »
»
(1)
gm
1
4 p C gs (1 + C gd C gs ) g d (Rg + Rs ) + 1 / 2 C gd C gs (Rs g m + C gd C gs )
(2)
fT
2 (Rs + Rg ) g ds + 2pf T Rg C gd
where Cgg, gm and gds are the total gate capacitance, gate
transconductance and channel conductance respectively.
Since gm~Nf Wf/Lg and Cgg~Nf Lg Wf, Nf being the
number of fingers, according to Eq.1 (in ideal case) fT is
expected to increase with length reduction as 1/Lg² and
be independent of Wf. Fig. 2 shows the fT and fmax
variations with Lg and Wf. Both fT and fmax increase with
Lg scaling down (Fig. 2a), but fT follows a 1/Lg trend
(and an even weaker one in shortest devices) i.e.
attenuated comparing with ideally predicted 1/Lg2. This
is due to velocity saturation, parasitic Rs, Rd and
extrinsic Cgg effects (which will be discussed below).
Similar trends were observed in other advanced devices
[3]. It is important to point out that in case of devices
shorter than 90 nm, fmax becomes smaller than fT (Fig.
2a). According to Eq. 2, this can be due to the increase
of Rg with Lg reduction. Fig. 2b evidences the fT
independence on Wf. This trend fits our expectations
thus suggesting that in this Wf range strong parasitic
effect at the finger perimeter (reported in [3]) does not
appear. In addition, one can see that Wf reduction leads
to increase of fmax (Fig. 2b). This can be a result of the
gate resistance reduction in narrow-finger devices.
(a)
(b)
Wf
Nf
5
20
2
60
1
100
0.3
180
higher than Cggi in shortest ones. This results in sublinear Cgg(Lg) dependence and can explain the fact that
fT(Lg) becomes even weaker than 1/Lg in shortest
devices. Fig. 3b evidences Rg increase with Lg reduction,
confirming above hypothesis about Rg as a reason of
fmax(Lg) saturation in short devices. It is useful to note
that Rg values extracted in these devices are 3-4 times
lower that previously reported for UTBB devices [3],
thus allowing for a strong improvement of fmax.
Fig. 4 shows the dependence of extracted equivalent
circuit elements on Wf. Firstly, gme slightly increases in
narrow Wf as a result of Rsd improvement with Wf
reduction (Fig. 4a). Secondly, one can see that while
Cgge effect on total Cgg increases with Wf reduction, it is
not that strong in our Wf range as was previously
observed in [3]. Thus, differently from [3], we do not
observe strong effect of parasitic capacitance at the
perimeter on fT. As a result, gm(Wf) and Cgg(Wf) trends
compensate each other assuring almost Wf-independent
fT (Fig. 2b). Thirdly, strong Rg reduction with Wf
evidenced in Fig. 4b confirms our explanation of fmax
improvement with Wf reduction. fT and fmax reported in
this work are higher than previously reported for UTBB
devices [3] showing considerable process maturity
( lower Rsd, Rg and Cgge). However, they are still slightly
lower than ITRS requirements for LSTP logic transistors
for microwave and mobile applications (fT = 322 GHz
and fmax = 284 GHz for Lg = 24 nm) [1].
(a)
Fig. 2. fT and fmax versus (a) gate lengths (Lg) for Wf = 2 µm, Nf = 60,
(b) gate finger widths (Wf) for Lg = 30 nm. Nf is shown as inset Table
in the figure.
These results evidence that fT and fmax dependence on Lg
and Wf deviates from theoretical expectation and is
dominated by the effect of parasitic elements. To
understand the observed trends, complete equivalent
circuit elements (both intrinsic and extrinsic, denoted ‘i’
and ‘e’) were extracted and analyzed.
Fig. 3 shows the dependence of extracted equivalent
circuit elements on Lg. From Fig. 3a, one can see that
Lg-dependence of both gme (as measured) and gmi (after
Rsd withdrawal) is much weaker than ideal 1/Lg. This
can be related to the velocity saturation effect. Rsd effect
can be seen through higher gmi w.r.t. gme values.
Furthermore, difference between gmi and gme increases
slightly with Lg reduction, pointing out stronger Rsd
effect on short-L devices. Next to that, Fig. 3b shows
that Cggi decreases proportionally with Lg reduction,
whereas Cgge stays almost unchanged. Furthermore, Cggi
dominates over Cgge in long devices, whereas Cgge is
(b)
Fig. 3. (a) Normalized gmi, gme and Rsd (Rs + Rd) versus gate lengths (Lg)
for Wf = 2µm, Nf = 60, (b) Cggi, Cgge and Rg versus gate lengths (Lg)
for for Wf = 2 µm, Nf = 60.
REFERENCES
Wf
Nf
5
20
2
60
1
100
0.3
180
[1]
‘International Technology Roadmap for Semiconductors.’,
http://www.public.itrs.net.
[2]
N. Planes et al., ‘28nm FDSOI Technology Platform for
High-Speed Low-Voltage Digital Applications,’ in
Symposium on VLSI Technology, pp.133-134, 2012.
[3]
M. K. Md Arshad et al., ’Effect of parasitic elements on
UTBB FD SOI MOSFETs RF figures of merit,’ Solid-State
Electronics, (2014), in press doi: 10.1016/j.sse.2014.04.027.
[4]
S. Makovejev et al., ‘Wide Frequency Band Assessment of
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[5]
J.-P. Raskin et al., ‘Accurate SOI MOSFET Characterization
at Microwave Frequencies for Device Performance
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[6]
A. Bracale et al., ‘A new approach for SOI devices smallsignal parameters extraction,’ Analog Integrated Circuits and
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[7]
H. L. Kao et al., ‘Limiting Factors of RF Performance
Improvement as Down-scaling to 65-nm Node MOSFETs,’ in
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[8]
J.-P. Raskin et al., ‘High-Frequency Noise Performance of
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(a)
Wf
Nf
5
20
2
60
1
100
0.3
180
(b)
Fig. 4. (a) Normalized gmi, gme and Rsd versus gate finger widths (Wf),
(b) normalized Cggi, Cgg and Rg versus gate finger widths (Wf) for Lg =
30 nm. Nf is shown as inset Table in the figure.
CONCLUSIONS
Perspectives of 28 FD SOI platform for RF applications
have been analyzed through cut-off frequencies
dependences on Lg and Wf. These characteristics have
been further detailed based on the small-signal
equivalent circuit extraction of parasitic elements. Good
RF performance with fT of ~275 GHz and fmax of ~250
GHz was demonstrated, close to the ITRS requirements.
Further improvement can be achieved through the
process and structure optimization in order to reduce
parasitics, particularly extrinsic capacitance and gate
resistance.
ACKNOWLEDGEMENT: This work was partially funded by FNRS
(Belgium), Catrene “Reaching 22” and Eniac “Places2Be” projects.