RF-SOI substrates and technology characterization
Mostafa Emam
mostafa.emam@incize.com
Friday September 22, 2016
Nanjing SOI Workshop & Tutorial – Nanjing
Louvain-la-Neuve, Belgium
Since 2014
M EASUREMENT, C HARACTERIZATION & M ODELING
S ERVICES FOR S I & III-V T ECHNOLOGIES &
R ADIATION H ARDENED IC S
Exclusive License
10 years
Background
Customers
2
7
Wa f e r s u p p l i e r s
Foundries
Fabless
4
Semiconductor Activity
Te c h n o l o g y E n a b l e m e n t
Tr a i n i n g
WELCOME – Characterization Facility
Frequency DC – 220 GHz
RF Power -25 – 40 dBm
Load-Pull 0.8 – 50 GHz
Temperature 4 – 600K
RF Noise 1 – 60 GHz
Flicker Noise 1 – 105 Hz
On-wafer,
co-axial & packaged
WELCOME – Raman Spectroscopy
High-resolution confocal
Raman microscope
Non-destructive characterization
Solid & liquid samples
Laser wavelengths –
458, 488, 514 & 633 nm
Motorized x-y-z stage
for 2D & 3D micro-Raman imaging
Raman-thermal analysis –
-196 to 600°C
Technology Enablement
Ä TCAD Simulations
Ä Design & Fabrication of Test
Structures
Ä Characterization & Measurements
Ä Compact & Macro Modeling
Ä PDK Support
Ä Design of Demonstrator Circuits
SOI – Training
Substrates
Transistors
Applications
FD SOI – Basics, fabrication,
SOI CMOS – Basics, physics,
Variability – Origin, impact,
RF SOI – Basics,
On-wafer Characterization –
Reliability – Basics, FoM,
Nonlinearities – Origin, FoM,
Self-heating – Origin,
RadHard – Introduction,
Noise – 1/f, RF, RTN, origin,
Analogue – Design tools,
physics, applications, vs FinFET
Applications, Advantages, FoM
Solutions, Modeling
characterization, Modeling
Setup, test-structures, hands-on
characterization, modeling
physics, characterization, modeling
solutions, design
mechanisms, design solutions
sources, characterization
advantages, hands-on
MEMS – Introduction, RF
applications, challenges
Mobile Data Usage Exploding
General Mobile Data Traffic Growth / Top Line
Device Data Consumption
30
24.3 EB
Exabytes per month
25
57%
CAGR
20
M2M Module
=
3X
Wearable Device =
6X
16.1 EB
15
Smartphone
= 37 X
Tablet
= 94 X
Laptop
= 119 X
10.7 EB
10
6.8 EB
5
2.5 B
16.7%
CAGR
4.2 EB
0
2014
2015
2016
2017
2018
2019
Source: Adapted from Cisco Global Mobile Data Traffic Forecast: 2014-2019, Feb 2015
Source: Peter A. Rabbeni, Director RF Product Marketing and Business Development, GLOBALFOUNDRIES
SOI Consortium RF SOI Workshop – Shanghai, September 2015
4
90%
80%
70%
60%
50%
Exabytes per Month
100%
Bulk-CMOS technology currently
the
only
competition
Global mobile data traffic by
device/functionto SOI - could
disappear, unless it 50is
The RF Switch
45
monolithically
integrated
market is
40
with other components into
dominated by
PAMs.
35
SOI and will
remain so.
30%
20%
10%
0%
2016
Smartphone data usage
2017
30
25
RF
MEMS
technology
20
will take off in 2019 and will
15
slowly grow in the high-end
10
antenna switch market.
5
40%
2015
Global mobile data traffic
2018
2019
Other devices data usage (PCs, Tablets…)
2020
2021
Voice only data usage
0
2015
2016
2017
5G related
2018
4G/4.5G
3G/3.5G
2019
2020
2021
2G/2.5G
Courtesy:
©2017 | www
Source: Peter A. Rabbeni, Director RF Product Marketing and Business Development, GLOBALFOUNDRIES
SOI Consortium RF SOI Workshop – Shanghai, September 2015
Source: Julio Costa, Director, New Technologies, QORVO
SOI Consortium RF SOI Workshop – Shanghai, September 2015
Key Issue for Rel 9 Carrier Aggregation 4G Standards
EXAMPLE: B17 AND B4 RX CARRIER AGGREGATION
© 2015 Qorvo, Inc.
6
Carrier Aggregation
q
LTE-A = Long Term Evolution – Advanced
q
Large number of bands, tightly packed
q
Bandwidths 1.4, 3, 5, 10, 15 or 20 MHz
q
Bandwidth ↑, data rate ↑
q
20 MHz = 150 Mbps
q
CA = combining smaller bands into one
q
Max 5 component carriers
q
Total bandwidth 100 MHz max
Source: Jeanette Wannstrom, for 3GPP, (Submission, June 2013)
Total RF components & FEM/PAMiD module manufacturers
Filters
Antenna tuners
Bulk-CMOS technology Switches
currently
the
only
PAs & LNAs
competition to SOI - could
disappear,
unless
it
$3,848M
RF
MEMS
technology
will take off in 2019 and will
$4,187M
slowly grow in the high-end
CAGR +1%
antenna switch market.
$1,026M
CAGR +14%
is
The RF Switch
$10,118M
monolithically
integrated
market is
with other components into$272M
dominated by
PAMs.
CAGR +40%
SOI and will
remain so.
$5,208M
$36M
$22,777M
$16,311M
CAGR +21%
$2,014M
CAGR +12%
Courtesy:
2016
2022
©2017 | www
CMOS technology The
RF Switch
ntly
the
only
market
is
etition to SOI - could
dominated
pear, unless
it isby
lithically SOIintegrated
and will
other components
into
remain so.
.
MEMS
technology
ake off in 2019 and will
y grow in the high-end
na switch market.
Bulk-CMOS technology currently
the
only
competition to SOI - could
disappear, unless it is
monolithically
integrated
with other components into
PAMs.
RF
MEMS
technology
will take off in 2019 and will
slowly grow in the high-end
antenna switch market.
Courtesy:
©2017 | www
Front End Module
4G
3G
2G
Courtesy: Eric Desbonnets, Soitec
100% of smartphones contain RF SOI
RF-SOI enables Full Front End module integration
RF Switches
ü
Antenna
Tuners
ü
Diplexers
ü
Power
Amplifiers
Filters
3G
LTE
ü
ü
Courtesy: Eric Desbonnets, Soitec
RF switch
ON state
OFF state
RON
COFF
t = RON x COFF
C o u r t e s y : P r o f . J . - P. R a s k i n , U C L
FD SOI
RF switch
Linearity @ device and substrate levels
Trap-rich HR SOI substrate
C o u r t e s y : P r o f . J . - P. R a s k i n , U C L
RF LNA, PA, VCO
High power gain at the frequency of operation
•
•
•
•
•
High cutoff frequency for transistors
High gate transconductance
Low parasitics (R and C)
Low output conductance
High linearity around the dc bias of operation
Trap-rich HR SOI substrate
Good matching network
• Low insertion loss
• High quality passives (inductors,
capacitors)
• High linearity of the substrate
• Low crosstalk
C o u r t e s y : P r o f . J . - P. R a s k i n , U C L
FD SOI
fT »
gm
2 × p × C gs æ C gd
ç1 +
ç C
gs
è
f max »
1
ö
æC
ö
÷ + (Rs + Rd ) × ç gd × ( g m + g d ) + g d ÷
÷
çC
÷
ø
è gs
ø
gm
4 × p × C gs æ C
ç1 + gd
ç C
gs
è
1
ö
C
÷ g d × (Rg + Rs ) + 1 × gd
÷
2 C gs
ø
æ
C
× ç Rs × g m + gd
ç
C gs
è
ö
÷
÷
ø
Cellular/PCS Handset & WLAN Requirements on
Primary Switch
• RF switches either connect or isolate RF signals
• Very demanding specifications
– Cellular IP2/3 specifications are ‘out of band’ two tones or known as blocker test *
– FET based switches preferred having no physical moving parts for better reliability
(billions of operations) and very low power supply requirements (<1mW)
Cellular/PCS
GSM/EDGE dictates, GSM/EDGE/3G/4G dictates, 3G/4G dictates
Insertion
Loss
Isolation
RL
Harmonics
IIP2*
IIP3*
Ts
35dBm
6:1 (~30Vpk or
~500mArms)
<0.3dB
40dB
>20dB
<-75dBc
115dBm
>83dBm**
<5µs
>1GHz-2.1GHz
33dBm
6:1
<0.4dB
35dB
>20dB
<-75dBc
115dBm
>83dBm**
<5µs
>2.1GHz-3.5GHz (4G)
30dBm
6:1
<1dB
30dB
>20dB
No Ref
115dBm
68dBm
<5µs
Frequency Coverage
P0.1dB
VSWR
Insertion
Loss
Isolation
RL
Harmonics
IIP2
IIP3
Ts
2.5GHz
26dBm
6:1 (10.8Vpk)
<0.5dB
30dB
>20dB
<-70dBc
No Ref
58dBm
<80ns
5.5GHz
26dBm
6:1 (10.8Vpk)
<0.5dB
20dB
>20dB
<-70dBc
No Ref
50dBm
<80ns
Frequency Coverage
P0.1dB
VSWR
700MHz-1GHz
WLAN ~ SPDT
Higher frequency bands and data-rate protocols needing larger bandwidths require high resistive
SOI for broadband operation
• Typical ESD requirement is 2kV HBM
• Positive supply and control logic: require negative charge pump and level shifters
•
* T. Ranta, et. al., “Antenna Switch Linearity Requirements for GSM/WCDMA Mobile Phone Front-Ends,” 2005 IEEE ECWT, Oct. 2005
**J.-E. Mueller, et. al., “Requirements for reconfigurable 4G front-ends,” in Microwave Symposium Digest (IMS), 2013 IEEE MTT-S International, Seattle, WA, USA, 2013
**J.P. Raskin, “SOI technology pushes the limits of CMOS for RF applications,” 2016 IEEE SiRF, Jan. 2016
Other specifications taken from products sheets taken in the public domain.
8
Source: Randy Wolf, GLOBALFOUNDRIES
“Designing Next-Gen Cellular and Wi-Fi Switches Using RF SOI Technology”
Cellular/PCS Handset & WLAN Requirements on
Primary Switch
• RF switches either connect or isolate RF signals
• Very demanding specifications
– Cellular IP2/3 specifications are ‘out of band’ two tones or known as blocker test *
– FET based switches preferred having no physical moving parts for better reliability
(billions of operations) and very low power supply requirements (<1mW)
Cellular/PCS
GSM/EDGE dictates, GSM/EDGE/3G/4G dictates, 3G/4G dictates
Insertion
Loss
Isolation
RL
Harmonics
IIP2*
IIP3*
Ts
35dBm
6:1 (~30Vpk or
~500mArms)
<0.3dB
40dB
>20dB
<-75dBc
115dBm
>83dBm**
<5µs
>1GHz-2.1GHz
33dBm
6:1
<0.4dB
35dB
>20dB
<-75dBc
115dBm
>83dBm**
<5µs
>2.1GHz-3.5GHz (4G)
30dBm
6:1
<1dB
30dB
>20dB
No Ref
115dBm
68dBm
<5µs
Frequency Coverage
P0.1dB
VSWR
Insertion
Loss
Isolation
RL
Harmonics
IIP2
IIP3
Ts
2.5GHz
26dBm
6:1 (10.8Vpk)
<0.5dB
30dB
>20dB
<-70dBc
No Ref
58dBm
<80ns
5.5GHz
26dBm
6:1 (10.8Vpk)
<0.5dB
20dB
>20dB
<-70dBc
No Ref
50dBm
<80ns
Frequency Coverage
P0.1dB
VSWR
700MHz-1GHz
WLAN ~ SPDT
Higher frequency bands and data-rate protocols needing larger bandwidths require high resistive
SOI for broadband operation
• Typical ESD requirement is 2kV HBM
• Positive supply and control logic: require negative charge pump and level shifters
•
* T. Ranta, et. al., “Antenna Switch Linearity Requirements for GSM/WCDMA Mobile Phone Front-Ends,” 2005 IEEE ECWT, Oct. 2005
**J.-E. Mueller, et. al., “Requirements for reconfigurable 4G front-ends,” in Microwave Symposium Digest (IMS), 2013 IEEE MTT-S International, Seattle, WA, USA, 2013
**J.P. Raskin, “SOI technology pushes the limits of CMOS for RF applications,” 2016 IEEE SiRF, Jan. 2016
Other specifications taken from products sheets taken in the public domain.
8
Source: Randy Wolf, GLOBALFOUNDRIES
“Designing Next-Gen Cellular and Wi-Fi Switches Using RF SOI Technology”
SOI Substrates – The Challenges
High Resistivity SOI substrats: how high should we go?
signal
Conductor losses (αcond)
Substrate losses (αsub)
Si substrate
STD SOI: 20 Ω.cm à high losses
>3 k
HR SOI of > 10 kΩ.cm
would correspond
27to a
lossless Si substrate
HR SOI Substrates – Parasitic Surface Conduction
HR-SOI suffers from Parasitic Surface Conduction (PSC)
effect at the SiO2/Si interface.
Parasitic Surface Conduction (PSC)
SiO2
Si
Mobile &
Interface trapped
charges
Fixed
charges
Accumulation
layer
Highly conductive
layer
HR-Si
n-type
28
10 kΩ.cm + PSC ≈ 200 Ω.cm
[C. Roda Neve et al., TED’12]
HR SOI Substrates – How to overcome PSC?
Trap Rich layer freezes the highly
conductive layer at BOX – Handle interface
Mono-crystal Top Silicon
SiO2 (BOX)
(BOX)
SiO
2
Mobile &
Interface trapped
charges
Fixed
charges
Highly conductive
Trap rich layer
layer
Trap rich layer
n-type
High Resistivity SI Base
Accumulation
layer
Trap-Rich SOI Substrates – Fabrication
• Amorphous Si
[Lederer et al., EDL’95]
• Polycrystalline Si
[Gamble et al., MGWL’99]
• Proton implantation
Mono-crystal Top Silicon
SiO2 (BOX)
(BOX)
SiO
2
Trap rich layer
[Wu et al., EDL’00]
• Oxygen-doped polycrystalline Si
[Rong et al., EDL’04]
• RTA-crystallized Polysilicon
[Lederer et al., EDL’05]
• Ar implantation
[Posada et al., EuMIC’06]
• Silicon etching
[Roda Neve et al., EUMC’07]
High Resistivity SI Base
• Nanocrystalline Si
[Chen et al., EDL’11]
SOI Substrates – Characterization Techniques
Substrates – RF Non-Destructive Characterization
Small-signal
Noise
Large-signal
S-Parameters
Harmonic
Distortion
Cross Talk
Intermodulation
Distortion
Digital Noise
Spreading Resistance Profiling (SRP)
Destructive.
Difficult to get
detailed wafer
mapping.
Does not
capture
interface
conduction.
Difficult to relate to
32
final processed RF
and Non-linear
wafer behavior.
Expensive
Substrates – I n n o v a t i v e C h a r a c t e r i z a t i o n Te c h n i q u e s
L arg e - S i g n al – Smal l - Si gnal – Cro s s - Tal k – D i gi t al N oi s e
CPW 2146 µm-long
.
900
900MHz
MHz
Substrates – I n n o v a t i v e C h a r a c t e r i z a t i o n Te c h n i q u e s
L arg e - S i g n al – Smal l - Si gnal – Cro s s - Tal k – D i gi t al N oi s e
CPW 2146 µm-long
.
900
900MHz
MHz
@ Pin = 15 dBm
Intermodulation Distortion
Non-linear
input
! " = $% & " + $( & ( " + $) & ) "
& " = * cos ."
output ! " = $% * cos ." + $( *( (cos .")( +$) *) (cos ."))
$( *(
3$) *)
$( *(
$) *)
=
+ $% * +
cos ." +
cos 2." +
cos 3."
2
4
2
4
!(")
Fund.
.
H2
2.
3.
H3
.
input
& " = *% cos .% " + *( cos .( "
output ! " = $% *% cos .% " + *( cos .( " + $( (*% cos .% " + *( cos .( ")(
+$) (*% cos .% " + *( cos .( "))
. = .% , .( ∶
3$) *%) 3$) *% *((
3$) *)( 3$) *( *%(
$% *% +
+
cos .% " + $% *( +
+
cos .( "
4
2
4
2
Fund.
. = .% ± .( ∶ $( *% *( cos .% + .( " + $( *% *( cos .% − .( " IMD2
3$) *%( *(
3$) *%( *(
. = 2.% ± .( ∶
cos 2.% + .( " +
cos 2.% − .( "
4
4
3$) *(( *%
3$) *(( *%
. = 2.( ± .% ∶
cos 2.( + .% " +
cos 2.( − .% "
4
4
IMD3
!(")
.( − .%
2.% − .(
.%
.(
2.( − .%
.( + .%
.
*<=>?"@AB CD 9:3
3$) *%( *(
3$) *)( 3$) *( *%(
9:;3 =
=
+
G $% *( +
*<=>?"@AB CD D@EA.
4
4
2
*<=>?"@AB CD H;3
$) *)
3$) *)
H3 =
=
G $% * +
*<=>?"@AB CD D@EA.
4
4
Assumptions
*% = *( = *
9:;3 = 3×H3 = H3 + 10 dB
9$) *)(
$% *( ≪
4
9:;2 = 2×H2 = H2 + 6 dB
)
!(")
$% * ≪
3$) *
4
IMD3
.( − .%
2.% − .(
.%
.(
2.( − .%
.( + .%
.
Substrates – I n n o v a t i v e C h a r a c t e r i z a t i o n Te c h n i q u e s
L arg e - S i g n al – Smal l - Si gnal – Cro s s - Tal k – D i gi t al N oi s e
IMD3
2.% − .(
.%
.(
2.( − .%
.( + .%
.
Substrates – I n n o v a t i v e C h a r a c t e r i z a t i o n Te c h n i q u e s
L arg e - S i g n al – Smal l - Si gnal – Cro s s - Tal k – D i gi t al N oi s e
Substrates – I n n o v a t i v e C h a r a c t e r i z a t i o n Te c h n i q u e s
L arg e - S i g n al – Smal l - Si gnal – Cro s s - Tal k – D i gi t al N oi s e
CPW 2146 µm-long
.
900 MHz
Band 8
f1 = 900 MHz, f2 = 955 MHz
fim3 = 845 MHz
Substrates – I n n o v a t i v e C h a r a c t e r i z a t i o n Te c h n i q u e s
L arge- Si gnal – S m al l - S i g n al – Cro s s - Tal k – D i gi t al N oi s e
CPW 2146 µm-long
.
S-parameters
900
900MHz
MHz
900 MHz
De-embedding
structures:
Open – Short – Thru
Substrates – I n n o v a t i v e C h a r a c t e r i z a t i o n Te c h n i q u e s
L arge- Si gnal – S m al l - S i g n al – Cro
s s - Tal k – D i gi t al N oi s e
5
2
10
std-Si
1.5
std-Si
HR-Si
trap-rich HR-Si
10
Quartz
Quartz
ρaeff[dB/mm]
[Ω-cm]
a [dB/mm]
HR-Si
trap-rich HR-Si
4
1
3
10
3 k W -cm
2
0.5
10
0
10
1
5
10
15
Freq. [GHz]
20
[Roda Neve et al., EUMIC’08]
std-Si
HR-Si
Quartz
trap-rich HR-Si
25
5
10
15
Freq. [GHz]
ρnom
[Ω-cm]
ρeff
[Ω-cm]
10
>5k
>5k
33
64
>5k
>5k
20
25
Qf ~ 3x1011
Substrates – I n n o v a t i v e C h a r a c t e r i z a t i o n Te c h n i q u e s
L arge- Si gnal – Smal l - Si gnal – C ro s s - Tal k – D i gi t al N oi s e
d
PAD
PAD
d= 50 µm
Low Frequency
-20
SiO2
-40
CROSSTALK
Si
HR-SOI
TR-SOI
SOS
S21 [dB]
-60
-80
Test structure
-100
-120
-140
150 x 50 µm d = 50µm
-160
1k
[K. Ben Ali et al., TED’11]
10 k
100k
1M
10M
Frequency [Hz]
44
100 M
1G
10G
Substrates – I n n o v a t i v e C h a r a c t e r i z a t i o n Te c h n i q u e s
L arge- Si gnal – Smal l - Si gnal – C ro s s - Tal k – D i gi t al N oi s e
d= 50 µm
Low Frequency
SiO2
-20
Trap-rich layer
-40
CROSSTALK
HR-SOI
TR-SOI
SOS
HR-Si
S21 [dB]
-60
20 dB/dec
-35 dB
-80
Test structure
-100
-120
-140
150 x 50 µm d = 50µm
-160
1k
[K. Ben Ali et al., TED’11]
10 k
100k
1M
10M
Frequency [Hz]
100 M
1G
10G
Substrates – I n n o v a t i v e C h a r a c t e r i z a t i o n Te c h n i q u e s
L arge- Si gnal – Smal l - Si gnal – Cro s s - Tal k – D i g i t al N o i s e
Mixed Output
RF in
NOISE SOURCE (digital)
VICTIM (analog)
Noise
900 MHz
900 MHz
Source
+
N
BOX
Gate
Si
Drain
+
N
Trap-rich layer
SUBSTRATE COUPLING
Bulk Si / SOI HR-Si
NP2N
L = 2 µm
W = 20 µm
Nf = 20
BULK
[D. Bol et al., SOI’07]
HR-Si (n-type)
UCL’s SOI FD MOSFET
HRSOI
Limited DSN reduction due to PSC
Substrates – I n n o v a t i v e C h a r a c t e r i z a t i o n Te c h n i q u e s
L arge- Si gnal – Smal l - Si gnal – Cro s s - Tal k – D i g i t al N o i s e
Without Noise
Mixed Output
RF in
Noise
900 MHz
900 MHz
Source
+
N
BOX
Gate
Si
Drain
+
N
Noise: square signal
@ 500 kHz
Trap-rich layer
HR-Si (n-type)
UCL’s SOI FD MOSFET
TR-SOI reduces Digital
Substrate Noise
HRSOI
Almost 25 dB
reduction of
the coupled
noise.
TR SOI
[K. Ben Ali, SOI Conf. 2012]
RF Measurements – Non-RF Characteristics
S e l f - h e a t i n g i n M O S F E Ts
Self-heating in MOSFETS – History
Intel CPU power density, W/cm²
10000
Sun surface
Rocket nozzle
1000
Nuclear reactor
100
10
1
1960
Hot plate
1970
1980
1990
2000
2010
2020
2030
Year
29
Self-heating in MOSFETS – Sources
Silicon
lStrained silicon
lSiO (silicon on insulator)
2
lGe, SiGe
lIII-V materials
l
Self-heating in MOSFETS – Implications
Self-heating in MOSFETS – Measurement Techniques
Self-heating in MOSFETS – Measurement Techniques
Nanosecond pulses are needed!
Not achievable!
Time domain à Frequency domain
Nanoseconds à Gigahertz
Self-heating in MOSFETS – RF technique
• Dynamic self-heating is
frequency-dependent
• gm = Re(Y21); gd = Re(Y22)
• Rth α Δgd
• Tdevice α Δgd
Conductance, mS
Self-heating in MOSFETS – RF technique
4
UTBB: Tsi = 7 nm and TBOX = 10 nm
L = 100 nm
SUB
3
SH
2
Vg=Vd=1V
1
Vg=0.6 V; Vd=1V
0
DC 104
106
gd (DC) is up to 3 times smaller than gd (HF)
108
1010
Frequency, Hz
[S. Makovejev et al., 2011]