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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
1
A Ka-Band Single-Chip SiGe BiCMOS
Phased-Array Transmit/Receive Front-End
Chao Liu, Student Member, IEEE, Qiang Li, Senior Member, IEEE, Yihu Li, Xiao-Dong Deng, Hailin Tang,
Ruitao Wang, Haitao Liu, and Yong-Zhong Xiong, Senior Member, IEEE
Abstract— This paper presents the detailed design and demonstration of a Ka-band single-chip transmit (TX)/receive (RX)
front-end in 0.13-μm SiGe BiCMOS technology. The front-end
includes single-pole double-throw (SPDT) switches, low-noise
amplifier, loss compensation amplifiers (LCAs), phase shifter, and
power amplifier. Distributed structures are utilized in gain amplifiers to ensure broadband performance while stacked structure
is adopted in power amplifier to deliver high output power in the
TX mode. A 5-b phase shifter with design strategies for low rms
phase/gain errors serves as the common leg of the RX and TX
paths. In the RX mode, measurements show a gain of 17 dB, an
output P−1 dB of −1 dBm, an rms phase error less than 4°, and
an rms gain error less than 0.6 dB with 0.528-W dc power from
30 to 40 GHz. In the TX mode, measurements show a gain of
14 dB, an output P−1 dB of 20.5 dBm, an rms phase error less
than 3.7°, and an rms gain error less than 0.55 dB with 1.587-W
dc power from 30 to 40 GHz. The whole front-end occupies
3.2 × 2.2 mm2 including the testing pads. By choosing inductors
and capacitors with reasonable values, designing a well-matched
SPDT switch with high isolation, and optimum ordering of phase
shift cells and LCAs in the phase shifter design, this TX/RX frontend achieves excellent rms phase/gain error performance without
any trimming in a system-level measurement at Ka-band.
Index Terms— Distributed amplifier, Ka-band, phase shifter,
phased array, rms phase/gain error, SiGe BiCMOS, stacked
power amplifier, transmit/receive (TX/RX) front-end.
I. I NTRODUCTION
M
ICROWAVE and millimeter-wave phased arrays have
been demonstrated in silicon-based technologies
(SiGe or CMOS) for low-cost wireless communications and
radar with better signal-to-noise ratio and higher channel
Manuscript received October 30, 2015; revised May 15, 2016 and
July 4, 2016; accepted July 7, 2016. This work was supported by the
National Natural Science Foundation of China under Grant 61534002 and
Grant 61474102, by the CAEP Terahertz Science and Technology Foundation
under Grant T2014-04-02, and by the Chinese National Program for Support
of Top-Notch Young Professionals (1st Batch).
C. Liu is with the Institute of Integrated Circuits and Systems and School of
Microelectronics and Solid State Electronics, University of Electronic Science
and Technology of China (UESTC), Chengdu 610054, China, and also with
the Semiconductor Device Research Laboratory, Terahertz Research Center,
China Academy of Engineering Physics (CAEP), Chengdu 611731, China
(e-mail: liuchaovvip@163.com).
Q. Li is with the Institute of Integrated Circuits and Systems and School of
Microelectronics and Solid State Electronics, University of Electronic Science
and Technology of China, Chengdu 610054, China (e-mail: qli@uestc.edu.cn).
Y. Li, X.-D. Deng, H. Tang, R. Wang, H. Liu, and Y.-Z. Xiong are with
the Semiconductor Device Research Laboratory, Terahertz Research Center,
China Academy of Engineering Physics, Chengdu 611731, China (e-mail:
eyzxiong@ieee.org).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2016.2602837
capacity [1], [2]. In millimeter-wave applications (>30 GHz),
the silicon-based solutions of phased arrays are even more
promising since the chip area can be further reduced due to
the increased operating frequency with higher data rate communication. Recently, many research focused on millimeterwave phased arrays using silicon-based technologies have been
demonstrated [2]–[13].
For satellite communication and high-resolution radars,
Min and Rebeiz [3] proposed single-ended and differential
Ka-band phased array receivers with switched LC 4-b phase
control, Koh et al. [4] and Koh and Rebeiz [5] proposed
a 40–45-GHz 16-element phased array transmitter and
a 30–50-GHz four-element phased array receiver both with
vector modulation to realize 4-b phase control. Ma et al. [6]
proposed Ka-band front-ends with true-time-delay method to
achieve continuous phase control. Pei et al. [7] proposed a
dual-band (30/35 GHz) phased array transmitter using local
oscillator-POVM techniques to realize 5-b phase control. For
full transceiver design, Ka-band single- and four-element
transmit (TX)/receive (RX) RFICs have been proposed in [8]
with 5-b amplitude and phase control, and a 44–46-GHz
16-element high-linearity TX/RX phased array with switched
LC-based 5-b phase resolution has been demonstrated in [9].
However, the rms phase/gain errors in most of the works
are relatively large (typically >7°/1 dB) and the transmitted
power is no larger than 15 dBm since a power amplifier is not
integrated in these front-ends.
In this paper, a Ka-band single-chip SiGe BiCMOS
TX/RX front-end is proposed using 0.13-μm SiGe
BiCMOS technology. The front-end integrates switches,
low-noise amplifier (LNA), phase shifter, loss compensation
amplifiers (LCAs), and power amplifier. Distributed structure
is utilized in the gain amplifiers to enhance the broadband
performance at Ka-band. In our proposed phase shifter
design, there are three main design strategies targeting low
phase error and gain variations and thus minimum rms phase
and gain errors. First, reasonable values of inductors and
capacitors are chosen. Second, a well-matched single-pole
double-throw (SPDT) switch with high isolation is designed
to achieve low phase error and gain variations. Third, the
optimum ordering of the phase shifter cells and LCAs is
chosen according to the simulation results of the rms phase
error and gain error caused by loading effect of cascading.
Adopting the above strategies, this paper achieves very
low rms gain/phase errors. Stacked power amplifier is also
adopted to deliver high output power in the transmitter that
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 2.
Schematic of the Ka-band SPDT switch.
III. B UILDING B LOCKS ’ D ESIGN
Fig. 1.
Block diagram of the Ka-band TX/RX front-end.
will potentially remove the use of III-V medium power
amplifier commonly put between the silicon TX output
and III-V high power amplifier.
This paper is organized as follows. Section II describes the
system considerations of the front-end. Section III focuses
on the detailed circuit design of the building blocks of the
TX/RX front-end. Then, the measurement results are provided
in Section IV. Finally, Section V draws the conclusion.
II. S YSTEM D ESIGN OF THE Ka-BAND
TX/RX F RONT-E ND
Fig. 1 shows the block diagram of our proposed Ka-band
TX/RX front-end that uses the all-RF structure. To save
the chip area, the 5-b phase shifter is shared by TX and
RX channels due to the fact that the proposed phase shifter
occupies a relatively larger chip area than other building
blocks. Three SPDT switches are used to control the signal
flow. The receiver includes two LNAs, a phase shifter, and an
LCA, whereas the transmitter includes a phase shifter, an LCA,
and a power amplifier. In both RX and TX channels, many
blocks are cascaded together, which will often result in gain
rolloff with increased frequency. Here, distributed structure is
adopted in the gain amplifiers to ease the situation and ensure
broadband performance. Furthermore, the working frequencies
of the blocks are intentionally shifted upward to make room
for possible drop of center frequencies during measurement.
This Ka-band TX/RX front-end chip is designed with a
0.13-μm SiGe BiCMOS technology. High-performance HBTs
with a cutoff frequency ( f T ) of 250 GHz and a maximum
oscillation frequency ( f max ) of 300 GHz are provided. CMOS
transistors are also provided for low-frequency and control
circuit design. The process contains seven metal layers of
which the topmost two layers (3- and 2-μm thick, respectively)
are for high-frequency passive design to get a relatively high
quality factor. Metal-insulator-metal capacitors and polyresistors are also available. In our design, each block is optimized
through extensive EM simulations. Then transmission lines are
used to connect the blocks to form the whole TX/RX front-end
system.
The main building blocks of the Ka-band TX/RX front-end
include SPDT switches, LCAs, LNAs, 5-b phase shifter, and
power amplifier. SiGe HBTs are used for amplifier designs,
while MOS transistors are used for SPDT switches and phase
shifter design.
A. SPDT Switch
Traditionally, switches utilizing silicon-based technologies
could not outperform their III-V counterparts in terms of
insertion loss and power handling. In recent years, it has been
demonstrated that millimeter-wave HBT switches can outperform CMOS counterparts with the HBT transistors working at
saturated or reverse saturated states [14], [15]. However, the
HBT switches are mostly λ/4 based, which means that they are
more appropriate for higher frequency use concerning the chip
area. Thus, at Ka-band, CMOS transistors are utilized in this
paper to save the chip area. With larger loss and lower power
handling ability, CMOS switches can be used for small signal
processing, while the loss can be compensated with amplifiers
at a cost of some more dc power consumption. In our proposed
TX/RX front-end design, only relatively low power is handled
by the SPDT switches. Our goal when designing the SPDT
switches is to get high isolation while maintaining acceptable
insertion loss and power handling ability. Utilizing a former
design [16], the shunt nMOS topology is adopted for the
SPDT switch design. Fig. 2 shows the schematic of the
Ka-band SPDT switch. The main idea is to adopt the OFF-state
capacitance of the nMOS transistors in the matching networks
to relieve the well-known tradeoffs between insertion loss and
isolation in series-nMOS switches design. As Fig. 2 shows, the
control voltages are applied to the gates of nMOS transistors
(60/0.13 μm) through high resistors Rg (2 k). When VC is
low, T1 and T2 are turned OFF, and T3 and T4 are turned ON.
From Port1 to Port2, the series inductor L 12 forms a network with the parasitic OFF-state capacitances of the shunt
transistors (T1 and T2 ). L 11 , C11 , and C12 in the upper path
also form a matching network. Higher order match in the
signal path imitates a transmission line to reduce the input and
output return loss, and a wideband performance is achieved.
With small ON-state resistance of T3 and T4 , C22 is shorted
to ground, and L 21 and C21 in the lower path form a parallel
resonator at the center frequency to present a high impendence
to Port1, thus, to get a large isolation of the switch.
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LIU et al.: Ka-BAND SINGLE-CHIP SiGe BiCMOS PHASED-ARRAY TX/RX FRONT-END
Fig. 3. Simulated and measured S-parameters of the Ka-band SPDT switch.
Fig. 4.
Schematic of the distributed LCA.
The simulated and measured S-parameters of the SPDT
switch are shown in Fig. 3 when VC is low voltage. Insertion
loss of 2.7–3.7 dB and isolation of 33–51 dB are achieved from
30 to 45 GHz. The measured isolation is even larger than the
simulated result, which is due to possible shift of resonant
frequency. The measured input and output return losses are
both better than 13 dB from 30 to 45 GHz. As can be seen,
the matches are shifted toward higher frequency to realize a
relatively flat insertion loss. The measured input P−1 dB of the
Ka-band SPDT switch is 8 dBm at 35 GHz.
B. Gain Amplifiers
To compensate for the high losses of the SPDT switches
and the passive phase shifter, several LCAs are inserted in the
channels. Distributed structure is adopted in the gain amplifiers
including LCAs and LNAs.
1) Loss Compensation Amplifier: The LCA is designed
mainly to compensate for the high loss of the SPDT switches
and SPDT switched passive phase shifters. The proposed
schematic of the LCA is depicted in Fig. 4. A three-stage
cascode distributed topology is utilized to realize broadband
amplification with good impendence matching. All the transistors are with an emitter size of 6 × 0.84 × 0.12 μm2 .
C1 –C4 are dc block capacitors, L 9 is the dc feed inductor
Fig. 5.
3
Simulated S-parameters of the LCA.
of the main power supply, while Rin and Rout are both 50-
termination resistors. In the input match, L 1 –L 4 along with the
parasitic base to ground capacitances of T2 , T4 , and T6 form
the input imitated transmission line; in the output match,
L 5 –L 8 along with the parasitic collector to ground capacitances of T1 , T3 , and T5 form the output imitated transmission
line. Re and Ce serve as the emitter feedback components
to lower the low frequency gain to balance the frequency
response of the amplifier. The LCA consumes 40 mA from
a 2.7 V supply.
The simulated frequency response of the LCA is depicted
in Fig. 5. A 3-dB gain bandwidth of 10-GHz is achieved with
10.4-13.4-dB small signal gain. The input and output return
losses are better than 13 dB from 10 to 45 GHz. Within
30–45 GHz, 10.4–11-dB gain is observed with input and
output return losses better than 13 dB. The simulated output
P−1 dB is around 10 dBm within Ka-band.
2) LNA: When designing an LNA, distributed amplifiers
are often dismissed due to their relatively complex structure
and high power dissipation. However, most DAs are optimized
to get a high gain-bandwidth product, which is the most
important design parameter rather than their noise [17], [18].
Reference [19] shows that with proper design, DAs can also
be candidates for LNA design. It is often assumed that the
noise figure (NF) of the DA is high due to the noise from
the input line termination resistor. However, as demonstrated
in [20], the reverse gain of the DA shields the noise of the
input termination resistor from the output, and therefore, the
NF is not bounded by a 3-dB floor, except at very low and very
high frequencies. Due to the “sinc” shape of the attenuation
factor, the input termination resistor noise appears at the output
only at very low and very high frequencies, but not in the
midband frequency. In this paper, a distributed LNA with
its noise performance optimized with moderate gain within
Ka-band is designed. The LNA schematic is shown in Fig. 6.
Using the minimum emitter width to get a lower NFmin , all the
transistors are with an emitter area of 8 × 0.84 × 0.12 μm2 .
The dc bias point of the transistors is chosen at a current
density of 8.3 mA/μm2 , lower than the current density for
maximum f T , to get lower NF with adequate gain across
Ka-band. The distributed LNA consumes 20 mA from a 2.4-V
power supply.
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 8.
Fig. 6.
Schematic of the Ka-band distributed LNA.
Fig. 7.
Simulated S-parameters and NF of the distributed LNA.
Fig. 7 shows the simulated S-parameters and the NF of
the proposed LNA. A 3-dB gain bandwidth of 9–55 GHz
is gained with good gain flatness from 30 to 45 GHz.
From 30 to 45 GHz, the gain is within 11.6–12.7 dB. The
output return loss is better than 18 dB lower than 45 GHz.
The input return loss is better than 9.5 dB lower than 45 GHz
due to the optimum noise match rather than impendence
match. The simulation result shows an NF of 3.8–5.1 dB
from 30 to 45 GHz. Since the gain of the distributed LNA
is relatively low, two distributed LNAs are cascaded to form
the whole LNA of the receiver input to prevent deterioration
of noise due to the backward stages.
C. Phase Shifter
Phase shifters used in the RX and TX paths should have
good linearity and phase resolution to meet the phased array
applications. Compared with vector modulators-based active
phase shifters, passive phase shifters have good linearity and
wideband phase shift with high reliability to process, voltage,
and temperature variations [21]. Here, a switched LC-type
5-b phase shifter is proposed. Relative phase shift is gained
between low-pass/high-pass (LP/HP) networks with two control SPDT switches as Fig. 8 shows. The LP/HP topology has
the advantages of simple architecture, compact area, and flat
frequency response over a broadband. However, the inductor
parasitics, loading effects, and nonideal switches all contribute
to the phase error. A comprehensive analysis of sources of
Diagram of one-stage phase shifter.
phase error in silicon-based LP/HP phase shifter has been
presented in [22]. To realize 5-b phase control in our case,
five stages of the cells shown in Fig. 8 should be cascaded
to form the phase shifter. When cascaded together, the high
loss of the phase shifter should be compensated for to result
in acceptable NF and linearity without deteriorating the phase
resolution. Our solution is to insert several LCAs to boost the
phase shifter gain.
In our proposed phase shifter design, there are three main
design strategies targeting low phase error and gain variations
and thus minimum rms phase and gain errors.
First, reasonable values of inductors and capacitors are
chosen. In the selection of HP or LP filters, it is necessary
to increase or reduce the filter orders to allow for component
values more compatible with the silicon-based fabrication
limitations. As to consideration of amplitude, it is the gain
mismatch of the LP/HP networks that mainly determine the
rms gain error. When designing a single-stage LP/HP phase
shifter with low rms phase and gain errors, the LP and
HP networks should deliver equal amplitude with the
desired phase difference. To get low gain variations between
LP/HP networks, the phase delay in the LP network and the
phase lead in the HP network can be adjusted not to be equal
to modify the gain response as long as their phase difference
is maintained at the desired value.
Second, a well-matched SPDT switch with high isolation
is necessary to achieve low phase error and gain variations.
Better port matches will alleviate the reflections between the
cascading stages of the phase shifter. A high isolation of the
SPDT switch can prevent some amount of power from flowing
through the isolated path, which will otherwise result in a
decrease of phase shift. There lies another interesting fact
that a relatively large switch loss will induce smaller phase
error [22]. This is due to reflections being attenuated within
the switch, which then act as a buffer for problems from
loading. In our phase shifter design, the above shunt-nMOS
SPDT switch is adopted. The good input and output match
(larger than 13 dB) with high isolation (larger than 33 dB)
make the switch appropriate for the low phase error phase
shifter design.
Third, the optimum ordering of the phase shifter cells and
LCAs is chosen according to the simulation results of the
rms phase error and gain error caused by loading effect of
cascading. In general, stages with smaller phase shift should
be shielded by stages with larger phase shift so as not to be
affected due to their relatively bad match. Fig. 9 shows three
typical diagrams out of the many combinations of orderings for
the phase shifter cells and LCAs to illustrate the design criteria
of choosing optimum ordering. The 90° cell is located in the
middle (between the 11.25° cell and the 22.5° cell) to shield
and isolate the 11.25° cell and the 22.5° cell. The simulated
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LIU et al.: Ka-BAND SINGLE-CHIP SiGe BiCMOS PHASED-ARRAY TX/RX FRONT-END
Fig. 9.
5
Different diagram topologies of the 5-b phase shifter with LCAs.
TABLE I
P ERFORMANCE OF THE P HASE S HIFTER W ITH D IFFERENT D IAGRAMS
corresponding performance of the three topologies within
30-40 GHz is listed in Table I; all the topologies result in a
gain of 1.8 dB. Topology a and c can achieve better linearity.
Topology c shows lower NF compared with topology a, but
in fact topology a is adopted because topology c suffers from
serious loading effect, which deteriorates the most important
phase characteristics. The reason that topology a can result
in better rms phase/gain errors is that the large loss due
to direct cascading of four phase shift cells can attenuate
the power reflections between stages within the whole phase
shifter. In other words, direct cascading of large loss stages
acts as a buffer for problems from loading, improves the phase
performance, and alleviates the gain variations.
The detailed schematic of the LP/HP networks is shown
in Fig. 10. The 180° adopts two-stage in the LP network
and one-stage T in the HP network. The 90° adopts twostage T in the LP network and an LC parallel structure in
the HP network. For 45° and 22.5°, a one-stage T is utilized
in the LP network, while an LC parallel structure is utilized in
the HP network. With relatively small phase shift, the 11.25°
adopts a series inductor and a series capacitor in the LP and
HP networks, respectively. The values of inductors are between
32 and 384 pH, and the values of capacitors are between
48 and 1250 fF. The reasonable values of passives in silicon
technology make sure that they can be realized with high
quality factor and good accuracies. All the component values
are optimized by iterative EM simulations to result in precise
phase shift with low gain variations between the LP and
HP networks.
Fig. 10. Circuit schematic of the LP/HP networks for (a) 180°, (b) 90°,
(c) 45° and 22.5°, and (d) 11.25° phase shifter.
Fig. 11.
Simulated gain of the 5-b phase shifter with LCAs.
The simulated gain response of the 5-b phase shifter is
depicted in Fig. 11; nearly “transparent” feature is achieved.
The phase shifter with LCAs shows almost no gain and no
loss at Ka-band. The simulated typical phase shift (180°,
90°, 45°, 22.5°, and 11.25°) is depicted in Fig. 12, which
shows broadband performance. The resulted rms phase and
gain errors are depicted in Fig. 13. Less than 3.7° rms phase
error and less than 0.54 dB rms gain error are achieved from
30 to 40 GHz.
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Fig. 12.
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Simulated typical phase shift of the 5-b phase shifter with LCAs.
Fig. 15.
Fig. 13.
Simulated rms phase and gain errors of the 5-b phase shifter
with LCAs.
Fig. 14.
Diagram of the Ka-band power amplifier.
D. Stacked Power Amplifier
Designing a power amplifier with high output power in
advanced silicon technologies is challenging due to the low
breakdown voltages compared with III-V semiconductors.
To address this problem, a typical approach is to increase
the transistor size for higher current swing instead of voltage
swing. However, this results in very low output impendence,
which makes the output match quite difficult with reduced
efficiency due to the high loss matching network. A popular
way to overcome the low breakdown voltage problem and
also with good output match is to use the stacked power
amplifier [23], [24]. With appropriate biasing and matching,
uniform voltage distributions can be obtained across the
stacked transistors [25]. For our Ka-band power amplifier,
a two-stage power amplifier adopting four-stacked structure
in the second stage has been designed. Then, two power
amplifiers are combined using Wilkinson power combiners.
The diagram of the whole power amplifier is shown in Fig. 14.
Fig. 15 shows the detailed schematic of the two-stage power
amplifier. In the second stage, four sets of HBT transistors
Schematic of the two-stage power amplifier.
(T1 –T4 ) are stacked to realize a high output voltage swing
at the output. Each set includes 14 parallel transistors with
each emitter size of 6 × 0.84 × 0.12 μm2 . Unlike cascade
structure, the bases of the stacked transistors (T2 –T4 ) are not
RF grounded. Cb2 –Cb4 along with their corresponding parasitic base-to-emitter capacitors form voltage dividers to make
the bases of stacked transistors experience RF swings. With
the bases, collectors, and emitters of the stacked transistors all
experience RF swings, it is possible to make base-to-emitter
voltages and collector-to-emitter voltages of stacked transistors
all below their breakdown values. Ideally, the collector-toemitter voltages of the stacked transistors are equal in amplitude, as well as in phase. For a relatively high frequency power
amplifier design at Ka-band, optimum interstage (between
adjacent stacked transistors) matching technique is also utilized by adding inductors (L 12 , L 23 , and L 34 ) to compensate
for the voltage phase mismatch of the stacked stages. Ci is
used to prevent the dc signal at the interstage from leaking
to ground. As shown in the schematic, transistors are biased
at class AB with a base-to-emitter voltage of 0.85 V and a
collector-to-emitter voltage of 1.5 V. The main power of 6 V
is supplied through an RF choke inductor whereas the bases
of stacked stages are supplied through resistive dividers from
the main power supply. To maintain high linearity at high
RF input power, the bases of the bottom transistors are biased
independently through an RF choke inductor [26]. Output
match networks are also shown in the schematic. To boost the
gain of the amplifier, a common source stage preamplifier is
cascaded before the four-stacked power amplifier. The emitter
size of the common emitter stage is 8 × 0.84 × 0.12 μm2 .
The common emitter transistor is biased at a base-to-emitter
voltage of 0.9 V and a collector-to-emitter voltage of 1.5 V
as shown in the schematic. Source degeneration inductor L e
is used to improve the linearity of the amplifier. The base bias
of the transistor is also fed by a large inductor. The interstage
matching and the input matching networks are also shown in
the schematic.
Fig. 16 shows the simulated S-parameters of the
combined power amplifier; 15.4–19.8-dB gain is achieved
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LIU et al.: Ka-BAND SINGLE-CHIP SiGe BiCMOS PHASED-ARRAY TX/RX FRONT-END
Fig. 16.
Simulated S-parameters of the Ka-band power amplifier.
Fig. 17.
Simulated output power and PAE of the Ka-band power amplifier.
from 30 to 40 GHz. The simulated power gain and the power
added efficiency (PAE) at 35 GHz of the power amplifier
are shown in Fig. 17; output P−1 dB of 20.5 dBm and Psat
of 22.6 dBm are achieved, respectively. The peak PAE is
simulated to be 18.6 %. With higher input power, which
further saturates the PA, the PAE drops due to higher dc power
consumption with large RF signal biasing of the transistors.
At the 1-dB compression point, the simulated collector currents of the four-stacked amplifier and predriving amplifier
are 55 and 15 mA, respectively. To illustrate the working
principle of stacked power amplifiers, the simulated waveforms at 35 GHz of the collector voltages (labeled in Fig. 15
as VC1 –VC4 ) of the four-stacked amplifier at maximum output
are depicted in Fig. 18(a). It is observed that good voltage stack is achieved with precise in phase characteristics.
Fig. 18(b) shows the collector-to-emitter voltages of the
stacked transistors; the peak voltages of all transistors are well
below 3 V to ensure reliability.
IV. M EASUREMENTS AND D ISCUSSION
This Ka-band TX/RX front-end chip has been fabricated
in a 0.13-μm SiGe BiCMOS technology. Micrograph of the
full chip is shown in Fig. 19. Chip area of 3.2 × 2.2 mm2 is
occupied including all the testing pads.
This chip is measured on wafer with ground-signal-ground
probes to demonstrate the performance of the Ka-band frontend. The S-parameter measurement is done with a Rohde and
Schwarz ZVA67. For power measurements, a signal source
and a spectrum analyzer are used.
7
Fig. 18. Simulated waveforms of the (a) collector voltages and (b) collectorto-emitter voltages of the four-stacked amplifier at maximum output.
Fig. 19. Chip micrograph of the fabricated Ka-band TX/RX front-end that
occupies 3.2 × 2.2 mm2 .
In the receive mode, the measured and simulated results of
the S-parameters are shown in Fig. 20. The measured results
in Fig. 20 are the S-parameters during 32 different phase
states, while the simulated S-parameters are the data when the
phase shifter is at the reference state (“00000”). An average
gain of 14.3–17 dB is achieved from 30 to 40 GHz with
a gain variation of 1.1 dB during 32 different states. From
32 to 38 GHz, an average gain of 16–17 dB is observed with
a gain variation of 1 dB during different states. The measured
gain is about 3 dB lower than simulated results due to possible
gain drop of the many cascading amplifiers. Input return losses
for different states are larger than 12.5 dB from 30 to 40 GHz
and larger than 17 dB from 32 to 38 GHz. Output return losses
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Fig. 20.
Measured and simulated S-parameters of the RX path.
Fig. 23. Measured and simulated gain and output power responses of the
RX path (at 35 GHz).
Fig. 21.
Measured relative phase shifts of the RX path.
Fig. 24.
Fig. 22.
Measured and simulated rms phase/gain errors of the RX path.
for different states are larger than 12 dB from 30 to 40 GHz
and larger than 15 dB from 32 to 38 GHz.
For phased array applications, the measured relative phase
shift performance of the RX path is depicted in Fig. 21, which
shows a clear resolution of 11.25° without phase overlaps
from 30 to 40 GHz. The comparison between measured and
simulated rms phase errors and rms gain errors of the RX path
is illustrated in Fig. 22, which shows good agreements. From
30 to 40 GHz, less than 4° rms phase error and less than 0.6 dB
rms gain error are achieved. From 32 to 38 GHz, less
than 2.7° rms phase error and less than 0.4-dB rms gain error
are achieved.
To demonstrate the power performance, Fig. 23 shows the
gain and output power response of the RX path measured with
Measured and simulated S-parameters of the TX path.
a 35-GHz input signal at the reference state of the phase shifter
(“00000”). An output P−1 dB of −1 dBm is observed. The
simulation results are also provided in Fig. 23 for comparison.
The measured gain is about 3 dB lower than simulation due
to gain drop of the cascading of many amplifiers. NF of the
receiver is not measured since we do not have conditions for
noise testing at Ka-band for the moment; the simulated NF of
the RX is between 7.9 and 8.4 dB from 30 to 40 GHz. The
total power consumption of the RX path is 0.528 W.
In the transmit mode, the measured and simulated results of
the S-parameters are shown in Fig. 24. The measured results
in Fig. 24 are the S-parameters during 32 different phase states,
while the simulated S-parameters are the data when the phase
shifter is at the reference state (“00000”). An average gain
of 12–14 dB is achieved from 30 to 40 GHz with a gain
variation of 1 dB during different states. From 32 to 38 GHz,
an average gain of 12.5–14 dB is observed with a gain
variation of 1 dB during different states. The measured gain is
about 2.5–3.5 dB lower than the simulated results due to gain
drop of the many cascading amplifiers. Input return losses for
different states are larger than 9 dB from 30 to 40 GHz and
larger than 10 dB from 32 to 38 GHz. Output return losses
for different states are larger than 12 dB from 30 to 40 GHz
and larger than 17 dB from 32 to 38 GHz.
For phased array applications, the measured relative phase
shift of the TX path is shown in Fig. 25, which shows
a clear resolution of 11.25° without phase overlaps from
30 to 40 GHz. The comparison between measured and
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LIU et al.: Ka-BAND SINGLE-CHIP SiGe BiCMOS PHASED-ARRAY TX/RX FRONT-END
9
TABLE II
P ERFORMANCE C OMPARISON OF S ILICON Ka-BAND P HASED A RRAY F RONT-E NDS
Fig. 25.
Measured relative phase shifts of the TX path.
simulated rms phase errors and rms gain errors of the TX path
is illustrated in Fig. 26, which shows good agreements. From
30 to 40 GHz, rms phase error less than 3.7° and rms gain
error less than 0.55 dB are achieved. From 32 to 38 GHz, rms
phase error less than 2° and rms gain error less than 0.4 dB
are achieved.
To demonstrate the power performance, Fig. 27 shows the
gain and output power response of the TX path measured
with a 35-GHz input signal at the reference state of the
phase shifter (“00000”). An output P−1 dB of 20.5 dBm and a
saturated output power (Psat ) of 22.5 dBm are observed. The
bias currents of the four-stacked amplifier and the preamplifier
Fig. 26.
Measured and simulated rms phase/gain errors of the TX path.
increase to 90 and 25 mA, respectively, during measurements
to maintain the output power performance. The simulation
results are also provided in Fig. 23 for comparison. The
measured gain is about 2 dB lower than simulation due to
gain drop of the cascading of many amplifiers. The TX system
results in a total power efficiency of 7% at 35 GHz at the
P−1 dB output point. The total power consumption of the
TX path is 1.587 W during measurements.
Table II presents a comparison of this paper with other
published Ka-band front-end chips on silicon for phased array
systems. In both RX and TX paths, high gain and high
output power are achieved with very low rms phase and gain
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10
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
Fig. 27.
Measured and simulated gain and output power responses
of TX path (at 35 GHz).
errors at Ka-band. The rms gain error performance can be
further improved with a VGA to trim the gain variations.
Similar to our previous design at X-band [27], this paper
demonstrates the effectiveness of output power enhancement
of the transmitter with stacked power amplifier for phasedarray applications. Furthermore, through design strategies for
low phase error and gain variations, very low measured rms
phase/gain errors can be achieved.
V. C ONCLUSION
A Ka-band single-chip TX/RX front-end for satellite
communication and high-resolution radar is designed and
demonstrated using 0.13-μm SiGe BiCMOS technology. The
front-end integrates LNA, SPDT switches, phase shifter,
LCAs, and power amplifier in a single chip. Through design
strategies for low phase error and gain variations to ease the
influence of major sources of phase/gain errors, very low
measured rms phase/gain errors are achieved. High output
power is also achieved with the integration of stacked power
amplifier.
ACKNOWLEDGMENT
The authors would like to thank Y. Liang, J.-F. Zhou,
X. Li, and W. Du in Terahertz Research Center, CAEP,
for their supports in layout design and chip measurements.
R EFERENCES
[1] X. Guan, H. Hashemi, and A. Hajimiri, “A fully integrated 24-GHz
eight-element phased-array receiver in silicon,” IEEE J. Solid-State
Circuits, vol. 39, no. 12, pp. 2311–2320, Dec. 2004.
[2] E. Cohen, C. Jakobson, S. Ravid, and D. Ritter, “A bidirectional TX/RX
four-element phased array at 60 GHz with RF-IF conversion block in
90-nm CMOS process,” IEEE Trans. Microw. Theory Techn., vol. 58,
no. 5, pp. 1438–1446, May 2010.
[3] B.-W. Min and G. M. Rebeiz, “Single-ended and differential Ka-band
BiCMOS phased array front-ends,” IEEE J. Solid-State Circuits, vol. 43,
no. 10, pp. 2239–2250, Oct. 2008.
[4] K.-J. Koh, J. W. May, and G. M. Rebeiz, “A millimeter-wave
(40–45 GHz) 16-element phased-array transmitter in 0.18-μm SiGe
BiCMOS technology,” IEEE J. Solid-State Circuits, vol. 44, no. 5,
pp. 1498–1509, May 2009.
[5] K.-J. Koh and G. M. Rebeiz, “A Q-band four-element phased-array
front-end receiver with integrated Wilkinson power combiners in
0.18-μm SiGe BiCMOS technology,” IEEE Trans. Microw. Theory
Techn., vol. 56, no. 9, pp. 2046–2053, Sep. 2008.
[6] Q. Ma, D. M. W. Leenaerts, and P. G. M. Baltus, “Silicon-based truetime-delay phased-array front-ends at Ka-band,” IEEE Trans. Microw.
Theory Techn., vol. 63, no. 9, pp. 2942–2952, Sep. 2015.
[7] Y. Pei, Y. Chen, D. M. W. Leenaerts, and A. H. M. van Roermund,
“A 30/35 GHz dual-band transmitter for phased arrays in
communication/radar applications,” IEEE J. Solid-State Circuits,
vol. 50, no. 7, pp. 1629–1644, Jul. 2015.
[8] D.-W. Kang, J.-G. Kim, B.-W. Min, and G. M. Rebeiz, “Single and
four-element K a-band transmit/receive phased-array silicon RFICs with
5-bit amplitude and phase control,” IEEE Trans. Microw. Theory Techn.,
vol. 57, no. 12, pp. 3534–3543, Dec. 2009.
[9] C.-Y. Kim, D.-W. Kang, and G. M. Rebeiz, “A 44–46-GHz
16-element SiGe BiCMOS high-linearity transmit/receive phased array,”
IEEE Trans. Microw. Theory Techn., vol. 60, no. 3, pp. 730–742,
Mar. 2012.
[10] K. J. Kim, K. H. Ahn, T. H. Lim, H. C. Park, and J.-W. Yu, “A 60 GHz
wideband phased-array LNA with short-stub passive vector generator,”
IEEE Microw. Wireless Compon. Lett., vol. 20, no. 11, pp. 628–630,
Nov. 2010.
[11] A. Valdes-Garcia et al., “A fully integrated 16-element phasedarray transmitter in SiGe BiCMOS for 60-GHz communications,”
IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2757–2773,
Dec. 2010.
[12] S. K. Reynolds et al., “A 16-element phased-array receiver IC for
60-GHz communications in SiGe BiCMOS,” in Proc. IEEE Radio Freq.
Integr. Circuits Symp., May 2010, pp. 461–464.
[13] Y. Yu, P. G. M. Baltus, A. De Graauw, E. van der Heijden, C. S. Vaucher,
and A. H. M. van Roermund, “A 60 GHz phase shifter integrated with
LNA and PA in 65 nm CMOS for phased array systems,” IEEE J.
Solid-State Circuits, vol. 45, no. 9, pp. 1697–1709, Sep. 2010.
[14] A. Ç. Ulusoy et al., “A low-loss and high isolation D-band SPDT switch
utilizing deep-saturated SiGe HBTs,” IEEE Microw. Wireless Compon.
Lett., vol. 24, no. 6, pp. 400–402, Jun. 2014.
[15] R. L. Schmid, P. Song, C. T. Coen, A. C. Ulusoy, and J. D. Cressler,
“On the analysis and design of low-loss single-pole double-throw
W-band switches utilizing saturated SiGe HBTs,” IEEE Trans. Microw.
Theory Techn., vol. 62, no. 11, pp. 2755–2767, Nov. 2014.
[16] C. Liu, Q. Li, and Y.-Z. Xiong, “A compact Ka-band SPDT switch
with high isolation,” in Proc. IEEE Int. Symp. Integr. Circuits (ISIC),
Singapore, Dec. 2014, pp. 304–307.
[17] K. Eriksson, I. Darwazeh, and H. Zirath, “InP DHBT distributed
amplifiers with up to 235-GHz bandwidth,” IEEE Trans. Microw. Theory
Techn., vol. 63, no. 4, pp. 1334–1341, Apr. 2015.
[18] Y. Li, W. L. Goh, and Y.-Z. Xiong, “A broadband mixer up to 110 GHz
with I–Q outputs,” IEEE Trans. THz Sci. Technol., vol. 5, no. 2,
pp. 251–259, Mar. 2015.
[19] F. Zhang and P. R. Kinget, “Low-power programmable gain CMOS
distributed LNA,” IEEE J. Solid-State Circuits, vol. 41, no. 6,
pp. 1333–1343, Jun. 2006.
[20] C. S. Aitchison, “The intrinsic noise figure of the MESFET distributed amplifier,” IEEE Trans. Microw. Theory Techn., vol. 33, no. 6,
pp. 460–466, Jun. 1985.
[21] K. Gharibdoust, N. Mousavi, M. Kalantari, M. Moezzi, and A. Medi,
“A fully integrated 0.18-μm CMOS transceiver chip for X-band phasedarray systems,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 7,
pp. 2192–2202, Jul. 2012.
[22] M. A. Morton, J. P. Comeau, J. D. Cressler, M. Mitchell, and
J. Papapolymerou, “Sources of phase error and design considerations for
silicon-based monolithic high-pass/low-pass microwave phase shifters,”
IEEE Trans. Microw. Theory Techn., vol. 54, no. 12, pp. 4032–4040,
Dec. 2006.
[23] S. Pornpromlikit, J. Jeong, C. D. Presti, A. Scuderi, and P. M. Asbeck,
“A watt-level stacked-FET linear power amplifier in silicon-on-insulator
CMOS,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 1, pp. 57–64,
Jan. 2010.
[24] D. Fritsche, R. Wolf, and F. Ellinger, “Analysis and design of a stacked
power amplifier with very high bandwidth,” IEEE Trans. Microw. Theory
Techn., vol. 60, no. 10, pp. 3223–3231, Oct. 2012.
[25] A. K. Ezzeddine and H. C. Huang, “The high voltage/high power
FET (HiVP),” in IEEE RFIC Symp. Dig., Jun. 2003, pp. 215–218.
[26] E. Taniguchi, T. Ikushima, K. Itoh, and N. Suematsu, “A dual
bias-feed circuit design for SiGe HBT low-noise linear amplifier,”
IEEE Trans. Microw. Theory Techn., vol. 51, no. 2, pp. 414–421,
Feb. 2003.
[27] C. Liu et al., “A fully integrated X-band phased-array transceiver in
0.13-μm SiGe BiCMOS technology,” IEEE Trans. Microw. Theory
Techn., vol. 64, no. 2, pp. 575–584, Feb. 2016.
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
LIU et al.: Ka-BAND SINGLE-CHIP SiGe BiCMOS PHASED-ARRAY TX/RX FRONT-END
Chao Liu (S’14) received the B.S. and
Ph.D. degrees in microelectronics from the
University of Electronic Science and Technology
of China, Chengdu, China, in 2011 and 2016,
respectively.
From 2013 to 2015, he was an Intern with the
Terahertz Research Center, China Academy of
Engineering Physics, Chengdu, where he was a
Radio Frequency Integrated Circuits/ Monolithic
Microwave Integrated Circuit Design Engineer. His
current research interests include CMOS/SiGe RF,
microwave, and millimeter-wave integrated circuits, particularly for phased
arrays.
Dr. Liu was honored as a Provincial Excellent Ph.D. Graduate in Sichuan,
China, in 2016.
Qiang Li (S’04–M’07–SM’13) received the
B.Eng. degree in electrical engineering from the
Huazhong University of Science and Technology,
Wuhan, China, in 2001, and the Ph.D. degree in
electrical and electronic engineering from Nanyang
Technological University, Singapore, in 2007.
He has been involved in analog/RF and mixedsignal circuits in both academia and industry,
holding the positions of Engineer, Senior Engineer,
Project Leader, Technical Consultant in Singapore,
and Associate Professor (permanent position) with
Aarhus University, Aarhus, Denmark. He is currently a Full Professor and
the Head of the Institute of Integrated Circuits and Systems, University of
Electronic Science and Technology of China (UESTC), Chengdu, China.
He has co-authored over 80 technical papers, 4 international patents,
and 2 books. His current research interests include ultralow voltage and
energy-efficient analog/RF circuits, data converters, and mixed-signal circuits
for biomedical and sensing applications.
Prof. Li was a recipient of the National Program for Support of Top-Notch
Young Professionals (First Batch) from the Chinese Central Government,
and the Teaching Excellence Award from UESTC. He has served on various
journal editorial boards and conference committees, including the Student
Research Preview Committee of the International Solid-State Circuits
Conference, and as a Reviewer for a number of scientific publications
and funding agencies. He also serves as the Vice Dean of the School of
Microelectronics and Solid-State Electronics, UESTC. He is a Changjiang
Young Scholar.
Yihu Li received the B.S. and Ph.D. degrees in
electrical and electronic engineering from Nanyang
Technological University, Singapore, in 2010 and
2015, respectively.
He is currently with the Semiconductor Device
Research Laboratories, China Academy of Engineering Physics, Chengdu, China.
Xiao-Dong Deng received the B.S. and
Ph.D. degrees in communication engineering
from the Nanjing University of Science and
Technology, Nanjing, China, in 2011 and 2016,
respectively.
He is currently with the China Academy of
Engineering Physics, Chengdu, China. His current
research interests include millimeter- and terahertzwave on-chip components, antennas, and integrated
circuits.
11
Hailin Tang was born in Guilin, China. He received
the B.S. degree from Sichuan University, Chengdu,
China, in 2001, and the M.S. degree from China
Academy of Engineering Physics (CAEP), Chengdu,
in 2004.
He is currently with CAEP. His current research
interests include semiconductor terahertz devices
and high-frequency IC packaging.
Ruitao Wang received the B.S. and M.S. degrees
in electromagnetic and microwave technology
from Northwestern Polytechnical University, Xi’an,
China, in 2011 and 2014, respectively.
He is currently with the China Academy of
Engineering Physics, Chengdu, China. His current
research interests include microwave and RF passive
components, packaging, and antennas.
Haitao Liu was born in LianYunGuang, China.
He received the B.S. and M.S. degrees from the
University of Electronic Science and Technology of
China, Chengdu, China, in 2011 and 2014, respectively.
He is currently with the China Academy of
Engineering Physics, Chengdu. His current research
interests include RF measurement, signal processing,
and IC design.
Yong-Zhong Xiong (M’98–SM’02) received the
B.S. and M.S. degrees in communication and electronic systems from the Nanjing University of Science and Technology (NUST), Nanjing, China, in
1986 and 1990, respectively, and the Ph.D. degree in
electrical and electronic engineering from Nanyang
Technological University (NTU), Singapore.
From 1986 to 1994, he was with the Department
of Electronic Engineering, NUST, where he was
involved with microwave systems and circuit design.
In 1994, he was a Research Scholar with NTU.
From 1995 to 1997, he was a Senior Engineer with the RF and Radios
Department, Singapore Technologies Engineering Ltd., Singapore. He was
with the Microelectronics Center, NTU. Since 2001, he has been with the
Institute of Microelectronics, Agency for Science, Technology and Research,
Singapore. He is currently a Professor and the Director of Semiconductor
Device Research Laboratories, China Academy of Engineering Physics,
Chengdu, China. He has authored or co-authored over 200 technical papers.
His current research interests include silicon-based monolithic IC design and
characterization for millimeter-wave and terahertz applications and device RF
and noise modeling and characterization.
Dr. Xiong was a co-recipient of the 2012 Best Paper Award of the IEEE
Components, Packaging and Manufacturing Technology Society.