IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 9, SEPTEMBER 2019
2361
Analysis and Design of Wideband I/Q CMOS
100–200 Gb/s Modulators
Hasan Al-Rubaye
Abstract— This paper presents the analysis and design of
wideband I/Q CMOS modulators and transmitters. Non-idealities
and performance limitations of Cartesian transmitter and modulator systems are discussed, and circuit design techniques and
analyses are shown. A DC-60 GHz I/Q modulator/transmitter
chip in 45-nm SOI CMOS is presented as a critical building block
for next-generation multi-standard and high-capacity wireless
backhaul links. The modulator consists of a wideband quadrature
signal generator, wideband buffers, and two current-combined
DC-100 GHz low-noise double-balanced mixers driven in quadrature. The 1.4 mm2 modulator chip achieves 60 dB of dynamic
range in a 1-GHz bandwidth, with an OP1dB of ∼ −10 dBm, thus
enabling spectrally efficient high-order modulation schemes such
as 256-QAM. The I/Q modulator achieves 200 Gb/s in 16-QAM
(50 Gbaud/s) while consuming 200 mW, resulting in record
1-pJ/bit modulation efficiency. In addition to backhaul links,
the modulator is an attractive and cost-effective alternative to
short-range optical links for data center interconnects (DCI) and
for chip-to-chip communications.
Index Terms— 45 nm, 5G, CMOS, direct-conversion,
quadratic-amplitude modulation (QAM), mm-wave, modulator,
radio, SOI, transmitter.
I. I NTRODUCTION
IRECT conversion architectures have become the design
of choice for wideband and multi-standard radios.
Non-zero intermediate frequency (IF) architectures generate an
undesired image frequency and thus require either image-reject
filters or image-rejection design techniques at the cost of larger
footprint and greater power consumption. Furthermore, the IF
used in heterodyne radios limits the maximum bandwidth that
can be handled by the transceiver while also complicating
the frequency planning and limiting the radio reconfigurability needed for multi-band and multi-standard communication
systems [1], [2].
Direct-conversion and direct-modulation transmitters,
on the other hand, offer the highest modulation bandwidth
and configurability [3], [4]. They, however, suffer from
well-known drawbacks such as I/Q imbalance and local
oscillator (LO) leakage (or carrier feedthrough) that limit
their dynamic range. These effects have become more
prominent in deeply scaled CMOS technologies due to
D
Manuscript received February 17, 2019; revised April 26, 2019; accepted
May 31, 2019. Date of publication June 26, 2019; date of current version August 23, 2019. This paper was approved by Guest Editor Shahriar
Shahramian. This work was supported by the UCSD Center for Wireless
Communications. (Corresponding author: Hasan Al-Rubaye.)
The authors are with the Department of Electrical and Computer Engineering, University of California at San Diego, San Diego, CA 92093 USA
(e-mail: halrubay@eng.ucsd.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2019.2923081
and Gabriel M. Rebeiz
Fig. 1.
Wideband DC-100-GHz software-defined transmitter with I/Q
modulator.
their limited voltage headroom and poor device matching
properties. Currently, this is mitigated in the digital domain
with adaptive digital calibration so as to maintain good
spectral purity and low bit-error rate (BER) under various
operating conditions.
Future generations of mm-wave systems will leverage MIMO techniques and wideband high-order modulation schemes to support the increasing data traffic.
Direct-conversion transmitters are well-suited for these solutions since they minimize the number of stages in the radio
chain, while also offering a much needed flexibility in frequency planning. Unfortunately, the effect of LO leakage and
I/Q imbalance is expected to worsen with MIMO-based systems since each antenna will utilize its own transceiver having
its own LO leakage and I/Q imbalance impairments, and thus
making the digital correction a power hungry solution if adequate analog performance is not attained from the core mmwave blocks [5], [6]. Furthermore, low carrier feedthrough and
near-ideal I/Q imbalance are needed to support high-dynamicrange levels, as required by the high-order modulation schemes
for the maximum spectral efficiency. In conclusion, wideband
and high-performance mm-wave I/Q modulators in deeply
scaled CMOS technologies are highly desirable and will play
an instrumental role in future mm-wave radios.
Fig. 1 shows one viable solution for future mm-wave
software-defined transmitters, where traditional baseband
DACs are employed with an ultra-wideband DC-100 GHz
wideband front end. Wideband synthesizers and frequency
multipliers for instrumentation and software-defined transceivers have been demonstrated before [7]–[9]. A bank of
bandpass filters and power amplifiers may be used to meet
0018-9200 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
2362
Fig. 2.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 9, SEPTEMBER 2019
Generic Cartesian transmitter block diagram.
the strict SNR and ACPR specifications and to relax the
design requirements for the baseband DACs (less resolution
and sampling rate) and thus reducing the overall system power
consumption.
This work presents a DC-60 GHz I/Q modulator fabricated
in GlobalFoundaries’ 45-nm CMOS SOI process [10]. The
objectives of this work are threefold: 1) present system and
circuit analysis of direct-conversion radio transmitters and
I/Q modulators highlighting bottlenecks and design tradeoffs;
2) present a state-of-the-art 200 Gb/s DC-60 GHz I/Q modulator where the circuit performance has been pushed to the
boundaries of current CMOS technology and instrumentation limits; and 3) introduce new potential applications of
ultra-wideband I/Q modulators such as carrier aggregation
across different mm-wave frequency bands.
II. S YSTEM A NALYSIS
Fig. 2 shows a block diagram of a Cartesian I/Q transmitter
along with its major sources of impairments that degrade the
system EVM and BER. These effects include I/Q amplitude
and phase mismatch, carrier feedthrough, LO phase noise,
wideband additive white Gaussian noise (AWGN), non-linear
distortion in the modulator, and power amplifier, and finally,
the non-ideal frequency response of the channel that results in
inter-symbol interference (ISI).
EVM impairments have been studied previously in [3]
and [11]. This work revisits some of these impairments with
additional detail and a particular emphasis on I/Q transmitters
and modulators and will also attempt to offer insight for circuit
designers to address these issues beforehand. The goal of
this section is to introduce a methodology to build optimum
wideband and high dynamic range I/Q modulators for a given
EVM or BER requirement.
A. EVM
For N number of symbols, the EVM at the kth symbol is
given by
0.5
E{|e(k)|2 }
(1)
EVMk,avg =
→
E{|−
a (k)|2 }
→
→
where −
a (ki ) is the ideal modulation vector, −
e (ki ) is the
error vector, and E {} is the expectation of ensemble averages.
All the constellation peaks are normalized to one. Here,
we distinguish again between two definitions of EVM [3]
EVMavg
(2)
C
where C is the crest factor of the particular waveform, thus
EVMpeak normalizes the error vector to the amplitude of a
vector pointing to a peak constellation symbol. We will employ
both EVM definitions throughout this paper. For m-QAM
square modulations without root-raised-cosine (RRC) filtering
applied, the crest factor is at a minimum value of
√
3( M − 1)
C=
√
.
(3)
M +1
EVMpeak =
The corresponding EVMrms, avg (or EVMrms, peak ) values are
simply the root mean square of EVMavg (or EVMpeak ) values
across N symbols within a given transmitted packet. EVMmax ,
not to be confused with EVMpeak , is the worst case EVM
across the N symbols tested and correlates strongly with the
BER, as will be shown in Section II-F.
B. Linearity of Short-Channel CMOS
Traditionally, I/Q modulators operate in deep backoff to
avoid non-linear distortion and to maintain high spectral purity.
Recently, with the increasing demand for ultra-wideband transmitters and the advancement of digital predistortion techniques, modulators operate increasingly close to their P1dB,
in order to maintain high SNR and dynamic range over a
wide bandwidth. Thus, AM–AM and AM–PM effects will be
studied in this section from both system-level and device-level
perspectives, with the goal of finding an optimum backoff level
to improve the transmit performance.
Fig. 3 shows the non-linear effects of AM–AM and AM–PM
distortion on a 64-QAM constellation with 30-dB SNR. The
constellations shown are based on a MATLAB simulation over
106 random symbols. In these constellations, the AM–AM
gain compression is assumed to be purely related to odd-order
2 ), where g represents the reducharmonics (gc ∝ g3 v gs
c
tion in signal gain due to compression, and AM–PM com2 ),
pression is related to even-order harmonics (φ ∝ g2 v gs
which are well-known modeling expressions [12]. It can
be observed that the nonlinearities in the I and Q paths,
AL-RUBAYE AND REBEIZ: ANALYSIS AND DESIGN OF WIDEBAND I/Q CMOS 100–200 Gb/s MODULATORS
2363
On the other hand, Class AB suffers from a significant
change in the gate–source capacitance, resulting in significant
AM–PM distortion [13], [14]. Since efficiency requirements
are typically relaxed for modulators, they are biased in class
A in order to operate linearly and maintain a good modulation
accuracy. Note that, however, a transconductance stage biased
in class-A will operate in class AB-like mode if the gate
is overdriven, such that the drive voltage swing increases
enough to bring the instantaneous voltage at the gate below
the threshold voltage.
For a simple common-source stage with a source resistance
Rs , the phase shift φ at frequency ωo is [13]
1
−1
−Rs ωo C gs0 − C gs2
(6)
φ = tan
2
Fig. 3. Simulated linearity-limited constellations with EVMrms, peak values
labeled. (a) I/Q modulator AM–AM. (b) I/Q modulator AM–PM. (c) I/Q
modulator AM–AM and AM–PM. (d) PA radial AM–AM compression. (e) PA
radial AM–AM expansion. (f) PA radial AM–AM compression with AM–PM.
as shown in Fig. 3(a)–(c), produce different distortion effects
in the constellation than simply distorting the IQ envelope
[Fig. 3(d)–(f)].
1) AM–AM: For short-channel FET devices, to find the
third-order non-linearity causing amplitude and gain compression, a Taylor series expansion is used, leading to the input
voltage compression point formula
2 + θ Vov
(1 + θ Vov )2
(4)
VIP1dB = 0.145Vov
6θ
where θ is a fitting factor that captures mobility degradation
and velocity saturation effects in short-channel devices, and
Vov is the overdrive voltage. The formula assumes soft nonlinearity at the input with no voltage clipping at the output that is
limited by the supply voltage. Nonetheless, these assumptions
were found to give a good quantitative prediction of the circuit
performance as will be demonstrated in the following sections.
Next, we attempt to predict EVM degradation due to AM–AM
compression. For a voltage compression factor gc , in linear
scale, such that gc ≤ 1, EVMrms is
EVMrms =
M
k=1
g0 − gc,k .
P(k) · g
(5)
0
The gain correction factor g0 linearly scales the constellation map such that EVMrms is minimized. P(k) factor is the
probability value of a constellation symbol k.
2) AM–PM: Under large-signal conditions, the change in
the gate–source capacitance, as a function of the input voltage,
causes AM–PM distortion and thereby disturbs the constellations, as shown in Fig. 3. AM–PM distortion is a strong
function of the transistor bias point. It can be shown that
for a pure class A and class B operations, the effective
capacitance does not change with the voltage swing, and
therefore, the AM–PM distortion is minimal.
where C gs0 and C gs2 are the Fourier coefficients of the
gate–source capacitance and are dependent on the intrinsic
gate–source capacitance, the bias point, and input voltage
amplitude v i , all calculated from [13]. The C gd effect can
be ignored in cases where the Miller effect is not dominant,
which is the case in the Gilbert-cell modulator used in this
work. It can be shown that for small φ AM−P M (t) values
EVMrms =
M
P(k) · φ AM−P M (k)
(7)
k=1
where the reference constellation is rotated by φ0 value that
minimizes EVMrms . It is worth noting that in most cases, the
AM–PM distortion occurs before the AM–AM compression,
but AM–AM compression dominates the degradation in EVM
and BER.
C. Carrier Feedthrough
Carrier feedthrough (CFT ) in I/Q modulators can be
generally attributed to device and layout mismatches.
At mm-wave frequencies, however, CFT can be dominated by
coupling through device layout parasitics and in the supply
interconnects, as well as through the silicon substrate [3].
These effects can be mitigated by applying DC offsets
across the differential transconductance pairs. Beyond that,
the leakage is dominated by the second-order non-linear
distortion, which produces data-dependent DC components
that mix with the carrier frequency driving the switching quad
2 ).
(CFT ∝ g2 v gs
In general, to minimize carrier feedthrough, a combination
of symmetric layout techniques and external bias trimming
control must be employed and will lead to leakage levels in
the −40 to −50 dBc range.
D. ISI and Equalization
The impact of limited bandwidth in producing ISI and its
effect on EVM and BER was presented in [3] and [15].
Given the fundamental tradeoff between noise and bandwidth in modulators, it is desirable to build I/Q modulators
with programmable bandwidth such that the two performance
metrics can be traded off dynamically, allowing the support
of high-order modulation formats in narrow bandwidths, in
addition to simpler modulation formats over wider bandwidths.
2364
Fig. 4.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 9, SEPTEMBER 2019
Simulated ACPR versus backoff level for different PAPR values.
Digital equalization is especially successful at compensating
for ripples in the frequency response. However, equalization
for ISI that is attributed to severe bandwidth limitation, or nulls
in the frequency response, leads to boosting the system noise,
i.e., while the distortion due to ISI is improved, the dynamic
range becomes SNR limited, degrading the overall modulation
accuracy [16]. This is especially true in analog (continuoustime) linear equalization (CTLE) or analog pre-emphasis and
in digital feed-forward equalization, which operates by applying the inverse analog or digital finite-impulse response (FIR)
filter that compensates for the channel response. Other
non-linear approaches such as decision-feedback equalization,
while addressing the aforementioned tradeoff, are not well
suited for high-order modulation schemes and are limited in
speed, but remain an active research topic [17]. In other words,
equalization does not replace wideband, linear, and low-noise
analog design, but rather assists in compensating the non-ideal
channel frequency response, as will be demonstrated in the
measurements section.
E. ACPR
The spectral purity of a modulated waveform is measured
using the adjacent channel power ratio (ACPR). ACPR is
defined as the ratio of the power integrated over an assigned
BW (BACP ) in the adjacent/alternate channel (at an offset
f 1 ) to the total desired transmit power over a bandwidth (BW).
It can be shown that the ACPR of a modulated signal is related
to the transmitter’s OP1dB using [15]
ACPRTX [dBc] = 2(PTX − OP1dB) − 32
+PAPR + 10 log
BACP
BW
(8)
where PTX is the average output power of the transmitter,
and the (PTX − OP1dB) term is defined as the backoff level.
The waveform peak-to-average power ratio (PAPR) depends
on the modulation and filtering level used. Fig. 4 shows the
simulated ACPR based on (8) and assumes that the ACPR
is linearity-limited and is not limited by the system noise.
Finding the relationship between ACPR and EVM requires
knowing the probability distribution function of the modulated
waveform.
Fig. 5.
(a) Simulated BER versus EVMrms, peak for a 64-QAM
waveform under different impairment conditions. Constellations for
(b) noise-limited waveform, (c) phase-noise-limited waveform, and (d) nonlinear compression-limited waveform.
F. EVM and BER
The relationship between BER and EVM in SNR-limited
links was presented in [3]. Fig. 5(a) shows the simulated BER
versus EVMrms, peak for a 64-QAM waveform. Three different
cases were simulated with 6 × 1010 bits tested in each. First,
an SNR-limited case was studied where the only impairment
added to the signal was white noise (AWGN) with various
power levels. The simulation result is in agreement with the
theoretical results presented in [3].
Similarly, phase noise and AM–AM compression cases
were also tested [Fig. 5(a)]. It can be observed that the
same EVMrms value can lead to remarkably different BER
outcomes, depending on the dominant source of EVM impairment. This can be intuitively explained in Fig. 5(b)–(d),
where three constellations are presented, all having the same
EVMrms, peak = 3% (EVMrms, avg = 4.6%). The constellations
presented, however, exhibit different EVMmax values, with
Fig. 5(b) having EVMmax = 9.1%, Fig. 5(c) has EVMmax =
13.3%, and Fig. 5(d) with EVMmax = 13.3%. This discrepancy in EVMmax values translates to different BER values.
This study confirms that the theoretical BER and EVM
relations presented in [3] may only be used for SNR-limited
links, or as a best-case BER estimate which is based on an
EVM measurement of a constellation that displays multiple
sources of impairment.
Fig. 6 shows a graphical guideline for selecting the optimum
backoff level for wideband modulators. An optimum backoff
level exists to minimize the BER and increasing the backoff
level beyond this level increases the carrier feedthrough and
degrades the SNR, thus leading to worse EVM and BER.
AL-RUBAYE AND REBEIZ: ANALYSIS AND DESIGN OF WIDEBAND I/Q CMOS 100–200 Gb/s MODULATORS
2365
Fig. 6. Modulator optimization scheme. A BER = 10−3 limit is imposed
throughout this paper.
Reducing the backoff level increases the non-linear distortion
and degrades the BER.
Given the continuous advancement of efficient forward
error correction (FEC) [18] and digital predistortion [19] techniques, operating the system near its P1dB operation point
has become an attractive proposition, since it increases the
overall system efficiency and its dynamic range and optimizes
the joule-per-bit system efficiency. This is shown in Fig. 6
where there is an optimum backoff level that can be targeted
to optimize the system efficiency, by maximizing the dynamic
range for a given bandwidth and power consumption, and as a
result, maximizing the data rate for a given power consumption
or minimizing the joule-per-bit system efficiency. However,
one must take into account the power consumed in the FEC
and DPD blocks and this may not be feasible for 100–200 Gb/s
modulators.
III. C IRCUITS A NALYSIS AND D ESIGN
A. Wideband Double-Balanced Mixer
A double-balanced mixer or Gilbert cell [Fig. 7(a)] forms
the basis for the high-speed and wideband I/Q modulator
presented in this work. In addition to its superior LO and IF
suppression properties, the double-balanced mixer architecture
has been shown to allow for the highest modulation BW in
comparison to other architectures [20].
Double-balanced mixers, on the other hand, have a higher
power consumption with worse noise figure (NF) in comparison with single-balanced mixers for a given supply voltage.
For mm-wave applications, however, the use of differential transconductance stages becomes irreplaceable since they
provide virtual grounds locally within the transistor layout.
This is, in contrast, with single-ended designs where the
interconnect parasitics to the ground dominate the performance
by degenerating the gain stages and thus degrading the mixer
gain and noise performance.
From Fig. 7(a), the mixer voltage gain is
Rterm
2
gm × R p ||R L + 20 log
(9)
Av = 20 log
π
Rterm + Rs
where gm = 51 mS, R p is the resistance presented by the
pMOS device biased in the triode region, R L is the load resistance driven by the mixer, and Rterm = 75 is the termination
resistor at the input. This resistance value results in a good
Fig. 7.
(a) Upconversion mixer Gilbert-cell schematic. Conversion gain
simulations with PLO values ranging from −8 to +2 dBm in 2-dB increments
at (b) f LO = 20 GHz and (c) f LO = 100 GHz.
balance between input matching, gain, and noise. For the given
bias condition, the voltage gain was found to be −4.67 dB
and the power gain, G, equals 3.3 dB. The minimum LO
power
√ required to fully steer the current through the switches
is 2Vov = 350 mV or 1 dBm for this design. Higher LO
drive power may be required to reduce the noise contribution
from the switches, as well as increasing the conversion gain
of the mixer. Fig. 7 shows the simulated conversion gain at
different carrier frequencies and under different LO power
drive conditions. As expected, the conversion gain improves
with increasing PLO up to +2 dBm, above which little or no
improvement was observed.
Fig. 8 shows the double-balanced Gilbert cell with active
pMOS loads along with its various noise sources. It can be
shown that the NF is
Rs
NF = 1 +
Rterm
γg
R L + RG p (gmp R L )2 + γ 2gm (R p ||R L )2 + 2m p R 2L
+
A2v Rs
and is 12 dB for a 50- load R L and sets the minimum lowfrequency NF achievable by the modulator. For simplicity, the
noise contribution from the switching quad transistors has been
ignored. This is a valid assumption as long as the LO drive
power is maintained sufficiently large, which is greater than
0 dBm in this case. Moreover, the analysis is valid only at
low frequencies where the capacitive and inductive parasitics
effects may be ignored. Note that the noise contribution of
2366
Fig. 8.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 9, SEPTEMBER 2019
Gilbert-cell noise model.
the pMOS switches decreases with frequency due to the
self-capacitance of the devices, and also due to the resonances
formed with the peaking inductors. Therefore, the mixer NF
drops with frequency before rising back again due to the mixer
gain reduction at higher frequencies.
Fig. 9(a) shows the actual Gilbert cell mixer used to realize
the wideband I/Q modulator. Source-follower buffers are first
used to present a low-capacitance load for the current-mode
logic (CML) quadrature generator and thus maximizing its
self-oscillation frequency. Fig. 9(b) shows the simulated conversion gain, IP1dB, and NF at different LO frequencies from
10 to 100 GHz and with an IF of 1 GHz. The simulated results
include transistor parasitic extraction up to the fifth metal (M5)
in the technology backend, and full electromagnetic (EM)
modeling of the interconnects between the transistor stages
and also of the peaking inductors. High-frequency peaking
is achieved using 130 and 30 pH shunt and series inductors,
respectively. Active 50- output matching is achieved using
tunable pMOS loads to realize a wideband output match. Furthermore, the tunable active pMOS load allows 2–3 dB of
pre-emphasis in the modulator frequency response, by boosting the high-frequency gain while attenuating low-frequency
gain as needed, thus compensating the low-pass frequency
response of the following stages [Fig. 9(c)].
Fig. 9(d) shows the simulated NF at 10–100 GHz, under
different LO power drive conditions. As expected, the NF
decreases with increasing PLO . Also, note that the NF
is 5.5–6 dB at 60 GHz, which is much better than the 12-dB
value at 10 GHz and is due to the reasons explained above.
B. Programmable DC-120-GHz Divider and Quadrature
I/Q Generator
The generation of quadrature signals with low phase and
amplitude errors remains a challenge for Cartesian transmitters. Digital techniques, such as frequency dividers, proved to
be the most successful but are limited in their frequency of
operation [21]. For example, CML static CMOS dividers have
been limited to around 30-GHz output frequency. Dynamic and
Fig. 9. (a) DC-100-GHz Gilbert-cell mixer. (b) Simulated conversion gain,
linearity, and NF up to 100 GHz. (c) Simulated conversion gain as a function
of the pMOS control voltage displaying peaking control by up to 3 dB at
60 GHz. (d) Simulated NF for PLO = −4 to +2 dBm.
injection-locked dividers are capable of operating at mm-wave
frequencies, but they suffer from a narrow frequency operation
range.
Figs. 10(a) and 11 show the wideband quadrature (I/Q) signal generator, which consists of two CML latches in feedback.
This traditional architecture is improved in two ways. First,
the I/Q generator is loaded with source-follower stages [not
shown—see Fig. 9(a)] to reduce the capacitive loading and
boost its frequency of operation. Second, a novel inductive
loading technique with tunable resistance is used. This controls
the locations of the frequency poles and, consequently, the
phase shift (and time delay) in the loop. It also allows the
AL-RUBAYE AND REBEIZ: ANALYSIS AND DESIGN OF WIDEBAND I/Q CMOS 100–200 Gb/s MODULATORS
Fig. 11.
Fig. 10. (a) DC-50-GHz quadrature signal generator [component values
shown in Fig. 11(a)]. (b) Simulated transient at 100 GHz.
control of the self-oscillation frequency of the divider, while
also introducing peaking control in the frequency response,
further boosting the maximum frequency of division. A transient simulation of the divider (connected to the modulator)
is shown in Fig. 10(b), with the input and output signals at
100 and 50 GHz, respectively, proving operation up to at least
100 GHz.
Frequency dividers exhibit sensitivity curves marked with
a self-oscillation frequency f osc . As the input frequency deviates from f osc , the required input power needed for proper
operation increases, requiring wideband LO buffers, which
can increase the overall system power consumption. The
self-oscillation frequency of a static divider is given by
f osc =
1
2tdelay
(10)
where tdelay is the time delay through a single latch. For a
generic static divider with a resistive load R L , tdelay when
driving a capacitive load C L is [22]
2Ibias R L
tdelay = R L C L · ln
(11)
√
Ibias R L − 2Vov
where R L = R2 + R1 ||Ron, p , and Ron, p is the ON-resistance
of the pMOS load for our particular design [Fig. 11(a)]. It
is evident that for a given capacitive load and voltage swing
conditions, there is a direct tradeoff between the self-resonance
2367
CML latch analysis. (a) Schematic. (b) Model.
frequency and power consumption. This tradeoff is relaxed in
the programmable divider design by turning the pMOS load on
and reducing R L to a minimum of ∼ R2 = 30 (corresponds
to f osc 99 GHz), where the inductive load contributes to
the impedance peaking, eliminating the need to increase the
power consumption or Ibias . In the lower frequency regime of
operation, the pMOS load is turned off, and R L = 130 ,
C L = 50 fF, Ibias = 4 mA, and Vov = 200 mV, and this
results in tdelay 10 ps, and f osc 50 GHz.
It is also of interest to find the maximum frequency of operation of static dividers f div,max . In order to do so, we adopt the
model shown in Fig. 11(b), where before the latching action
begins, and the divider starts operating as a digital circuit, it
can be viewed as a mixer circuit with a negative resistance load
due to the cross-coupled pair at its output. For the circuit to
divide properly, two conditions must be met: first, the output
frequency must satisfy the loop equation. This condition is
readily met, since f out = fin /2 meets this criterion. Second,
the mixer circuit must have sufficient gain to guarantee at least
unity gain through the loop (gm R L ≥ 1). As we approach
f div,max , the capacitive load at the output dominates, and most
of the current generated by the transconductance stage flows
through the capacitor. If we assume C L = C gs , such that latch
drives another latch of similar size, then the second condition
becomes
1 2
≥ 1.
(12)
gm π
j ωC gs
Neglecting the phase shift in the loop and recalling that
f t (gm /C gs ), we then arrive at the approximate expression
2
ft .
(13)
π
The divider should be carefully designed such that the
“mixer” stage exhibits sufficient gain at all frequencies. Alternatively, tunable gain peaking techniques may be used, as is
the case in this work.
f max,div ≤
C. DC-60-GHz I/Q Modulator
Current combining is used to combine the I and
Q modulation paths since it offer the highest bandwidth.
Quadrature amplitude and phase mismatches are minimized
2368
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 9, SEPTEMBER 2019
Fig. 12. Symmetric I/Q modulator layout in 45 RFSOI (top metal layers are
shown).
by the following symmetric layout strategies such that LO
and data distribution are fully differential with a minimum
mismatch (Fig. 12). The fully differential layout maximizes
the transmitter speed by taking advantage of local on-chip
ac grounds and desensitizing it to any common-mode ground
and supply parasitics. Furthermore, common-mode rejection is
achieved using a common-mode choke inductor at mm-wave
frequencies [L choke in Fig. 9(a)], where the current mirror
exhibits a low output impedance due to its capacitance.
Any minimal amplitude mismatch that may rise from layout
or variations in the transistors properties can be corrected
by changing the modulator gain control using the current
source available at the bottom of each Gilbert cell [Fig. 9(a)].
Furthermore, LO leakage can be corrected using the external
baseband DACs, which are DC coupled, thus enabling DC
offsets between the differential IF inputs. Fig. 13 shows
the conversion gain and output noise simulation results for
different control voltages. For the Gilbert cell with Vov 0.15 V, it follows from (4) that VIP1dB = 0.137 V or −9 dBm
into a 75- load, under a 0.1-mA/μm bias current density.
In addition, there is 3 dB of combining loss when combining
the I and Q modulation paths. This combining loss may be
reduced using high-frequency quadrature LO generators with
25% duty cycle [23], [24].
The double-balanced mixers of the I/Q modulator each
consume 14 mA of current from a 3-V supply, while the
I/Q signal generator consumes 45 mA from a 2.5-V supply.
The total power consumption of the modulator is 200 mW
including biasing.
IV. M EASUREMENTS
A. Programmable DC-110-GHz Divider
A breakout of the programmable divider loaded by the
common-source driver was first tested using a GSSG differential probe, and the input signal was swept in frequency
(DC-70 GHz) and in power (up to 0 dBm) for a given divider
Fig. 13. I/Q modulator simulations. (a) Conversion gain as a function of the
pMOS control voltage Vb . (b) Conversion gain and output noise at an IF of
1 GHz from DC-60 GHz for different divider control voltage values Vc .
tuning control voltage Vc . The output spectrum was then
observed using a Keysight E4448A DC-50-GHz spectrum
analyzer. In the 70–110 GHz input frequency range, a WR10 waveguide setup was used with the VDI AMC-335 multiplier chain. An external downconversion mixer was also used
to cover the 50–55 GHz output frequency range.
Fig. 14(a) shows that the divider’s self-oscillation frequency
can be tuned in an analog fashion from 44 to 99 GHz,
depending on the control voltage applied to the pMOS transistors. This work presents the first DC-110 GHz CMOS
static frequency divider with record self-oscillation frequency
of 99 GHz [Fig. 14(b)] and allows the generation of a
near-perfect quadrature LO drive from DC-55 GHz, while
also directly driving an I/Q modulator without the need for
additional amplification stages.
B. Wideband Mixer Measurements
A mixer breakout was also tested using differential (GSSG)
RF, LO, and IF probes and a Keysight 4-port N5247A PNA-X
network analyzer. Fig. 15 shows the measured S-parameters
of the LO and RF ports from DC-70 GHz, demonstrating the
wideband matching at these ports. Matching at the IF ports is
achieved using shunt 50 resistors and a return loss > 10 dB
is achieved up to 30 GHz.
Fig. 16 shows the measured conversion gain and OP1dB
from DC to 50 GHz (limited by the measurement setup).
The conversion gain was evaluated by sweeping the LO
AL-RUBAYE AND REBEIZ: ANALYSIS AND DESIGN OF WIDEBAND I/Q CMOS 100–200 Gb/s MODULATORS
Fig. 14. CML divider measurements. (a) Sensitivity curves for three different
control voltage values. (b) Measured output spectrum for Vc = 1.5 V showing
self-oscillation at 99 GHz.
Fig. 16.
Double-balanced mixer measurements.
Fig. 17.
Measured mixer conversion gain for LO = 25 GHz.
2369
Note that the noise floor of most commercial spectrum analyzers without the pre-amplifier option is in the −150 dBm/Hz
range. Therefore, three amplifiers were used with 25–40 dB
gain range and covering the 0.5–50 GHz frequency spectrum
in three parts: 0.5–18 GHz, 18–40 GHz, and 40–50 GHz.
The S-parameters of the amplifiers were then measured and
de-embedded from the spectrum analyzer measurements.
C. I/Q Modulator Measurements
Fig. 15. Measured double-balanced mixer return loss for the LO (port 1)
and RF (port 2).
frequency while fixing the IF frequency at 1 GHz. A wideband
conversion gain of 0 dB and an OP1dB of −12 to −10 dBm
is achieved at DC-50 GHz. The measured output noise floor
in the same BW is approximately −162 dBm/Hz, leading to
150 dB/Hz of dynamic range at the output. This is sufficient
to support very high-order modulations (e.g., 256 QAM) in
10 GHz of BW with 50 dB of dynamic range (at P1dB).
Fig. 17 shows the measured conversion gain up to 50 GHz
with a 25-GHz LO frequency. The mixer’s conversion gain
varies by less than 2 dB over the entire bandwidth, making
it possible to support a minimum of 50 Gbaud rate when
employed in the IQ modulator.
Fig. 18(a) shows the measurement setup used to evaluate
the wideband I/Q modulator. The fully differential modulator
chip occupies 1 × 1.4 mm2 area including pads (core area
of 0.18 × 0.1 mm2 ) and is fabricated in the GlobalFoundaries
45-nm SOI CMOS process [Fig. 18(b)], [10]. The differential
LO ports are driven by a 1 MHz-70 GHz network analyzer
(Keysight N5247A PNA-X). The differential and quadrature IF
inputs are driven with two channels from the Keysight M8196
92-GSa/s arbitrary waveform generator (AWG).
Four phase-matched SMA cables are connected to a 2.9-mm
GSSGSSG probe for the quadrature I and Q data inputs,
as shown in Fig. 18(c). Wideband 10-dB attenuators are used
at the output of the AWG channels in order to use the external
DACs at their full scale, thus maximizing the dynamic range
available from the DACs. The differential RF output signal is
measured using an E4448A spectrum analyzer up to 50 GHz,
and also using a 160 GSa/s DC-63 GHz Keysight DSAZ634A
real-time oscilloscope. The dynamic range of the oscilloscope
is limited to approximately 35 dB at its widest capture BW
2370
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 9, SEPTEMBER 2019
Fig. 19.
SSB and LO leakage measurements.
Fig. 20.
EVM and ACPR measurements versus backoff level at an
LO (carrier) of 5 GHz. (a) 64-QAM with 100 Mbaud. (b) 256-QAM with
100 Mbaud.
Fig. 18.
(a) Chip micrograph. (b) I/Q modulator measurement setup.
(c) Measurement setup photo.
and sets the dynamic range of the 100–200 Gb/s measurement
setup.
1) SSB Suppression and Carrier Feedthrough: To evaluate
the transmitter dynamic range, it is first configured as a
single-sideband (SSB) transmitter to measure the LO leakage
and SSB suppression. Furthermore, SSB suppression will indicate the quality of the IQ generator in terms of its amplitude
and phase mismatch. A 100-MHz tone is generated using an
AWG that is controlled in software by MATLAB, such that the
first channel of the AWG generates the 100-MHz sinusoidal
tone and the second channel generates the Hilbert transform
(quadrature signal in the case of a single tone) of the signal
in channel 1. The two channels are synchronized and phase
adjusted such that the two quadrature signals arrive at the I and
Q input data pads of the die with correct phases. The output of
the transmitter is then connected to a spectrum analyzer, where
the LO leakage and SSB suppression are readily determined.
Fig. 19 shows the measured sideband suppression and
LO leakage as a function of the LO frequency. Sideband
suppression is measured by first determining the phase setting
to account for the mismatch between the I and Q paths at
100 MHz that is due to the measurement setup, then the LO
frequency is swept without changing any phase settings from
the AWG. This determines the true wideband performance
of the I/Q modulator chip. The measured SSB suppression
is >30 dB over the entire DC-50 GHz band.
Fig. 19 also shows that the LO leakage can be as high
as −25 dBc—normalized to the transmitted power—prior to
calibration. The increase in carrier feedthrough with frequency
is expected and has been discussed in Section II-C. After calibration, the leakage levels are significantly improved down to a
worst case level of −50 dBc. The optimum calibration settings
vary for each LO frequency, even though the IF frequency is
fixed at 100 MHz. This is due to frequency-dependent leakage
mechanisms such as the direct LO to RF leakage through the
transistor parasitics and supply network. The output of the
I/Q transmitter is measured in a single-ended fashion, which
further contributes to the LO feedthrough. This is because
external or on-chip baluns are limited in BW and are not
capable of covering the DC-60 GHz frequency range.
Given the worst case SSB rejection and carrier feedthrough
of 35 dB (at an LO of 35 GHz) and −50 dBc, respectively,
a worst case EVM of approximately 1.8% is to be expected,
limiting the use of very-high order modulation formats such
as 256-QAM and 1024-QAM to LO carrier frequencies below
20 GHz (where the SSB rejection is > 45 dB).
2) Linearity Measurements: Fig. 20 shows the measured
EVM and ACPR at a 5-GHz carrier for 64-QAM and
256-QAM. As expected, both ACPR and EVM are minimum
AL-RUBAYE AND REBEIZ: ANALYSIS AND DESIGN OF WIDEBAND I/Q CMOS 100–200 Gb/s MODULATORS
2371
Fig. 21.
Equalization effects for a 28-GHz carrier. (a) 16-QAM with
100 Mbaud. (b) 64-QAM with 100 Mbaud.
Fig. 22. Quadrature amplitude and phase errors versus backoff level at
28 GHz. (a) 16-QAM with 100 Mbaud. (b) 64-QAM with 100 Mbaud.
at certain backoff levels, above which they degrade due to
non-linear distortion. Increasing the backoff level degrades the
EVM and ACPR due to CFT and SNR degradation.
Fig. 21 shows the benefit of applying linear equalization
to the measured EVM of 100-Mbaud signals at a 28-GHz
carrier. In general, significant improvement in the measured
EVM is observed, even over narrow modulation bandwidths.
At 100-MHz BW, the frequency response of the circuit can
be assumed ideal, and therefore, any ISI resulting from
non-ideal amplitude and phase response of the channel arises
from the measurement setup. Furthermore, as the backoff
level decreases the EVM becomes dominated by non-linear
effects and the equalized and non-equalized results become
comparable.
Fig. 22 shows the measured quadrature amplitude and phase
errors at 28 GHz as a function of the backoff level. Initially,
the quadrature amplitude and phase errors are small owing
to the accuracy of the digital CML IQ generator. As the
input power to the baseband transconductance stages increases,
AM–AM and AM–PM distortions lead to data-dependent
quadrature amplitude and phase errors. Simulations of the
double-balanced mixer show 2◦ of AM–PM distortion at
P1dB, which directly translates to phase errors in the Cartesian
IQ transmitter.
3) Single-Carrier Measurements: Single-carrier modulation
measurements of the I/Q modulator were carried out up to
63 GHz. Since the differential signal source is limited to
70 GHz, the transmitter operates in direct-conversion mode
up to 35 GHz and in a heterodyne mode with SSB rejection
above 35 GHz.
Fig. 23 shows the measured EVM versus data rate for
various carrier frequencies and modulation formats up to
Fig. 23. (a) Measured EVM versus baud rate for different modulation formats
at a 28-GHz carrier. (b) Measured output spectrum of a 1-Gbaud 16-QAM
modulated signal with a RRC filter applied (rolloff factor α = 0.15). (c) 5GHz measurements. (d) 15-GHz measurements. (e) 35-GHz measurements.
(f) 60-GHz measurements.
Fig. 24. Measured constellations at 28 GHz for various modulation formats,
demonstrating low-EVM at (a) 64-QAM/1-GHz BW and peak data rate
of 200 Gb/s, (b) 16-QAM/50-GHz BW, and (c) 32-QAM/40-GHz BW.
60 GHz. Measurements of the modulator proved its capability of supporting a maximum baud rate of 60 Gbaud/s
in QPSK (120 Gb/s), 50 Gbaud/s in 16-QAM (200 Gb/s),
40 Gbaud/s in 32-QAM (200 Gb/s), and 20 Gbaud/s
in 64-QAM (120 Gb/s). The measurement was carried out at
6-dB backoff and with an expected worst case BER better
than 10−3 . To the best of authors’ knowledge, this the first
demonstration of transmit data rates exceeding 100 Gb/s in
silicon technologies. Fig. 24 shows examples of measured
constellations at 28 GHz.
2372
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 9, SEPTEMBER 2019
TABLE I
C OMPARISON W ITH THE S TATE - OF - THE -A RT U LTRAWIDEBAND
T RANSMITTERS IN S ILICON T ECHNOLOGIES
Fig. 26.
60 GHz.
Demonstration of 5G mm-wave carrier aggregation at 28 and
Fig. 27. Measured spectrum and constellation of 100-MHz 64-QAM OFDM
signal at 28 GHz with −31.8 dB EVM.
Fig. 25.
Demonstration of 5G mm-wave carrier aggregation at 28 and
39 GHz using the wideband I/Q modulator. (a) 32 Gb/s, 4.8% EVM at
28 GHz. (b) 32 Gb/s, 7% EVM at 39 GHz. (c) Measured spectrum showing
simultaneous transmission of the two carriers.
Table I gives a comparison with state-of-the-art modulators
and transmitters. A significant improvement is demonstrated
in the data throughput and energy/bit efficiency. The output
power can be increased using wideband distributed amplifier
topologies [28].
4) Multi-Carrier Measurements: Single-channel wideband
modulations are highly susceptible to channel impairments,
such as multi-path fading, and are generally difficult to process
efficiently in baseband. Therefore, carrier aggregation techniques are expected to be a driving technology in future wideband communication systems. Inter-band carrier aggregation
of mm-wave systems is of particular interest for ultra-high
data rate scenarios.
Fig. 25 demonstrates an example of an ultra-wideband 5G
carrier aggregation link, where 2 × 8 Gbaud 16-QAM signals
are modulated with 28- and 39-GHz carriers, resulting in a
record aggregate data rate of 64 Gb/s.
Fig. 26 shows another mm-wave carrier aggregation scenario where 28- and 60-GHz carriers were simultaneously
modulated, each at 100 Mbaud and in 16-QAM, resulting
in 800-Mbps aggregate data rate. The transmitter operates
in direct-conversion mode for the 28-GHz carrier and as an
image-rejecting wideband-IF transmitter at 60 GHz.
Similarly, multi-carrier OFDM waveforms are expected to
be highly used in mm-wave 5G due to their spectral efficiency
and efficient MIMO implementation. Fig. 27 shows the measurement of a 100-MHz 64-QAM 52-subcarriers OFDM signal
at 28 GHz, with −31.8-dB EVM at 10-dB backoff.
V. C ONCLUSION
A wideband state-of-the-art DC-60 GHz I/Q modulator/transmitter chip in 45-nm SOI CMOS was presented.
The 1.4 mm2 (0.18 × 0.1 mm2 core) modulator consists of
AL-RUBAYE AND REBEIZ: ANALYSIS AND DESIGN OF WIDEBAND I/Q CMOS 100–200 Gb/s MODULATORS
a wideband quadrature signal generator, wideband buffers,
and two current-combined DC-100 GHz low-noise doublebalanced mixers. The I/Q modulator achieves 200 Gb/s
in 16-QAM (50 Gbaud/s), while consuming 200 mW, resulting
in a record 1-pJ/bit modulation efficiency. In addition to
backhaul links, the modulator is an attractive and cost-effective
alternative to short-range optical links for data center interconnects (DCI) applications. Future work may include increasing
the modulator output power to alleviate the need for an
additional power amplifier stage.
ACKNOWLEDGMENT
The authors would like to thank Keysight for the
M8196 AWG and for technical support and Integrand for the
EMX simulation software.
R EFERENCES
[1] A. Boveda and J. I. Alonso, “A 0.7-3 GHz GaAs QPSK/QAM direct
modulator,” IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1340–1349,
Dec. 1993.
[2] Y. Baeyens et al., “A wideband SiGe BiCMOS transceiver chip-set
for high-performance microwave links in the 5.6–43.5 GHz range,”
in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), Jun. 2017,
pp. 376–379.
[3] H. Al-Rubaye and G. M. Rebeiz, “W -band direct-modulation >20-Gb/s
transmit and receive building blocks in 32-nm SOI CMOS,” IEEE J.
Solid-State Circuits, vol. 52, no. 9, pp. 2277–2291, Sep. 2017.
[4] K. Khalaf et al., “Digitally modulated CMOS polar transmitters for
highly-efficient mm-wave wireless communication,” IEEE J. Solid-State
Circuits, vol. 51, no. 7, pp. 1579–1592, Jul. 2016.
[5] L. Anttila, P. Handel, and M. Valkama, “Joint mitigation of power
amplifier and I/Q modulator impairments in broadband direct-conversion
transmitters,” IEEE Trans. Microw. Theory Techn., vol. 58, no. 4,
pp. 730–739, Apr. 2010.
[6] P.-Y. Wu, Y. Liu, B. Hanafi, H. Dabag, P. Asbeck, and J. Buckwalter,
“A 45-GHz Si/SiGe 256-QAM transmitter with digital predistortion,” in
IEEE MTT-S Int. Microw. Symp. Dig., May. 2015, pp. 1–3.
[7] S.-A. Yu et al., “A single-chip 125-MHz to 32-GHz signal source in
0.18-μm SiGe BiCMOS,” IEEE J. Solid-State Circuits, vol. 46, no. 3,
pp. 598–614, Mar. 2011.
[8] H. Chung, Q. Ma, and G. M. Rebeiz, “A 10–40 GHz frequency quadrupler source with switchable bandpass filters and > 30 dBc harmonic
rejection,” in Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC),
Jun. 2017, pp. 49–52.
[9] L. Vera and J. R. Long, “A DC-100 GHz active frequency doubler with a
low-voltage multiplier core,” IEEE J. Solid-State Circuits, vol. 50, no. 9,
pp. 1963–1973, Sep. 2015.
[10] O. Inac, M. Uzunkol, and G. M. Rebeiz, “45-nm CMOS SOI technology
characterization for millimeter-wave applications,” IEEE Trans. Microw.
Theory Techn., vol. 62, no. 6, pp. 1301–1311, Jun. 2014.
[11] A. K. Gupta and J. F. Buckwalter, “Linearity considerations for
low-EVM, millimeter-wave direct-conversion modulators,” IEEE Trans.
Microw. Theory Techn., vol. 60, no. 10, pp. 3272–3285, Oct. 2012.
[12] A. A. M. Saleh, “Frequency-independent and frequency-dependent nonlinear models of TWT amplifiers,” IEEE Trans. Commun., vol. 29,
no. 11, pp. 1715–1720, Nov. 1981.
[13] S. Golara, S. Moloudi, and A. A. Abidi, “Processes of AM-PM distortion
in large-signal single-FET amplifiers,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 64, no. 2, pp. 245–260, Feb. 2017.
[14] C. Wang, M. Vaidyanathan, and L. E. Larson, “A capacitancecompensation technique for improved linearity in CMOS class-AB
power amplifiers,” IEEE J. Solid-State Circuits, vol. 39, no. 11,
pp. 1927–1937, Nov. 2004.
[15] Q. Gu, RF System Design Transceivers for Wireless Commun., 1st ed.
Springer, 2005.
[16] S. H. Hall and H. L. Heck, Advanced Signal Integrity for High-Speed
Digital Designs. Hoboken, NJ, USA: Wiley, 2009.
[17] C. Thakkar, “Design of multi-Gb/s multi-coefficient mixedsignal equalizers,” Ph.D. dissertation, Univ. California, Berkeley,
CA, USA, 2012. [Online]. Available: https://www.eecs.berkeley.
edu/Pubs/TechRpts/2014/EECS2014-189.html
2373
[18] A. J. Viterbi, “Wireless digital communication: A view based on three
lessons learned,” IEEE Commun. Mag., vol. 29, no. 9, pp. 33–36,
Sep. 1991.
[19] P. Asbeck, Linearization Techniques. San Diego, CA, USA: UCSD.
2014.
[20] S. Shopov, A. Balteanu, and S. P. Voinigescu, “A 19 dBm, 15 Gbaud,
9 bit SOI CMOS power-DAC cell for high-order QAM W-band transmitters,” IEEE J. Solid-State Circuits, vol. 49, no. 7, pp. 1653–1664,
Jul. 2014.
[21] S. Voinigescu, High-Frequency Integr. Circuits. Cambridge, U.K.: Cambridge Univ. Press, 2013.
[22] A. Ghilioni, A. Mazzanti, and F. Svelto, “Analysis and design of
mm-Wave frequency dividers based on dynamic latches with load
modulation,” IEEE J. Solid-State Circuits, vol. 48, no. 8, pp. 1842–1850,
Aug. 2013.
[23] N. Weiss, S. Shopov, P. Schvan, P. Chevalier, A. Cathelin, and
S. P. Voinigescu, “DC-62 GHz 4-phase 25% duty cycle quadrature
clock generator,” in Proc. IEEE Compound Semiconductor Integr. Circuit
Symp. (CSICS), Oct. 2017, pp. 1–4.
[24] K. Kibaroglu and G. M. Rebeiz, “A 0.05–6 GHz voltage-mode harmonic
rejection mixer with up to 30 dBm in-band IIP3 and 35 dBc HRR in
32 nm SOI CMOS,” in Proc. IEEE Radio Freq. Integr. Circuits Symp.
(RFIC), Jun. 2017, pp. 304–307.
[25] S. Shopov, N. Cahoon, and S. P. Voinigescu, “Ultra-broadband I/Q RFDAC transmitters,” IEEE Trans. Microw. Theory Techn., vol. 65, no. 12,
pp. 5411–5421, Dec. 2017.
[26] S. Daneshgar et al., “A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm
CMOS with polarization MIMO,” in IEEE ISSCC Dig. Tech. Papers,
Feb. 2018, pp. 166–168.
[27] J. Pang et al., “24.9 A 128-QAM 60GHz CMOS transceiver for
IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance,”
in IEEE ISSCC Dig. Tech. Papers, Feb. 2017, pp. 424–425.
[28] O. El-Aassar and G. M. Rebeiz, “4.7 A compact DC-to-108 GHz
stacked-SOI distributed PA/driver using multi-drive inter-stack coupling,
achieving 1.525 THz GBW, 20.8 dBm peak P1dB, and over 100 Gb/s in
64-QAM and PAM-4 modulation,” in IEEE ISSCC Dig. Tech. Papers,
Feb. 2019, pp. 86–88.
Hasan Al-Rubaye (S’11) received the B.Sc. degree
in electrical engineering from the University of
Toronto, Toronto, ON, Canada, in 2013, and the
Ph.D. degree from the University of California at
San Diego (UCSD), San Diego, CA, USA, in 2018.
He held internships with Advanced Micro
Devices (AMD) and Nokia Bell Labs, where he
was involved in research and development efforts in
mm-wave phased array systems. From March 2018
to June 2019, he was at Roshmere, Inc., working
on 64 Gbaud RF front ends for 400G and 800G
optical coherent systems. He is currently an R&D IC Design Engineer in the
Wireless Communications and Connectivity (WCC) division at Broadcom,
Inc., San Diego, CA.
Dr. Al-Rubaye was a recipient of the ISSCC Analog Devices Outstanding
Designer Award and the Best Conference Paper Award twice during the course
of his graduate studies.
2374
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 54, NO. 9, SEPTEMBER 2019
Gabriel M. Rebeiz (S’86–M’88–SM’93–F’97))
received the Ph.D. degree from the California Institute of Technology, Pasadena, CA, USA.
From 1988 to 2004, he was with the University
of Michigan, Ann Arbor, MI, USA. His group
has optimized the dielectric lens antenna that is
the most widely used antenna at millimeter-wave
and terahertz frequencies. His group also developed
6–18-GHz, 30–35-GHz, 40–50-GHz, 77–86-GHz,
and 90–110-GHz 8- and 16-element phased arrays
on a single silicon chip, the first silicon phased-array
chip with built-in self-test capabilities, the first wafer-scale phased arrays with
on-chip antennas, and the first SiGe millimeter-wave silicon passive imager
chip at 85–105 GHz. His group also demonstrated high-performance RF
MEMS tunable filters at 0.7–6 GHz, RF MEMS phase shifters at 1–100 GHz,
and high-power high-reliability RF MEMS metal-contact switches. As a
Consultant, he helped to develop 24- and 77-GHz single-chip SiGe automotive
radars, phased arrays operating at X- to W-band for defense and commercial
applications (SATCOM, automotive, and point to point), digital beamforming
systems, and several industrial RF MEMS switches. He has graduated
72 Ph.D. students and 22 Post-Doctoral Fellows. He currently leads a group
of 22 Ph.D. students and Post-Doctoral Fellows in the area of millimeter-wave
radio frequency integrated circuits (RFICs), tunable microwaves circuits,
RF MEMS, planar millimeter-wave antennas, and terahertz systems.
He is currently a Distinguished Professor and the Wireless Communications
Industry Chair Professor of Electrical and Computer Engineering with
the University of California at San Diego (UCSD), San Diego, CA,
USA. He has authored or coauthored more than 720 IEEE publications. He has authored RF MEMS: Theory, Design and Technology
(Wiley, 2003).
Dr. Rebeiz is a member of the National Academy. He was a National
Science Foundation Presidential Young Investigator and the 2003 IEEE
Microwave Theory and Technique Society (MTT-S) Distinguished Young
Engineer. He was a recipient of an URSI Koga Gold Medal, the IEEE MTT-S
2000 and 2014 Microwave Prize, the IEEE MTT-S 2010 Distinguished Educator Award, the IEEE Antennas and Propagation Society (AP-S) 2011 John
D. Kraus Antenna Award, the 2012 Intel Semiconductor Technology Council
Outstanding Researcher in Microsystems, the R&D100 2014 Award for this
work on phased-array automotive radars, the 2014 IEEE Daniel E. Noble
Field Medal for his work on RF MEMS, the IEEE AP-S 2015 Harold A.
Wheeler Applications Prize Paper Award, the 1997–1998 Eta Kappa Nu
Professor of the Year Award, the 1998 College of Engineering Teaching
Award, the 1998 Amoco Teaching Award given to the Best Undergraduate
Teacher at the University of Michigan, and the 2008 Teacher of the Year
Award of the Jacobs School of Engineering, UCSD. His students were the
recipient of 23 Best Paper Awards from the IEEE MTT-S, RFIC, and AP-S
Conferences. He serves as a Distinguished Lecturer for the IEEE MTT-S,
the IEEE AP-S, and the IEEE Solid-State Circuit Society. He serves as an
Associate Editor for the IEEE T RANSACTIONS ON M ICROWAVE T HEORY
AND T ECHNIQUES .